Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2067441	1			T2	194		T3	4327		T4	596
all_values[1]	2067441	1			T2	194		T3	4327		T4	596
all_values[2]	2067441	1			T2	194		T3	4327		T4	596
all_values[3]	2067441	1			T2	194		T3	4327		T4	596
all_values[4]	2067441	1			T2	194		T3	4327		T4	596
all_values[5]	2067441	1			T2	194		T3	4327		T4	596
all_values[6]	2067441	1			T2	194		T3	4327		T4	596
all_values[7]	2067441	1			T2	194		T3	4327		T4	596

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15983277

1

T2

1552

T3

34616

T4

2972

auto[1]

556251

1

T4

1796

T31

88

T63

52

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16519330

1

T2

1552

T3

34461

T4

4731

auto[1]

20198

1

T3

155

T4

37

T31

71

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1993187	1			T2	194		T3	4221		T4	4
all_values[0]	auto[0]	auto[1]	8634	1			T3	106		T31	2		T32	54
all_values[0]	auto[1]	auto[0]	64962	1			T4	590		T31	7		T16	4
all_values[0]	auto[1]	auto[1]	658	1			T4	2		T31	9		T15	1
all_values[1]	auto[0]	auto[0]	1996664	1			T2	194		T3	4278		T5	1
all_values[1]	auto[0]	auto[1]	5914	1			T3	49		T4	2		T31	4
all_values[1]	auto[1]	auto[0]	64440	1			T4	586		T31	7		T63	4
all_values[1]	auto[1]	auto[1]	423	1			T4	8		T31	3		T63	1
all_values[2]	auto[0]	auto[0]	2021458	1			T2	194		T3	4327		T4	589
all_values[2]	auto[0]	auto[1]	2187	1			T4	1		T31	6		T32	31
all_values[2]	auto[1]	auto[0]	43523	1			T4	3		T31	3		T63	1
all_values[2]	auto[1]	auto[1]	273	1			T4	3		T31	5		T63	1
all_values[3]	auto[0]	auto[0]	1940466	1			T2	194		T3	4327		T4	590
all_values[3]	auto[0]	auto[1]	221	1			T4	3		T31	3		T63	2
all_values[3]	auto[1]	auto[0]	126543	1			T4	2		T31	5		T63	1
all_values[3]	auto[1]	auto[1]	211	1			T4	1		T31	2		T63	3
all_values[4]	auto[0]	auto[0]	2016651	1			T2	194		T3	4327		T4	590
all_values[4]	auto[0]	auto[1]	222	1			T4	2		T31	5		T54	4
all_values[4]	auto[1]	auto[0]	50363	1			T4	3		T31	5		T63	8
all_values[4]	auto[1]	auto[1]	205	1			T4	1		T31	8		T63	2
all_values[5]	auto[0]	auto[0]	1986659	1			T2	194		T3	4327		T4	3
all_values[5]	auto[0]	auto[1]	193	1			T4	1		T31	2		T63	2
all_values[5]	auto[1]	auto[0]	80378	1			T4	589		T31	6		T63	6
all_values[5]	auto[1]	auto[1]	211	1			T4	3		T31	7		T63	5
all_values[6]	auto[0]	auto[0]	2066445	1			T2	194		T3	4327		T4	589
all_values[6]	auto[0]	auto[1]	210	1			T4	5		T31	2		T63	6
all_values[6]	auto[1]	auto[0]	565	1			T4	1		T31	9		T63	5
all_values[6]	auto[1]	auto[1]	221	1			T4	1		T31	5		T63	1
all_values[7]	auto[0]	auto[0]	1943953	1			T2	194		T3	4327		T4	589
all_values[7]	auto[0]	auto[1]	213	1			T4	4		T31	4		T63	3
all_values[7]	auto[1]	auto[0]	123073	1			T4	3		T31	3		T63	7
all_values[7]	auto[1]	auto[1]	202	1			T31	4		T63	7		T15	2