Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	28492	1			T3	89		T4	543		T7	265
auto[SpiFlashAddrCfg]	6839	1			T3	38		T4	47		T7	72
auto[SpiFlashAddr3b]	8197	1			T3	58		T4	63		T7	65
auto[SpiFlashAddr4b]	6876	1			T3	26		T4	62		T7	39

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28949

1

T3

113

T4

412

T7

212

auto[1]

21455

1

T3

98

T4

303

T7

229

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26258

1

T3

95

T4

258

T7

296

auto[1]

24146

1

T3

116

T4

457

T7

145

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	32576	1			T3	111		T4	582		T7	280
values[1]	943	1			T3	3		T4	12		T7	6
values[2]	1334	1			T3	3		T4	7		T7	11
values[3]	1340	1			T3	4		T4	15		T7	7
values[4]	1271	1			T3	12		T4	8		T7	13
values[5]	1237	1			T3	11		T4	10		T7	10
values[6]	1237	1			T3	8		T4	4		T7	24
values[7]	1356	1			T3	10		T4	10		T7	18
values[8]	9110	1			T3	49		T4	67		T7	72

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25825

1

T3

211

T4

30

T7

441

auto[1]

24579

1

T4

685

T12

3

T14

597

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

47598

1

T3

194

T4

691

T7

427

write

2806

1

T3

17

T4

24

T7

14

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

17223

1

T3

82

T4

132

T7

148

valids[0x1]

33181

1

T3

129

T4

583

T7

293

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1415	1			T3	6		T4	9		T7	7
internal_process_ops[0x5a]	1475	1			T3	12		T4	13		T7	10
internal_process_ops[0x05]	16012	1			T3	34		T4	432		T7	173
internal_process_ops[0x35]	1397	1			T3	9		T4	23		T7	7
internal_process_ops[0x15]	1506	1			T3	4		T4	15		T7	13
internal_process_ops[0x03]	905	1			T3	2		T4	6		T7	11
internal_process_ops[0x0b]	990	1			T3	11		T4	2		T7	7
internal_process_ops[0x3b]	927	1			T3	5		T4	2		T7	11
internal_process_ops[0x6b]	931	1			T3	7		T4	4		T7	7
internal_process_ops[0xbb]	1009	1			T3	9		T4	5		T7	9
internal_process_ops[0xeb]	962	1			T3	9		T4	4		T7	15

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49022

1

T3

201

T4

701

T7

432

auto[1]

1382

1

T3

10

T4

14

T7

9

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48433

1

T3

202

T4

698

T7

429

auto[1]

1971

1

T3

9

T4

17

T7

12

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8493

1

T3

63

T4

8

T7

114

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4716

1

T3

26

T4

11

T7

148

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1857

1

T3

9

T4

3

T7

45

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1695

1

T3

24

T4

1

T7

21

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2371

1

T3

28

T7

25

T8

11

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1918

1

T3

25

T4

4

T7

37

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1867

1

T3

7

T4

2

T7

17

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1621

1

T3

12

T7

20

T8

12

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

74

1

T7

3

T32

1

T57

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

75

1

T32

1

T39

1

T25

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

69

1

T32

3

T39

2

T25

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

81

1

T41

2

T57

1

T167

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

91

1

T7

1

T89

2

T39

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

66

1

T7

2

T32

1

T39

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

103

1

T3

1

T8

3

T32

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

89

1

T3

4

T7

3

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

102

1

T3

1

T7

1

T9

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

64

1

T3

2

T7

2

T25

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

64

1

T3

2

T32

2

T25

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

81

1

T8

1

T32

2

T25

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

84

1

T4

1

T32

1

T168

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

75

1

T3

3

T7

2

T32

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

87

1

T3

3

T32

1

T39

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

82

1

T3

1

T8

1

T39

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8622

1

T4

310

T14

106

T49

49

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6000

1

T4

209

T14

331

T49

14

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1294

1

T4

17

T12

2

T14

23

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1259

1

T4

24

T14

15

T49

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1683

1

T4

32

T14

26

T49

18

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1554

1

T4

23

T14

24

T49

20

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1405

1

T4

24

T12

1

T14

29

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1243

1

T4

23

T14

25

T49

12

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

86

1

T4

3

T14

1

T26

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

80

1

T14

1

T49

1

T60

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

99

1

T14

3

T49

1

T51

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

97

1

T4

2

T26

1

T17

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

99

1

T4

1

T14

1

T49

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

94

1

T14

1

T60

1

T169

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

101

1

T4

1

T14

1

T51

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

91

1

T14

3

T51

2

T15

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

70

1

T18

1

T170

1

T171

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

94

1

T4

3

T14

4

T51

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

104

1

T14

1

T49

4

T51

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

92

1

T4

1

T51

2

T60

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

91

1

T4

3

T51

1

T60

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

112

1

T4

5

T14

1

T51

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

100

1

T4

1

T15

1

T26

6

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

109

1

T4

3

T14

1

T51

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3283	1			T3	29		T4	4		T7	50
auto[0]	values[0]	valids[0x1]	12318	1			T3	82		T4	19		T7	230
auto[0]	values[1]	valids[0x1]	486	1			T3	3		T7	6		T8	4
auto[0]	values[2]	valids[0x0]	478	1			T3	2		T7	9		T8	2
auto[0]	values[2]	valids[0x1]	304	1			T3	1		T7	2		T8	1
auto[0]	values[3]	valids[0x0]	499	1			T3	3		T4	1		T7	7
auto[0]	values[3]	valids[0x1]	305	1			T3	1		T32	5		T172	2
auto[0]	values[4]	valids[0x0]	442	1			T3	7		T4	2		T7	10
auto[0]	values[4]	valids[0x1]	265	1			T3	5		T7	3		T8	1
auto[0]	values[5]	valids[0x0]	465	1			T3	11		T7	8		T8	6
auto[0]	values[5]	valids[0x1]	276	1			T7	2		T8	2		T32	1
auto[0]	values[6]	valids[0x0]	507	1			T3	1		T7	12		T8	2
auto[0]	values[6]	valids[0x1]	227	1			T3	7		T7	12		T39	1
auto[0]	values[7]	valids[0x0]	498	1			T3	3		T7	9		T8	1
auto[0]	values[7]	valids[0x1]	284	1			T3	7		T7	9		T32	2
auto[0]	values[8]	valids[0x0]	3270	1			T3	26		T4	2		T7	43
auto[0]	values[8]	valids[0x1]	1918	1			T3	23		T4	2		T7	29
auto[1]	values[0]	valids[0x0]	3577	1			T4	52		T14	53		T49	36
auto[1]	values[0]	valids[0x1]	13398	1			T4	507		T14	414		T49	42
auto[1]	values[1]	valids[0x1]	457	1			T4	12		T14	11		T49	7
auto[1]	values[2]	valids[0x0]	336	1			T4	5		T14	4		T49	2
auto[1]	values[2]	valids[0x1]	216	1			T4	2		T14	6		T49	2
auto[1]	values[3]	valids[0x0]	298	1			T4	7		T14	4		T49	2
auto[1]	values[3]	valids[0x1]	238	1			T4	7		T14	2		T49	3
auto[1]	values[4]	valids[0x0]	358	1			T4	4		T12	1		T14	4
auto[1]	values[4]	valids[0x1]	206	1			T4	2		T14	2		T51	3
auto[1]	values[5]	valids[0x0]	309	1			T4	6		T14	2		T51	1
auto[1]	values[5]	valids[0x1]	187	1			T4	4		T14	4		T49	3
auto[1]	values[6]	valids[0x0]	311	1			T4	3		T14	10		T49	7
auto[1]	values[6]	valids[0x1]	192	1			T4	1		T14	4		T49	1
auto[1]	values[7]	valids[0x0]	333	1			T4	7		T14	7		T49	8
auto[1]	values[7]	valids[0x1]	241	1			T4	3		T14	8		T49	1
auto[1]	values[8]	valids[0x0]	2259	1			T4	39		T12	2		T14	43
auto[1]	values[8]	valids[0x1]	1663	1			T4	24		T14	19		T49	23