Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3153204

1

T3

11506

T4

25813

T7

19808

auto[1]

23823

1

T3

31

T4

415

T7

161

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1016222

1

T3

46

T4

91

T7

78

auto[1]

2160805

1

T3

11491

T4

26137

T7

19891

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	548197	1			T3	1		T4	698		T7	786
auto[524288:1048575]	352498	1			T3	4818		T4	2853		T7	5639
auto[1048576:1572863]	368567	1			T3	536		T4	2944		T7	2352
auto[1572864:2097151]	402335	1			T3	5633		T4	9015		T7	4352
auto[2097152:2621439]	366408	1			T3	273		T4	4739		T8	3005
auto[2621440:3145727]	416634	1			T3	16		T4	1774		T7	1023
auto[3145728:3670015]	343926	1			T4	1702		T7	3474		T8	258
auto[3670016:4194303]	378462	1			T3	260		T4	2503		T7	2343

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2193395

1

T3

11537

T4

26226

T7

19960

auto[1]

983632

1

T4

2

T7

9

T8

5

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2768754

1

T3

8140

T4

23697

T7

15686

auto[1]

408273

1

T3

3397

T4

2531

T7

4283

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	162270	1			T4	4		T7	7		T8	12
auto[0]	auto[0]	auto[0:524287]	auto[1]	338176	1			T4	256		T7	767		T8	4998
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	108796	1			T3	3		T4	6		T7	8
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	190696	1			T3	4810		T4	2805		T7	5582
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	117040	1			T3	4		T4	12		T7	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	201560	1			T3	130		T4	2559		T7	1537
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	101573	1			T3	6		T4	18		T7	13
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	229819	1			T3	2893		T4	7558		T7	4326
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	117723	1			T3	2		T4	12		T8	10
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	190341	1			T3	5		T4	4099		T8	2983
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	143817	1			T3	2		T4	7		T7	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	214762	1			T3	4		T4	1767		T7	1019
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	103518	1			T4	2		T7	5		T8	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	191941	1			T4	1699		T7	1		T8	256
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	148171	1			T3	4		T4	5		T7	6
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	189547	1			T3	256		T4	2485		T7	2318
auto[0]	auto[1]	auto[0:524287]	auto[0]	2953	1			T3	1		T14	1		T51	9
auto[0]	auto[1]	auto[0:524287]	auto[1]	39614	1			T4	438		T14	5		T32	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	600	1			T3	2		T4	4		T7	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	50105	1			T7	1		T8	2		T49	128
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	609	1			T3	7		T4	1		T7	11
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	46276	1			T3	386		T4	256		T7	729
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	792	1			T3	4		T7	1		T14	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	67776	1			T3	2726		T4	1303		T14	128
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	2249	1			T3	2		T4	2		T14	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	53558	1			T3	259		T4	514		T51	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1517	1			T14	4		T25	3		T28	7
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	53589	1			T14	4497		T25	257		T28	1816
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	506	1			T4	1		T7	4		T14	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	44848	1			T7	3462		T14	256		T51	256
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	407	1			T8	1		T14	2		T32	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	38055	1			T39	2		T26	1354		T28	4
auto[1]	auto[0]	auto[0:524287]	auto[0]	535	1			T7	2		T8	2		T50	8
auto[1]	auto[0]	auto[0:524287]	auto[1]	2713	1			T7	10		T8	33		T50	167
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	375	1			T3	1		T4	1		T7	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1302	1			T3	2		T4	37		T7	31
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	351	1			T3	2		T4	3		T7	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2303	1			T3	2		T4	113		T7	12
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	390	1			T3	1		T4	6		T7	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1685	1			T3	3		T4	130		T7	11
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	286	1			T4	4		T8	1		T49	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1641	1			T4	96		T8	11		T51	256
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	329	1			T3	2		T14	3		T51	7
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2337	1			T3	8		T14	35		T32	11
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	349	1			T7	1		T14	3		T49	23
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2402	1			T7	1		T14	136		T51	135
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	349	1			T4	2		T7	1		T14	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1657	1			T4	11		T7	18		T14	73
auto[1]	auto[1]	auto[0:524287]	auto[0]	159	1			T14	1		T32	1		T25	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	1777	1			T14	12		T32	26		T78	28
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	85	1			T7	1		T8	2		T49	4
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	539	1			T7	11		T8	51		T43	14
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	77	1			T3	2		T7	4		T26	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	351	1			T3	3		T7	55		T26	38
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	72	1			T49	2		T28	1		T170	6
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	228	1			T28	5		T22	8		T298	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	109	1			T3	1		T4	1		T49	8
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	501	1			T3	4		T4	11		T49	128
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	81	1			T14	2		T25	1		T28	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	202	1			T14	20		T25	1		T28	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	81	1			T28	1		T57	1		T78	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	281	1			T28	2		T57	37		T78	48
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	53	1			T39	2		T28	1		T78	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	223	1			T39	2		T28	12		T78	9

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1772148	1			T3	8119		T4	23293		T7	15594
auto[0]	auto[0]	auto[1]	977602	1			T4	1		T7	2		T8	1
auto[0]	auto[1]	auto[0]	398061	1			T3	3387		T4	2519		T7	4208
auto[0]	auto[1]	auto[1]	5393	1			T7	4		T8	1		T14	2
auto[1]	auto[0]	auto[0]	18480	1			T3	21		T4	402		T7	88
auto[1]	auto[0]	auto[1]	524	1			T4	1		T7	2		T8	2
auto[1]	auto[1]	auto[0]	4706	1			T3	10		T4	12		T7	70
auto[1]	auto[1]	auto[1]	113	1			T7	1		T8	1		T49	1