Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2067441	1			T2	194		T3	4327		T4	596
all_pins[1]	2067441	1			T2	194		T3	4327		T4	596
all_pins[2]	2067441	1			T2	194		T3	4327		T4	596
all_pins[3]	2067441	1			T2	194		T3	4327		T4	596
all_pins[4]	2067441	1			T2	194		T3	4327		T4	596
all_pins[5]	2067441	1			T2	194		T3	4327		T4	596
all_pins[6]	2067441	1			T2	194		T3	4327		T4	596
all_pins[7]	2067441	1			T2	194		T3	4327		T4	596

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	16536126	1			T2	1552		T3	34616		T4	4683
values[0x1]	3402	1			T4	85		T31	43		T63	20
transitions[0x0=>0x1]	2918	1			T4	64		T31	28		T63	17
transitions[0x1=>0x0]	2931	1			T4	64		T31	28		T63	17

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2066709	1			T2	194		T3	4327		T4	577
all_pins[0]	values[0x1]	732	1			T4	19		T31	9		T15	1
all_pins[0]	transitions[0x0=>0x1]	615	1			T4	3		T31	6		T15	1
all_pins[0]	transitions[0x1=>0x0]	337	1			T4	6		T63	1		T15	2
all_pins[1]	values[0x0]	2066987	1			T2	194		T3	4327		T4	574
all_pins[1]	values[0x1]	454	1			T4	22		T31	3		T63	1
all_pins[1]	transitions[0x0=>0x1]	391	1			T4	19		T31	2		T63	1
all_pins[1]	transitions[0x1=>0x0]	215	1			T31	4		T63	1		T17	29
all_pins[2]	values[0x0]	2067163	1			T2	194		T3	4327		T4	593
all_pins[2]	values[0x1]	278	1			T4	3		T31	5		T63	1
all_pins[2]	transitions[0x0=>0x1]	225	1			T4	2		T31	4		T63	1
all_pins[2]	transitions[0x1=>0x0]	158	1			T31	1		T63	3		T16	4
all_pins[3]	values[0x0]	2067230	1			T2	194		T3	4327		T4	595
all_pins[3]	values[0x1]	211	1			T4	1		T31	2		T63	3
all_pins[3]	transitions[0x0=>0x1]	158	1			T4	1		T31	2		T63	2
all_pins[3]	transitions[0x1=>0x0]	152	1			T4	1		T31	8		T63	1
all_pins[4]	values[0x0]	2067236	1			T2	194		T3	4327		T4	595
all_pins[4]	values[0x1]	205	1			T4	1		T31	8		T63	2
all_pins[4]	transitions[0x0=>0x1]	158	1			T31	4		T63	1		T16	4
all_pins[4]	transitions[0x1=>0x0]	810	1			T4	37		T31	3		T63	4
all_pins[5]	values[0x0]	2066584	1			T2	194		T3	4327		T4	558
all_pins[5]	values[0x1]	857	1			T4	38		T31	7		T63	5
all_pins[5]	transitions[0x0=>0x1]	813	1			T4	38		T31	5		T63	4
all_pins[5]	transitions[0x1=>0x0]	419	1			T4	1		T31	3		T16	4
all_pins[6]	values[0x0]	2066978	1			T2	194		T3	4327		T4	595
all_pins[6]	values[0x1]	463	1			T4	1		T31	5		T63	1
all_pins[6]	transitions[0x0=>0x1]	414	1			T4	1		T31	4		T63	1
all_pins[6]	transitions[0x1=>0x0]	153	1			T31	3		T63	7		T15	2
all_pins[7]	values[0x0]	2067239	1			T2	194		T3	4327		T4	596
all_pins[7]	values[0x1]	202	1			T31	4		T63	7		T15	2
all_pins[7]	transitions[0x0=>0x1]	144	1			T31	1		T63	7		T15	1
all_pins[7]	transitions[0x1=>0x0]	687	1			T4	19		T31	6		T17	1