Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15219

1

T3

113

T4

14

T7

212

auto[1]

10606

1

T3

98

T4

16

T7

229

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3378	1			T7	40		T32	98		T39	87
values[1]	2997	1			T3	78		T4	30		T7	170
values[2]	3498	1			T3	23		T8	112		T50	199
values[3]	3080	1			T3	20		T7	40		T8	71
values[4]	3150	1			T7	20		T32	69		T57	40
values[5]	3256	1			T7	87		T39	40		T56	20
values[6]	3471	1			T3	70		T7	62		T9	8
values[7]	2995	1			T3	20		T7	22		T32	67

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2897	1			T3	23		T4	30		T7	107
values[1]	3348	1			T3	34		T7	40		T172	18
values[2]	3022	1			T7	22		T8	51		T9	8
values[3]	3038	1			T7	62		T8	36		T32	69
values[4]	3436	1			T3	23		T7	78		T8	76
values[5]	2758	1			T3	44		T7	40		T88	10
values[6]	4094	1			T3	64		T7	40		T8	20
values[7]	3232	1			T3	23		T7	52		T8	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	194	1			T39	10		T135	4		T22	13
auto[0]	values[0]	values[1]	211	1			T7	8		T198	26		T195	9
auto[0]	values[0]	values[2]	315	1			T134	2		T299	95		T181	12
auto[0]	values[0]	values[3]	187	1			T40	76		T203	8		T224	11
auto[0]	values[0]	values[4]	264	1			T187	10		T211	10		T300	14
auto[0]	values[0]	values[5]	253	1			T32	68		T39	18		T185	12
auto[0]	values[0]	values[6]	280	1			T7	16		T32	15		T195	8
auto[0]	values[0]	values[7]	214	1			T39	23		T24	14		T168	19
auto[0]	values[1]	values[0]	213	1			T4	14		T32	19		T195	9
auto[0]	values[1]	values[1]	147	1			T3	24		T7	12		T28	12
auto[0]	values[1]	values[2]	134	1			T39	17		T22	13		T301	10
auto[0]	values[1]	values[3]	175	1			T28	6		T184	13		T224	12
auto[0]	values[1]	values[4]	366	1			T7	39		T25	9		T131	18
auto[0]	values[1]	values[5]	174	1			T3	8		T302	4		T202	12
auto[0]	values[1]	values[6]	252	1			T3	12		T7	12		T25	40
auto[0]	values[1]	values[7]	190	1			T7	12		T8	11		T89	16
auto[0]	values[2]	values[0]	189	1			T57	24		T75	10		T184	11
auto[0]	values[2]	values[1]	304	1			T25	13		T28	43		T57	120
auto[0]	values[2]	values[2]	237	1			T77	18		T173	39		T203	9
auto[0]	values[2]	values[3]	263	1			T8	9		T57	78		T132	7
auto[0]	values[2]	values[4]	191	1			T8	8		T40	27		T181	14
auto[0]	values[2]	values[5]	250	1			T191	10		T168	53		T197	16
auto[0]	values[2]	values[6]	587	1			T50	199		T178	241		T40	14
auto[0]	values[2]	values[7]	347	1			T3	16		T303	14		T22	74
auto[0]	values[3]	values[0]	213	1			T188	4		T178	12		T184	20
auto[0]	values[3]	values[1]	155	1			T28	10		T181	13		T304	16
auto[0]	values[3]	values[2]	189	1			T8	6		T212	16		T25	8
auto[0]	values[3]	values[3]	140	1			T39	14		T57	13		T174	6
auto[0]	values[3]	values[4]	231	1			T114	14		T39	13		T193	4
auto[0]	values[3]	values[5]	300	1			T7	26		T32	17		T25	14
auto[0]	values[3]	values[6]	308	1			T3	9		T8	13		T57	20
auto[0]	values[3]	values[7]	253	1			T39	15		T72	4		T168	12
auto[0]	values[4]	values[0]	151	1			T132	13		T43	17		T211	6
auto[0]	values[4]	values[1]	254	1			T40	13		T305	58		T306	28
auto[0]	values[4]	values[2]	314	1			T32	17		T223	24		T177	6
auto[0]	values[4]	values[3]	245	1			T7	13		T32	10		T184	9
auto[0]	values[4]	values[4]	213	1			T206	10		T168	8		T195	19
auto[0]	values[4]	values[5]	189	1			T32	9		T57	17		T307	2
auto[0]	values[4]	values[6]	345	1			T187	34		T178	15		T22	35
auto[0]	values[4]	values[7]	161	1			T57	13		T199	10		T40	11
auto[0]	values[5]	values[0]	248	1			T7	16		T308	2		T267	13
auto[0]	values[5]	values[1]	293	1			T28	10		T196	14		T187	11
auto[0]	values[5]	values[2]	193	1			T187	11		T40	11		T43	26
auto[0]	values[5]	values[3]	216	1			T173	23		T203	8		T220	9
auto[0]	values[5]	values[4]	274	1			T39	23		T28	12		T187	63
auto[0]	values[5]	values[5]	260	1			T215	6		T168	11		T22	11
auto[0]	values[5]	values[6]	185	1			T28	8		T200	4		T184	8
auto[0]	values[5]	values[7]	211	1			T207	18		T175	6		T176	6
auto[0]	values[6]	values[0]	227	1			T3	11		T7	8		T10	4
auto[0]	values[6]	values[1]	398	1			T57	39		T178	14		T40	10
auto[0]	values[6]	values[2]	147	1			T9	8		T283	14		T43	14
auto[0]	values[6]	values[3]	285	1			T7	33		T185	15		T22	8
auto[0]	values[6]	values[4]	192	1			T3	13		T174	11		T210	6
auto[0]	values[6]	values[5]	144	1			T3	8		T88	10		T236	31
auto[0]	values[6]	values[6]	197	1			T184	10		T203	10		T309	48
auto[0]	values[6]	values[7]	421	1			T32	29		T213	22		T132	9
auto[0]	values[7]	values[0]	174	1			T178	10		T181	14		T232	13
auto[0]	values[7]	values[1]	168	1			T172	18		T310	16		T181	12
auto[0]	values[7]	values[2]	171	1			T7	17		T28	7		T181	12
auto[0]	values[7]	values[3]	183	1			T32	40		T187	9		T178	11
auto[0]	values[7]	values[4]	274	1			T32	9		T28	13		T132	10
auto[0]	values[7]	values[5]	175	1			T168	18		T311	12		T181	8
auto[0]	values[7]	values[6]	345	1			T3	12		T22	9		T312	8
auto[0]	values[7]	values[7]	240	1			T25	14		T29	4		T178	22
auto[1]	values[0]	values[0]	229	1			T39	10		T22	99		T182	13
auto[1]	values[0]	values[1]	153	1			T7	12		T195	26		T173	52
auto[1]	values[0]	values[2]	137	1			T181	8		T286	51		T313	8
auto[1]	values[0]	values[3]	134	1			T40	27		T203	12		T224	12
auto[1]	values[0]	values[4]	197	1			T187	44		T211	10		T225	8
auto[1]	values[0]	values[5]	142	1			T32	10		T39	5		T185	8
auto[1]	values[0]	values[6]	231	1			T7	4		T32	5		T195	37
auto[1]	values[0]	values[7]	237	1			T39	21		T168	5		T184	4
auto[1]	values[1]	values[0]	143	1			T4	16		T32	7		T195	11
auto[1]	values[1]	values[1]	122	1			T3	10		T7	8		T28	11
auto[1]	values[1]	values[2]	165	1			T39	7		T22	58		T235	16
auto[1]	values[1]	values[3]	135	1			T28	39		T184	7		T224	8
auto[1]	values[1]	values[4]	226	1			T7	39		T25	14		T184	35
auto[1]	values[1]	values[5]	135	1			T3	12		T220	9		T224	15
auto[1]	values[1]	values[6]	182	1			T3	12		T7	8		T25	6
auto[1]	values[1]	values[7]	238	1			T7	40		T8	9		T168	118
auto[1]	values[2]	values[0]	101	1			T57	6		T184	9		T40	8
auto[1]	values[2]	values[1]	174	1			T25	7		T28	31		T57	6
auto[1]	values[2]	values[2]	130	1			T173	7		T203	11		T227	12
auto[1]	values[2]	values[3]	156	1			T8	27		T57	14		T132	15
auto[1]	values[2]	values[4]	166	1			T8	68		T40	9		T181	6
auto[1]	values[2]	values[5]	111	1			T168	7		T195	11		T178	3
auto[1]	values[2]	values[6]	94	1			T178	5		T40	6		T43	7
auto[1]	values[2]	values[7]	198	1			T3	7		T22	71		T314	4
auto[1]	values[3]	values[0]	168	1			T41	18		T178	8		T184	5
auto[1]	values[3]	values[1]	133	1			T28	10		T133	6		T181	7
auto[1]	values[3]	values[2]	200	1			T8	45		T25	24		T315	20
auto[1]	values[3]	values[3]	135	1			T39	6		T57	7		T174	20
auto[1]	values[3]	values[4]	220	1			T39	7		T57	8		T200	22
auto[1]	values[3]	values[5]	166	1			T7	14		T32	5		T25	14
auto[1]	values[3]	values[6]	196	1			T3	11		T8	7		T57	31
auto[1]	values[3]	values[7]	73	1			T39	10		T168	8		T185	8
auto[1]	values[4]	values[0]	66	1			T132	8		T43	7		T211	14
auto[1]	values[4]	values[1]	191	1			T216	10		T40	7		T316	3
auto[1]	values[4]	values[2]	274	1			T32	8		T178	149		T22	10
auto[1]	values[4]	values[3]	179	1			T7	7		T32	12		T184	11
auto[1]	values[4]	values[4]	133	1			T168	12		T195	21		T178	8
auto[1]	values[4]	values[5]	123	1			T32	13		T57	3		T69	22
auto[1]	values[4]	values[6]	220	1			T187	4		T178	5		T22	25
auto[1]	values[4]	values[7]	92	1			T57	7		T40	10		T220	5
auto[1]	values[5]	values[0]	264	1			T7	71		T267	7		T286	4
auto[1]	values[5]	values[1]	171	1			T28	10		T187	9		T195	4
auto[1]	values[5]	values[2]	156	1			T56	20		T187	9		T40	9
auto[1]	values[5]	values[3]	195	1			T167	20		T173	3		T203	12
auto[1]	values[5]	values[4]	135	1			T39	17		T28	12		T187	10
auto[1]	values[5]	values[5]	142	1			T215	24		T168	9		T22	9
auto[1]	values[5]	values[6]	156	1			T28	18		T200	16		T184	25
auto[1]	values[5]	values[7]	157	1			T176	17		T267	12		T161	8
auto[1]	values[6]	values[0]	155	1			T3	12		T7	12		T32	12
auto[1]	values[6]	values[1]	344	1			T57	10		T178	9		T40	10
auto[1]	values[6]	values[2]	100	1			T43	6		T236	13		T313	22
auto[1]	values[6]	values[3]	238	1			T7	9		T185	16		T22	31
auto[1]	values[6]	values[4]	181	1			T3	10		T174	10		T132	6
auto[1]	values[6]	values[5]	93	1			T3	16		T236	9		T240	8
auto[1]	values[6]	values[6]	237	1			T184	59		T203	10		T161	8
auto[1]	values[6]	values[7]	112	1			T32	8		T132	11		T187	12
auto[1]	values[7]	values[0]	162	1			T178	10		T181	6		T232	7
auto[1]	values[7]	values[1]	130	1			T181	8		T182	11		T267	9
auto[1]	values[7]	values[2]	160	1			T7	5		T28	13		T209	14
auto[1]	values[7]	values[3]	172	1			T32	7		T113	6		T187	11
auto[1]	values[7]	values[4]	173	1			T32	11		T28	8		T265	18
auto[1]	values[7]	values[5]	101	1			T168	8		T181	12		T211	8
auto[1]	values[7]	values[6]	279	1			T3	8		T22	11		T291	5
auto[1]	values[7]	values[7]	88	1			T25	8		T178	36		T181	5