Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12954

1

T3

91

T4

19

T7

166

auto[1]

37450

1

T3

120

T4

696

T7

275

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	1082	1			T3	3		T4	8		T7	12
auto[4:7]	18883	1			T3	47		T4	452		T7	196
auto[8:11]	1207	1			T3	11		T4	3		T7	9
auto[12:15]	251	1			T3	3		T7	3		T14	3
auto[16:19]	287	1			T7	7		T8	2		T9	2
auto[20:23]	1744	1			T3	4		T4	19		T7	13
auto[24:27]	319	1			T3	2		T4	3		T7	2
auto[28:31]	284	1			T3	3		T4	2		T7	3
auto[32:35]	273	1			T4	1		T8	1		T14	4
auto[36:39]	276	1			T3	1		T7	2		T50	2
auto[40:43]	286	1			T4	3		T7	3		T14	1
auto[44:47]	332	1			T4	2		T7	5		T14	3
auto[48:51]	233	1			T3	1		T7	2		T14	1
auto[52:55]	1592	1			T3	10		T4	26		T7	8
auto[56:59]	1152	1			T3	5		T4	3		T7	13
auto[60:63]	307	1			T4	5		T7	2		T14	2
auto[64:67]	303	1			T4	3		T7	1		T8	1
auto[68:71]	268	1			T3	4		T4	1		T7	2
auto[72:75]	278	1			T3	2		T4	4		T7	2
auto[76:79]	290	1			T3	5		T4	2		T7	2
auto[80:83]	288	1			T4	2		T7	4		T14	4
auto[84:87]	286	1			T3	1		T4	4		T7	1
auto[88:91]	1654	1			T3	12		T4	17		T7	10
auto[92:95]	285	1			T3	1		T4	4		T14	1
auto[96:99]	284	1			T4	6		T7	2		T14	4
auto[100:103]	273	1			T3	2		T14	1		T49	2
auto[104:107]	1159	1			T3	8		T4	6		T7	9
auto[108:111]	303	1			T4	1		T7	3		T8	1
auto[112:115]	247	1			T3	1		T4	6		T7	5
auto[116:119]	283	1			T3	2		T49	1		T51	3
auto[120:123]	280	1			T3	1		T4	3		T8	2
auto[124:127]	298	1			T4	3		T8	2		T14	6
auto[128:131]	261	1			T3	1		T4	2		T7	3
auto[132:135]	222	1			T3	1		T4	2		T14	2
auto[136:139]	277	1			T3	2		T4	4		T7	1
auto[140:143]	261	1			T3	1		T4	3		T7	6
auto[144:147]	293	1			T3	3		T4	1		T7	1
auto[148:151]	289	1			T3	1		T4	7		T7	2
auto[152:155]	295	1			T4	1		T7	5		T8	1
auto[156:159]	1631	1			T3	6		T4	9		T7	8
auto[160:163]	298	1			T4	1		T8	2		T14	7
auto[164:167]	328	1			T3	1		T4	4		T7	2
auto[168:171]	327	1			T3	4		T4	2		T7	2
auto[172:175]	282	1			T4	3		T7	5		T8	1
auto[176:179]	309	1			T3	1		T4	4		T7	2
auto[180:183]	1577	1			T3	9		T4	20		T7	9
auto[184:187]	1236	1			T3	11		T4	6		T7	11
auto[188:191]	320	1			T3	1		T4	3		T7	2
auto[192:195]	292	1			T3	1		T4	3		T14	1
auto[196:199]	310	1			T3	5		T4	1		T7	1
auto[200:203]	341	1			T3	6		T4	1		T7	1
auto[204:207]	300	1			T4	1		T7	3		T8	3
auto[208:211]	311	1			T4	3		T8	2		T14	4
auto[212:215]	279	1			T3	1		T7	4		T8	1
auto[216:219]	304	1			T4	5		T7	2		T8	1
auto[220:223]	283	1			T3	2		T4	5		T7	1
auto[224:227]	291	1			T4	2		T7	3		T14	2
auto[228:231]	319	1			T3	2		T4	3		T7	2
auto[232:235]	2474	1			T3	12		T4	16		T7	31
auto[236:239]	296	1			T3	2		T7	8		T8	2
auto[240:243]	284	1			T3	1		T4	5		T7	3
auto[244:247]	278	1			T3	1		T4	3		T8	3
auto[248:251]	255	1			T3	1		T4	5		T8	1
auto[252:255]	294	1			T3	6		T4	1		T7	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	378	1			T3	2		T7	3		T8	1
auto[0:3]	auto[1]	704	1			T3	1		T4	8		T7	9
auto[4:7]	auto[0]	4521	1			T3	14		T4	11		T7	55
auto[4:7]	auto[1]	14362	1			T3	33		T4	441		T7	141
auto[8:11]	auto[0]	449	1			T3	9		T7	2		T8	1
auto[8:11]	auto[1]	758	1			T3	2		T4	3		T7	7
auto[12:15]	auto[0]	60	1			T57	1		T205	1		T187	1
auto[12:15]	auto[1]	191	1			T3	3		T7	3		T14	3
auto[16:19]	auto[0]	67	1			T7	2		T8	2		T9	1
auto[16:19]	auto[1]	220	1			T7	5		T9	1		T14	1
auto[20:23]	auto[0]	417	1			T3	3		T7	6		T8	2
auto[20:23]	auto[1]	1327	1			T3	1		T4	19		T7	7
auto[24:27]	auto[0]	75	1			T3	2		T7	2		T50	2
auto[24:27]	auto[1]	244	1			T4	3		T14	4		T50	2
auto[28:31]	auto[0]	68	1			T3	2		T7	1		T56	2
auto[28:31]	auto[1]	216	1			T3	1		T4	2		T7	2
auto[32:35]	auto[0]	62	1			T8	1		T28	1		T187	2
auto[32:35]	auto[1]	211	1			T4	1		T14	4		T51	2
auto[36:39]	auto[0]	69	1			T7	1		T50	1		T32	1
auto[36:39]	auto[1]	207	1			T3	1		T7	1		T50	1
auto[40:43]	auto[0]	81	1			T39	3		T25	1		T28	1
auto[40:43]	auto[1]	205	1			T4	3		T7	3		T14	1
auto[44:47]	auto[0]	104	1			T7	3		T32	2		T39	1
auto[44:47]	auto[1]	228	1			T4	2		T7	2		T14	3
auto[48:51]	auto[0]	70	1			T32	1		T178	1		T22	2
auto[48:51]	auto[1]	163	1			T3	1		T7	2		T14	1
auto[52:55]	auto[0]	388	1			T3	4		T7	3		T8	1
auto[52:55]	auto[1]	1204	1			T3	6		T4	26		T7	5
auto[56:59]	auto[0]	426	1			T3	1		T7	8		T8	4
auto[56:59]	auto[1]	726	1			T3	4		T4	3		T7	5
auto[60:63]	auto[0]	71	1			T4	2		T7	2		T32	2
auto[60:63]	auto[1]	236	1			T4	3		T14	2		T32	1
auto[64:67]	auto[0]	80	1			T7	1		T32	1		T39	2
auto[64:67]	auto[1]	223	1			T4	3		T8	1		T14	2
auto[68:71]	auto[0]	73	1			T7	2		T32	4		T39	3
auto[68:71]	auto[1]	195	1			T3	4		T4	1		T14	5
auto[72:75]	auto[0]	47	1			T3	1		T39	1		T56	1
auto[72:75]	auto[1]	231	1			T3	1		T4	4		T7	2
auto[76:79]	auto[0]	52	1			T3	2		T7	1		T32	3
auto[76:79]	auto[1]	238	1			T3	3		T4	2		T7	1
auto[80:83]	auto[0]	67	1			T7	3		T32	1		T57	2
auto[80:83]	auto[1]	221	1			T4	2		T7	1		T14	4
auto[84:87]	auto[0]	78	1			T3	1		T7	1		T8	1
auto[84:87]	auto[1]	208	1			T4	4		T49	1		T51	1
auto[88:91]	auto[0]	432	1			T3	10		T7	4		T89	1
auto[88:91]	auto[1]	1222	1			T3	2		T4	17		T7	6
auto[92:95]	auto[0]	68	1			T113	1		T25	1		T57	3
auto[92:95]	auto[1]	217	1			T3	1		T4	4		T14	1
auto[96:99]	auto[0]	54	1			T7	2		T89	1		T39	2
auto[96:99]	auto[1]	230	1			T4	6		T14	4		T49	2
auto[100:103]	auto[0]	75	1			T3	2		T39	3		T24	1
auto[100:103]	auto[1]	198	1			T14	1		T49	2		T51	3
auto[104:107]	auto[0]	393	1			T3	1		T4	1		T7	5
auto[104:107]	auto[1]	766	1			T3	7		T4	5		T7	4
auto[108:111]	auto[0]	72	1			T32	1		T25	1		T57	1
auto[108:111]	auto[1]	231	1			T4	1		T7	3		T8	1
auto[112:115]	auto[0]	50	1			T3	1		T7	1		T32	3
auto[112:115]	auto[1]	197	1			T4	6		T7	4		T14	3
auto[116:119]	auto[0]	51	1			T32	2		T28	2		T57	3
auto[116:119]	auto[1]	232	1			T3	2		T49	1		T51	3
auto[120:123]	auto[0]	74	1			T8	1		T25	1		T28	1
auto[120:123]	auto[1]	206	1			T3	1		T4	3		T8	1
auto[124:127]	auto[0]	63	1			T8	2		T50	1		T32	2
auto[124:127]	auto[1]	235	1			T4	3		T14	6		T50	1
auto[128:131]	auto[0]	56	1			T39	2		T207	1		T185	2
auto[128:131]	auto[1]	205	1			T3	1		T4	2		T7	3
auto[132:135]	auto[0]	49	1			T185	2		T187	1		T40	3
auto[132:135]	auto[1]	173	1			T3	1		T4	2		T14	2
auto[136:139]	auto[0]	59	1			T3	2		T32	3		T28	2
auto[136:139]	auto[1]	218	1			T4	4		T7	1		T14	5
auto[140:143]	auto[0]	70	1			T3	1		T7	3		T172	1
auto[140:143]	auto[1]	191	1			T4	3		T7	3		T14	1
auto[144:147]	auto[0]	68	1			T3	1		T212	1		T57	3
auto[144:147]	auto[1]	225	1			T3	2		T4	1		T7	1
auto[148:151]	auto[0]	71	1			T113	1		T39	1		T28	1
auto[148:151]	auto[1]	218	1			T3	1		T4	7		T7	2
auto[152:155]	auto[0]	72	1			T7	4		T8	1		T57	4
auto[152:155]	auto[1]	223	1			T4	1		T7	1		T14	7
auto[156:159]	auto[0]	435	1			T3	3		T4	1		T7	5
auto[156:159]	auto[1]	1196	1			T3	3		T4	8		T7	3
auto[160:163]	auto[0]	55	1			T32	1		T212	1		T57	1
auto[160:163]	auto[1]	243	1			T4	1		T8	2		T14	7
auto[164:167]	auto[0]	85	1			T3	1		T7	2		T32	1
auto[164:167]	auto[1]	243	1			T4	4		T51	3		T26	4
auto[168:171]	auto[0]	70	1			T3	2		T7	2		T56	2
auto[168:171]	auto[1]	257	1			T3	2		T4	2		T8	3
auto[172:175]	auto[0]	59	1			T7	4		T32	2		T215	1
auto[172:175]	auto[1]	223	1			T4	3		T7	1		T8	1
auto[176:179]	auto[0]	85	1			T3	1		T4	2		T7	1
auto[176:179]	auto[1]	224	1			T4	2		T7	1		T8	1
auto[180:183]	auto[0]	380	1			T3	7		T7	5		T8	1
auto[180:183]	auto[1]	1197	1			T3	2		T4	20		T7	4
auto[184:187]	auto[0]	422	1			T3	2		T7	4		T8	5
auto[184:187]	auto[1]	814	1			T3	9		T4	6		T7	7
auto[188:191]	auto[0]	68	1			T89	2		T25	4		T282	2
auto[188:191]	auto[1]	252	1			T3	1		T4	3		T7	2
auto[192:195]	auto[0]	76	1			T28	2		T57	4		T168	2
auto[192:195]	auto[1]	216	1			T3	1		T4	3		T14	1
auto[196:199]	auto[0]	63	1			T3	3		T7	1		T8	1
auto[196:199]	auto[1]	247	1			T3	2		T4	1		T14	4
auto[200:203]	auto[0]	80	1			T3	1		T7	1		T32	2
auto[200:203]	auto[1]	261	1			T3	5		T4	1		T14	3
auto[204:207]	auto[0]	68	1			T7	2		T8	2		T25	3
auto[204:207]	auto[1]	232	1			T4	1		T7	1		T8	1
auto[208:211]	auto[0]	69	1			T32	1		T39	1		T132	1
auto[208:211]	auto[1]	242	1			T4	3		T8	2		T14	4
auto[212:215]	auto[0]	70	1			T7	2		T8	1		T39	2
auto[212:215]	auto[1]	209	1			T3	1		T7	2		T49	4
auto[216:219]	auto[0]	69	1			T7	1		T32	1		T39	1
auto[216:219]	auto[1]	235	1			T4	5		T7	1		T8	1
auto[220:223]	auto[0]	79	1			T3	2		T7	1		T8	2
auto[220:223]	auto[1]	204	1			T4	5		T14	5		T49	2
auto[224:227]	auto[0]	70	1			T7	1		T32	1		T39	1
auto[224:227]	auto[1]	221	1			T4	2		T7	2		T14	2
auto[228:231]	auto[0]	69	1			T3	2		T4	1		T28	3
auto[228:231]	auto[1]	250	1			T4	2		T7	2		T14	4
auto[232:235]	auto[0]	744	1			T3	5		T4	1		T7	16
auto[232:235]	auto[1]	1730	1			T3	7		T4	15		T7	15
auto[236:239]	auto[0]	87	1			T3	2		T7	1		T8	2
auto[236:239]	auto[1]	209	1			T7	7		T49	1		T51	1
auto[240:243]	auto[0]	63	1			T7	2		T57	1		T69	1
auto[240:243]	auto[1]	221	1			T3	1		T4	5		T7	1
auto[244:247]	auto[0]	75	1			T8	3		T32	2		T28	1
auto[244:247]	auto[1]	203	1			T3	1		T4	3		T14	5
auto[248:251]	auto[0]	62	1			T3	1		T8	1		T32	1
auto[248:251]	auto[1]	193	1			T4	5		T14	1		T49	1
auto[252:255]	auto[0]	71	1			T8	1		T89	1		T172	1
auto[252:255]	auto[1]	223	1			T3	6		T4	1		T7	2