Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	351	1			T3	4		T7	3		T8	2
auto[ReadAddrCrossIntoMailbox]	252	1			T3	5		T7	11		T8	2
auto[ReadAddrCrossOutOfMailbox]	264	1			T3	1		T7	2		T8	2
auto[ReadAddrCrossAllMailbox]	184	1			T3	3		T7	3		T8	3
auto[ReadAddrOutsideMailbox]	3312	1			T3	30		T4	4		T7	41

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2136

1

T3

16

T4

1

T7

22

auto[1]

2227

1

T3

27

T4

3

T7

38

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	675	1			T3	2		T4	3		T7	11
read_ops[0x0b]	757	1			T3	11		T7	7		T8	2
read_ops[0x3b]	689	1			T3	5		T7	11		T8	6
read_ops[0x6b]	725	1			T3	7		T4	1		T7	7
read_ops[0xbb]	785	1			T3	9		T7	9		T8	7
read_ops[0xeb]	732	1			T3	9		T7	15		T8	8

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T7	1		T28	2		T302	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T39	1		T57	1		T302	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T7	1		T178	1		T22	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T7	1		T8	1		T185	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	14	1			T57	1		T317	1		T179	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T28	1		T22	2		T203	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T187	1		T220	1		T318	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T7	1		T185	1		T22	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	255	1			T3	2		T8	1		T50	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	270	1			T4	3		T7	7		T8	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T7	1		T32	1		T178	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T7	1		T168	1		T132	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T75	1		T22	1		T181	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T7	2		T32	1		T57	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T185	1		T22	1		T181	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T168	1		T132	1		T319	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T8	1		T32	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T28	1		T22	1		T224	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	279	1			T3	9		T7	1		T9	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T3	2		T7	2		T8	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T32	2		T28	2		T75	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T3	1		T28	1		T75	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T3	1		T39	1		T28	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T7	1		T32	2		T57	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T8	1		T32	1		T28	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T57	1		T174	1		T185	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T8	1		T57	1		T75	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T75	1		T320	1		T137	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	286	1			T7	6		T8	2		T10	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	237	1			T3	3		T7	4		T8	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T114	2		T178	1		T22	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T3	1		T32	1		T114	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T7	1		T185	1		T184	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T7	2		T39	1		T57	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T57	1		T178	2		T184	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T3	1		T200	1		T40	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T28	1		T43	1		T286	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T32	1		T178	1		T184	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	264	1			T3	1		T4	1		T7	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T3	4		T7	1		T8	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T114	1		T28	3		T217	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T3	1		T114	1		T168	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	11	1			T32	1		T39	1		T57	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T3	2		T168	1		T195	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T28	1		T57	4		T184	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T195	1		T22	1		T181	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T7	1		T195	1		T181	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T3	1		T8	1		T195	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	284	1			T7	1		T8	5		T89	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	314	1			T3	5		T7	7		T8	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T3	1		T8	1		T39	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T8	1		T302	1		T40	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T39	1		T168	1		T184	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T3	2		T7	3		T8	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T191	1		T184	1		T22	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T7	2		T8	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T3	2		T191	1		T75	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T7	1		T191	1		T75	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T7	6		T8	1		T50	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	277	1			T3	4		T7	3		T8	3