Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2695	1			T3	34		T28	63		T57	72
values[1]	3343	1			T7	94		T8	20		T9	8
values[2]	3585	1			T3	43		T7	39		T88	10
values[3]	3155	1			T3	24		T7	20		T32	47
values[4]	3305	1			T3	20		T4	30		T7	59
values[5]	3598	1			T3	47		T7	127		T8	56
values[6]	3067	1			T7	62		T8	127		T10	4
values[7]	3077	1			T3	43		T7	40		T32	42

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3981	1			T7	111		T8	76		T89	16
values[1]	3382	1			T3	20		T7	20		T9	8
values[2]	3235	1			T3	23		T8	20		T10	4
values[3]	2829	1			T3	48		T7	127		T32	63
values[4]	2900	1			T3	46		T7	60		T8	71
values[5]	3277	1			T7	20		T25	45		T57	113
values[6]	3253	1			T3	34		T7	39		T50	199
values[7]	2968	1			T3	40		T4	30		T7	64

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25212

1

T3

201

T4

30

T7

432

auto[1]

613

1

T3

10

T7

9

T8

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[7]]	[values[3]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	375	1			T57	72		T40	31		T173	26
auto[0]	values[0]	values[1]	443	1			T28	62		T174	23		T175	6
auto[0]	values[0]	values[2]	347	1			T168	20		T176	23		T177	6
auto[0]	values[0]	values[3]	270	1			T178	154		T179	23		T180	17
auto[0]	values[0]	values[4]	366	1			T40	19		T181	18		T182	22
auto[0]	values[0]	values[5]	338	1			T168	79		T183	11		T184	18
auto[0]	values[0]	values[6]	149	1			T3	34		T185	19		T178	20
auto[0]	values[0]	values[7]	337	1			T186	2		T40	19		T181	19
auto[0]	values[1]	values[0]	450	1			T7	51		T39	22		T57	46
auto[0]	values[1]	values[1]	611	1			T7	20		T9	8		T32	77
auto[0]	values[1]	values[2]	352	1			T8	20		T133	6		T135	4
auto[0]	values[1]	values[3]	241	1			T57	20		T131	18		T187	20
auto[0]	values[1]	values[4]	208	1			T188	4		T22	31		T189	6
auto[0]	values[1]	values[5]	509	1			T25	22		T187	71		T40	24
auto[0]	values[1]	values[6]	467	1			T50	199		T22	20		T40	20
auto[0]	values[1]	values[7]	428	1			T7	22		T185	18		T184	20
auto[0]	values[2]	values[0]	803	1			T7	39		T25	30		T190	12
auto[0]	values[2]	values[1]	407	1			T22	37		T40	20		T43	70
auto[0]	values[2]	values[2]	233	1			T32	22		T172	18		T191	10
auto[0]	values[2]	values[3]	376	1			T32	26		T178	19		T192	12
auto[0]	values[2]	values[4]	410	1			T3	23		T193	4		T28	20
auto[0]	values[2]	values[5]	361	1			T57	24		T194	22		T195	20
auto[0]	values[2]	values[6]	546	1			T77	18		T178	19		T40	21
auto[0]	values[2]	values[7]	352	1			T3	18		T88	10		T39	18
auto[0]	values[3]	values[0]	456	1			T39	25		T174	21		T132	20
auto[0]	values[3]	values[1]	260	1			T113	6		T39	23		T57	20
auto[0]	values[3]	values[2]	415	1			T196	14		T197	16		T132	20
auto[0]	values[3]	values[3]	494	1			T3	20		T198	26		T199	10
auto[0]	values[3]	values[4]	378	1			T32	45		T200	36		T173	20
auto[0]	values[3]	values[5]	364	1			T7	20		T25	21		T195	18
auto[0]	values[3]	values[6]	377	1			T201	24		T195	22		T202	12
auto[0]	values[3]	values[7]	346	1			T24	14		T167	18		T187	45
auto[0]	values[4]	values[0]	550	1			T89	16		T32	20		T28	21
auto[0]	values[4]	values[1]	220	1			T3	20		T132	20		T187	22
auto[0]	values[4]	values[2]	297	1			T25	36		T85	4		T182	20
auto[0]	values[4]	values[3]	317	1			T7	20		T203	17		T204	12
auto[0]	values[4]	values[4]	409	1			T32	45		T39	41		T25	27
auto[0]	values[4]	values[5]	494	1			T205	16		T168	20		T200	27
auto[0]	values[4]	values[6]	587	1			T7	37		T32	23		T28	42
auto[0]	values[4]	values[7]	353	1			T4	30		T206	10		T184	32
auto[0]	values[5]	values[0]	364	1			T207	18		T187	20		T208	14
auto[0]	values[5]	values[1]	561	1			T57	29		T209	14		T184	67
auto[0]	values[5]	values[2]	568	1			T210	6		T168	25		T211	18
auto[0]	values[5]	values[3]	473	1			T3	22		T7	86		T212	16
auto[0]	values[5]	values[4]	276	1			T3	22		T7	38		T8	20
auto[0]	values[5]	values[5]	415	1			T57	88		T72	4		T22	20
auto[0]	values[5]	values[6]	370	1			T39	20		T213	22		T168	124
auto[0]	values[5]	values[7]	485	1			T8	35		T56	16		T132	18
auto[0]	values[6]	values[0]	360	1			T7	19		T8	75		T39	20
auto[0]	values[6]	values[1]	433	1			T28	45		T214	14		T178	20
auto[0]	values[6]	values[2]	546	1			T10	4		T28	30		T215	30
auto[0]	values[6]	values[3]	261	1			T32	37		T75	10		T216	10
auto[0]	values[6]	values[4]	327	1			T8	51		T217	2		T195	19
auto[0]	values[6]	values[5]	429	1			T185	30		T218	8		T219	2
auto[0]	values[6]	values[6]	355	1			T25	20		T28	20		T57	39
auto[0]	values[6]	values[7]	291	1			T7	40		T114	14		T41	16
auto[0]	values[7]	values[0]	543	1			T28	25		T29	4		T200	19
auto[0]	values[7]	values[1]	366	1			T39	19		T22	20		T181	19
auto[0]	values[7]	values[2]	397	1			T3	22		T220	43		T221	16
auto[0]	values[7]	values[3]	336	1			T7	20		T25	46		T222	20
auto[0]	values[7]	values[4]	452	1			T7	20		T39	20		T57	126
auto[0]	values[7]	values[5]	293	1			T134	2		T181	20		T203	19
auto[0]	values[7]	values[6]	329	1			T32	22		T178	36		T40	21
auto[0]	values[7]	values[7]	286	1			T3	20		T32	20		T223	24
auto[1]	values[0]	values[0]	8	1			T40	1		T173	1		T224	2
auto[1]	values[0]	values[1]	13	1			T28	1		T174	3		T225	1
auto[1]	values[0]	values[2]	6	1			T211	1		T137	1		T226	2
auto[1]	values[0]	values[3]	7	1			T178	3		T179	1		T180	3
auto[1]	values[0]	values[4]	8	1			T40	3		T181	2		T227	1
auto[1]	values[0]	values[5]	8	1			T168	1		T184	2		T221	1
auto[1]	values[0]	values[6]	4	1			T185	1		T40	1		T228	2
auto[1]	values[0]	values[7]	16	1			T40	1		T181	1		T211	3
auto[1]	values[1]	values[0]	10	1			T7	1		T39	2		T57	3
auto[1]	values[1]	values[1]	11	1			T32	1		T220	1		T229	3
auto[1]	values[1]	values[2]	10	1			T227	2		T179	7		T164	1
auto[1]	values[1]	values[3]	9	1			T230	4		T231	5		-	-
auto[1]	values[1]	values[4]	6	1			T232	3		T233	2		T234	1
auto[1]	values[1]	values[5]	12	1			T25	1		T187	2		T235	2
auto[1]	values[1]	values[6]	6	1			T43	1		T236	3		T237	2
auto[1]	values[1]	values[7]	13	1			T185	2		T40	2		T43	2
auto[1]	values[2]	values[0]	12	1			T25	2		T178	3		T238	1
auto[1]	values[2]	values[1]	17	1			T22	2		T43	1		T239	1
auto[1]	values[2]	values[2]	5	1			T184	1		T180	2		T139	2
auto[1]	values[2]	values[3]	14	1			T178	1		T224	3		T240	1
auto[1]	values[2]	values[4]	13	1			T28	1		T40	1		T182	5
auto[1]	values[2]	values[5]	13	1			T40	1		T241	1		T242	4
auto[1]	values[2]	values[6]	9	1			T178	1		T43	3		T243	3
auto[1]	values[2]	values[7]	14	1			T3	2		T39	2		T244	2
auto[1]	values[3]	values[0]	5	1			T43	1		T221	1		T245	2
auto[1]	values[3]	values[1]	2	1			T22	2		-	-		-	-
auto[1]	values[3]	values[2]	10	1			T132	2		T195	4		T243	4
auto[1]	values[3]	values[3]	7	1			T3	4		T184	1		T211	1
auto[1]	values[3]	values[4]	11	1			T32	2		T246	1		T234	3
auto[1]	values[3]	values[5]	10	1			T25	1		T195	2		T211	1
auto[1]	values[3]	values[6]	13	1			T245	1		T180	2		T247	7
auto[1]	values[3]	values[7]	7	1			T167	2		T195	2		T238	2
auto[1]	values[4]	values[0]	10	1			T28	1		T195	2		T182	4
auto[1]	values[4]	values[1]	5	1			T181	1		T248	4		-	-
auto[1]	values[4]	values[2]	3	1			T161	1		T249	2		-	-
auto[1]	values[4]	values[3]	8	1			T203	3		T250	3		T251	2
auto[1]	values[4]	values[4]	14	1			T32	2		T39	3		T25	1
auto[1]	values[4]	values[5]	8	1			T252	1		T253	2		T164	2
auto[1]	values[4]	values[6]	17	1			T7	2		T32	1		T28	2
auto[1]	values[4]	values[7]	13	1			T184	1		T137	1		T254	2
auto[1]	values[5]	values[0]	7	1			T232	3		T255	4		-	-
auto[1]	values[5]	values[1]	13	1			T57	1		T184	2		T256	2
auto[1]	values[5]	values[2]	17	1			T168	1		T211	2		T256	1
auto[1]	values[5]	values[3]	11	1			T3	2		T7	1		T40	2
auto[1]	values[5]	values[4]	13	1			T3	1		T7	2		T43	2
auto[1]	values[5]	values[5]	9	1			T57	1		T249	2		T239	2
auto[1]	values[5]	values[6]	7	1			T168	2		T203	1		T179	1
auto[1]	values[5]	values[7]	9	1			T8	1		T56	4		T132	3
auto[1]	values[6]	values[0]	8	1			T7	1		T8	1		T184	1
auto[1]	values[6]	values[1]	7	1			T257	2		T258	2		T259	2
auto[1]	values[6]	values[2]	15	1			T28	2		T184	2		T40	1
auto[1]	values[6]	values[3]	5	1			T260	2		T247	1		T243	1
auto[1]	values[6]	values[4]	4	1			T195	1		T261	3		-	-
auto[1]	values[6]	values[5]	8	1			T185	1		T225	1		T238	2
auto[1]	values[6]	values[6]	7	1			T57	1		T262	2		T263	1
auto[1]	values[6]	values[7]	11	1			T7	2		T41	2		T57	2
auto[1]	values[7]	values[0]	20	1			T28	1		T200	1		T22	2
auto[1]	values[7]	values[1]	13	1			T39	1		T181	1		T245	1
auto[1]	values[7]	values[2]	14	1			T3	1		T221	4		T264	1
auto[1]	values[7]	values[4]	5	1			T265	2		T233	1		T243	1
auto[1]	values[7]	values[5]	6	1			T203	1		T253	3		T266	1
auto[1]	values[7]	values[6]	10	1			T178	2		T227	2		T267	1
auto[1]	values[7]	values[7]	7	1			T268	3		T59	1		T269	2