Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	869	1			T4	10		T31	17		T63	14
all_values[1]	869	1			T4	10		T31	17		T63	14
all_values[2]	869	1			T4	10		T31	17		T63	14
all_values[3]	869	1			T4	10		T31	17		T63	14
all_values[4]	869	1			T4	10		T31	17		T63	14
all_values[5]	869	1			T4	10		T31	17		T63	14
all_values[6]	869	1			T4	10		T31	17		T63	14
all_values[7]	869	1			T4	10		T31	17		T63	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3693

1

T4

39

T31

61

T63

75

auto[1]

3259

1

T4

41

T31

75

T63

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2796

1

T4

33

T31

43

T63

47

auto[1]

4156

1

T4

47

T31

93

T63

65

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3948

1

T4

44

T31

69

T63

64

auto[1]

3004

1

T4

36

T31

67

T63

48

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	205	1			T4	3		T31	1		T63	6
all_values[0]	auto[0]	auto[0]	auto[1]	85	1			T31	1		T63	4		T16	1
all_values[0]	auto[0]	auto[1]	auto[0]	163	1			T4	3		T31	1		T15	1
all_values[0]	auto[0]	auto[1]	auto[1]	78	1			T4	1		T31	3		T17	1
all_values[0]	auto[1]	auto[0]	auto[1]	184	1			T4	1		T31	1		T63	4
all_values[0]	auto[1]	auto[1]	auto[1]	154	1			T4	2		T31	10		T15	1
all_values[1]	auto[0]	auto[0]	auto[0]	176	1			T31	5		T63	2		T16	1
all_values[1]	auto[0]	auto[0]	auto[1]	92	1			T31	1		T63	3		T16	2
all_values[1]	auto[0]	auto[1]	auto[0]	149	1			T31	3		T63	3		T15	1
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T4	3		T31	2		T63	1
all_values[1]	auto[1]	auto[0]	auto[1]	209	1			T4	2		T31	2		T63	4
all_values[1]	auto[1]	auto[1]	auto[1]	158	1			T4	5		T31	4		T63	1
all_values[2]	auto[0]	auto[0]	auto[0]	184	1			T4	2		T31	3		T63	6
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T31	3		T16	1		T18	1
all_values[2]	auto[0]	auto[1]	auto[0]	167	1			T4	2		T31	2		T15	1
all_values[2]	auto[0]	auto[1]	auto[1]	73	1			T31	4		T63	1		T15	1
all_values[2]	auto[1]	auto[0]	auto[1]	192	1			T4	1		T31	2		T63	6
all_values[2]	auto[1]	auto[1]	auto[1]	181	1			T4	5		T31	3		T63	1
all_values[3]	auto[0]	auto[0]	auto[0]	183	1			T4	3		T31	7		T63	6
all_values[3]	auto[0]	auto[0]	auto[1]	84	1			T4	1		T31	2		T63	1
all_values[3]	auto[0]	auto[1]	auto[0]	137	1			T4	2		T31	1		T15	2
all_values[3]	auto[0]	auto[1]	auto[1]	80	1			T4	1		T31	1		T16	1
all_values[3]	auto[1]	auto[0]	auto[1]	200	1			T4	3		T31	4		T63	5
all_values[3]	auto[1]	auto[1]	auto[1]	185	1			T31	2		T63	2		T16	4
all_values[4]	auto[0]	auto[0]	auto[0]	166	1			T4	3		T63	7		T15	3
all_values[4]	auto[0]	auto[0]	auto[1]	92	1			T4	2		T31	2		T16	1
all_values[4]	auto[0]	auto[1]	auto[0]	171	1			T4	2		T31	1		T63	2
all_values[4]	auto[0]	auto[1]	auto[1]	85	1			T31	3		T63	2		T16	1
all_values[4]	auto[1]	auto[0]	auto[1]	185	1			T4	1		T31	4		T63	1
all_values[4]	auto[1]	auto[1]	auto[1]	170	1			T4	2		T31	7		T63	2
all_values[5]	auto[0]	auto[0]	auto[0]	241	1			T4	3		T31	5		T63	5
all_values[5]	auto[0]	auto[1]	auto[0]	224	1			T4	3		T31	3		T63	2
all_values[5]	auto[1]	auto[0]	auto[1]	208	1			T4	1		T31	3		T63	3
all_values[5]	auto[1]	auto[1]	auto[1]	196	1			T4	3		T31	6		T63	4
all_values[6]	auto[0]	auto[0]	auto[0]	158	1			T31	1		T15	1		T17	1
all_values[6]	auto[0]	auto[0]	auto[1]	85	1			T4	2		T63	3		T15	1
all_values[6]	auto[0]	auto[1]	auto[0]	147	1			T4	1		T31	6		T63	4
all_values[6]	auto[0]	auto[1]	auto[1]	85	1			T31	1		T16	1		T18	2
all_values[6]	auto[1]	auto[0]	auto[1]	204	1			T4	5		T31	2		T63	5
all_values[6]	auto[1]	auto[1]	auto[1]	190	1			T4	2		T31	7		T63	2
all_values[7]	auto[0]	auto[0]	auto[0]	179	1			T4	3		T31	3		T15	1
all_values[7]	auto[0]	auto[0]	auto[1]	72	1			T4	1		T31	2		T166	1
all_values[7]	auto[0]	auto[1]	auto[0]	146	1			T4	3		T31	1		T63	4
all_values[7]	auto[0]	auto[1]	auto[1]	84	1			T31	1		T63	2		T15	1
all_values[7]	auto[1]	auto[0]	auto[1]	237	1			T4	2		T31	7		T63	4
all_values[7]	auto[1]	auto[1]	auto[1]	151	1			T4	1		T31	3		T63	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal