Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1609

1

T3

10

T36

1

T30

4

auto[1]

1654

1

T3

17

T4

1

T30

8

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1733

1

T3

21

T4

1

T30

12

auto[1]

1530

1

T3

6

T36

1

T33

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2591

1

T3

23

T4

1

T36

1

auto[1]

672

1

T3

4

T30

5

T32

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	612	1			T3	7		T30	1		T32	1
valid[1]	661	1			T3	1		T30	5		T32	2
valid[2]	650	1			T3	6		T36	1		T30	1
valid[3]	692	1			T3	7		T4	1		T30	2
valid[4]	648	1			T3	6		T30	3		T32	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	86	1			T3	1		T35	1		T15	4
auto[0]	auto[0]	valid[0]	auto[1]	144	1			T3	1		T37	1		T15	1
auto[0]	auto[0]	valid[1]	auto[0]	106	1			T3	1		T35	1		T38	1
auto[0]	auto[0]	valid[1]	auto[1]	161	1			T37	1		T15	1		T84	1
auto[0]	auto[0]	valid[2]	auto[0]	93	1			T38	1		T15	1		T25	1
auto[0]	auto[0]	valid[2]	auto[1]	149	1			T3	3		T36	1		T344	1
auto[0]	auto[0]	valid[3]	auto[0]	103	1			T3	1		T30	1		T35	2
auto[0]	auto[0]	valid[3]	auto[1]	162	1			T33	1		T37	1		T27	1
auto[0]	auto[0]	valid[4]	auto[0]	100	1			T30	1		T15	1		T25	2
auto[0]	auto[0]	valid[4]	auto[1]	154	1			T3	1		T37	3		T38	1
auto[0]	auto[1]	valid[0]	auto[0]	111	1			T3	4		T30	1		T32	1
auto[0]	auto[1]	valid[0]	auto[1]	148	1			T33	1		T37	3		T15	1
auto[0]	auto[1]	valid[1]	auto[0]	112	1			T30	1		T32	1		T38	1
auto[0]	auto[1]	valid[1]	auto[1]	147	1			T37	1		T39	1		T15	1
auto[0]	auto[1]	valid[2]	auto[0]	111	1			T3	3		T32	1		T35	1
auto[0]	auto[1]	valid[2]	auto[1]	156	1			T39	1		T215	1		T345	2
auto[0]	auto[1]	valid[3]	auto[0]	134	1			T3	4		T4	1		T30	1
auto[0]	auto[1]	valid[3]	auto[1]	153	1			T33	1		T37	1		T38	1
auto[0]	auto[1]	valid[4]	auto[0]	105	1			T3	3		T30	2		T32	1
auto[0]	auto[1]	valid[4]	auto[1]	156	1			T3	1		T37	2		T15	1
auto[1]	auto[0]	valid[0]	auto[0]	66	1			T38	1		T39	1		T15	1
auto[1]	auto[0]	valid[1]	auto[0]	63	1			T30	2		T32	1		T35	2
auto[1]	auto[0]	valid[2]	auto[0]	77	1			T35	1		T15	1		T25	1
auto[1]	auto[0]	valid[3]	auto[0]	76	1			T3	2		T35	1		T27	2
auto[1]	auto[0]	valid[4]	auto[0]	69	1			T35	1		T15	2		T25	3
auto[1]	auto[1]	valid[0]	auto[0]	57	1			T3	1		T215	1		T339	1
auto[1]	auto[1]	valid[1]	auto[0]	72	1			T30	2		T38	2		T39	1
auto[1]	auto[1]	valid[2]	auto[0]	64	1			T30	1		T35	2		T39	1
auto[1]	auto[1]	valid[3]	auto[0]	64	1			T35	1		T38	1		T39	1
auto[1]	auto[1]	valid[4]	auto[0]	64	1			T3	1		T15	1		T28	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal