Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44719

1

T2

3

T3

442

T4

30

auto[1]

15516

1

T3

69

T36

1

T33

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43957

1

T3

341

T4

23

T36

1

auto[1]

16278

1

T2

3

T3

170

T4

7

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31078	1			T3	252		T4	16		T36	1
others[1]	5149	1			T3	47		T4	1		T30	36
others[2]	5034	1			T3	42		T4	5		T30	32
others[3]	5790	1			T2	2		T3	51		T4	1
interest[1]	3291	1			T3	24		T4	2		T30	20
interest[4]	20374	1			T3	159		T4	10		T36	1
interest[64]	9893	1			T2	1		T3	95		T4	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14652	1			T3	121		T4	12		T30	133
auto[0]	auto[0]	others[1]	2476	1			T3	30		T4	1		T30	26
auto[0]	auto[0]	others[2]	2396	1			T3	26		T4	4		T30	18
auto[0]	auto[0]	others[3]	2715	1			T3	29		T4	1		T30	25
auto[0]	auto[0]	interest[1]	1555	1			T3	15		T4	2		T30	13
auto[0]	auto[0]	interest[4]	9540	1			T3	79		T4	8		T30	86
auto[0]	auto[0]	interest[64]	4647	1			T3	51		T4	3		T30	39
auto[0]	auto[1]	others[0]	8103	1			T3	42		T36	1		T33	3
auto[0]	auto[1]	others[1]	1304	1			T3	3		T38	4		T39	3
auto[0]	auto[1]	others[2]	1263	1			T3	3		T38	5		T39	5
auto[0]	auto[1]	others[3]	1473	1			T3	5		T38	4		T39	5
auto[0]	auto[1]	interest[1]	836	1			T3	1		T38	3		T39	1
auto[0]	auto[1]	interest[4]	5402	1			T3	23		T36	1		T33	3
auto[0]	auto[1]	interest[64]	2537	1			T3	15		T38	8		T39	5
auto[1]	auto[0]	others[0]	8323	1			T3	89		T4	4		T30	65
auto[1]	auto[0]	others[1]	1369	1			T3	14		T30	10		T32	4
auto[1]	auto[0]	others[2]	1375	1			T3	13		T4	1		T30	14
auto[1]	auto[0]	others[3]	1602	1			T2	2		T3	17		T30	14
auto[1]	auto[0]	interest[1]	900	1			T3	8		T30	7		T32	3
auto[1]	auto[0]	interest[4]	5432	1			T3	57		T4	2		T30	39
auto[1]	auto[0]	interest[64]	2709	1			T2	1		T3	29		T4	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal