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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.10 98.62 89.36 97.29 95.43 99.21


Total test records in report: 1148
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T1043 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4074600844 Aug 10 06:17:15 PM PDT 24 Aug 10 06:17:16 PM PDT 24 13432979 ps
T111 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3217900643 Aug 10 06:16:53 PM PDT 24 Aug 10 06:16:55 PM PDT 24 23010772 ps
T1044 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.499258872 Aug 10 06:16:58 PM PDT 24 Aug 10 06:17:00 PM PDT 24 26136037 ps
T1045 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4173260942 Aug 10 06:16:32 PM PDT 24 Aug 10 06:16:45 PM PDT 24 2762610616 ps
T1046 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.86879486 Aug 10 06:16:58 PM PDT 24 Aug 10 06:16:59 PM PDT 24 28044066 ps
T102 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2973166888 Aug 10 06:16:52 PM PDT 24 Aug 10 06:16:56 PM PDT 24 576490411 ps
T119 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3837309861 Aug 10 06:16:38 PM PDT 24 Aug 10 06:16:39 PM PDT 24 17646978 ps
T112 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3868054581 Aug 10 06:17:00 PM PDT 24 Aug 10 06:17:02 PM PDT 24 79713580 ps
T1047 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4004352364 Aug 10 06:17:17 PM PDT 24 Aug 10 06:17:18 PM PDT 24 14835792 ps
T1048 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3444283714 Aug 10 06:17:24 PM PDT 24 Aug 10 06:17:24 PM PDT 24 37392627 ps
T1049 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.547305592 Aug 10 06:17:09 PM PDT 24 Aug 10 06:17:10 PM PDT 24 23322673 ps
T1050 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2059763606 Aug 10 06:16:51 PM PDT 24 Aug 10 06:16:52 PM PDT 24 208740373 ps
T155 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2114426869 Aug 10 06:17:11 PM PDT 24 Aug 10 06:17:14 PM PDT 24 106838974 ps
T1051 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3160631600 Aug 10 06:17:11 PM PDT 24 Aug 10 06:17:12 PM PDT 24 38840416 ps
T1052 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3854732970 Aug 10 06:16:48 PM PDT 24 Aug 10 06:16:50 PM PDT 24 65124803 ps
T104 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3739908447 Aug 10 06:16:44 PM PDT 24 Aug 10 06:16:47 PM PDT 24 47157689 ps
T81 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2243454869 Aug 10 06:16:30 PM PDT 24 Aug 10 06:16:31 PM PDT 24 63849644 ps
T1053 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1259331980 Aug 10 06:17:18 PM PDT 24 Aug 10 06:17:21 PM PDT 24 113327459 ps
T103 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1851342788 Aug 10 06:17:07 PM PDT 24 Aug 10 06:17:09 PM PDT 24 85107824 ps
T1054 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2189691905 Aug 10 06:16:31 PM PDT 24 Aug 10 06:16:32 PM PDT 24 22735477 ps
T120 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4085384057 Aug 10 06:17:07 PM PDT 24 Aug 10 06:17:09 PM PDT 24 92239213 ps
T1055 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2165364075 Aug 10 06:17:07 PM PDT 24 Aug 10 06:17:08 PM PDT 24 12845125 ps
T1056 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2879880416 Aug 10 06:16:52 PM PDT 24 Aug 10 06:16:53 PM PDT 24 37027699 ps
T1057 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1291079415 Aug 10 06:17:15 PM PDT 24 Aug 10 06:17:18 PM PDT 24 395761676 ps
T1058 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1796578332 Aug 10 06:17:16 PM PDT 24 Aug 10 06:17:18 PM PDT 24 70802335 ps
T107 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1451452532 Aug 10 06:16:37 PM PDT 24 Aug 10 06:16:41 PM PDT 24 61070891 ps
T1059 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1696064019 Aug 10 06:17:02 PM PDT 24 Aug 10 06:17:03 PM PDT 24 18768194 ps
T99 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2252525647 Aug 10 06:17:03 PM PDT 24 Aug 10 06:17:07 PM PDT 24 142636408 ps
T95 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3539460126 Aug 10 06:17:08 PM PDT 24 Aug 10 06:17:28 PM PDT 24 3775305813 ps
T101 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3425240929 Aug 10 06:17:07 PM PDT 24 Aug 10 06:17:11 PM PDT 24 143960107 ps
T1060 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.565253457 Aug 10 06:17:19 PM PDT 24 Aug 10 06:17:20 PM PDT 24 57918530 ps
T121 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.712314941 Aug 10 06:16:39 PM PDT 24 Aug 10 06:16:40 PM PDT 24 163535788 ps
T156 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3561428856 Aug 10 06:16:40 PM PDT 24 Aug 10 06:16:45 PM PDT 24 297033491 ps
T122 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2109677262 Aug 10 06:16:45 PM PDT 24 Aug 10 06:16:47 PM PDT 24 358383251 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1653178465 Aug 10 06:16:34 PM PDT 24 Aug 10 06:16:36 PM PDT 24 146332140 ps
T123 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2658982613 Aug 10 06:16:45 PM PDT 24 Aug 10 06:16:53 PM PDT 24 205053918 ps
T1062 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2283915559 Aug 10 06:16:48 PM PDT 24 Aug 10 06:16:49 PM PDT 24 16948720 ps
T1063 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3820040829 Aug 10 06:17:16 PM PDT 24 Aug 10 06:17:17 PM PDT 24 29006210 ps
T157 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3228355392 Aug 10 06:17:08 PM PDT 24 Aug 10 06:17:12 PM PDT 24 212855328 ps
T1064 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4169195689 Aug 10 06:17:07 PM PDT 24 Aug 10 06:17:10 PM PDT 24 454415959 ps
T271 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.440539521 Aug 10 06:16:48 PM PDT 24 Aug 10 06:17:10 PM PDT 24 3252174307 ps
T1065 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2798505245 Aug 10 06:16:53 PM PDT 24 Aug 10 06:16:55 PM PDT 24 28358085 ps
T124 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3135134897 Aug 10 06:16:31 PM PDT 24 Aug 10 06:16:34 PM PDT 24 40246155 ps
T1066 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3772213541 Aug 10 06:17:21 PM PDT 24 Aug 10 06:17:25 PM PDT 24 218475525 ps
T1067 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1774785137 Aug 10 06:16:30 PM PDT 24 Aug 10 06:16:39 PM PDT 24 319102752 ps
T158 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3068168952 Aug 10 06:16:52 PM PDT 24 Aug 10 06:16:54 PM PDT 24 146205855 ps
T1068 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1252249396 Aug 10 06:17:08 PM PDT 24 Aug 10 06:17:10 PM PDT 24 26168959 ps
T1069 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4097580718 Aug 10 06:17:09 PM PDT 24 Aug 10 06:17:09 PM PDT 24 51149482 ps
T277 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1792427859 Aug 10 06:16:53 PM PDT 24 Aug 10 06:17:00 PM PDT 24 1678314948 ps
T1070 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.759106377 Aug 10 06:17:17 PM PDT 24 Aug 10 06:17:18 PM PDT 24 52701136 ps
T1071 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1399175331 Aug 10 06:16:39 PM PDT 24 Aug 10 06:16:52 PM PDT 24 609954458 ps
T1072 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2207235714 Aug 10 06:17:18 PM PDT 24 Aug 10 06:17:19 PM PDT 24 37051067 ps
T1073 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3038580899 Aug 10 06:16:38 PM PDT 24 Aug 10 06:16:38 PM PDT 24 12884536 ps
T1074 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1480429323 Aug 10 06:16:52 PM PDT 24 Aug 10 06:16:53 PM PDT 24 106744115 ps
T1075 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2538023041 Aug 10 06:16:56 PM PDT 24 Aug 10 06:16:57 PM PDT 24 107051135 ps
T125 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1578868678 Aug 10 06:16:38 PM PDT 24 Aug 10 06:17:00 PM PDT 24 716413099 ps
T1076 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.612184262 Aug 10 06:17:10 PM PDT 24 Aug 10 06:17:13 PM PDT 24 58561641 ps
T1077 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2290194553 Aug 10 06:16:52 PM PDT 24 Aug 10 06:16:54 PM PDT 24 54006960 ps
T278 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1236770725 Aug 10 06:17:15 PM PDT 24 Aug 10 06:17:30 PM PDT 24 1127549591 ps
T1078 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2260884461 Aug 10 06:16:51 PM PDT 24 Aug 10 06:16:52 PM PDT 24 210374984 ps
T1079 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1111562296 Aug 10 06:16:59 PM PDT 24 Aug 10 06:17:02 PM PDT 24 65072190 ps
T1080 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3666376985 Aug 10 06:16:31 PM PDT 24 Aug 10 06:16:32 PM PDT 24 14046628 ps
T1081 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2589293825 Aug 10 06:17:22 PM PDT 24 Aug 10 06:17:23 PM PDT 24 33635728 ps
T1082 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2393873810 Aug 10 06:17:18 PM PDT 24 Aug 10 06:17:19 PM PDT 24 119315043 ps
T1083 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1980312328 Aug 10 06:16:52 PM PDT 24 Aug 10 06:16:55 PM PDT 24 89232520 ps
T1084 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2104730897 Aug 10 06:17:24 PM PDT 24 Aug 10 06:17:25 PM PDT 24 54512792 ps
T165 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2757576567 Aug 10 06:17:15 PM PDT 24 Aug 10 06:17:18 PM PDT 24 1521454183 ps
T105 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4071418056 Aug 10 06:16:57 PM PDT 24 Aug 10 06:16:59 PM PDT 24 133114317 ps
T274 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.196238145 Aug 10 06:17:19 PM PDT 24 Aug 10 06:17:27 PM PDT 24 1099942987 ps
T1085 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3857589242 Aug 10 06:17:17 PM PDT 24 Aug 10 06:17:17 PM PDT 24 57792483 ps
T1086 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2385405486 Aug 10 06:17:27 PM PDT 24 Aug 10 06:17:28 PM PDT 24 14402989 ps
T106 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4055445088 Aug 10 06:16:32 PM PDT 24 Aug 10 06:16:35 PM PDT 24 58709249 ps
T1087 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1044710915 Aug 10 06:16:34 PM PDT 24 Aug 10 06:16:35 PM PDT 24 13039048 ps
T100 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.484484578 Aug 10 06:17:19 PM PDT 24 Aug 10 06:17:24 PM PDT 24 395539487 ps
T108 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3008390831 Aug 10 06:16:53 PM PDT 24 Aug 10 06:16:57 PM PDT 24 402364665 ps
T82 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3573300580 Aug 10 06:16:45 PM PDT 24 Aug 10 06:16:46 PM PDT 24 35261364 ps
T1088 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2493800870 Aug 10 06:16:40 PM PDT 24 Aug 10 06:16:53 PM PDT 24 194317686 ps
T1089 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2773811993 Aug 10 06:16:55 PM PDT 24 Aug 10 06:17:03 PM PDT 24 1144237633 ps
T1090 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2274022055 Aug 10 06:16:40 PM PDT 24 Aug 10 06:16:42 PM PDT 24 113595712 ps
T1091 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4084775084 Aug 10 06:17:08 PM PDT 24 Aug 10 06:17:12 PM PDT 24 192770153 ps
T1092 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2746012698 Aug 10 06:16:36 PM PDT 24 Aug 10 06:16:37 PM PDT 24 34231696 ps
T1093 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.468169384 Aug 10 06:17:24 PM PDT 24 Aug 10 06:17:24 PM PDT 24 11366942 ps
T83 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1291615060 Aug 10 06:16:40 PM PDT 24 Aug 10 06:16:41 PM PDT 24 40619852 ps
T1094 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.325341147 Aug 10 06:17:09 PM PDT 24 Aug 10 06:17:11 PM PDT 24 277214558 ps
T272 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2493380562 Aug 10 06:17:00 PM PDT 24 Aug 10 06:17:22 PM PDT 24 966550395 ps
T270 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1411228479 Aug 10 06:17:19 PM PDT 24 Aug 10 06:17:24 PM PDT 24 344304982 ps
T126 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4106438411 Aug 10 06:16:30 PM PDT 24 Aug 10 06:16:32 PM PDT 24 150896729 ps
T1095 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3459532536 Aug 10 06:17:17 PM PDT 24 Aug 10 06:17:19 PM PDT 24 134095779 ps
T275 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3517390889 Aug 10 06:16:40 PM PDT 24 Aug 10 06:17:02 PM PDT 24 1617777262 ps
T1096 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2075803899 Aug 10 06:17:09 PM PDT 24 Aug 10 06:17:22 PM PDT 24 785288464 ps
T1097 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.769647739 Aug 10 06:17:22 PM PDT 24 Aug 10 06:17:23 PM PDT 24 28993297 ps
T276 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1500721364 Aug 10 06:16:31 PM PDT 24 Aug 10 06:16:37 PM PDT 24 689834199 ps
T1098 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1727267470 Aug 10 06:17:17 PM PDT 24 Aug 10 06:17:18 PM PDT 24 29692583 ps
T1099 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3490644108 Aug 10 06:17:11 PM PDT 24 Aug 10 06:17:13 PM PDT 24 31035408 ps
T1100 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2107399266 Aug 10 06:16:59 PM PDT 24 Aug 10 06:17:00 PM PDT 24 36372757 ps
T1101 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3094297168 Aug 10 06:17:17 PM PDT 24 Aug 10 06:17:18 PM PDT 24 14306964 ps
T1102 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2960011972 Aug 10 06:17:17 PM PDT 24 Aug 10 06:17:18 PM PDT 24 25299688 ps
T1103 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3005619417 Aug 10 06:16:39 PM PDT 24 Aug 10 06:16:40 PM PDT 24 14316110 ps
T1104 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2836303860 Aug 10 06:17:10 PM PDT 24 Aug 10 06:17:11 PM PDT 24 50846117 ps
T1105 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.247456208 Aug 10 06:16:44 PM PDT 24 Aug 10 06:16:59 PM PDT 24 3802790722 ps
T127 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1296437795 Aug 10 06:16:39 PM PDT 24 Aug 10 06:16:53 PM PDT 24 829775153 ps
T1106 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3464997990 Aug 10 06:16:32 PM PDT 24 Aug 10 06:16:36 PM PDT 24 147170910 ps
T1107 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2329764782 Aug 10 06:17:19 PM PDT 24 Aug 10 06:17:20 PM PDT 24 48940671 ps
T1108 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2790305953 Aug 10 06:17:10 PM PDT 24 Aug 10 06:17:13 PM PDT 24 156692892 ps
T279 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4009974312 Aug 10 06:16:58 PM PDT 24 Aug 10 06:17:21 PM PDT 24 3464974029 ps
T1109 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1714834760 Aug 10 06:16:54 PM PDT 24 Aug 10 06:16:56 PM PDT 24 49052441 ps
T128 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4187203751 Aug 10 06:16:36 PM PDT 24 Aug 10 06:16:53 PM PDT 24 618411530 ps
T1110 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.851783923 Aug 10 06:17:09 PM PDT 24 Aug 10 06:17:13 PM PDT 24 336602195 ps
T1111 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1749887124 Aug 10 06:16:56 PM PDT 24 Aug 10 06:16:57 PM PDT 24 26640587 ps
T1112 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3169246668 Aug 10 06:16:38 PM PDT 24 Aug 10 06:16:40 PM PDT 24 241759037 ps
T1113 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.769559742 Aug 10 06:16:46 PM PDT 24 Aug 10 06:16:46 PM PDT 24 19163474 ps
T1114 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2576193448 Aug 10 06:16:34 PM PDT 24 Aug 10 06:16:42 PM PDT 24 547738961 ps
T1115 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3386999922 Aug 10 06:17:00 PM PDT 24 Aug 10 06:17:01 PM PDT 24 27138082 ps
T1116 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1793550609 Aug 10 06:16:38 PM PDT 24 Aug 10 06:16:40 PM PDT 24 121536766 ps
T1117 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3411390135 Aug 10 06:17:01 PM PDT 24 Aug 10 06:17:23 PM PDT 24 4050146343 ps
T109 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1189039191 Aug 10 06:17:07 PM PDT 24 Aug 10 06:17:19 PM PDT 24 265578099 ps
T1118 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3975158022 Aug 10 06:17:16 PM PDT 24 Aug 10 06:17:19 PM PDT 24 101313756 ps
T1119 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2252792045 Aug 10 06:16:58 PM PDT 24 Aug 10 06:17:18 PM PDT 24 8977818097 ps
T1120 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1775479831 Aug 10 06:17:08 PM PDT 24 Aug 10 06:17:09 PM PDT 24 44946812 ps
T1121 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4005142063 Aug 10 06:17:22 PM PDT 24 Aug 10 06:17:24 PM PDT 24 13942974 ps
T1122 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1018980319 Aug 10 06:17:10 PM PDT 24 Aug 10 06:17:13 PM PDT 24 104394847 ps
T1123 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4235441354 Aug 10 06:17:24 PM PDT 24 Aug 10 06:17:25 PM PDT 24 170184318 ps
T1124 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1418911209 Aug 10 06:17:17 PM PDT 24 Aug 10 06:17:19 PM PDT 24 90738060 ps
T1125 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.349453623 Aug 10 06:17:19 PM PDT 24 Aug 10 06:17:20 PM PDT 24 16972993 ps
T1126 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3455903813 Aug 10 06:17:16 PM PDT 24 Aug 10 06:17:16 PM PDT 24 15082164 ps
T1127 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.406199323 Aug 10 06:17:17 PM PDT 24 Aug 10 06:17:18 PM PDT 24 50092553 ps
T1128 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2673232832 Aug 10 06:17:15 PM PDT 24 Aug 10 06:17:15 PM PDT 24 17336481 ps
T1129 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.441883242 Aug 10 06:16:30 PM PDT 24 Aug 10 06:16:32 PM PDT 24 74807039 ps
T273 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1029412655 Aug 10 06:17:08 PM PDT 24 Aug 10 06:17:16 PM PDT 24 4689079942 ps
T1130 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.821196581 Aug 10 06:17:08 PM PDT 24 Aug 10 06:17:10 PM PDT 24 82730502 ps
T1131 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2151829280 Aug 10 06:16:38 PM PDT 24 Aug 10 06:16:43 PM PDT 24 970934122 ps
T1132 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3620464815 Aug 10 06:17:08 PM PDT 24 Aug 10 06:17:11 PM PDT 24 184028677 ps
T1133 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1970801349 Aug 10 06:17:10 PM PDT 24 Aug 10 06:17:23 PM PDT 24 2708952163 ps
T1134 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3965304056 Aug 10 06:16:45 PM PDT 24 Aug 10 06:16:46 PM PDT 24 116689074 ps
T1135 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3103942438 Aug 10 06:17:24 PM PDT 24 Aug 10 06:17:25 PM PDT 24 20221543 ps
T1136 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4252423178 Aug 10 06:16:32 PM PDT 24 Aug 10 06:16:35 PM PDT 24 431821424 ps
T1137 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.714893823 Aug 10 06:17:07 PM PDT 24 Aug 10 06:17:10 PM PDT 24 156144629 ps
T1138 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2279912674 Aug 10 06:16:38 PM PDT 24 Aug 10 06:16:42 PM PDT 24 371887506 ps
T1139 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4005411747 Aug 10 06:17:17 PM PDT 24 Aug 10 06:17:18 PM PDT 24 50440396 ps
T1140 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.79945189 Aug 10 06:17:16 PM PDT 24 Aug 10 06:17:20 PM PDT 24 111229793 ps
T1141 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1668819162 Aug 10 06:17:25 PM PDT 24 Aug 10 06:17:26 PM PDT 24 22382392 ps
T1142 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3465753726 Aug 10 06:16:59 PM PDT 24 Aug 10 06:17:02 PM PDT 24 413722247 ps
T1143 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3647574281 Aug 10 06:16:37 PM PDT 24 Aug 10 06:16:41 PM PDT 24 232201015 ps
T1144 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2519368220 Aug 10 06:16:38 PM PDT 24 Aug 10 06:16:41 PM PDT 24 392450768 ps
T1145 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1938012026 Aug 10 06:17:16 PM PDT 24 Aug 10 06:17:17 PM PDT 24 115914842 ps
T1146 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1099165598 Aug 10 06:17:03 PM PDT 24 Aug 10 06:17:06 PM PDT 24 280297827 ps
T1147 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3465771554 Aug 10 06:17:15 PM PDT 24 Aug 10 06:17:15 PM PDT 24 39750077 ps
T1148 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2157842385 Aug 10 06:17:17 PM PDT 24 Aug 10 06:17:18 PM PDT 24 25498092 ps

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3375221965
Short name T3
Test name
Test status
Simulation time 4042296887 ps
CPU time 103.99 seconds
Started Aug 10 06:18:26 PM PDT 24
Finished Aug 10 06:20:10 PM PDT 24
Peak memory 257728 kb
Host smart-dd8c5e22-f21e-4a88-ba83-d5f848bf3c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375221965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3375221965
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.4072524378
Short name T7
Test name
Test status
Simulation time 29196054745 ps
CPU time 253.99 seconds
Started Aug 10 06:19:12 PM PDT 24
Finished Aug 10 06:23:26 PM PDT 24
Peak memory 252552 kb
Host smart-bc188676-2e0d-4ab4-b634-c39b6133d12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072524378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.4072524378
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.772865961
Short name T40
Test name
Test status
Simulation time 20596048304 ps
CPU time 336.84 seconds
Started Aug 10 06:18:58 PM PDT 24
Finished Aug 10 06:24:35 PM PDT 24
Peak memory 274556 kb
Host smart-9fd11a88-b053-46c7-af2d-c8e85b269684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772865961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.772865961
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2903399317
Short name T110
Test name
Test status
Simulation time 110451716 ps
CPU time 2.67 seconds
Started Aug 10 06:16:57 PM PDT 24
Finished Aug 10 06:17:00 PM PDT 24
Peak memory 216840 kb
Host smart-85acf351-72b3-4778-8887-3bdf2ba2e251
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903399317 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2903399317
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2677350757
Short name T15
Test name
Test status
Simulation time 105678875537 ps
CPU time 220.95 seconds
Started Aug 10 06:19:20 PM PDT 24
Finished Aug 10 06:23:01 PM PDT 24
Peak memory 250120 kb
Host smart-aafff89e-69ca-4c4c-84b1-450e2fbde899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677350757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2677350757
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2782165586
Short name T25
Test name
Test status
Simulation time 170709475531 ps
CPU time 174.15 seconds
Started Aug 10 06:18:39 PM PDT 24
Finished Aug 10 06:21:33 PM PDT 24
Peak memory 258180 kb
Host smart-9e3c350d-a753-4a80-9ccc-b23cd86c5c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782165586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2782165586
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3278128647
Short name T64
Test name
Test status
Simulation time 42834940 ps
CPU time 0.74 seconds
Started Aug 10 06:18:03 PM PDT 24
Finished Aug 10 06:18:04 PM PDT 24
Peak memory 216672 kb
Host smart-b37e5017-bc27-4dfe-b5bf-587b1d7dd86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278128647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3278128647
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.9017184
Short name T22
Test name
Test status
Simulation time 348783651780 ps
CPU time 365.95 seconds
Started Aug 10 06:19:11 PM PDT 24
Finished Aug 10 06:25:17 PM PDT 24
Peak memory 274040 kb
Host smart-aa140bcf-3aa8-428f-82e6-9d156136d4c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9017184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_
all.9017184
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.628288696
Short name T19
Test name
Test status
Simulation time 71327176 ps
CPU time 1.05 seconds
Started Aug 10 06:18:19 PM PDT 24
Finished Aug 10 06:18:20 PM PDT 24
Peak memory 235592 kb
Host smart-5e750e03-757d-4a68-b31f-f62fedceecdd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628288696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.628288696
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1609680114
Short name T132
Test name
Test status
Simulation time 5315717659 ps
CPU time 86.38 seconds
Started Aug 10 06:19:20 PM PDT 24
Finished Aug 10 06:20:46 PM PDT 24
Peak memory 250620 kb
Host smart-1f905cb8-f2bd-41e0-9f63-6bd3177af946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609680114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1609680114
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1678065758
Short name T54
Test name
Test status
Simulation time 1667092940 ps
CPU time 10.61 seconds
Started Aug 10 06:20:24 PM PDT 24
Finished Aug 10 06:20:35 PM PDT 24
Peak memory 225228 kb
Host smart-413dc6e6-9ea4-4448-8014-c766ad2ecd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678065758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1678065758
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.4169569778
Short name T57
Test name
Test status
Simulation time 10913103154 ps
CPU time 101.84 seconds
Started Aug 10 06:18:38 PM PDT 24
Finished Aug 10 06:20:20 PM PDT 24
Peak memory 266272 kb
Host smart-9e6e9764-abd4-4357-a495-805d8b031cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169569778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.4169569778
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.611248163
Short name T178
Test name
Test status
Simulation time 11269438873 ps
CPU time 102.16 seconds
Started Aug 10 06:18:59 PM PDT 24
Finished Aug 10 06:20:41 PM PDT 24
Peak memory 269264 kb
Host smart-775c2da7-a6b3-47c7-a3bb-c8022736ca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611248163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.611248163
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.440539521
Short name T271
Test name
Test status
Simulation time 3252174307 ps
CPU time 21.6 seconds
Started Aug 10 06:16:48 PM PDT 24
Finished Aug 10 06:17:10 PM PDT 24
Peak memory 215548 kb
Host smart-1453d047-2fdf-42bd-8ad3-0c7d7e47de5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440539521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.440539521
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3433966430
Short name T164
Test name
Test status
Simulation time 18643140185 ps
CPU time 256.57 seconds
Started Aug 10 06:18:21 PM PDT 24
Finished Aug 10 06:22:38 PM PDT 24
Peak memory 273648 kb
Host smart-857d4159-16ee-4105-be4f-0e6eecfaa33d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433966430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3433966430
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1201899441
Short name T51
Test name
Test status
Simulation time 41510556262 ps
CPU time 60.91 seconds
Started Aug 10 06:18:09 PM PDT 24
Finished Aug 10 06:19:10 PM PDT 24
Peak memory 249920 kb
Host smart-e1540b10-7f00-4838-9327-11dac6a0f2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201899441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1201899441
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.764277223
Short name T93
Test name
Test status
Simulation time 641705350 ps
CPU time 3.9 seconds
Started Aug 10 06:17:00 PM PDT 24
Finished Aug 10 06:17:04 PM PDT 24
Peak memory 215832 kb
Host smart-0ba87335-7f2e-4724-b4b5-54be951940a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764277223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.764277223
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.712314941
Short name T121
Test name
Test status
Simulation time 163535788 ps
CPU time 1.37 seconds
Started Aug 10 06:16:39 PM PDT 24
Finished Aug 10 06:16:40 PM PDT 24
Peak memory 215472 kb
Host smart-b84d953e-a862-4208-8d22-70fe22ac8ef0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712314941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.712314941
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3579982803
Short name T43
Test name
Test status
Simulation time 7788699694 ps
CPU time 108.33 seconds
Started Aug 10 06:19:35 PM PDT 24
Finished Aug 10 06:21:24 PM PDT 24
Peak memory 250008 kb
Host smart-4d41306d-6b88-4a0f-996f-9af998b7ea4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579982803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3579982803
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3996924496
Short name T203
Test name
Test status
Simulation time 204547127498 ps
CPU time 378.47 seconds
Started Aug 10 06:18:40 PM PDT 24
Finished Aug 10 06:24:58 PM PDT 24
Peak memory 257244 kb
Host smart-60c06ec6-a021-4da1-8776-720d1f723819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996924496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3996924496
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3203368553
Short name T137
Test name
Test status
Simulation time 5862718485 ps
CPU time 118.02 seconds
Started Aug 10 06:19:55 PM PDT 24
Finished Aug 10 06:21:53 PM PDT 24
Peak memory 257244 kb
Host smart-01f0f08b-3cf4-45f5-957a-319e31159dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203368553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3203368553
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1448348391
Short name T48
Test name
Test status
Simulation time 341565585 ps
CPU time 1.16 seconds
Started Aug 10 06:18:02 PM PDT 24
Finished Aug 10 06:18:03 PM PDT 24
Peak memory 217200 kb
Host smart-a62490ee-6725-4384-a6f1-c4f52d50c983
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448348391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1448348391
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1048568529
Short name T227
Test name
Test status
Simulation time 32301637403 ps
CPU time 133.36 seconds
Started Aug 10 06:18:33 PM PDT 24
Finished Aug 10 06:20:47 PM PDT 24
Peak memory 272144 kb
Host smart-1a7d8616-4674-4cc5-8d46-3265a388c61c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048568529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1048568529
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.4186881338
Short name T243
Test name
Test status
Simulation time 12054038961 ps
CPU time 155.37 seconds
Started Aug 10 06:19:20 PM PDT 24
Finished Aug 10 06:21:56 PM PDT 24
Peak memory 272880 kb
Host smart-b3ebb98b-5d19-41af-b10d-89ada07b4130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186881338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.4186881338
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.796259836
Short name T39
Test name
Test status
Simulation time 21503351543 ps
CPU time 229.16 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:24:12 PM PDT 24
Peak memory 255068 kb
Host smart-47b6733d-1c8e-4624-9f9e-421195aad9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796259836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.796259836
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.485402227
Short name T373
Test name
Test status
Simulation time 48454697 ps
CPU time 0.73 seconds
Started Aug 10 06:18:38 PM PDT 24
Finished Aug 10 06:18:39 PM PDT 24
Peak memory 205756 kb
Host smart-8b698335-0626-4cd1-92b6-dcebdc6443e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485402227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.485402227
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.161336527
Short name T234
Test name
Test status
Simulation time 73979719657 ps
CPU time 661.99 seconds
Started Aug 10 06:19:25 PM PDT 24
Finished Aug 10 06:30:28 PM PDT 24
Peak memory 265820 kb
Host smart-6eabb1fb-7fec-4e32-8641-26bbf9b13e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161336527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.161336527
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.140777283
Short name T220
Test name
Test status
Simulation time 23587759464 ps
CPU time 265.5 seconds
Started Aug 10 06:19:42 PM PDT 24
Finished Aug 10 06:24:08 PM PDT 24
Peak memory 252184 kb
Host smart-5600b187-02e9-4ebe-a5e7-2de7b5e0aaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140777283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.140777283
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.703379249
Short name T18
Test name
Test status
Simulation time 12657745214 ps
CPU time 97.5 seconds
Started Aug 10 06:18:17 PM PDT 24
Finished Aug 10 06:19:55 PM PDT 24
Peak memory 249980 kb
Host smart-e27b846b-9452-407e-9697-bf14b86a7cf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703379249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.703379249
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2252525647
Short name T99
Test name
Test status
Simulation time 142636408 ps
CPU time 3.38 seconds
Started Aug 10 06:17:03 PM PDT 24
Finished Aug 10 06:17:07 PM PDT 24
Peak memory 216812 kb
Host smart-8809be2c-4c10-407a-8192-fefe97bf809b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252525647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
252525647
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2493380562
Short name T272
Test name
Test status
Simulation time 966550395 ps
CPU time 21.83 seconds
Started Aug 10 06:17:00 PM PDT 24
Finished Aug 10 06:17:22 PM PDT 24
Peak memory 216120 kb
Host smart-61e41982-d379-4136-992a-44070b4ce0c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493380562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2493380562
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.978508529
Short name T240
Test name
Test status
Simulation time 23509292833 ps
CPU time 82.98 seconds
Started Aug 10 06:19:26 PM PDT 24
Finished Aug 10 06:20:49 PM PDT 24
Peak memory 265920 kb
Host smart-ebf28bd6-1244-40d1-9b6a-b571889c7cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978508529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.978508529
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.441961715
Short name T967
Test name
Test status
Simulation time 252451092762 ps
CPU time 395.07 seconds
Started Aug 10 06:19:00 PM PDT 24
Finished Aug 10 06:25:35 PM PDT 24
Peak memory 258104 kb
Host smart-885388e1-ff96-4d30-a2b3-dec0ffde17cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441961715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.441961715
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2064303601
Short name T238
Test name
Test status
Simulation time 24493875455 ps
CPU time 211.76 seconds
Started Aug 10 06:19:04 PM PDT 24
Finished Aug 10 06:22:36 PM PDT 24
Peak memory 255272 kb
Host smart-6107e88a-8e4a-45d0-8d14-b178a20f4daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064303601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2064303601
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1047493446
Short name T221
Test name
Test status
Simulation time 227779069096 ps
CPU time 209.16 seconds
Started Aug 10 06:19:34 PM PDT 24
Finished Aug 10 06:23:03 PM PDT 24
Peak memory 250380 kb
Host smart-667253e0-fa02-41fb-ab27-b0851976c9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047493446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1047493446
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1761359766
Short name T322
Test name
Test status
Simulation time 234576115 ps
CPU time 6.94 seconds
Started Aug 10 06:18:26 PM PDT 24
Finished Aug 10 06:18:33 PM PDT 24
Peak memory 225308 kb
Host smart-11d10c62-b4b2-415e-b011-1ed35f58c742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761359766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1761359766
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1054362521
Short name T465
Test name
Test status
Simulation time 2580573754 ps
CPU time 34.15 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:20:57 PM PDT 24
Peak memory 250084 kb
Host smart-38789ff1-93de-412e-833c-047e868d4b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054362521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1054362521
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.564622113
Short name T282
Test name
Test status
Simulation time 958679517 ps
CPU time 3.32 seconds
Started Aug 10 06:19:20 PM PDT 24
Finished Aug 10 06:19:23 PM PDT 24
Peak memory 225232 kb
Host smart-54a2bf5a-6e39-43e7-a839-2261646b8362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564622113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.564622113
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.198497893
Short name T151
Test name
Test status
Simulation time 17039590696 ps
CPU time 16.73 seconds
Started Aug 10 06:19:48 PM PDT 24
Finished Aug 10 06:20:05 PM PDT 24
Peak memory 225344 kb
Host smart-e78d8944-3f5b-4d22-8bf8-668340ea7f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198497893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.198497893
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.885574826
Short name T98
Test name
Test status
Simulation time 73451199 ps
CPU time 4.31 seconds
Started Aug 10 06:17:08 PM PDT 24
Finished Aug 10 06:17:12 PM PDT 24
Peak memory 215900 kb
Host smart-c90fc042-3466-47ac-876d-5705ad4a73a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885574826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.885574826
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1189039191
Short name T109
Test name
Test status
Simulation time 265578099 ps
CPU time 12.37 seconds
Started Aug 10 06:17:07 PM PDT 24
Finished Aug 10 06:17:19 PM PDT 24
Peak memory 215624 kb
Host smart-78fb872b-5c64-42ed-9737-6b637b831e17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189039191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1189039191
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.902708562
Short name T215
Test name
Test status
Simulation time 1885234906 ps
CPU time 26.47 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:19:16 PM PDT 24
Peak memory 235852 kb
Host smart-bee74e36-ebd6-4d2f-8bee-70bc9949fdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902708562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.902708562
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.163260789
Short name T449
Test name
Test status
Simulation time 47408420898 ps
CPU time 134.68 seconds
Started Aug 10 06:18:55 PM PDT 24
Finished Aug 10 06:21:10 PM PDT 24
Peak memory 249164 kb
Host smart-799cfe9c-9cf7-4165-b008-dc122ff6d27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163260789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.163260789
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.4086061050
Short name T232
Test name
Test status
Simulation time 3658292670 ps
CPU time 71.1 seconds
Started Aug 10 06:19:02 PM PDT 24
Finished Aug 10 06:20:14 PM PDT 24
Peak memory 253284 kb
Host smart-830e2911-6c02-48a0-a522-038ed2cf503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086061050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.4086061050
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.829731532
Short name T231
Test name
Test status
Simulation time 3486166111 ps
CPU time 87.92 seconds
Started Aug 10 06:19:02 PM PDT 24
Finished Aug 10 06:20:30 PM PDT 24
Peak memory 273780 kb
Host smart-7226f4be-e8a4-497d-b4f8-2bbc3376d0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829731532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.829731532
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1336784969
Short name T180
Test name
Test status
Simulation time 46646357346 ps
CPU time 161.24 seconds
Started Aug 10 06:19:15 PM PDT 24
Finished Aug 10 06:21:56 PM PDT 24
Peak memory 270672 kb
Host smart-c7a64a91-d46e-477f-82a4-415b1e1c6980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336784969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1336784969
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.672463910
Short name T249
Test name
Test status
Simulation time 20907929658 ps
CPU time 37.54 seconds
Started Aug 10 06:19:20 PM PDT 24
Finished Aug 10 06:19:58 PM PDT 24
Peak memory 238072 kb
Host smart-a6477b98-3442-4004-ac44-ef7263df355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672463910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.672463910
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.410536685
Short name T261
Test name
Test status
Simulation time 52032951855 ps
CPU time 481.7 seconds
Started Aug 10 06:19:31 PM PDT 24
Finished Aug 10 06:27:33 PM PDT 24
Peak memory 255464 kb
Host smart-90e612e6-2f09-4387-b6fd-151b9ac1d253
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410536685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.410536685
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3922139460
Short name T181
Test name
Test status
Simulation time 256943449911 ps
CPU time 274.52 seconds
Started Aug 10 06:19:47 PM PDT 24
Finished Aug 10 06:24:22 PM PDT 24
Peak memory 255980 kb
Host smart-4535efc5-26ca-4a44-a3f9-2821575352c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922139460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3922139460
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4027711609
Short name T59
Test name
Test status
Simulation time 26919433699 ps
CPU time 277.11 seconds
Started Aug 10 06:20:38 PM PDT 24
Finished Aug 10 06:25:15 PM PDT 24
Peak memory 250212 kb
Host smart-72fcfdb3-8c3d-4391-a5c9-4256ee4234b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027711609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4027711609
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.441883242
Short name T1129
Test name
Test status
Simulation time 74807039 ps
CPU time 1.99 seconds
Started Aug 10 06:16:30 PM PDT 24
Finished Aug 10 06:16:32 PM PDT 24
Peak memory 215876 kb
Host smart-323d890d-6004-489e-a223-300e829e2cf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441883242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.441883242
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3573300580
Short name T82
Test name
Test status
Simulation time 35261364 ps
CPU time 1.1 seconds
Started Aug 10 06:16:45 PM PDT 24
Finished Aug 10 06:16:46 PM PDT 24
Peak memory 216636 kb
Host smart-0213ac6c-24ba-4978-9e82-d54cfdd0acf5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573300580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3573300580
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1058099013
Short name T86
Test name
Test status
Simulation time 6447138899 ps
CPU time 46.82 seconds
Started Aug 10 06:20:59 PM PDT 24
Finished Aug 10 06:21:46 PM PDT 24
Peak memory 250084 kb
Host smart-2370ca4c-466b-4032-91ce-6ae43304e4bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058099013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1058099013
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2744062081
Short name T52
Test name
Test status
Simulation time 3236391455 ps
CPU time 10.63 seconds
Started Aug 10 06:18:07 PM PDT 24
Finished Aug 10 06:18:18 PM PDT 24
Peak memory 241300 kb
Host smart-c5a0e803-38c3-454c-b2dc-361957d1ab53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744062081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2744062081
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1774785137
Short name T1067
Test name
Test status
Simulation time 319102752 ps
CPU time 8.46 seconds
Started Aug 10 06:16:30 PM PDT 24
Finished Aug 10 06:16:39 PM PDT 24
Peak memory 207360 kb
Host smart-dc351ec2-ccdd-478d-9d55-3dfe66f4070a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774785137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1774785137
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4173260942
Short name T1045
Test name
Test status
Simulation time 2762610616 ps
CPU time 12.97 seconds
Started Aug 10 06:16:32 PM PDT 24
Finished Aug 10 06:16:45 PM PDT 24
Peak memory 207536 kb
Host smart-d12b9a18-1dc9-41b3-883b-c640bd1e2d20
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173260942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4173260942
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.774338516
Short name T80
Test name
Test status
Simulation time 229914770 ps
CPU time 0.97 seconds
Started Aug 10 06:16:31 PM PDT 24
Finished Aug 10 06:16:32 PM PDT 24
Peak memory 207116 kb
Host smart-4e099b11-6e74-4f80-82b7-3905448e3c30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774338516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.774338516
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3464997990
Short name T1106
Test name
Test status
Simulation time 147170910 ps
CPU time 3.68 seconds
Started Aug 10 06:16:32 PM PDT 24
Finished Aug 10 06:16:36 PM PDT 24
Peak memory 218584 kb
Host smart-c1fb56e2-68b2-4806-a096-0583de13715a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464997990 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3464997990
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3135134897
Short name T124
Test name
Test status
Simulation time 40246155 ps
CPU time 2.46 seconds
Started Aug 10 06:16:31 PM PDT 24
Finished Aug 10 06:16:34 PM PDT 24
Peak memory 215560 kb
Host smart-c8d14326-6af4-419f-a01f-de6d45672131
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135134897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
135134897
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3666376985
Short name T1080
Test name
Test status
Simulation time 14046628 ps
CPU time 0.77 seconds
Started Aug 10 06:16:31 PM PDT 24
Finished Aug 10 06:16:32 PM PDT 24
Peak memory 204028 kb
Host smart-7bc4bcde-261e-40e6-9130-53ad928b5405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666376985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
666376985
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4106438411
Short name T126
Test name
Test status
Simulation time 150896729 ps
CPU time 1.3 seconds
Started Aug 10 06:16:30 PM PDT 24
Finished Aug 10 06:16:32 PM PDT 24
Peak memory 215496 kb
Host smart-58410926-db51-44b7-8c14-b479ea6c9a43
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106438411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.4106438411
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2189691905
Short name T1054
Test name
Test status
Simulation time 22735477 ps
CPU time 0.66 seconds
Started Aug 10 06:16:31 PM PDT 24
Finished Aug 10 06:16:32 PM PDT 24
Peak memory 203888 kb
Host smart-ad8b1bb1-6726-4476-ade6-220e06b14770
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189691905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2189691905
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4252423178
Short name T1136
Test name
Test status
Simulation time 431821424 ps
CPU time 2.9 seconds
Started Aug 10 06:16:32 PM PDT 24
Finished Aug 10 06:16:35 PM PDT 24
Peak memory 215432 kb
Host smart-d60b9fb3-8ea5-4bec-87fd-5bf5fdd6d122
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252423178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.4252423178
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2576193448
Short name T1114
Test name
Test status
Simulation time 547738961 ps
CPU time 7.28 seconds
Started Aug 10 06:16:34 PM PDT 24
Finished Aug 10 06:16:42 PM PDT 24
Peak memory 215932 kb
Host smart-5e93e87b-22bd-4e3f-884c-0da2b576da67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576193448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2576193448
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2930904007
Short name T117
Test name
Test status
Simulation time 1827373972 ps
CPU time 23.77 seconds
Started Aug 10 06:16:41 PM PDT 24
Finished Aug 10 06:17:05 PM PDT 24
Peak memory 215588 kb
Host smart-bd0a3861-560f-4a1d-a13b-231df24bb272
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930904007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2930904007
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1399175331
Short name T1071
Test name
Test status
Simulation time 609954458 ps
CPU time 13.1 seconds
Started Aug 10 06:16:39 PM PDT 24
Finished Aug 10 06:16:52 PM PDT 24
Peak memory 215568 kb
Host smart-fe365d76-26b1-43b2-b290-b998656364f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399175331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1399175331
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2243454869
Short name T81
Test name
Test status
Simulation time 63849644 ps
CPU time 1.09 seconds
Started Aug 10 06:16:30 PM PDT 24
Finished Aug 10 06:16:31 PM PDT 24
Peak memory 207332 kb
Host smart-5cc531ec-5b91-45db-bc40-88a504b042c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243454869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2243454869
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2279912674
Short name T1138
Test name
Test status
Simulation time 371887506 ps
CPU time 3.69 seconds
Started Aug 10 06:16:38 PM PDT 24
Finished Aug 10 06:16:42 PM PDT 24
Peak memory 217324 kb
Host smart-fad827c8-7985-4681-8a83-3052c3a018b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279912674 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2279912674
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1653178465
Short name T1061
Test name
Test status
Simulation time 146332140 ps
CPU time 1.35 seconds
Started Aug 10 06:16:34 PM PDT 24
Finished Aug 10 06:16:36 PM PDT 24
Peak memory 207376 kb
Host smart-ee7821b8-5817-43c0-aed7-5db2e17b74c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653178465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
653178465
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1044710915
Short name T1087
Test name
Test status
Simulation time 13039048 ps
CPU time 0.71 seconds
Started Aug 10 06:16:34 PM PDT 24
Finished Aug 10 06:16:35 PM PDT 24
Peak memory 203996 kb
Host smart-0bc53046-3269-4b91-b99c-736ca778bb93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044710915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
044710915
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2274489465
Short name T116
Test name
Test status
Simulation time 52839354 ps
CPU time 1.82 seconds
Started Aug 10 06:16:31 PM PDT 24
Finished Aug 10 06:16:33 PM PDT 24
Peak memory 215596 kb
Host smart-942f7d5c-bec0-4686-b91a-8f2d7e596923
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274489465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2274489465
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1769444344
Short name T1037
Test name
Test status
Simulation time 11657064 ps
CPU time 0.65 seconds
Started Aug 10 06:16:31 PM PDT 24
Finished Aug 10 06:16:32 PM PDT 24
Peak memory 203960 kb
Host smart-c8247f9e-2e47-4a9a-9a73-d608fc2e85d1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769444344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1769444344
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3935031947
Short name T1042
Test name
Test status
Simulation time 52827410 ps
CPU time 1.76 seconds
Started Aug 10 06:16:40 PM PDT 24
Finished Aug 10 06:16:42 PM PDT 24
Peak memory 215428 kb
Host smart-495af454-1c42-4cac-b79d-c0408f8eb2c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935031947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3935031947
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4055445088
Short name T106
Test name
Test status
Simulation time 58709249 ps
CPU time 3.32 seconds
Started Aug 10 06:16:32 PM PDT 24
Finished Aug 10 06:16:35 PM PDT 24
Peak memory 215892 kb
Host smart-dd7ad0c4-fb6e-4612-bd3b-2d608d52ec94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055445088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
055445088
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1500721364
Short name T276
Test name
Test status
Simulation time 689834199 ps
CPU time 5.98 seconds
Started Aug 10 06:16:31 PM PDT 24
Finished Aug 10 06:16:37 PM PDT 24
Peak memory 215752 kb
Host smart-b0aa72fd-65ea-401a-9fbe-677437536247
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500721364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1500721364
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3868054581
Short name T112
Test name
Test status
Simulation time 79713580 ps
CPU time 1.52 seconds
Started Aug 10 06:17:00 PM PDT 24
Finished Aug 10 06:17:02 PM PDT 24
Peak memory 216688 kb
Host smart-664f683c-623b-45c2-a6a9-1bf00e543fdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868054581 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3868054581
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3465753726
Short name T1142
Test name
Test status
Simulation time 413722247 ps
CPU time 2.61 seconds
Started Aug 10 06:16:59 PM PDT 24
Finished Aug 10 06:17:02 PM PDT 24
Peak memory 215588 kb
Host smart-febd5622-2852-4871-a973-4adaa1b4de32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465753726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3465753726
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2107399266
Short name T1100
Test name
Test status
Simulation time 36372757 ps
CPU time 0.69 seconds
Started Aug 10 06:16:59 PM PDT 24
Finished Aug 10 06:17:00 PM PDT 24
Peak memory 204268 kb
Host smart-a5910ba7-7c7f-4c7d-9468-5db2efbbb5d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107399266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2107399266
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3046110876
Short name T144
Test name
Test status
Simulation time 57391742 ps
CPU time 3.91 seconds
Started Aug 10 06:17:01 PM PDT 24
Finished Aug 10 06:17:05 PM PDT 24
Peak memory 215608 kb
Host smart-ba173c7f-b0f3-4950-990b-41691a318476
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046110876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3046110876
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3411390135
Short name T1117
Test name
Test status
Simulation time 4050146343 ps
CPU time 22.37 seconds
Started Aug 10 06:17:01 PM PDT 24
Finished Aug 10 06:17:23 PM PDT 24
Peak memory 217352 kb
Host smart-be18968a-87e2-4e0d-966f-d3cb3ef937e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411390135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3411390135
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4169195689
Short name T1064
Test name
Test status
Simulation time 454415959 ps
CPU time 3.3 seconds
Started Aug 10 06:17:07 PM PDT 24
Finished Aug 10 06:17:10 PM PDT 24
Peak memory 217440 kb
Host smart-3e6db1aa-94c8-49b9-bef3-fb996c180ace
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169195689 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4169195689
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2453664059
Short name T141
Test name
Test status
Simulation time 32575888 ps
CPU time 1.95 seconds
Started Aug 10 06:17:07 PM PDT 24
Finished Aug 10 06:17:10 PM PDT 24
Peak memory 207296 kb
Host smart-31c6fb6b-a2b8-4a24-8187-bb438bf9e461
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453664059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2453664059
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1696064019
Short name T1059
Test name
Test status
Simulation time 18768194 ps
CPU time 0.72 seconds
Started Aug 10 06:17:02 PM PDT 24
Finished Aug 10 06:17:03 PM PDT 24
Peak memory 204308 kb
Host smart-cef8d142-b4c7-463d-81d6-b433a4ea8d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696064019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1696064019
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.714893823
Short name T1137
Test name
Test status
Simulation time 156144629 ps
CPU time 2.8 seconds
Started Aug 10 06:17:07 PM PDT 24
Finished Aug 10 06:17:10 PM PDT 24
Peak memory 215484 kb
Host smart-215d2025-1fcb-4627-9a26-611689391760
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714893823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.714893823
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.59292722
Short name T97
Test name
Test status
Simulation time 42189645 ps
CPU time 2.52 seconds
Started Aug 10 06:16:59 PM PDT 24
Finished Aug 10 06:17:02 PM PDT 24
Peak memory 215760 kb
Host smart-174d661a-79c5-4625-a63a-3f4f70213da1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59292722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.59292722
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3425240929
Short name T101
Test name
Test status
Simulation time 143960107 ps
CPU time 4 seconds
Started Aug 10 06:17:07 PM PDT 24
Finished Aug 10 06:17:11 PM PDT 24
Peak memory 218540 kb
Host smart-6e7db320-9bba-4ea2-87e0-12c8a76fa8fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425240929 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3425240929
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1775479831
Short name T1120
Test name
Test status
Simulation time 44946812 ps
CPU time 1.35 seconds
Started Aug 10 06:17:08 PM PDT 24
Finished Aug 10 06:17:09 PM PDT 24
Peak memory 215532 kb
Host smart-1519d449-7097-4b8c-ae05-4a1df88bad2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775479831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1775479831
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.547305592
Short name T1049
Test name
Test status
Simulation time 23322673 ps
CPU time 0.7 seconds
Started Aug 10 06:17:09 PM PDT 24
Finished Aug 10 06:17:10 PM PDT 24
Peak memory 204024 kb
Host smart-7b4233fd-1e41-436f-8548-bbd4aa4be1fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547305592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.547305592
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.612184262
Short name T1076
Test name
Test status
Simulation time 58561641 ps
CPU time 3.46 seconds
Started Aug 10 06:17:10 PM PDT 24
Finished Aug 10 06:17:13 PM PDT 24
Peak memory 215556 kb
Host smart-e63a04f9-195e-4aa6-9ab8-dc2e81c0cc2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612184262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.612184262
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3539460126
Short name T95
Test name
Test status
Simulation time 3775305813 ps
CPU time 19.53 seconds
Started Aug 10 06:17:08 PM PDT 24
Finished Aug 10 06:17:28 PM PDT 24
Peak memory 215648 kb
Host smart-d2024a71-5f2a-4544-ad0a-37189f583456
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539460126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3539460126
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2114426869
Short name T155
Test name
Test status
Simulation time 106838974 ps
CPU time 2.62 seconds
Started Aug 10 06:17:11 PM PDT 24
Finished Aug 10 06:17:14 PM PDT 24
Peak memory 216544 kb
Host smart-1c7f7fa1-ee1e-4a5b-bfd6-0a7322f0c249
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114426869 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2114426869
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1018980319
Short name T1122
Test name
Test status
Simulation time 104394847 ps
CPU time 2.52 seconds
Started Aug 10 06:17:10 PM PDT 24
Finished Aug 10 06:17:13 PM PDT 24
Peak memory 220460 kb
Host smart-f2d89824-638f-454e-9557-f7d4328b7298
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018980319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1018980319
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4097580718
Short name T1069
Test name
Test status
Simulation time 51149482 ps
CPU time 0.72 seconds
Started Aug 10 06:17:09 PM PDT 24
Finished Aug 10 06:17:09 PM PDT 24
Peak memory 204384 kb
Host smart-ac668ea8-44cb-4157-92ba-921ddae4a0f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097580718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
4097580718
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1252249396
Short name T1068
Test name
Test status
Simulation time 26168959 ps
CPU time 1.81 seconds
Started Aug 10 06:17:08 PM PDT 24
Finished Aug 10 06:17:10 PM PDT 24
Peak memory 215580 kb
Host smart-6a1a1903-7d8c-495e-9bba-662d8bb61ae5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252249396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1252249396
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3490644108
Short name T1099
Test name
Test status
Simulation time 31035408 ps
CPU time 1.83 seconds
Started Aug 10 06:17:11 PM PDT 24
Finished Aug 10 06:17:13 PM PDT 24
Peak memory 215716 kb
Host smart-bb6be107-8fae-4fa7-92fa-610f83944451
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490644108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3490644108
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1029412655
Short name T273
Test name
Test status
Simulation time 4689079942 ps
CPU time 8.15 seconds
Started Aug 10 06:17:08 PM PDT 24
Finished Aug 10 06:17:16 PM PDT 24
Peak memory 215516 kb
Host smart-ef0c8ce9-514e-47b7-b16f-49a8a62665bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029412655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1029412655
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.325341147
Short name T1094
Test name
Test status
Simulation time 277214558 ps
CPU time 1.75 seconds
Started Aug 10 06:17:09 PM PDT 24
Finished Aug 10 06:17:11 PM PDT 24
Peak memory 215764 kb
Host smart-5cdd874c-f007-41a3-8ed5-ac0859e4417e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325341147 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.325341147
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.821196581
Short name T1130
Test name
Test status
Simulation time 82730502 ps
CPU time 2.57 seconds
Started Aug 10 06:17:08 PM PDT 24
Finished Aug 10 06:17:10 PM PDT 24
Peak memory 215524 kb
Host smart-3227f1db-c84f-4695-90f7-9a41fbbbc8e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821196581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.821196581
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2836303860
Short name T1104
Test name
Test status
Simulation time 50846117 ps
CPU time 0.73 seconds
Started Aug 10 06:17:10 PM PDT 24
Finished Aug 10 06:17:11 PM PDT 24
Peak memory 204380 kb
Host smart-e6f86728-113c-4b0d-8b1a-5a7ae17797f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836303860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2836303860
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3228355392
Short name T157
Test name
Test status
Simulation time 212855328 ps
CPU time 4.31 seconds
Started Aug 10 06:17:08 PM PDT 24
Finished Aug 10 06:17:12 PM PDT 24
Peak memory 215548 kb
Host smart-b32218bd-e4ee-4470-aa20-9757e40ec248
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228355392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3228355392
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3620464815
Short name T1132
Test name
Test status
Simulation time 184028677 ps
CPU time 3.16 seconds
Started Aug 10 06:17:08 PM PDT 24
Finished Aug 10 06:17:11 PM PDT 24
Peak memory 215772 kb
Host smart-0a8f8c7f-2dec-405a-803f-c3626e442e1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620464815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3620464815
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1970801349
Short name T1133
Test name
Test status
Simulation time 2708952163 ps
CPU time 13.07 seconds
Started Aug 10 06:17:10 PM PDT 24
Finished Aug 10 06:17:23 PM PDT 24
Peak memory 215748 kb
Host smart-dba438b2-fac3-4307-b20d-f3322d9337dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970801349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1970801349
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.851783923
Short name T1110
Test name
Test status
Simulation time 336602195 ps
CPU time 3.95 seconds
Started Aug 10 06:17:09 PM PDT 24
Finished Aug 10 06:17:13 PM PDT 24
Peak memory 218340 kb
Host smart-57e49ecc-423a-440f-8d64-50b06532148b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851783923 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.851783923
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4085384057
Short name T120
Test name
Test status
Simulation time 92239213 ps
CPU time 2.14 seconds
Started Aug 10 06:17:07 PM PDT 24
Finished Aug 10 06:17:09 PM PDT 24
Peak memory 215520 kb
Host smart-dabcbeab-f0d1-4a69-ad02-54c04debb178
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085384057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4085384057
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2165364075
Short name T1055
Test name
Test status
Simulation time 12845125 ps
CPU time 0.74 seconds
Started Aug 10 06:17:07 PM PDT 24
Finished Aug 10 06:17:08 PM PDT 24
Peak memory 204032 kb
Host smart-ffb2b4a4-530a-4aba-88e0-c7b580b9f0e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165364075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2165364075
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2790305953
Short name T1108
Test name
Test status
Simulation time 156692892 ps
CPU time 2.78 seconds
Started Aug 10 06:17:10 PM PDT 24
Finished Aug 10 06:17:13 PM PDT 24
Peak memory 215536 kb
Host smart-8e396cb5-86d2-4f0b-998b-e1f2bd948bfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790305953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2790305953
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1851342788
Short name T103
Test name
Test status
Simulation time 85107824 ps
CPU time 1.42 seconds
Started Aug 10 06:17:07 PM PDT 24
Finished Aug 10 06:17:09 PM PDT 24
Peak memory 215708 kb
Host smart-f9af9784-e1b1-4397-85af-102c8ce51132
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851342788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1851342788
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2075803899
Short name T1096
Test name
Test status
Simulation time 785288464 ps
CPU time 12.86 seconds
Started Aug 10 06:17:09 PM PDT 24
Finished Aug 10 06:17:22 PM PDT 24
Peak memory 215720 kb
Host smart-f676ac83-ec8a-4d6c-8f3b-a31587059c13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075803899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2075803899
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.79945189
Short name T1140
Test name
Test status
Simulation time 111229793 ps
CPU time 3.89 seconds
Started Aug 10 06:17:16 PM PDT 24
Finished Aug 10 06:17:20 PM PDT 24
Peak memory 217580 kb
Host smart-869f9122-0542-48f1-8cf9-a1888a669107
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79945189 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.79945189
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1418911209
Short name T1124
Test name
Test status
Simulation time 90738060 ps
CPU time 1.92 seconds
Started Aug 10 06:17:17 PM PDT 24
Finished Aug 10 06:17:19 PM PDT 24
Peak memory 215516 kb
Host smart-94bd3007-cc32-40ef-83f1-5d1054f11599
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418911209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1418911209
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3160631600
Short name T1051
Test name
Test status
Simulation time 38840416 ps
CPU time 0.69 seconds
Started Aug 10 06:17:11 PM PDT 24
Finished Aug 10 06:17:12 PM PDT 24
Peak memory 203892 kb
Host smart-4d35b8ed-fd3f-4310-88a3-da55b0c78b30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160631600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3160631600
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1259331980
Short name T1053
Test name
Test status
Simulation time 113327459 ps
CPU time 3.03 seconds
Started Aug 10 06:17:18 PM PDT 24
Finished Aug 10 06:17:21 PM PDT 24
Peak memory 215508 kb
Host smart-33fff1ba-e704-448b-902d-412f5cb48398
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259331980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1259331980
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4084775084
Short name T1091
Test name
Test status
Simulation time 192770153 ps
CPU time 4.2 seconds
Started Aug 10 06:17:08 PM PDT 24
Finished Aug 10 06:17:12 PM PDT 24
Peak memory 215784 kb
Host smart-d03d7489-9bcc-43aa-b9a0-201cc5974af4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084775084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
4084775084
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1522693660
Short name T94
Test name
Test status
Simulation time 88480130 ps
CPU time 1.7 seconds
Started Aug 10 06:17:15 PM PDT 24
Finished Aug 10 06:17:17 PM PDT 24
Peak memory 215604 kb
Host smart-3168a86f-a59a-4f58-ae51-60e609631858
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522693660 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1522693660
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3975158022
Short name T1118
Test name
Test status
Simulation time 101313756 ps
CPU time 2.76 seconds
Started Aug 10 06:17:16 PM PDT 24
Finished Aug 10 06:17:19 PM PDT 24
Peak memory 215596 kb
Host smart-0872436f-5a65-4b31-8c7d-fdbe73c72ef5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975158022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3975158022
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4005411747
Short name T1139
Test name
Test status
Simulation time 50440396 ps
CPU time 0.79 seconds
Started Aug 10 06:17:17 PM PDT 24
Finished Aug 10 06:17:18 PM PDT 24
Peak memory 204012 kb
Host smart-f93f32f0-6a5e-4140-8153-8e9585ab89fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005411747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
4005411747
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4199736503
Short name T143
Test name
Test status
Simulation time 156880851 ps
CPU time 2.72 seconds
Started Aug 10 06:17:16 PM PDT 24
Finished Aug 10 06:17:19 PM PDT 24
Peak memory 215560 kb
Host smart-f0a18ca6-5b15-4ea5-ba8d-fe725872039c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199736503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.4199736503
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.484484578
Short name T100
Test name
Test status
Simulation time 395539487 ps
CPU time 4.59 seconds
Started Aug 10 06:17:19 PM PDT 24
Finished Aug 10 06:17:24 PM PDT 24
Peak memory 215752 kb
Host smart-e1784a92-9a3e-4c3f-86c7-d333b9135e71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484484578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.484484578
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1323848602
Short name T92
Test name
Test status
Simulation time 624475202 ps
CPU time 7.15 seconds
Started Aug 10 06:17:16 PM PDT 24
Finished Aug 10 06:17:24 PM PDT 24
Peak memory 215928 kb
Host smart-e51cb363-5882-44d7-9d5f-d1cecc747343
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323848602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1323848602
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1291079415
Short name T1057
Test name
Test status
Simulation time 395761676 ps
CPU time 2.72 seconds
Started Aug 10 06:17:15 PM PDT 24
Finished Aug 10 06:17:18 PM PDT 24
Peak memory 216708 kb
Host smart-1187deeb-9adb-40e5-90a6-4952aaded71a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291079415 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1291079415
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1796578332
Short name T1058
Test name
Test status
Simulation time 70802335 ps
CPU time 1.35 seconds
Started Aug 10 06:17:16 PM PDT 24
Finished Aug 10 06:17:18 PM PDT 24
Peak memory 215560 kb
Host smart-95cd984e-6dd7-4f54-ada9-e2361cc7a4d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796578332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1796578332
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4074600844
Short name T1043
Test name
Test status
Simulation time 13432979 ps
CPU time 0.75 seconds
Started Aug 10 06:17:15 PM PDT 24
Finished Aug 10 06:17:16 PM PDT 24
Peak memory 204392 kb
Host smart-e8658162-7f54-4df8-a620-154e008c25e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074600844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
4074600844
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2757576567
Short name T165
Test name
Test status
Simulation time 1521454183 ps
CPU time 3.72 seconds
Started Aug 10 06:17:15 PM PDT 24
Finished Aug 10 06:17:18 PM PDT 24
Peak memory 215580 kb
Host smart-51138227-4513-4c22-829b-0f2903e6d08d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757576567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2757576567
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1411228479
Short name T270
Test name
Test status
Simulation time 344304982 ps
CPU time 4.56 seconds
Started Aug 10 06:17:19 PM PDT 24
Finished Aug 10 06:17:24 PM PDT 24
Peak memory 215784 kb
Host smart-f41414ad-369f-43fb-bbe9-64b70ae95e78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411228479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1411228479
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1236770725
Short name T278
Test name
Test status
Simulation time 1127549591 ps
CPU time 14.57 seconds
Started Aug 10 06:17:15 PM PDT 24
Finished Aug 10 06:17:30 PM PDT 24
Peak memory 215440 kb
Host smart-821810ca-295a-473c-804b-80422c7520f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236770725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1236770725
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3772213541
Short name T1066
Test name
Test status
Simulation time 218475525 ps
CPU time 3.93 seconds
Started Aug 10 06:17:21 PM PDT 24
Finished Aug 10 06:17:25 PM PDT 24
Peak memory 219336 kb
Host smart-3dbc1948-6e25-499b-9497-7ee770ad4b27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772213541 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3772213541
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2207235714
Short name T1072
Test name
Test status
Simulation time 37051067 ps
CPU time 1.34 seconds
Started Aug 10 06:17:18 PM PDT 24
Finished Aug 10 06:17:19 PM PDT 24
Peak memory 207276 kb
Host smart-3dab0d3c-01cd-4be0-b143-affc8e053a1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207235714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2207235714
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3465771554
Short name T1147
Test name
Test status
Simulation time 39750077 ps
CPU time 0.74 seconds
Started Aug 10 06:17:15 PM PDT 24
Finished Aug 10 06:17:15 PM PDT 24
Peak memory 204024 kb
Host smart-96ae9be0-b55a-444d-a50f-9e7f2223f803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465771554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3465771554
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3459532536
Short name T1095
Test name
Test status
Simulation time 134095779 ps
CPU time 1.89 seconds
Started Aug 10 06:17:17 PM PDT 24
Finished Aug 10 06:17:19 PM PDT 24
Peak memory 215492 kb
Host smart-c5ff906c-a44f-4329-8fb3-a90799ad5787
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459532536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3459532536
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2885848132
Short name T91
Test name
Test status
Simulation time 661050195 ps
CPU time 2.74 seconds
Started Aug 10 06:17:20 PM PDT 24
Finished Aug 10 06:17:23 PM PDT 24
Peak memory 215776 kb
Host smart-e609b53c-7bcb-4e16-85ac-5ab95411ba80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885848132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2885848132
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.196238145
Short name T274
Test name
Test status
Simulation time 1099942987 ps
CPU time 7.67 seconds
Started Aug 10 06:17:19 PM PDT 24
Finished Aug 10 06:17:27 PM PDT 24
Peak memory 215820 kb
Host smart-a37e719b-ed5d-419c-8c31-2785ad18484d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196238145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.196238145
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1296437795
Short name T127
Test name
Test status
Simulation time 829775153 ps
CPU time 14.29 seconds
Started Aug 10 06:16:39 PM PDT 24
Finished Aug 10 06:16:53 PM PDT 24
Peak memory 215608 kb
Host smart-d527e680-203e-4889-a102-e2883e099387
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296437795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1296437795
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1578868678
Short name T125
Test name
Test status
Simulation time 716413099 ps
CPU time 21.32 seconds
Started Aug 10 06:16:38 PM PDT 24
Finished Aug 10 06:17:00 PM PDT 24
Peak memory 207348 kb
Host smart-2b93c705-6656-408e-8ceb-99d3c3497ef5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578868678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1578868678
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1291615060
Short name T83
Test name
Test status
Simulation time 40619852 ps
CPU time 1.21 seconds
Started Aug 10 06:16:40 PM PDT 24
Finished Aug 10 06:16:41 PM PDT 24
Peak memory 207320 kb
Host smart-23334a43-c690-482d-b88d-6e47b05f04b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291615060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1291615060
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3169246668
Short name T1112
Test name
Test status
Simulation time 241759037 ps
CPU time 1.79 seconds
Started Aug 10 06:16:38 PM PDT 24
Finished Aug 10 06:16:40 PM PDT 24
Peak memory 215720 kb
Host smart-8598c973-acc2-4765-99fc-b852ba6926db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169246668 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3169246668
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3005619417
Short name T1103
Test name
Test status
Simulation time 14316110 ps
CPU time 0.66 seconds
Started Aug 10 06:16:39 PM PDT 24
Finished Aug 10 06:16:40 PM PDT 24
Peak memory 204392 kb
Host smart-75f7e256-9b36-42c4-bcf9-7ef842408759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005619417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
005619417
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2274022055
Short name T1090
Test name
Test status
Simulation time 113595712 ps
CPU time 1.26 seconds
Started Aug 10 06:16:40 PM PDT 24
Finished Aug 10 06:16:42 PM PDT 24
Peak memory 215524 kb
Host smart-ffdbbcae-59d2-48b2-a82c-53d904013267
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274022055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2274022055
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.155869668
Short name T1039
Test name
Test status
Simulation time 35511526 ps
CPU time 0.63 seconds
Started Aug 10 06:16:39 PM PDT 24
Finished Aug 10 06:16:40 PM PDT 24
Peak memory 204248 kb
Host smart-0431f04f-d9d6-4ec8-b0ff-805dd1d4f6c7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155869668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.155869668
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3561428856
Short name T156
Test name
Test status
Simulation time 297033491 ps
CPU time 4.4 seconds
Started Aug 10 06:16:40 PM PDT 24
Finished Aug 10 06:16:45 PM PDT 24
Peak memory 215504 kb
Host smart-0d8cd412-4f7f-4555-934e-863289b70e5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561428856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3561428856
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3647574281
Short name T1143
Test name
Test status
Simulation time 232201015 ps
CPU time 3.8 seconds
Started Aug 10 06:16:37 PM PDT 24
Finished Aug 10 06:16:41 PM PDT 24
Peak memory 215900 kb
Host smart-0cf29007-2ca5-4cc4-90ed-5475077892d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647574281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
647574281
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2493800870
Short name T1088
Test name
Test status
Simulation time 194317686 ps
CPU time 12.63 seconds
Started Aug 10 06:16:40 PM PDT 24
Finished Aug 10 06:16:53 PM PDT 24
Peak memory 215884 kb
Host smart-74c54768-a775-4130-87f5-0b9226d9ebb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493800870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2493800870
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2673232832
Short name T1128
Test name
Test status
Simulation time 17336481 ps
CPU time 0.7 seconds
Started Aug 10 06:17:15 PM PDT 24
Finished Aug 10 06:17:15 PM PDT 24
Peak memory 204052 kb
Host smart-7ab8582c-e9a8-4e2e-9b6f-bf59ed0a1f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673232832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2673232832
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4004352364
Short name T1047
Test name
Test status
Simulation time 14835792 ps
CPU time 0.76 seconds
Started Aug 10 06:17:17 PM PDT 24
Finished Aug 10 06:17:18 PM PDT 24
Peak memory 203916 kb
Host smart-6f4da8d6-3f59-4339-afd3-d2897e41676a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004352364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4004352364
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.349453623
Short name T1125
Test name
Test status
Simulation time 16972993 ps
CPU time 0.76 seconds
Started Aug 10 06:17:19 PM PDT 24
Finished Aug 10 06:17:20 PM PDT 24
Peak memory 204088 kb
Host smart-6975ae0b-f712-406c-b6c0-491d9009bd29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349453623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.349453623
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.33464958
Short name T1038
Test name
Test status
Simulation time 176179176 ps
CPU time 0.72 seconds
Started Aug 10 06:17:14 PM PDT 24
Finished Aug 10 06:17:15 PM PDT 24
Peak memory 204344 kb
Host smart-2f2b5095-b244-44b2-a71f-d8d17f5c323e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33464958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.33464958
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.769647739
Short name T1097
Test name
Test status
Simulation time 28993297 ps
CPU time 0.7 seconds
Started Aug 10 06:17:22 PM PDT 24
Finished Aug 10 06:17:23 PM PDT 24
Peak memory 204032 kb
Host smart-af56729d-56b2-42f2-a089-adc3d198754f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769647739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.769647739
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1938012026
Short name T1145
Test name
Test status
Simulation time 115914842 ps
CPU time 0.7 seconds
Started Aug 10 06:17:16 PM PDT 24
Finished Aug 10 06:17:17 PM PDT 24
Peak memory 204356 kb
Host smart-f9f3ca5a-342f-44e4-990e-3ee4b89e32ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938012026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1938012026
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3094297168
Short name T1101
Test name
Test status
Simulation time 14306964 ps
CPU time 0.76 seconds
Started Aug 10 06:17:17 PM PDT 24
Finished Aug 10 06:17:18 PM PDT 24
Peak memory 204000 kb
Host smart-4bf9fb86-f41e-41ac-88d5-c97d029cf104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094297168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3094297168
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3857589242
Short name T1085
Test name
Test status
Simulation time 57792483 ps
CPU time 0.77 seconds
Started Aug 10 06:17:17 PM PDT 24
Finished Aug 10 06:17:17 PM PDT 24
Peak memory 204064 kb
Host smart-8146848d-5cf4-40ac-9c6f-1db422329df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857589242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3857589242
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1727267470
Short name T1098
Test name
Test status
Simulation time 29692583 ps
CPU time 0.75 seconds
Started Aug 10 06:17:17 PM PDT 24
Finished Aug 10 06:17:18 PM PDT 24
Peak memory 204356 kb
Host smart-1caf162e-0f42-4060-a873-b0a04f10f13f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727267470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1727267470
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2157842385
Short name T1148
Test name
Test status
Simulation time 25498092 ps
CPU time 0.72 seconds
Started Aug 10 06:17:17 PM PDT 24
Finished Aug 10 06:17:18 PM PDT 24
Peak memory 204328 kb
Host smart-53ea9cfe-7534-44f8-b1ce-58ce14c4fd10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157842385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2157842385
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4187203751
Short name T128
Test name
Test status
Simulation time 618411530 ps
CPU time 16.04 seconds
Started Aug 10 06:16:36 PM PDT 24
Finished Aug 10 06:16:53 PM PDT 24
Peak memory 215556 kb
Host smart-27060410-2345-4992-93a4-e4e1e790ab5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187203751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.4187203751
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2748491006
Short name T115
Test name
Test status
Simulation time 11244073286 ps
CPU time 39.4 seconds
Started Aug 10 06:16:36 PM PDT 24
Finished Aug 10 06:17:16 PM PDT 24
Peak memory 215424 kb
Host smart-25e70bd6-7cda-4111-ae0a-fb58f8b89f35
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748491006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2748491006
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1793550609
Short name T1116
Test name
Test status
Simulation time 121536766 ps
CPU time 1.16 seconds
Started Aug 10 06:16:38 PM PDT 24
Finished Aug 10 06:16:40 PM PDT 24
Peak memory 216428 kb
Host smart-b24249d2-c9b0-4db7-a695-dda81bef0059
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793550609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1793550609
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1451452532
Short name T107
Test name
Test status
Simulation time 61070891 ps
CPU time 3.85 seconds
Started Aug 10 06:16:37 PM PDT 24
Finished Aug 10 06:16:41 PM PDT 24
Peak memory 217892 kb
Host smart-650f3384-729b-48bd-9be0-b5c676b1532d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451452532 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1451452532
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2519368220
Short name T1144
Test name
Test status
Simulation time 392450768 ps
CPU time 2.51 seconds
Started Aug 10 06:16:38 PM PDT 24
Finished Aug 10 06:16:41 PM PDT 24
Peak memory 215588 kb
Host smart-e04fb903-0136-4e2d-a254-a5b1c2f8a996
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519368220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
519368220
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2746012698
Short name T1092
Test name
Test status
Simulation time 34231696 ps
CPU time 0.68 seconds
Started Aug 10 06:16:36 PM PDT 24
Finished Aug 10 06:16:37 PM PDT 24
Peak memory 204244 kb
Host smart-f3385622-42fd-43b4-8e28-2d545c8dbf90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746012698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
746012698
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3837309861
Short name T119
Test name
Test status
Simulation time 17646978 ps
CPU time 1.25 seconds
Started Aug 10 06:16:38 PM PDT 24
Finished Aug 10 06:16:39 PM PDT 24
Peak memory 215572 kb
Host smart-fe19a9f6-b8c1-4778-ac1f-0f486c1642ca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837309861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3837309861
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3038580899
Short name T1073
Test name
Test status
Simulation time 12884536 ps
CPU time 0.64 seconds
Started Aug 10 06:16:38 PM PDT 24
Finished Aug 10 06:16:38 PM PDT 24
Peak memory 203964 kb
Host smart-c2dc700e-f340-4b80-89c3-a1a6a1a6a9d0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038580899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3038580899
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2148372708
Short name T140
Test name
Test status
Simulation time 192681760 ps
CPU time 4.08 seconds
Started Aug 10 06:16:38 PM PDT 24
Finished Aug 10 06:16:42 PM PDT 24
Peak memory 215528 kb
Host smart-5eb97165-0edd-4b7d-8b1b-bd17b817274b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148372708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2148372708
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2151829280
Short name T1131
Test name
Test status
Simulation time 970934122 ps
CPU time 4.22 seconds
Started Aug 10 06:16:38 PM PDT 24
Finished Aug 10 06:16:43 PM PDT 24
Peak memory 215792 kb
Host smart-d369de8a-446f-4e81-bcc2-e306de5fb5e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151829280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
151829280
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3517390889
Short name T275
Test name
Test status
Simulation time 1617777262 ps
CPU time 21.52 seconds
Started Aug 10 06:16:40 PM PDT 24
Finished Aug 10 06:17:02 PM PDT 24
Peak memory 215604 kb
Host smart-dea4381e-c7ab-46f7-ab09-2687323250ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517390889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3517390889
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3455903813
Short name T1126
Test name
Test status
Simulation time 15082164 ps
CPU time 0.74 seconds
Started Aug 10 06:17:16 PM PDT 24
Finished Aug 10 06:17:16 PM PDT 24
Peak memory 204056 kb
Host smart-d3829a32-5fe5-47c5-b3d1-785e63d8dd9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455903813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3455903813
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2960011972
Short name T1102
Test name
Test status
Simulation time 25299688 ps
CPU time 0.77 seconds
Started Aug 10 06:17:17 PM PDT 24
Finished Aug 10 06:17:18 PM PDT 24
Peak memory 203996 kb
Host smart-4c3f901e-7777-4357-9e20-dd3925c7a157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960011972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2960011972
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2393873810
Short name T1082
Test name
Test status
Simulation time 119315043 ps
CPU time 0.74 seconds
Started Aug 10 06:17:18 PM PDT 24
Finished Aug 10 06:17:19 PM PDT 24
Peak memory 204308 kb
Host smart-66e5d7a0-122f-4678-9ac9-8658e56507cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393873810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2393873810
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2329764782
Short name T1107
Test name
Test status
Simulation time 48940671 ps
CPU time 0.76 seconds
Started Aug 10 06:17:19 PM PDT 24
Finished Aug 10 06:17:20 PM PDT 24
Peak memory 203988 kb
Host smart-99ccf909-4bba-432c-952a-ff67df3f5d56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329764782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2329764782
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3820040829
Short name T1063
Test name
Test status
Simulation time 29006210 ps
CPU time 0.68 seconds
Started Aug 10 06:17:16 PM PDT 24
Finished Aug 10 06:17:17 PM PDT 24
Peak memory 204392 kb
Host smart-f89549c1-8585-4f78-9576-33d936452c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820040829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3820040829
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.759106377
Short name T1070
Test name
Test status
Simulation time 52701136 ps
CPU time 0.76 seconds
Started Aug 10 06:17:17 PM PDT 24
Finished Aug 10 06:17:18 PM PDT 24
Peak memory 204072 kb
Host smart-ace8cdad-a59c-45d3-aef5-c713b9ac53ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759106377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.759106377
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.565253457
Short name T1060
Test name
Test status
Simulation time 57918530 ps
CPU time 0.78 seconds
Started Aug 10 06:17:19 PM PDT 24
Finished Aug 10 06:17:20 PM PDT 24
Peak memory 204004 kb
Host smart-da057acc-4c40-433d-8949-a6a1c8bbc362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565253457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.565253457
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1747597138
Short name T1041
Test name
Test status
Simulation time 14370705 ps
CPU time 0.73 seconds
Started Aug 10 06:17:18 PM PDT 24
Finished Aug 10 06:17:19 PM PDT 24
Peak memory 204372 kb
Host smart-74f78e8d-1847-4e54-897b-5253d064c96e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747597138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1747597138
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.406199323
Short name T1127
Test name
Test status
Simulation time 50092553 ps
CPU time 0.77 seconds
Started Aug 10 06:17:17 PM PDT 24
Finished Aug 10 06:17:18 PM PDT 24
Peak memory 204312 kb
Host smart-c43e7aac-46ae-4bbd-a971-7614bc9e1a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406199323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.406199323
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2104730897
Short name T1084
Test name
Test status
Simulation time 54512792 ps
CPU time 0.79 seconds
Started Aug 10 06:17:24 PM PDT 24
Finished Aug 10 06:17:25 PM PDT 24
Peak memory 204024 kb
Host smart-09d4ce5e-ede4-484e-950e-2be8591981d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104730897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2104730897
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2658982613
Short name T123
Test name
Test status
Simulation time 205053918 ps
CPU time 7.52 seconds
Started Aug 10 06:16:45 PM PDT 24
Finished Aug 10 06:16:53 PM PDT 24
Peak memory 215572 kb
Host smart-2d1a8fd6-df2d-4fc9-abb7-621578bdd374
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658982613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2658982613
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.247456208
Short name T1105
Test name
Test status
Simulation time 3802790722 ps
CPU time 14.38 seconds
Started Aug 10 06:16:44 PM PDT 24
Finished Aug 10 06:16:59 PM PDT 24
Peak memory 207536 kb
Host smart-42f9c099-d61d-4dbb-a6b0-b3ecdf81f6ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247456208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.247456208
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2109677262
Short name T122
Test name
Test status
Simulation time 358383251 ps
CPU time 2.42 seconds
Started Aug 10 06:16:45 PM PDT 24
Finished Aug 10 06:16:47 PM PDT 24
Peak memory 215504 kb
Host smart-f961fd2e-6853-4616-9ed8-112d81f7b3a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109677262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
109677262
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2283915559
Short name T1062
Test name
Test status
Simulation time 16948720 ps
CPU time 0.74 seconds
Started Aug 10 06:16:48 PM PDT 24
Finished Aug 10 06:16:49 PM PDT 24
Peak memory 203896 kb
Host smart-cb81de0a-91d3-4c06-b573-018826458f8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283915559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
283915559
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3965304056
Short name T1134
Test name
Test status
Simulation time 116689074 ps
CPU time 1.36 seconds
Started Aug 10 06:16:45 PM PDT 24
Finished Aug 10 06:16:46 PM PDT 24
Peak memory 215568 kb
Host smart-bc9bec76-168a-4eeb-9786-6001fc4f463f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965304056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3965304056
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.769559742
Short name T1113
Test name
Test status
Simulation time 19163474 ps
CPU time 0.65 seconds
Started Aug 10 06:16:46 PM PDT 24
Finished Aug 10 06:16:46 PM PDT 24
Peak memory 203988 kb
Host smart-16ef100c-d44e-42ef-8a02-bf6cac46191a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769559742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.769559742
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3854732970
Short name T1052
Test name
Test status
Simulation time 65124803 ps
CPU time 1.94 seconds
Started Aug 10 06:16:48 PM PDT 24
Finished Aug 10 06:16:50 PM PDT 24
Peak memory 215480 kb
Host smart-4135b5d0-9eca-4616-9945-4a19a55b8f66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854732970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3854732970
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3739908447
Short name T104
Test name
Test status
Simulation time 47157689 ps
CPU time 2.79 seconds
Started Aug 10 06:16:44 PM PDT 24
Finished Aug 10 06:16:47 PM PDT 24
Peak memory 215728 kb
Host smart-2fef582d-a222-4489-979b-501de84a7a5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739908447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
739908447
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2385405486
Short name T1086
Test name
Test status
Simulation time 14402989 ps
CPU time 0.77 seconds
Started Aug 10 06:17:27 PM PDT 24
Finished Aug 10 06:17:28 PM PDT 24
Peak memory 204324 kb
Host smart-40a606c9-6822-4182-bb54-bb89ad5d7e5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385405486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2385405486
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1859346187
Short name T1040
Test name
Test status
Simulation time 54266757 ps
CPU time 0.75 seconds
Started Aug 10 06:17:25 PM PDT 24
Finished Aug 10 06:17:26 PM PDT 24
Peak memory 204024 kb
Host smart-961f1e74-061a-411f-af04-6aaefecf9003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859346187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1859346187
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4120274757
Short name T1036
Test name
Test status
Simulation time 52450591 ps
CPU time 0.75 seconds
Started Aug 10 06:17:23 PM PDT 24
Finished Aug 10 06:17:24 PM PDT 24
Peak memory 204032 kb
Host smart-9cf2d723-dcc5-4a97-b020-7ccd6ffc4db9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120274757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4120274757
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3444283714
Short name T1048
Test name
Test status
Simulation time 37392627 ps
CPU time 0.69 seconds
Started Aug 10 06:17:24 PM PDT 24
Finished Aug 10 06:17:24 PM PDT 24
Peak memory 204016 kb
Host smart-82e78ac1-1cea-4d07-8181-9c171ac9894c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444283714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3444283714
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4005142063
Short name T1121
Test name
Test status
Simulation time 13942974 ps
CPU time 0.76 seconds
Started Aug 10 06:17:22 PM PDT 24
Finished Aug 10 06:17:24 PM PDT 24
Peak memory 204004 kb
Host smart-69948f48-3161-4bb1-8368-9a25dec6d6b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005142063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
4005142063
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3103942438
Short name T1135
Test name
Test status
Simulation time 20221543 ps
CPU time 0.69 seconds
Started Aug 10 06:17:24 PM PDT 24
Finished Aug 10 06:17:25 PM PDT 24
Peak memory 204068 kb
Host smart-98ea2e7a-0edf-4bfd-8f99-65d113991c72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103942438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3103942438
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.468169384
Short name T1093
Test name
Test status
Simulation time 11366942 ps
CPU time 0.74 seconds
Started Aug 10 06:17:24 PM PDT 24
Finished Aug 10 06:17:24 PM PDT 24
Peak memory 203984 kb
Host smart-ed9e07cf-07f4-496a-8c96-40ae49d9bdee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468169384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.468169384
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1668819162
Short name T1141
Test name
Test status
Simulation time 22382392 ps
CPU time 0.75 seconds
Started Aug 10 06:17:25 PM PDT 24
Finished Aug 10 06:17:26 PM PDT 24
Peak memory 204004 kb
Host smart-2cf5facc-8b0c-4806-997e-e70bd25be11f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668819162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1668819162
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2589293825
Short name T1081
Test name
Test status
Simulation time 33635728 ps
CPU time 0.68 seconds
Started Aug 10 06:17:22 PM PDT 24
Finished Aug 10 06:17:23 PM PDT 24
Peak memory 204284 kb
Host smart-e35ec924-f0bb-4b65-ba42-66e83f688d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589293825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2589293825
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4235441354
Short name T1123
Test name
Test status
Simulation time 170184318 ps
CPU time 0.7 seconds
Started Aug 10 06:17:24 PM PDT 24
Finished Aug 10 06:17:25 PM PDT 24
Peak memory 204004 kb
Host smart-83db9dde-507d-4911-a280-8953676ee7d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235441354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
4235441354
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1980312328
Short name T1083
Test name
Test status
Simulation time 89232520 ps
CPU time 2.86 seconds
Started Aug 10 06:16:52 PM PDT 24
Finished Aug 10 06:16:55 PM PDT 24
Peak memory 216960 kb
Host smart-099ac72d-7144-4428-9ac6-feae9db3ce9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980312328 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1980312328
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3564269444
Short name T154
Test name
Test status
Simulation time 183166402 ps
CPU time 1.34 seconds
Started Aug 10 06:16:54 PM PDT 24
Finished Aug 10 06:16:56 PM PDT 24
Peak memory 215512 kb
Host smart-8b6fc69d-6a2e-4b63-93a7-ef3bb82a58ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564269444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
564269444
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1749887124
Short name T1111
Test name
Test status
Simulation time 26640587 ps
CPU time 0.7 seconds
Started Aug 10 06:16:56 PM PDT 24
Finished Aug 10 06:16:57 PM PDT 24
Peak memory 204024 kb
Host smart-5a639cb5-3221-43e9-9689-ae8bb540ff85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749887124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
749887124
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2059763606
Short name T1050
Test name
Test status
Simulation time 208740373 ps
CPU time 1.62 seconds
Started Aug 10 06:16:51 PM PDT 24
Finished Aug 10 06:16:52 PM PDT 24
Peak memory 215532 kb
Host smart-cdfb0c72-3422-417e-a95d-6db9a4f1e27f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059763606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2059763606
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3008390831
Short name T108
Test name
Test status
Simulation time 402364665 ps
CPU time 4.42 seconds
Started Aug 10 06:16:53 PM PDT 24
Finished Aug 10 06:16:57 PM PDT 24
Peak memory 215736 kb
Host smart-ceeac5a7-cb88-4d0c-8283-faa32430c885
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008390831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
008390831
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3741278904
Short name T90
Test name
Test status
Simulation time 1133973097 ps
CPU time 14.2 seconds
Started Aug 10 06:16:53 PM PDT 24
Finished Aug 10 06:17:08 PM PDT 24
Peak memory 215804 kb
Host smart-dbde58e4-ccd2-4473-b913-78c59fe013f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741278904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3741278904
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3068168952
Short name T158
Test name
Test status
Simulation time 146205855 ps
CPU time 1.74 seconds
Started Aug 10 06:16:52 PM PDT 24
Finished Aug 10 06:16:54 PM PDT 24
Peak memory 215696 kb
Host smart-1d7fcc7b-8bd9-46f0-aa70-5bd6b2bba696
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068168952 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3068168952
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1714834760
Short name T1109
Test name
Test status
Simulation time 49052441 ps
CPU time 1.91 seconds
Started Aug 10 06:16:54 PM PDT 24
Finished Aug 10 06:16:56 PM PDT 24
Peak memory 215572 kb
Host smart-1841738a-83e9-417f-82f5-392d574afdac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714834760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
714834760
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2879880416
Short name T1056
Test name
Test status
Simulation time 37027699 ps
CPU time 0.73 seconds
Started Aug 10 06:16:52 PM PDT 24
Finished Aug 10 06:16:53 PM PDT 24
Peak memory 204308 kb
Host smart-2e7d598b-1a76-426c-bee7-db91a1b950d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879880416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
879880416
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1480429323
Short name T1074
Test name
Test status
Simulation time 106744115 ps
CPU time 1.69 seconds
Started Aug 10 06:16:52 PM PDT 24
Finished Aug 10 06:16:53 PM PDT 24
Peak memory 215632 kb
Host smart-7000971a-22c6-4ba0-88c5-0cdacab7672e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480429323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1480429323
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2973166888
Short name T102
Test name
Test status
Simulation time 576490411 ps
CPU time 3.94 seconds
Started Aug 10 06:16:52 PM PDT 24
Finished Aug 10 06:16:56 PM PDT 24
Peak memory 216836 kb
Host smart-19a4cc4f-74bd-45ca-89e7-17c2593a53cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973166888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
973166888
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1792427859
Short name T277
Test name
Test status
Simulation time 1678314948 ps
CPU time 6.58 seconds
Started Aug 10 06:16:53 PM PDT 24
Finished Aug 10 06:17:00 PM PDT 24
Peak memory 215880 kb
Host smart-727fd4eb-4bcb-49d5-946a-2e21094b1762
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792427859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1792427859
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2290194553
Short name T1077
Test name
Test status
Simulation time 54006960 ps
CPU time 1.75 seconds
Started Aug 10 06:16:52 PM PDT 24
Finished Aug 10 06:16:54 PM PDT 24
Peak memory 215668 kb
Host smart-fb393aa6-257e-48bd-9591-9996f05bde71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290194553 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2290194553
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2260884461
Short name T1078
Test name
Test status
Simulation time 210374984 ps
CPU time 1.19 seconds
Started Aug 10 06:16:51 PM PDT 24
Finished Aug 10 06:16:52 PM PDT 24
Peak memory 215556 kb
Host smart-29a0df6a-48a4-4727-b67b-68df7ae2fa60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260884461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
260884461
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2538023041
Short name T1075
Test name
Test status
Simulation time 107051135 ps
CPU time 0.69 seconds
Started Aug 10 06:16:56 PM PDT 24
Finished Aug 10 06:16:57 PM PDT 24
Peak memory 204040 kb
Host smart-bdabbcb0-b2cc-4e53-b158-da6b4c5d172f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538023041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
538023041
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2798505245
Short name T1065
Test name
Test status
Simulation time 28358085 ps
CPU time 2.13 seconds
Started Aug 10 06:16:53 PM PDT 24
Finished Aug 10 06:16:55 PM PDT 24
Peak memory 215568 kb
Host smart-464e2005-ad35-41f3-8841-82ea31653ce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798505245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2798505245
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3217900643
Short name T111
Test name
Test status
Simulation time 23010772 ps
CPU time 1.57 seconds
Started Aug 10 06:16:53 PM PDT 24
Finished Aug 10 06:16:55 PM PDT 24
Peak memory 216868 kb
Host smart-147798ff-9eb3-457f-9de1-51fc77e3b68b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217900643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
217900643
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2773811993
Short name T1089
Test name
Test status
Simulation time 1144237633 ps
CPU time 7.71 seconds
Started Aug 10 06:16:55 PM PDT 24
Finished Aug 10 06:17:03 PM PDT 24
Peak memory 216980 kb
Host smart-b3e48e60-2765-4db6-b4bd-8ee05c7ce9b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773811993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2773811993
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2090895535
Short name T96
Test name
Test status
Simulation time 152937070 ps
CPU time 2.84 seconds
Started Aug 10 06:17:01 PM PDT 24
Finished Aug 10 06:17:05 PM PDT 24
Peak memory 217004 kb
Host smart-9c4732ad-8172-4c0c-bddb-dfec88e5da94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090895535 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2090895535
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1111562296
Short name T1079
Test name
Test status
Simulation time 65072190 ps
CPU time 2.47 seconds
Started Aug 10 06:16:59 PM PDT 24
Finished Aug 10 06:17:02 PM PDT 24
Peak memory 207524 kb
Host smart-7d14ceb0-b919-4ee7-aad9-b90d64b0a0ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111562296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
111562296
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.86879486
Short name T1046
Test name
Test status
Simulation time 28044066 ps
CPU time 0.69 seconds
Started Aug 10 06:16:58 PM PDT 24
Finished Aug 10 06:16:59 PM PDT 24
Peak memory 204028 kb
Host smart-f29ca6b6-dc9a-42e0-9291-ad4b3a592f7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86879486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.86879486
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.499258872
Short name T1044
Test name
Test status
Simulation time 26136037 ps
CPU time 1.51 seconds
Started Aug 10 06:16:58 PM PDT 24
Finished Aug 10 06:17:00 PM PDT 24
Peak memory 215544 kb
Host smart-eed5cfb9-7be9-4547-ab64-5fd4fbe294e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499258872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.499258872
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2252792045
Short name T1119
Test name
Test status
Simulation time 8977818097 ps
CPU time 20.41 seconds
Started Aug 10 06:16:58 PM PDT 24
Finished Aug 10 06:17:18 PM PDT 24
Peak memory 216168 kb
Host smart-f9f1c4d3-65bd-45f0-a3bf-6a4e50800e57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252792045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2252792045
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1099165598
Short name T1146
Test name
Test status
Simulation time 280297827 ps
CPU time 3.34 seconds
Started Aug 10 06:17:03 PM PDT 24
Finished Aug 10 06:17:06 PM PDT 24
Peak memory 217176 kb
Host smart-cb3685e8-6091-48d0-af51-bc7fe432dae4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099165598 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1099165598
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1151433183
Short name T118
Test name
Test status
Simulation time 132476982 ps
CPU time 2.74 seconds
Started Aug 10 06:16:59 PM PDT 24
Finished Aug 10 06:17:02 PM PDT 24
Peak memory 215496 kb
Host smart-0c4787e9-d412-4d32-abe2-c49cc5334538
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151433183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
151433183
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3386999922
Short name T1115
Test name
Test status
Simulation time 27138082 ps
CPU time 0.79 seconds
Started Aug 10 06:17:00 PM PDT 24
Finished Aug 10 06:17:01 PM PDT 24
Peak memory 204008 kb
Host smart-2e3ad23d-9d79-431d-9911-7ab7f5246399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386999922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
386999922
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.711680339
Short name T142
Test name
Test status
Simulation time 212494086 ps
CPU time 2.59 seconds
Started Aug 10 06:16:59 PM PDT 24
Finished Aug 10 06:17:02 PM PDT 24
Peak memory 215580 kb
Host smart-b53387af-3247-43c2-a6f9-73d720a4540c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711680339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.711680339
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4071418056
Short name T105
Test name
Test status
Simulation time 133114317 ps
CPU time 2.04 seconds
Started Aug 10 06:16:57 PM PDT 24
Finished Aug 10 06:16:59 PM PDT 24
Peak memory 215708 kb
Host smart-672b29a9-da4d-4eb5-abbb-2eab40eb3d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071418056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
071418056
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4009974312
Short name T279
Test name
Test status
Simulation time 3464974029 ps
CPU time 22.26 seconds
Started Aug 10 06:16:58 PM PDT 24
Finished Aug 10 06:17:21 PM PDT 24
Peak memory 215692 kb
Host smart-189c5454-3924-42b1-b481-505ae4f0b29d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009974312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.4009974312
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.433311061
Short name T459
Test name
Test status
Simulation time 42794830 ps
CPU time 0.73 seconds
Started Aug 10 06:18:10 PM PDT 24
Finished Aug 10 06:18:11 PM PDT 24
Peak memory 205248 kb
Host smart-755a3e50-a2ed-4cb5-bc40-a25afc044740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433311061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.433311061
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.433336582
Short name T850
Test name
Test status
Simulation time 172806551 ps
CPU time 2.44 seconds
Started Aug 10 06:18:05 PM PDT 24
Finished Aug 10 06:18:08 PM PDT 24
Peak memory 233376 kb
Host smart-1398b76a-f7de-4a5c-9569-bbfce71ee7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433336582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.433336582
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2227876397
Short name T791
Test name
Test status
Simulation time 15182285 ps
CPU time 0.79 seconds
Started Aug 10 06:18:03 PM PDT 24
Finished Aug 10 06:18:04 PM PDT 24
Peak memory 207412 kb
Host smart-76368f5f-ce9d-4f2a-b186-3f7c4bc2b3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227876397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2227876397
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4088906033
Short name T493
Test name
Test status
Simulation time 85601188409 ps
CPU time 121.07 seconds
Started Aug 10 06:18:03 PM PDT 24
Finished Aug 10 06:20:04 PM PDT 24
Peak memory 254748 kb
Host smart-bbcf9815-a8b2-4a00-b220-2300097305ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088906033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4088906033
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.4154290939
Short name T38
Test name
Test status
Simulation time 10067032068 ps
CPU time 28.18 seconds
Started Aug 10 06:18:04 PM PDT 24
Finished Aug 10 06:18:33 PM PDT 24
Peak memory 218260 kb
Host smart-da16e949-ce6f-43dc-a8e0-25ec397fc163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154290939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.4154290939
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.4249507978
Short name T224
Test name
Test status
Simulation time 55933756898 ps
CPU time 152.03 seconds
Started Aug 10 06:18:06 PM PDT 24
Finished Aug 10 06:20:38 PM PDT 24
Peak memory 256728 kb
Host smart-1330b07c-c87e-42c2-9687-dbef227828d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249507978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.4249507978
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3400952315
Short name T729
Test name
Test status
Simulation time 18196019412 ps
CPU time 133.9 seconds
Started Aug 10 06:18:04 PM PDT 24
Finished Aug 10 06:20:18 PM PDT 24
Peak memory 241672 kb
Host smart-548158e9-f753-49bc-9c78-f417be366182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400952315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3400952315
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3799338116
Short name T975
Test name
Test status
Simulation time 311045742 ps
CPU time 4.87 seconds
Started Aug 10 06:18:03 PM PDT 24
Finished Aug 10 06:18:08 PM PDT 24
Peak memory 233424 kb
Host smart-cf164ba2-0127-40aa-b870-4fd81a4b7ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799338116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3799338116
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1175433076
Short name T320
Test name
Test status
Simulation time 79235539943 ps
CPU time 64.35 seconds
Started Aug 10 06:18:04 PM PDT 24
Finished Aug 10 06:19:08 PM PDT 24
Peak memory 241512 kb
Host smart-659f3dd1-c46a-42ba-bf49-3bfd69d0f69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175433076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1175433076
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4011170056
Short name T244
Test name
Test status
Simulation time 6805443909 ps
CPU time 12.26 seconds
Started Aug 10 06:18:02 PM PDT 24
Finished Aug 10 06:18:14 PM PDT 24
Peak memory 225328 kb
Host smart-8df59944-db59-4bdb-b7b4-64df363a222e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011170056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4011170056
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2231821971
Short name T9
Test name
Test status
Simulation time 4541240328 ps
CPU time 4.97 seconds
Started Aug 10 06:18:04 PM PDT 24
Finished Aug 10 06:18:09 PM PDT 24
Peak memory 225332 kb
Host smart-15e9c47f-3c9c-4457-99d6-8146b4c99488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231821971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2231821971
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3006873589
Short name T467
Test name
Test status
Simulation time 112279696 ps
CPU time 4.1 seconds
Started Aug 10 06:18:01 PM PDT 24
Finished Aug 10 06:18:05 PM PDT 24
Peak memory 220572 kb
Host smart-d8f43578-8b92-4d73-bb87-40c28f9dcaab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3006873589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3006873589
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2234598701
Short name T68
Test name
Test status
Simulation time 642154160 ps
CPU time 1.15 seconds
Started Aug 10 06:18:08 PM PDT 24
Finished Aug 10 06:18:09 PM PDT 24
Peak memory 235580 kb
Host smart-ddc9fb6b-eceb-46b5-950a-08ebfe18890b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234598701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2234598701
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3209653567
Short name T876
Test name
Test status
Simulation time 49184940908 ps
CPU time 241.61 seconds
Started Aug 10 06:18:07 PM PDT 24
Finished Aug 10 06:22:09 PM PDT 24
Peak memory 266324 kb
Host smart-c681f253-7487-47bd-b534-6e6223b4da6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209653567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3209653567
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3979393348
Short name T30
Test name
Test status
Simulation time 2748182661 ps
CPU time 25.19 seconds
Started Aug 10 06:18:03 PM PDT 24
Finished Aug 10 06:18:29 PM PDT 24
Peak memory 217188 kb
Host smart-b5a6dea2-dcb7-4728-b258-7fb2fe8bed1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979393348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3979393348
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.4180059331
Short name T517
Test name
Test status
Simulation time 4744736720 ps
CPU time 5.38 seconds
Started Aug 10 06:18:00 PM PDT 24
Finished Aug 10 06:18:05 PM PDT 24
Peak memory 217040 kb
Host smart-4a6c0cea-f192-4159-b913-be2ace85156b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180059331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.4180059331
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1860904038
Short name T361
Test name
Test status
Simulation time 10887282 ps
CPU time 0.66 seconds
Started Aug 10 06:18:03 PM PDT 24
Finished Aug 10 06:18:04 PM PDT 24
Peak memory 206124 kb
Host smart-27c33ed3-819a-4fa7-8425-585ae2b8f68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860904038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1860904038
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1393729350
Short name T479
Test name
Test status
Simulation time 17854333 ps
CPU time 0.73 seconds
Started Aug 10 06:18:07 PM PDT 24
Finished Aug 10 06:18:08 PM PDT 24
Peak memory 206596 kb
Host smart-52a83181-4bb9-4e18-82ca-246f46ba9b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393729350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1393729350
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1519702498
Short name T665
Test name
Test status
Simulation time 1377111756 ps
CPU time 5.58 seconds
Started Aug 10 06:18:07 PM PDT 24
Finished Aug 10 06:18:13 PM PDT 24
Peak memory 233388 kb
Host smart-8d8f0fee-4cdf-4f51-b800-6ab3aaf63c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519702498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1519702498
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3437491446
Short name T406
Test name
Test status
Simulation time 40695979 ps
CPU time 0.74 seconds
Started Aug 10 06:18:07 PM PDT 24
Finished Aug 10 06:18:08 PM PDT 24
Peak memory 205320 kb
Host smart-1e1f3b7e-3307-46ea-be91-727443c5a345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437491446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
437491446
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.769489273
Short name T737
Test name
Test status
Simulation time 1566058073 ps
CPU time 5.01 seconds
Started Aug 10 06:18:07 PM PDT 24
Finished Aug 10 06:18:12 PM PDT 24
Peak memory 225232 kb
Host smart-41478053-1f4e-4e66-ad19-51ec56188cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769489273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.769489273
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.609369598
Short name T1007
Test name
Test status
Simulation time 63892045 ps
CPU time 0.79 seconds
Started Aug 10 06:18:08 PM PDT 24
Finished Aug 10 06:18:09 PM PDT 24
Peak memory 207356 kb
Host smart-ae1702df-0ebc-4797-8c10-3672dcf075cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609369598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.609369598
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1454830361
Short name T173
Test name
Test status
Simulation time 22204798391 ps
CPU time 178.21 seconds
Started Aug 10 06:18:06 PM PDT 24
Finished Aug 10 06:21:05 PM PDT 24
Peak memory 249896 kb
Host smart-677be59b-fbde-47c2-a9d2-08433423a500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454830361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1454830361
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.4126805595
Short name T32
Test name
Test status
Simulation time 103147007043 ps
CPU time 260.07 seconds
Started Aug 10 06:18:07 PM PDT 24
Finished Aug 10 06:22:27 PM PDT 24
Peak memory 262960 kb
Host smart-997047ee-3e39-48f6-b283-4b7fa16cd6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126805595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.4126805595
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1557128061
Short name T726
Test name
Test status
Simulation time 24266207196 ps
CPU time 74.9 seconds
Started Aug 10 06:18:07 PM PDT 24
Finished Aug 10 06:19:22 PM PDT 24
Peak memory 241760 kb
Host smart-04063e20-cedd-42f7-ab7d-5cd53339508b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557128061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1557128061
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2590178256
Short name T324
Test name
Test status
Simulation time 1475199343 ps
CPU time 15.61 seconds
Started Aug 10 06:18:05 PM PDT 24
Finished Aug 10 06:18:20 PM PDT 24
Peak memory 233436 kb
Host smart-35734028-c53b-44e7-a9f5-1122d07f984b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590178256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2590178256
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.829475186
Short name T957
Test name
Test status
Simulation time 811144843 ps
CPU time 3.88 seconds
Started Aug 10 06:18:05 PM PDT 24
Finished Aug 10 06:18:09 PM PDT 24
Peak memory 225180 kb
Host smart-f197ee1d-e1b6-492d-bba9-349a69813990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829475186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.829475186
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3909166966
Short name T619
Test name
Test status
Simulation time 696573965 ps
CPU time 8.86 seconds
Started Aug 10 06:18:08 PM PDT 24
Finished Aug 10 06:18:17 PM PDT 24
Peak memory 249660 kb
Host smart-4d48b791-025d-4430-af94-b7f60fb22b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909166966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3909166966
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2504650233
Short name T906
Test name
Test status
Simulation time 60605477 ps
CPU time 1.05 seconds
Started Aug 10 06:18:06 PM PDT 24
Finished Aug 10 06:18:07 PM PDT 24
Peak memory 218500 kb
Host smart-2f8bdafc-b953-4c63-9c8f-23cd066b974d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504650233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2504650233
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2249698963
Short name T237
Test name
Test status
Simulation time 434877901 ps
CPU time 4.47 seconds
Started Aug 10 06:18:10 PM PDT 24
Finished Aug 10 06:18:14 PM PDT 24
Peak memory 225168 kb
Host smart-e40e4e5c-2522-4520-a0fd-4b2f25cfe8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249698963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2249698963
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.218093539
Short name T821
Test name
Test status
Simulation time 346051786 ps
CPU time 2.16 seconds
Started Aug 10 06:18:07 PM PDT 24
Finished Aug 10 06:18:10 PM PDT 24
Peak memory 225244 kb
Host smart-ae6d17e4-c03a-4370-9457-7cad553dbbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218093539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.218093539
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2503598941
Short name T781
Test name
Test status
Simulation time 94929238 ps
CPU time 4 seconds
Started Aug 10 06:18:08 PM PDT 24
Finished Aug 10 06:18:12 PM PDT 24
Peak memory 222884 kb
Host smart-5bf8a583-5c47-4643-9d30-876528011698
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2503598941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2503598941
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.824767024
Short name T66
Test name
Test status
Simulation time 81519593 ps
CPU time 1.18 seconds
Started Aug 10 06:18:08 PM PDT 24
Finished Aug 10 06:18:10 PM PDT 24
Peak memory 235656 kb
Host smart-2133b047-e248-4eb0-8f14-0b65e8cfc3a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824767024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.824767024
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2753503363
Short name T702
Test name
Test status
Simulation time 100830332684 ps
CPU time 88.54 seconds
Started Aug 10 06:18:09 PM PDT 24
Finished Aug 10 06:19:38 PM PDT 24
Peak memory 249940 kb
Host smart-248facb8-c18e-4e03-83b4-02ca775fe1d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753503363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2753503363
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3969106159
Short name T806
Test name
Test status
Simulation time 1878112856 ps
CPU time 3.73 seconds
Started Aug 10 06:18:08 PM PDT 24
Finished Aug 10 06:18:12 PM PDT 24
Peak memory 218892 kb
Host smart-8a0ec5b4-d3ba-4bce-8230-06455f9d7d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969106159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3969106159
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1342781045
Short name T70
Test name
Test status
Simulation time 12401342 ps
CPU time 0.72 seconds
Started Aug 10 06:18:05 PM PDT 24
Finished Aug 10 06:18:05 PM PDT 24
Peak memory 206184 kb
Host smart-a7f3f15c-da0c-4fe6-9ed2-243a48e53a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342781045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1342781045
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2213828487
Short name T484
Test name
Test status
Simulation time 2387869006 ps
CPU time 3.7 seconds
Started Aug 10 06:18:08 PM PDT 24
Finished Aug 10 06:18:12 PM PDT 24
Peak memory 217040 kb
Host smart-06e96293-42ac-44d5-94cd-1fd0991417d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213828487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2213828487
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3596884493
Short name T699
Test name
Test status
Simulation time 104238127 ps
CPU time 1.06 seconds
Started Aug 10 06:18:07 PM PDT 24
Finished Aug 10 06:18:08 PM PDT 24
Peak memory 206528 kb
Host smart-bc328cdc-6925-4f2d-b218-750b7ee02506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596884493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3596884493
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1504452869
Short name T299
Test name
Test status
Simulation time 4691011671 ps
CPU time 15.24 seconds
Started Aug 10 06:18:09 PM PDT 24
Finished Aug 10 06:18:24 PM PDT 24
Peak memory 225264 kb
Host smart-65372e6f-d8c1-4dcb-a69d-116c0997bb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504452869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1504452869
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1322455408
Short name T802
Test name
Test status
Simulation time 68501889 ps
CPU time 0.72 seconds
Started Aug 10 06:18:46 PM PDT 24
Finished Aug 10 06:18:47 PM PDT 24
Peak memory 205796 kb
Host smart-5097a310-5f83-4647-a417-201ec1822c8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322455408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1322455408
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.887241676
Short name T1032
Test name
Test status
Simulation time 3930374924 ps
CPU time 13.4 seconds
Started Aug 10 06:18:40 PM PDT 24
Finished Aug 10 06:18:54 PM PDT 24
Peak memory 225192 kb
Host smart-5a1ef892-6430-4605-9465-e2f63ff9fa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887241676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.887241676
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2935764177
Short name T507
Test name
Test status
Simulation time 22408468 ps
CPU time 0.81 seconds
Started Aug 10 06:18:37 PM PDT 24
Finished Aug 10 06:18:38 PM PDT 24
Peak memory 207068 kb
Host smart-b604565b-e22b-4bf9-9a5c-16fc82e19ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935764177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2935764177
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2276386678
Short name T424
Test name
Test status
Simulation time 20378690095 ps
CPU time 38.27 seconds
Started Aug 10 06:18:46 PM PDT 24
Finished Aug 10 06:19:24 PM PDT 24
Peak memory 241624 kb
Host smart-67968443-92fe-49d8-9bae-1f5472798609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276386678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2276386678
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.177550296
Short name T953
Test name
Test status
Simulation time 9439015556 ps
CPU time 64.13 seconds
Started Aug 10 06:18:36 PM PDT 24
Finished Aug 10 06:19:40 PM PDT 24
Peak memory 254444 kb
Host smart-a88b703f-ed54-4ee7-a049-71fc72289f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177550296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.177550296
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1048352490
Short name T445
Test name
Test status
Simulation time 87829643 ps
CPU time 2.22 seconds
Started Aug 10 06:18:35 PM PDT 24
Finished Aug 10 06:18:37 PM PDT 24
Peak memory 224236 kb
Host smart-18c335db-53e6-4918-94f8-f07f26056f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048352490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1048352490
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.105979036
Short name T420
Test name
Test status
Simulation time 100752834123 ps
CPU time 260.01 seconds
Started Aug 10 06:18:35 PM PDT 24
Finished Aug 10 06:22:56 PM PDT 24
Peak memory 254492 kb
Host smart-e050df72-79a8-4087-af8a-b2157cdbab96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105979036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.105979036
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1390021950
Short name T901
Test name
Test status
Simulation time 576187852 ps
CPU time 10.79 seconds
Started Aug 10 06:18:40 PM PDT 24
Finished Aug 10 06:18:51 PM PDT 24
Peak memory 221244 kb
Host smart-08728e81-f0af-467b-bc16-921b1fe302eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390021950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1390021950
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3381166341
Short name T217
Test name
Test status
Simulation time 1232614691 ps
CPU time 14.07 seconds
Started Aug 10 06:18:41 PM PDT 24
Finished Aug 10 06:18:55 PM PDT 24
Peak memory 233364 kb
Host smart-f3f47c2b-4a8f-491d-9175-9224c70af5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381166341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3381166341
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.484255935
Short name T792
Test name
Test status
Simulation time 48107341 ps
CPU time 0.99 seconds
Started Aug 10 06:18:35 PM PDT 24
Finished Aug 10 06:18:37 PM PDT 24
Peak memory 218428 kb
Host smart-0b089225-5750-4a4f-af2a-98624d74dbc0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484255935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.484255935
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2727851210
Short name T924
Test name
Test status
Simulation time 10761286104 ps
CPU time 31.12 seconds
Started Aug 10 06:18:36 PM PDT 24
Finished Aug 10 06:19:07 PM PDT 24
Peak memory 238980 kb
Host smart-e19c3786-0bd4-439d-bf5d-a650f0057195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727851210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2727851210
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1436536388
Short name T844
Test name
Test status
Simulation time 18756451444 ps
CPU time 7.13 seconds
Started Aug 10 06:18:35 PM PDT 24
Finished Aug 10 06:18:42 PM PDT 24
Peak memory 233496 kb
Host smart-68e76291-1826-4beb-961d-e8d23f636736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436536388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1436536388
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2960216196
Short name T599
Test name
Test status
Simulation time 523228690 ps
CPU time 7.11 seconds
Started Aug 10 06:18:39 PM PDT 24
Finished Aug 10 06:18:46 PM PDT 24
Peak memory 222716 kb
Host smart-629d0200-e854-43fd-8caa-c8d612eb8bc8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2960216196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2960216196
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1047662391
Short name T20
Test name
Test status
Simulation time 199064747 ps
CPU time 1.04 seconds
Started Aug 10 06:18:38 PM PDT 24
Finished Aug 10 06:18:39 PM PDT 24
Peak memory 207292 kb
Host smart-06fce417-b7b1-4cba-a844-9d6ff25bebfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047662391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1047662391
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3031005046
Short name T477
Test name
Test status
Simulation time 325618753 ps
CPU time 3.69 seconds
Started Aug 10 06:18:38 PM PDT 24
Finished Aug 10 06:18:42 PM PDT 24
Peak memory 217076 kb
Host smart-d27020a5-6f36-4c69-92b2-29497563c4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031005046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3031005046
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1741623361
Short name T848
Test name
Test status
Simulation time 35403583 ps
CPU time 0.71 seconds
Started Aug 10 06:18:37 PM PDT 24
Finished Aug 10 06:18:38 PM PDT 24
Peak memory 206180 kb
Host smart-9e97c97b-8d56-404d-b886-964262273857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741623361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1741623361
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3984902955
Short name T480
Test name
Test status
Simulation time 373686254 ps
CPU time 5.07 seconds
Started Aug 10 06:18:38 PM PDT 24
Finished Aug 10 06:18:43 PM PDT 24
Peak memory 216988 kb
Host smart-b37b25c0-eea0-4a05-b6d0-0ca3d728864e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984902955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3984902955
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.716351698
Short name T889
Test name
Test status
Simulation time 27256879 ps
CPU time 0.68 seconds
Started Aug 10 06:18:40 PM PDT 24
Finished Aug 10 06:18:41 PM PDT 24
Peak memory 206068 kb
Host smart-952bbac1-91c0-4582-9538-74ab351b73c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716351698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.716351698
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.4181373918
Short name T868
Test name
Test status
Simulation time 739768332 ps
CPU time 4.85 seconds
Started Aug 10 06:18:41 PM PDT 24
Finished Aug 10 06:18:46 PM PDT 24
Peak memory 225164 kb
Host smart-875a69f5-820e-46ee-bf61-88326cd97412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181373918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.4181373918
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4186322771
Short name T689
Test name
Test status
Simulation time 216834557 ps
CPU time 2.35 seconds
Started Aug 10 06:18:41 PM PDT 24
Finished Aug 10 06:18:44 PM PDT 24
Peak memory 225176 kb
Host smart-d908a93b-eb6f-42d5-b98c-15d1bbe9d2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186322771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4186322771
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4176628487
Short name T389
Test name
Test status
Simulation time 89710222 ps
CPU time 0.76 seconds
Started Aug 10 06:18:36 PM PDT 24
Finished Aug 10 06:18:37 PM PDT 24
Peak memory 207092 kb
Host smart-a8fc2fc3-dcff-4160-8a75-b8471d97c2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176628487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4176628487
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2583332093
Short name T245
Test name
Test status
Simulation time 25678400124 ps
CPU time 78.56 seconds
Started Aug 10 06:18:46 PM PDT 24
Finished Aug 10 06:20:05 PM PDT 24
Peak memory 249848 kb
Host smart-9540c5b0-03f4-48f3-8341-06ff38f2b974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583332093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2583332093
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1156463878
Short name T138
Test name
Test status
Simulation time 19607500376 ps
CPU time 96.43 seconds
Started Aug 10 06:18:41 PM PDT 24
Finished Aug 10 06:20:17 PM PDT 24
Peak memory 250856 kb
Host smart-98b5268c-3fff-4d96-a1ae-0ef97b543b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156463878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1156463878
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2164210516
Short name T486
Test name
Test status
Simulation time 859788963 ps
CPU time 7.45 seconds
Started Aug 10 06:18:46 PM PDT 24
Finished Aug 10 06:18:54 PM PDT 24
Peak memory 236352 kb
Host smart-dab5cf83-dc15-4811-abaf-1e72907c5607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164210516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2164210516
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2728443570
Short name T742
Test name
Test status
Simulation time 312845900 ps
CPU time 4.67 seconds
Started Aug 10 06:18:41 PM PDT 24
Finished Aug 10 06:18:46 PM PDT 24
Peak memory 233400 kb
Host smart-eb07a3ab-156d-4d84-84d4-6468d048e40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728443570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2728443570
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3010590419
Short name T171
Test name
Test status
Simulation time 50032608690 ps
CPU time 87.81 seconds
Started Aug 10 06:18:38 PM PDT 24
Finished Aug 10 06:20:06 PM PDT 24
Peak memory 241680 kb
Host smart-4fd53aeb-b25e-4e72-9dd3-44a7c5ac065b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010590419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3010590419
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3385650677
Short name T933
Test name
Test status
Simulation time 54338003 ps
CPU time 2.82 seconds
Started Aug 10 06:18:35 PM PDT 24
Finished Aug 10 06:18:38 PM PDT 24
Peak memory 233400 kb
Host smart-8665781a-e411-4f5d-af0a-5bf16c56f0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385650677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3385650677
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.982999457
Short name T189
Test name
Test status
Simulation time 294225625 ps
CPU time 4.33 seconds
Started Aug 10 06:18:37 PM PDT 24
Finished Aug 10 06:18:42 PM PDT 24
Peak memory 225244 kb
Host smart-a5af6dde-2faf-48bb-89ba-e62f8328adff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982999457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.982999457
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1148330061
Short name T464
Test name
Test status
Simulation time 86311023 ps
CPU time 1.06 seconds
Started Aug 10 06:18:40 PM PDT 24
Finished Aug 10 06:18:42 PM PDT 24
Peak memory 218368 kb
Host smart-e7b84a2e-0747-40d3-9dce-77b808d1ff98
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148330061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1148330061
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2133896059
Short name T260
Test name
Test status
Simulation time 387114175 ps
CPU time 5.98 seconds
Started Aug 10 06:18:38 PM PDT 24
Finished Aug 10 06:18:45 PM PDT 24
Peak memory 233464 kb
Host smart-939d8807-7bad-4ecc-870e-66a344ec8460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133896059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2133896059
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.88916152
Short name T879
Test name
Test status
Simulation time 32396599 ps
CPU time 2.29 seconds
Started Aug 10 06:18:39 PM PDT 24
Finished Aug 10 06:18:41 PM PDT 24
Peak memory 233120 kb
Host smart-2c5a9771-0dca-4267-9c7e-4c605e89bfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88916152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.88916152
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1213439534
Short name T146
Test name
Test status
Simulation time 496735438 ps
CPU time 3.92 seconds
Started Aug 10 06:18:39 PM PDT 24
Finished Aug 10 06:18:43 PM PDT 24
Peak memory 219860 kb
Host smart-398b710f-25de-4d81-aec5-0e6be44601d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1213439534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1213439534
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.4010498661
Short name T904
Test name
Test status
Simulation time 108478870317 ps
CPU time 237.45 seconds
Started Aug 10 06:18:46 PM PDT 24
Finished Aug 10 06:22:44 PM PDT 24
Peak memory 247224 kb
Host smart-9ff1ff1f-a9dd-47ef-9180-5faecb206741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010498661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.4010498661
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1988546135
Short name T514
Test name
Test status
Simulation time 5501308161 ps
CPU time 27.6 seconds
Started Aug 10 06:18:46 PM PDT 24
Finished Aug 10 06:19:13 PM PDT 24
Peak memory 221032 kb
Host smart-e95935d8-3285-47c7-b951-bd4a423c349d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988546135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1988546135
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.4028384214
Short name T977
Test name
Test status
Simulation time 1275605989 ps
CPU time 7.62 seconds
Started Aug 10 06:18:37 PM PDT 24
Finished Aug 10 06:18:45 PM PDT 24
Peak memory 216960 kb
Host smart-3277b83b-c959-430d-a3f3-a80e137046f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028384214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.4028384214
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.806498212
Short name T690
Test name
Test status
Simulation time 48475057 ps
CPU time 1.51 seconds
Started Aug 10 06:18:40 PM PDT 24
Finished Aug 10 06:18:42 PM PDT 24
Peak memory 216872 kb
Host smart-6c7fc8f8-5de1-4f13-b09c-1649a505c600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806498212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.806498212
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1484914770
Short name T440
Test name
Test status
Simulation time 546736939 ps
CPU time 1.01 seconds
Started Aug 10 06:18:39 PM PDT 24
Finished Aug 10 06:18:41 PM PDT 24
Peak memory 207456 kb
Host smart-59f2fa6b-f8eb-446d-bc07-b105447d9903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484914770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1484914770
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.660343812
Short name T538
Test name
Test status
Simulation time 10994055357 ps
CPU time 14.06 seconds
Started Aug 10 06:18:39 PM PDT 24
Finished Aug 10 06:18:54 PM PDT 24
Peak memory 233536 kb
Host smart-e53f1664-bcca-48aa-88bd-e6f2c804f73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660343812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.660343812
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1247221348
Short name T1004
Test name
Test status
Simulation time 23640587 ps
CPU time 0.7 seconds
Started Aug 10 06:18:42 PM PDT 24
Finished Aug 10 06:18:43 PM PDT 24
Peak memory 205292 kb
Host smart-40f83b6f-713e-4c29-855b-793dd596b77b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247221348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1247221348
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3428384887
Short name T752
Test name
Test status
Simulation time 68172387 ps
CPU time 2.47 seconds
Started Aug 10 06:18:44 PM PDT 24
Finished Aug 10 06:18:46 PM PDT 24
Peak memory 233376 kb
Host smart-510913a3-e81f-4715-9e00-e4f7db2a702d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428384887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3428384887
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1390469728
Short name T1028
Test name
Test status
Simulation time 19511924 ps
CPU time 0.78 seconds
Started Aug 10 06:18:37 PM PDT 24
Finished Aug 10 06:18:38 PM PDT 24
Peak memory 207376 kb
Host smart-9a931836-2128-4b9e-a1e3-a6b8361d2d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390469728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1390469728
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1708202454
Short name T722
Test name
Test status
Simulation time 238926810257 ps
CPU time 432.13 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:26:02 PM PDT 24
Peak memory 258120 kb
Host smart-2816efa5-9f9d-4df3-837f-560fece171bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708202454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1708202454
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.942178196
Short name T176
Test name
Test status
Simulation time 1031480253 ps
CPU time 20.03 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:19:10 PM PDT 24
Peak memory 240240 kb
Host smart-bc682e48-a23c-4fa9-9ed9-18c4bf153932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942178196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.942178196
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2704067411
Short name T474
Test name
Test status
Simulation time 17604162910 ps
CPU time 48.27 seconds
Started Aug 10 06:18:42 PM PDT 24
Finished Aug 10 06:19:30 PM PDT 24
Peak memory 218424 kb
Host smart-2167081f-b41e-4169-b711-6dc2e2244ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704067411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2704067411
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1059824856
Short name T490
Test name
Test status
Simulation time 258176416 ps
CPU time 2.67 seconds
Started Aug 10 06:18:43 PM PDT 24
Finished Aug 10 06:18:46 PM PDT 24
Peak memory 229872 kb
Host smart-868f544a-5703-4e0a-a4a6-01eac1a254ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059824856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1059824856
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2253524374
Short name T885
Test name
Test status
Simulation time 4866171375 ps
CPU time 33.82 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:19:24 PM PDT 24
Peak memory 236040 kb
Host smart-2c7bfa7d-cb21-4c86-a7a7-1c5b5b0f0de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253524374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2253524374
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2654504689
Short name T283
Test name
Test status
Simulation time 109978708 ps
CPU time 3.48 seconds
Started Aug 10 06:18:43 PM PDT 24
Finished Aug 10 06:18:46 PM PDT 24
Peak memory 233436 kb
Host smart-a70ca625-21bc-462c-9e8a-7868b2f0fd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654504689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2654504689
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3322463109
Short name T318
Test name
Test status
Simulation time 4812687174 ps
CPU time 16.56 seconds
Started Aug 10 06:18:44 PM PDT 24
Finished Aug 10 06:19:01 PM PDT 24
Peak memory 225120 kb
Host smart-bdd6b5e5-755f-47fc-9577-0ed87c1a9a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322463109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3322463109
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.147631529
Short name T859
Test name
Test status
Simulation time 38544998 ps
CPU time 1.13 seconds
Started Aug 10 06:18:38 PM PDT 24
Finished Aug 10 06:18:40 PM PDT 24
Peak memory 217140 kb
Host smart-471ced87-b437-4ae8-aed6-fc71abe55eab
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147631529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.147631529
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3675275678
Short name T851
Test name
Test status
Simulation time 634169560 ps
CPU time 7.81 seconds
Started Aug 10 06:18:43 PM PDT 24
Finished Aug 10 06:18:51 PM PDT 24
Peak memory 233448 kb
Host smart-c4248750-3212-435e-a427-346918567d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675275678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3675275678
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.338072610
Short name T872
Test name
Test status
Simulation time 2398668896 ps
CPU time 8.28 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:18:58 PM PDT 24
Peak memory 225352 kb
Host smart-8eee7edb-2079-4aaf-b288-270316186448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338072610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.338072610
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.831137491
Short name T983
Test name
Test status
Simulation time 543842688 ps
CPU time 4.07 seconds
Started Aug 10 06:18:43 PM PDT 24
Finished Aug 10 06:18:47 PM PDT 24
Peak memory 221420 kb
Host smart-e29c3410-744d-4401-af06-f9a7ad3ea74c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=831137491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.831137491
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1574090326
Short name T721
Test name
Test status
Simulation time 7791178379 ps
CPU time 52.15 seconds
Started Aug 10 06:18:43 PM PDT 24
Finished Aug 10 06:19:35 PM PDT 24
Peak memory 241480 kb
Host smart-8823bbba-dcba-4710-8779-0d2f42ac3dc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574090326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1574090326
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1869584409
Short name T432
Test name
Test status
Simulation time 3218475867 ps
CPU time 12.13 seconds
Started Aug 10 06:18:49 PM PDT 24
Finished Aug 10 06:19:01 PM PDT 24
Peak memory 220772 kb
Host smart-3fe9da59-e2b7-4d7c-8243-ea8c15cad1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869584409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1869584409
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3092773034
Short name T873
Test name
Test status
Simulation time 11085740075 ps
CPU time 9.04 seconds
Started Aug 10 06:18:38 PM PDT 24
Finished Aug 10 06:18:48 PM PDT 24
Peak memory 216916 kb
Host smart-685e4e21-66be-4a05-a5c9-863384e594fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092773034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3092773034
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.884677334
Short name T688
Test name
Test status
Simulation time 21574459 ps
CPU time 0.77 seconds
Started Aug 10 06:18:43 PM PDT 24
Finished Aug 10 06:18:44 PM PDT 24
Peak memory 206604 kb
Host smart-9b0a41c3-9c79-4368-8152-fde4db3417f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884677334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.884677334
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3598636393
Short name T622
Test name
Test status
Simulation time 13423137 ps
CPU time 0.76 seconds
Started Aug 10 06:18:43 PM PDT 24
Finished Aug 10 06:18:44 PM PDT 24
Peak memory 206572 kb
Host smart-f970e1b9-2f94-4f3b-98d1-cf5dba32f473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598636393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3598636393
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2013706371
Short name T732
Test name
Test status
Simulation time 606079594 ps
CPU time 3.91 seconds
Started Aug 10 06:18:46 PM PDT 24
Finished Aug 10 06:18:50 PM PDT 24
Peak memory 233472 kb
Host smart-9a5d6501-da47-4d67-8368-129ada2e5720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013706371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2013706371
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2707543376
Short name T944
Test name
Test status
Simulation time 11907007 ps
CPU time 0.74 seconds
Started Aug 10 06:18:44 PM PDT 24
Finished Aug 10 06:18:45 PM PDT 24
Peak memory 205884 kb
Host smart-a1c688d5-4c26-484c-8da2-5429509a9f6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707543376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2707543376
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3806553291
Short name T85
Test name
Test status
Simulation time 1324989202 ps
CPU time 5.96 seconds
Started Aug 10 06:18:42 PM PDT 24
Finished Aug 10 06:18:48 PM PDT 24
Peak memory 225280 kb
Host smart-b121cfe0-ec95-45aa-8db7-23cadb165f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806553291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3806553291
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.4265876184
Short name T696
Test name
Test status
Simulation time 18910656 ps
CPU time 0.87 seconds
Started Aug 10 06:18:45 PM PDT 24
Finished Aug 10 06:18:46 PM PDT 24
Peak memory 207392 kb
Host smart-4e9e7959-6d4b-490f-969f-694cdebf2c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265876184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.4265876184
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.128514147
Short name T886
Test name
Test status
Simulation time 8350973811 ps
CPU time 25.41 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:19:16 PM PDT 24
Peak memory 236776 kb
Host smart-b8ba170e-7618-4d36-9830-68f027527cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128514147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.128514147
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1336922444
Short name T251
Test name
Test status
Simulation time 11387432823 ps
CPU time 109.74 seconds
Started Aug 10 06:18:43 PM PDT 24
Finished Aug 10 06:20:33 PM PDT 24
Peak memory 241756 kb
Host smart-614f6a50-faa0-4fd1-9bd8-fcb3fdb75509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336922444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1336922444
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2887866027
Short name T930
Test name
Test status
Simulation time 5291453180 ps
CPU time 141.18 seconds
Started Aug 10 06:18:44 PM PDT 24
Finished Aug 10 06:21:05 PM PDT 24
Peak memory 264800 kb
Host smart-4e272dd7-5d40-419a-9168-e110ba9cad23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887866027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2887866027
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.955144527
Short name T704
Test name
Test status
Simulation time 63293712 ps
CPU time 2.69 seconds
Started Aug 10 06:18:45 PM PDT 24
Finished Aug 10 06:18:48 PM PDT 24
Peak memory 233324 kb
Host smart-417980e4-f4a8-4425-b30e-2a47a034803d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955144527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.955144527
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1943700735
Short name T735
Test name
Test status
Simulation time 291535214 ps
CPU time 4.95 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:18:55 PM PDT 24
Peak memory 225284 kb
Host smart-1ec2ded2-bd55-4e4c-a97a-93a74cd08f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943700735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1943700735
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2662979313
Short name T551
Test name
Test status
Simulation time 991038552 ps
CPU time 7.59 seconds
Started Aug 10 06:18:43 PM PDT 24
Finished Aug 10 06:18:51 PM PDT 24
Peak memory 233428 kb
Host smart-515cb1eb-78a2-4c8c-a196-d7663b8de84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662979313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2662979313
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3451199862
Short name T387
Test name
Test status
Simulation time 41434177452 ps
CPU time 47.91 seconds
Started Aug 10 06:18:43 PM PDT 24
Finished Aug 10 06:19:31 PM PDT 24
Peak memory 240628 kb
Host smart-ce16682c-b87a-45e6-98a6-f6f863c2de5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451199862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3451199862
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3750704239
Short name T46
Test name
Test status
Simulation time 85857045 ps
CPU time 1.02 seconds
Started Aug 10 06:18:43 PM PDT 24
Finished Aug 10 06:18:45 PM PDT 24
Peak memory 218284 kb
Host smart-c03f0bec-68f6-4008-b16d-187d09bdeaa2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750704239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3750704239
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1626166576
Short name T625
Test name
Test status
Simulation time 919960942 ps
CPU time 4.25 seconds
Started Aug 10 06:18:46 PM PDT 24
Finished Aug 10 06:18:50 PM PDT 24
Peak memory 225228 kb
Host smart-a0a3cedc-a507-463f-aef7-a560fe2cde0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626166576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1626166576
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3468277418
Short name T664
Test name
Test status
Simulation time 11970131510 ps
CPU time 9.66 seconds
Started Aug 10 06:18:43 PM PDT 24
Finished Aug 10 06:18:53 PM PDT 24
Peak memory 233528 kb
Host smart-d5771799-5d1f-48a1-aca7-0a205ea4e9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468277418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3468277418
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2628906641
Short name T413
Test name
Test status
Simulation time 3654209780 ps
CPU time 7.88 seconds
Started Aug 10 06:18:49 PM PDT 24
Finished Aug 10 06:18:57 PM PDT 24
Peak memory 220004 kb
Host smart-92c7fa61-ae0f-4238-81b3-d1cbd46dddaa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2628906641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2628906641
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3517998153
Short name T44
Test name
Test status
Simulation time 35854595220 ps
CPU time 393.44 seconds
Started Aug 10 06:18:45 PM PDT 24
Finished Aug 10 06:25:18 PM PDT 24
Peak memory 265952 kb
Host smart-9f3eae37-49e6-4863-babe-66b4248dba07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517998153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3517998153
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.184644655
Short name T430
Test name
Test status
Simulation time 2781163799 ps
CPU time 28.22 seconds
Started Aug 10 06:18:45 PM PDT 24
Finished Aug 10 06:19:13 PM PDT 24
Peak memory 220616 kb
Host smart-bbec82bf-f604-4d01-b99a-0cb75ff21e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184644655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.184644655
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.4169889567
Short name T571
Test name
Test status
Simulation time 880041227 ps
CPU time 2.93 seconds
Started Aug 10 06:18:46 PM PDT 24
Finished Aug 10 06:18:49 PM PDT 24
Peak memory 216976 kb
Host smart-aad86270-db9a-4b67-812c-f18b95957e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169889567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.4169889567
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3365043794
Short name T605
Test name
Test status
Simulation time 239908096 ps
CPU time 10.33 seconds
Started Aug 10 06:18:42 PM PDT 24
Finished Aug 10 06:18:52 PM PDT 24
Peak memory 216964 kb
Host smart-c457e31e-41eb-47ed-ae6f-2503ffaf0dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365043794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3365043794
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.214225714
Short name T597
Test name
Test status
Simulation time 46470815 ps
CPU time 0.8 seconds
Started Aug 10 06:18:43 PM PDT 24
Finished Aug 10 06:18:44 PM PDT 24
Peak memory 206444 kb
Host smart-ebd63c37-8037-406f-a502-ed65c4b42faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214225714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.214225714
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.4136310847
Short name T523
Test name
Test status
Simulation time 4130306762 ps
CPU time 14 seconds
Started Aug 10 06:18:42 PM PDT 24
Finished Aug 10 06:18:56 PM PDT 24
Peak memory 225356 kb
Host smart-f672b27a-09fb-4576-a7b7-8df8e3ba2e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136310847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4136310847
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.126385847
Short name T635
Test name
Test status
Simulation time 12130709 ps
CPU time 0.73 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:18:51 PM PDT 24
Peak memory 205828 kb
Host smart-bf89e276-d8a9-48f7-98c9-293f40df1298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126385847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.126385847
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2051371428
Short name T723
Test name
Test status
Simulation time 1409667916 ps
CPU time 13.03 seconds
Started Aug 10 06:18:51 PM PDT 24
Finished Aug 10 06:19:04 PM PDT 24
Peak memory 225252 kb
Host smart-9c040b84-a9b0-43ea-be99-67543dc60f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051371428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2051371428
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.450296038
Short name T1033
Test name
Test status
Simulation time 19207729 ps
CPU time 0.8 seconds
Started Aug 10 06:18:45 PM PDT 24
Finished Aug 10 06:18:46 PM PDT 24
Peak memory 207404 kb
Host smart-ffff54d6-98c3-4eb0-ae53-df8709ca6b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450296038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.450296038
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1440507928
Short name T281
Test name
Test status
Simulation time 11709331773 ps
CPU time 16.3 seconds
Started Aug 10 06:18:51 PM PDT 24
Finished Aug 10 06:19:08 PM PDT 24
Peak memory 225308 kb
Host smart-49294a3a-f16d-4514-afbc-173f2cad0851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440507928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1440507928
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3101135755
Short name T890
Test name
Test status
Simulation time 2525152528 ps
CPU time 14.37 seconds
Started Aug 10 06:18:49 PM PDT 24
Finished Aug 10 06:19:04 PM PDT 24
Peak memory 241804 kb
Host smart-7cacea70-8c8a-4a03-ac8f-ddfa9f51587a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101135755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3101135755
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.798801876
Short name T640
Test name
Test status
Simulation time 1816167196 ps
CPU time 27 seconds
Started Aug 10 06:18:54 PM PDT 24
Finished Aug 10 06:19:21 PM PDT 24
Peak memory 237004 kb
Host smart-7d8a45ca-2e59-4174-a897-e2ae89c6148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798801876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.798801876
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3053953464
Short name T259
Test name
Test status
Simulation time 88648792970 ps
CPU time 287.54 seconds
Started Aug 10 06:18:52 PM PDT 24
Finished Aug 10 06:23:39 PM PDT 24
Peak memory 256092 kb
Host smart-b15058ee-621a-45b5-8cf1-50de7b907eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053953464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3053953464
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.478689338
Short name T188
Test name
Test status
Simulation time 299850059 ps
CPU time 4.18 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:18:54 PM PDT 24
Peak memory 225216 kb
Host smart-aaec79bd-5d4b-4651-9290-8cc13aa588fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478689338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.478689338
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.32561455
Short name T527
Test name
Test status
Simulation time 997226100 ps
CPU time 5.22 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:18:56 PM PDT 24
Peak memory 225248 kb
Host smart-c30364f5-d6f7-46fb-8988-8deebbac089c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32561455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.32561455
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1747911720
Short name T481
Test name
Test status
Simulation time 43403324 ps
CPU time 1.02 seconds
Started Aug 10 06:18:49 PM PDT 24
Finished Aug 10 06:18:50 PM PDT 24
Peak memory 217220 kb
Host smart-521bb261-28e1-45a4-b9e5-c5ad95e9b5cc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747911720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1747911720
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4036246865
Short name T315
Test name
Test status
Simulation time 646028269 ps
CPU time 9.49 seconds
Started Aug 10 06:18:51 PM PDT 24
Finished Aug 10 06:19:01 PM PDT 24
Peak memory 240816 kb
Host smart-79fb8209-9d45-4c60-9fa5-209aa24c9aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036246865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4036246865
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1010812673
Short name T461
Test name
Test status
Simulation time 2132914387 ps
CPU time 8.29 seconds
Started Aug 10 06:18:52 PM PDT 24
Finished Aug 10 06:19:00 PM PDT 24
Peak memory 239392 kb
Host smart-5b55556f-d04f-4262-bd49-cb03f085f90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010812673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1010812673
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.834394349
Short name T773
Test name
Test status
Simulation time 2328622934 ps
CPU time 11.1 seconds
Started Aug 10 06:18:52 PM PDT 24
Finished Aug 10 06:19:03 PM PDT 24
Peak memory 219940 kb
Host smart-f244edb9-c5af-4daf-a245-01413117fd0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=834394349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.834394349
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2107902244
Short name T23
Test name
Test status
Simulation time 4354259207 ps
CPU time 76.23 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:20:07 PM PDT 24
Peak memory 257172 kb
Host smart-44cdc7a7-05fc-465a-a4bd-b35892ef4f7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107902244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2107902244
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4130663264
Short name T621
Test name
Test status
Simulation time 290649099 ps
CPU time 6.01 seconds
Started Aug 10 06:18:48 PM PDT 24
Finished Aug 10 06:18:55 PM PDT 24
Peak memory 217108 kb
Host smart-4ceb6e70-6451-4fbd-8ec3-d646d8b8d291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130663264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4130663264
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3468434479
Short name T73
Test name
Test status
Simulation time 2882398619 ps
CPU time 8.9 seconds
Started Aug 10 06:18:41 PM PDT 24
Finished Aug 10 06:18:50 PM PDT 24
Peak memory 217032 kb
Host smart-dda366a8-bb30-4bd1-ac6b-944d07e42f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468434479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3468434479
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1609846906
Short name T508
Test name
Test status
Simulation time 66694224 ps
CPU time 0.84 seconds
Started Aug 10 06:18:49 PM PDT 24
Finished Aug 10 06:18:50 PM PDT 24
Peak memory 206612 kb
Host smart-878d2624-f53e-4c67-936f-67603b02271c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609846906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1609846906
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.43706428
Short name T593
Test name
Test status
Simulation time 14475006 ps
CPU time 0.74 seconds
Started Aug 10 06:18:52 PM PDT 24
Finished Aug 10 06:18:53 PM PDT 24
Peak memory 206596 kb
Host smart-49c849bb-dd62-4310-a217-5b496206289e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43706428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.43706428
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1560117858
Short name T954
Test name
Test status
Simulation time 842262374 ps
CPU time 5.23 seconds
Started Aug 10 06:18:52 PM PDT 24
Finished Aug 10 06:18:57 PM PDT 24
Peak memory 233452 kb
Host smart-90a7e83d-a0ff-4176-ad42-56832c3a23e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560117858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1560117858
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.319318101
Short name T777
Test name
Test status
Simulation time 97852201 ps
CPU time 0.73 seconds
Started Aug 10 06:18:57 PM PDT 24
Finished Aug 10 06:18:57 PM PDT 24
Peak memory 205844 kb
Host smart-81f3b118-ea0c-4bee-b693-a6b0fa581e2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319318101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.319318101
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.533471255
Short name T831
Test name
Test status
Simulation time 6135819036 ps
CPU time 28.74 seconds
Started Aug 10 06:18:55 PM PDT 24
Finished Aug 10 06:19:24 PM PDT 24
Peak memory 225292 kb
Host smart-366438c2-1945-401c-924d-e921a94b27f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533471255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.533471255
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.954096136
Short name T738
Test name
Test status
Simulation time 19513404 ps
CPU time 0.78 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:18:52 PM PDT 24
Peak memory 207380 kb
Host smart-dd08dae2-7145-480b-8199-e396a750af49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954096136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.954096136
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2691403424
Short name T476
Test name
Test status
Simulation time 59197500281 ps
CPU time 145.15 seconds
Started Aug 10 06:18:56 PM PDT 24
Finished Aug 10 06:21:21 PM PDT 24
Peak memory 256312 kb
Host smart-d6a179ad-6ca4-4d4b-89ab-1da92b6f5cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691403424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2691403424
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1902966590
Short name T327
Test name
Test status
Simulation time 261085053 ps
CPU time 4.47 seconds
Started Aug 10 06:18:51 PM PDT 24
Finished Aug 10 06:18:56 PM PDT 24
Peak memory 233132 kb
Host smart-c406ccc0-dea6-431f-8583-458f236b3c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902966590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1902966590
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1490832508
Short name T819
Test name
Test status
Simulation time 17679413319 ps
CPU time 94.15 seconds
Started Aug 10 06:18:51 PM PDT 24
Finished Aug 10 06:20:25 PM PDT 24
Peak memory 258116 kb
Host smart-698c8636-604d-4b98-be57-2503c81a3e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490832508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1490832508
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.347029278
Short name T218
Test name
Test status
Simulation time 5184566507 ps
CPU time 20.19 seconds
Started Aug 10 06:18:51 PM PDT 24
Finished Aug 10 06:19:11 PM PDT 24
Peak memory 225264 kb
Host smart-1b3ac307-0b34-4fb1-8959-7e56eb9627c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347029278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.347029278
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2330666997
Short name T835
Test name
Test status
Simulation time 28622991929 ps
CPU time 115.91 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:20:47 PM PDT 24
Peak memory 249932 kb
Host smart-6bb4ac03-d23b-43ae-a18a-5e903db7372d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330666997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2330666997
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2343664096
Short name T923
Test name
Test status
Simulation time 126447364 ps
CPU time 1.07 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:18:51 PM PDT 24
Peak memory 217156 kb
Host smart-bdfefe0d-90dd-422b-8aa1-2bdabb613885
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343664096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2343664096
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.789692389
Short name T382
Test name
Test status
Simulation time 74715316 ps
CPU time 2.24 seconds
Started Aug 10 06:18:55 PM PDT 24
Finished Aug 10 06:18:57 PM PDT 24
Peak memory 224556 kb
Host smart-86a1f191-f86e-4253-9349-b626933b1c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789692389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.789692389
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.355686082
Short name T462
Test name
Test status
Simulation time 29520246 ps
CPU time 2.44 seconds
Started Aug 10 06:18:51 PM PDT 24
Finished Aug 10 06:18:54 PM PDT 24
Peak memory 233056 kb
Host smart-81c008a0-69ed-4564-b00b-fc7afc5a7bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355686082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.355686082
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2492778311
Short name T370
Test name
Test status
Simulation time 992279952 ps
CPU time 5.52 seconds
Started Aug 10 06:18:49 PM PDT 24
Finished Aug 10 06:18:55 PM PDT 24
Peak memory 222836 kb
Host smart-546c2882-38bf-4cd4-accc-952437ab4d10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2492778311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2492778311
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2903832282
Short name T832
Test name
Test status
Simulation time 1368136151 ps
CPU time 21.67 seconds
Started Aug 10 06:18:57 PM PDT 24
Finished Aug 10 06:19:19 PM PDT 24
Peak memory 249380 kb
Host smart-f4fb64e1-7697-4226-8d50-9981d1a04fb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903832282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2903832282
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2342578682
Short name T436
Test name
Test status
Simulation time 13648333917 ps
CPU time 40.27 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:19:31 PM PDT 24
Peak memory 217040 kb
Host smart-06d3e23b-bbdc-4d51-a3c2-230e328fc2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342578682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2342578682
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2001592440
Short name T513
Test name
Test status
Simulation time 37070212 ps
CPU time 0.69 seconds
Started Aug 10 06:18:50 PM PDT 24
Finished Aug 10 06:18:51 PM PDT 24
Peak memory 206180 kb
Host smart-f0461e0d-a22f-4e62-af8c-6c0d607ea535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001592440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2001592440
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2906664506
Short name T764
Test name
Test status
Simulation time 251514109 ps
CPU time 1.16 seconds
Started Aug 10 06:18:51 PM PDT 24
Finished Aug 10 06:18:53 PM PDT 24
Peak memory 207740 kb
Host smart-cf4cacfe-da65-4e59-9b58-922b880f3a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906664506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2906664506
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1974874593
Short name T569
Test name
Test status
Simulation time 35648730 ps
CPU time 0.73 seconds
Started Aug 10 06:18:51 PM PDT 24
Finished Aug 10 06:18:52 PM PDT 24
Peak memory 206596 kb
Host smart-eda32085-e5d7-4ad5-b9a4-85190edcea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974874593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1974874593
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2254884188
Short name T460
Test name
Test status
Simulation time 3932140859 ps
CPU time 7.79 seconds
Started Aug 10 06:18:52 PM PDT 24
Finished Aug 10 06:19:00 PM PDT 24
Peak memory 233540 kb
Host smart-b3d0bc78-37ba-4070-97c3-80e0ff330511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254884188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2254884188
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2378570827
Short name T487
Test name
Test status
Simulation time 38123585 ps
CPU time 0.73 seconds
Started Aug 10 06:18:57 PM PDT 24
Finished Aug 10 06:18:57 PM PDT 24
Peak memory 205256 kb
Host smart-df51014b-c464-42c8-984e-ae0ab1d551be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378570827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2378570827
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2286748542
Short name T552
Test name
Test status
Simulation time 91871537 ps
CPU time 2.47 seconds
Started Aug 10 06:18:58 PM PDT 24
Finished Aug 10 06:19:01 PM PDT 24
Peak memory 225228 kb
Host smart-49c5caa5-1ce9-437f-9a48-f6dc0f9d6e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286748542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2286748542
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2054621149
Short name T1035
Test name
Test status
Simulation time 21338276 ps
CPU time 0.76 seconds
Started Aug 10 06:18:56 PM PDT 24
Finished Aug 10 06:18:57 PM PDT 24
Peak memory 206024 kb
Host smart-26ab4bf7-d96d-48c4-8c22-44bac25610c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054621149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2054621149
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3759565023
Short name T289
Test name
Test status
Simulation time 55427195764 ps
CPU time 129.46 seconds
Started Aug 10 06:18:54 PM PDT 24
Finished Aug 10 06:21:04 PM PDT 24
Peak memory 265400 kb
Host smart-277062b8-c64b-4df6-9a33-0001df48d2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759565023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3759565023
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.177775527
Short name T292
Test name
Test status
Simulation time 33246998342 ps
CPU time 49.04 seconds
Started Aug 10 06:18:56 PM PDT 24
Finished Aug 10 06:19:45 PM PDT 24
Peak memory 223936 kb
Host smart-c0559b41-3cf4-46e5-a893-bd5aa0181c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177775527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.177775527
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2445008552
Short name T422
Test name
Test status
Simulation time 44601212 ps
CPU time 2.85 seconds
Started Aug 10 06:18:56 PM PDT 24
Finished Aug 10 06:18:59 PM PDT 24
Peak memory 233496 kb
Host smart-42d5353a-c8e0-460e-998b-27a939fc7cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445008552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2445008552
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2138172395
Short name T947
Test name
Test status
Simulation time 1354243396 ps
CPU time 15.87 seconds
Started Aug 10 06:18:56 PM PDT 24
Finished Aug 10 06:19:12 PM PDT 24
Peak memory 233460 kb
Host smart-43808c1f-393e-4912-8cd2-027cf9e4e90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138172395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2138172395
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3480450910
Short name T660
Test name
Test status
Simulation time 1181326587 ps
CPU time 10.95 seconds
Started Aug 10 06:19:03 PM PDT 24
Finished Aug 10 06:19:15 PM PDT 24
Peak memory 233456 kb
Host smart-710e1e58-0503-4b32-b8da-5ebc1132bb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480450910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3480450910
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3786872620
Short name T564
Test name
Test status
Simulation time 40563187 ps
CPU time 1.01 seconds
Started Aug 10 06:18:59 PM PDT 24
Finished Aug 10 06:19:00 PM PDT 24
Peak memory 217156 kb
Host smart-c9ac85fb-687b-40c1-8e34-2e22d7f4765d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786872620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3786872620
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2714297767
Short name T56
Test name
Test status
Simulation time 57648661915 ps
CPU time 21.28 seconds
Started Aug 10 06:19:02 PM PDT 24
Finished Aug 10 06:19:23 PM PDT 24
Peak memory 241500 kb
Host smart-488b73be-67e3-4fb5-b3e1-cab63f61a70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714297767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2714297767
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2010832873
Short name T13
Test name
Test status
Simulation time 187327967 ps
CPU time 4.14 seconds
Started Aug 10 06:18:57 PM PDT 24
Finished Aug 10 06:19:01 PM PDT 24
Peak memory 241300 kb
Host smart-2c1be8c9-1f5f-4e97-a7ba-71191cc47fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010832873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2010832873
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2050220950
Short name T565
Test name
Test status
Simulation time 1194887873 ps
CPU time 4.37 seconds
Started Aug 10 06:18:57 PM PDT 24
Finished Aug 10 06:19:02 PM PDT 24
Peak memory 219632 kb
Host smart-b2018c70-2e0f-4cb7-9aef-fdf0e442efdc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2050220950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2050220950
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.4146032310
Short name T331
Test name
Test status
Simulation time 9084802858 ps
CPU time 43.05 seconds
Started Aug 10 06:19:00 PM PDT 24
Finished Aug 10 06:19:43 PM PDT 24
Peak memory 216972 kb
Host smart-c2e1dbb9-4ea2-4da2-868e-e5fca32ac348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146032310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4146032310
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3483858563
Short name T1030
Test name
Test status
Simulation time 7226768639 ps
CPU time 8.94 seconds
Started Aug 10 06:19:00 PM PDT 24
Finished Aug 10 06:19:09 PM PDT 24
Peak memory 217036 kb
Host smart-efa2f180-a5d0-4b2f-82f3-655801120ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483858563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3483858563
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.110653873
Short name T395
Test name
Test status
Simulation time 144404715 ps
CPU time 2.32 seconds
Started Aug 10 06:18:56 PM PDT 24
Finished Aug 10 06:18:58 PM PDT 24
Peak memory 217008 kb
Host smart-aeb035dc-d9de-4041-b605-1981a744528c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110653873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.110653873
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3544325417
Short name T661
Test name
Test status
Simulation time 41141507 ps
CPU time 0.67 seconds
Started Aug 10 06:18:57 PM PDT 24
Finished Aug 10 06:18:58 PM PDT 24
Peak memory 206040 kb
Host smart-aa4b648e-6d97-47a6-8182-f7ad035e77e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544325417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3544325417
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2083528514
Short name T678
Test name
Test status
Simulation time 406330026 ps
CPU time 2.39 seconds
Started Aug 10 06:18:57 PM PDT 24
Finished Aug 10 06:19:00 PM PDT 24
Peak memory 225236 kb
Host smart-39ac7580-c481-4cb4-a33a-dd810268d828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083528514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2083528514
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3683530677
Short name T391
Test name
Test status
Simulation time 30919070 ps
CPU time 0.73 seconds
Started Aug 10 06:19:04 PM PDT 24
Finished Aug 10 06:19:05 PM PDT 24
Peak memory 205212 kb
Host smart-4b7e0f39-fc9f-489c-89c2-ea0bc81adbdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683530677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3683530677
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.891393023
Short name T701
Test name
Test status
Simulation time 2073286942 ps
CPU time 6.81 seconds
Started Aug 10 06:19:04 PM PDT 24
Finished Aug 10 06:19:10 PM PDT 24
Peak memory 233436 kb
Host smart-8ff82879-29f3-45ff-8c5b-43d04977698e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891393023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.891393023
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2254332601
Short name T454
Test name
Test status
Simulation time 21525261 ps
CPU time 0.81 seconds
Started Aug 10 06:18:58 PM PDT 24
Finished Aug 10 06:18:59 PM PDT 24
Peak memory 207080 kb
Host smart-6d2485a3-7994-4b18-b9bd-f529dafc1537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254332601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2254332601
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1352952520
Short name T818
Test name
Test status
Simulation time 80508586140 ps
CPU time 346.89 seconds
Started Aug 10 06:19:04 PM PDT 24
Finished Aug 10 06:24:51 PM PDT 24
Peak memory 258192 kb
Host smart-ec331391-9a2a-47b0-8666-cde524903f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352952520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1352952520
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3517734148
Short name T496
Test name
Test status
Simulation time 1322176682 ps
CPU time 16.13 seconds
Started Aug 10 06:19:06 PM PDT 24
Finished Aug 10 06:19:22 PM PDT 24
Peak memory 233440 kb
Host smart-185ab710-95b6-4cc2-9527-2dc7d5fec628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517734148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3517734148
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1092282527
Short name T651
Test name
Test status
Simulation time 4455868193 ps
CPU time 20.21 seconds
Started Aug 10 06:19:08 PM PDT 24
Finished Aug 10 06:19:29 PM PDT 24
Peak memory 225364 kb
Host smart-043c9414-b9bc-4e38-a111-e2ffaef547b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092282527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1092282527
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2183223725
Short name T201
Test name
Test status
Simulation time 40469420099 ps
CPU time 70.67 seconds
Started Aug 10 06:19:04 PM PDT 24
Finished Aug 10 06:20:15 PM PDT 24
Peak memory 233560 kb
Host smart-727824b8-448f-45cc-9fa3-1f0c2ef34b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183223725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2183223725
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2823124697
Short name T47
Test name
Test status
Simulation time 36226317 ps
CPU time 1.02 seconds
Started Aug 10 06:18:59 PM PDT 24
Finished Aug 10 06:19:01 PM PDT 24
Peak memory 217208 kb
Host smart-f36b86c3-ccb8-4dce-b788-640a3802046a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823124697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2823124697
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2623557826
Short name T265
Test name
Test status
Simulation time 12206285224 ps
CPU time 18.7 seconds
Started Aug 10 06:19:04 PM PDT 24
Finished Aug 10 06:19:23 PM PDT 24
Peak memory 241692 kb
Host smart-d61753fe-cb43-4050-811c-b062a83ffdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623557826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2623557826
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2512633747
Short name T198
Test name
Test status
Simulation time 21136388162 ps
CPU time 13.41 seconds
Started Aug 10 06:19:03 PM PDT 24
Finished Aug 10 06:19:16 PM PDT 24
Peak memory 225284 kb
Host smart-544db696-a191-4a3f-baaa-c8cc16ad7d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512633747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2512633747
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1963269870
Short name T1006
Test name
Test status
Simulation time 208856557 ps
CPU time 5.13 seconds
Started Aug 10 06:19:03 PM PDT 24
Finished Aug 10 06:19:08 PM PDT 24
Peak memory 221068 kb
Host smart-c5e86359-d2bd-49c8-9c10-d70d3723bb8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1963269870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1963269870
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1146283285
Short name T669
Test name
Test status
Simulation time 16989070684 ps
CPU time 61.46 seconds
Started Aug 10 06:19:03 PM PDT 24
Finished Aug 10 06:20:05 PM PDT 24
Peak memory 251996 kb
Host smart-6a1aac63-031c-4ae5-8cc4-f703ae68a369
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146283285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1146283285
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3700151215
Short name T334
Test name
Test status
Simulation time 8919859845 ps
CPU time 22.17 seconds
Started Aug 10 06:19:03 PM PDT 24
Finished Aug 10 06:19:26 PM PDT 24
Peak memory 217080 kb
Host smart-209431c6-b146-471d-867c-079712c3b057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700151215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3700151215
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2254474133
Short name T866
Test name
Test status
Simulation time 2791159288 ps
CPU time 6.41 seconds
Started Aug 10 06:19:03 PM PDT 24
Finished Aug 10 06:19:10 PM PDT 24
Peak memory 217052 kb
Host smart-89fc3764-2d36-42a4-b9a1-f069a2f387db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254474133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2254474133
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3875071562
Short name T556
Test name
Test status
Simulation time 35935124 ps
CPU time 1.99 seconds
Started Aug 10 06:19:05 PM PDT 24
Finished Aug 10 06:19:07 PM PDT 24
Peak memory 217124 kb
Host smart-7c42b090-f463-4dba-9999-d4b400f67bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875071562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3875071562
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3248458254
Short name T136
Test name
Test status
Simulation time 86608369 ps
CPU time 0.81 seconds
Started Aug 10 06:19:04 PM PDT 24
Finished Aug 10 06:19:05 PM PDT 24
Peak memory 206584 kb
Host smart-933bf179-29b9-45cc-b225-136c81c5e6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248458254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3248458254
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3612306484
Short name T1034
Test name
Test status
Simulation time 9763623451 ps
CPU time 22.68 seconds
Started Aug 10 06:19:05 PM PDT 24
Finished Aug 10 06:19:28 PM PDT 24
Peak memory 235732 kb
Host smart-d53ae7ba-4b83-46a6-8951-2c5695feab81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612306484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3612306484
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1337447023
Short name T753
Test name
Test status
Simulation time 16456086 ps
CPU time 0.77 seconds
Started Aug 10 06:19:02 PM PDT 24
Finished Aug 10 06:19:03 PM PDT 24
Peak memory 206164 kb
Host smart-10beb3f5-88d2-45ea-8e41-87f5e319168a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337447023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1337447023
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2708912379
Short name T733
Test name
Test status
Simulation time 184748054 ps
CPU time 2.94 seconds
Started Aug 10 06:19:06 PM PDT 24
Finished Aug 10 06:19:09 PM PDT 24
Peak memory 233424 kb
Host smart-cc739501-0031-4a9c-9d07-8f8dc42a0e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708912379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2708912379
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2602383473
Short name T362
Test name
Test status
Simulation time 52224545 ps
CPU time 0.78 seconds
Started Aug 10 06:19:06 PM PDT 24
Finished Aug 10 06:19:06 PM PDT 24
Peak memory 206076 kb
Host smart-3bab396e-d274-4d9a-97cb-557e18512f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602383473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2602383473
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2383234491
Short name T717
Test name
Test status
Simulation time 3031419451 ps
CPU time 13.77 seconds
Started Aug 10 06:19:08 PM PDT 24
Finished Aug 10 06:19:22 PM PDT 24
Peak memory 241728 kb
Host smart-ab9a3150-37ab-4683-8b70-3ef0f3382d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383234491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2383234491
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1351163599
Short name T60
Test name
Test status
Simulation time 505576864 ps
CPU time 10.06 seconds
Started Aug 10 06:19:04 PM PDT 24
Finished Aug 10 06:19:15 PM PDT 24
Peak memory 225248 kb
Host smart-4d02b9d3-3939-4ba7-ae13-3864c753dbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351163599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1351163599
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3073680100
Short name T79
Test name
Test status
Simulation time 89190219377 ps
CPU time 201.18 seconds
Started Aug 10 06:19:05 PM PDT 24
Finished Aug 10 06:22:27 PM PDT 24
Peak memory 249952 kb
Host smart-05b67717-afa5-424e-a459-9a2960d5322f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073680100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3073680100
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3832585890
Short name T670
Test name
Test status
Simulation time 1525562452 ps
CPU time 4.41 seconds
Started Aug 10 06:19:06 PM PDT 24
Finished Aug 10 06:19:10 PM PDT 24
Peak memory 219572 kb
Host smart-218f6e24-a54c-413f-aa8a-d1a95125dd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832585890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3832585890
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1601859824
Short name T264
Test name
Test status
Simulation time 78414631104 ps
CPU time 151.66 seconds
Started Aug 10 06:19:04 PM PDT 24
Finished Aug 10 06:21:36 PM PDT 24
Peak memory 256232 kb
Host smart-855a3dfd-57f6-4282-aa17-25ed3da4ae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601859824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1601859824
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1320858226
Short name T988
Test name
Test status
Simulation time 210093323 ps
CPU time 3.54 seconds
Started Aug 10 06:19:06 PM PDT 24
Finished Aug 10 06:19:10 PM PDT 24
Peak memory 233524 kb
Host smart-5f3af525-f29f-4706-91fd-510fc16595e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320858226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1320858226
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2628239686
Short name T740
Test name
Test status
Simulation time 52871019 ps
CPU time 2.6 seconds
Started Aug 10 06:19:06 PM PDT 24
Finished Aug 10 06:19:09 PM PDT 24
Peak memory 225196 kb
Host smart-0f96ff9c-8ee6-4f1d-bf8b-f502774b906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628239686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2628239686
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1693645983
Short name T842
Test name
Test status
Simulation time 60870435 ps
CPU time 1.17 seconds
Started Aug 10 06:19:06 PM PDT 24
Finished Aug 10 06:19:08 PM PDT 24
Peak memory 217136 kb
Host smart-2db883c9-a871-42e6-8628-f9f1bf5d4263
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693645983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1693645983
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.83772699
Short name T611
Test name
Test status
Simulation time 306015730 ps
CPU time 3.87 seconds
Started Aug 10 06:19:04 PM PDT 24
Finished Aug 10 06:19:08 PM PDT 24
Peak memory 225168 kb
Host smart-c4f3059f-8f90-4f70-8f80-7252ba00637e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83772699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.83772699
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3322106632
Short name T512
Test name
Test status
Simulation time 749973440 ps
CPU time 3.97 seconds
Started Aug 10 06:19:05 PM PDT 24
Finished Aug 10 06:19:09 PM PDT 24
Peak memory 225192 kb
Host smart-f927de86-7464-4591-8726-5047965de3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322106632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3322106632
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3589056928
Short name T881
Test name
Test status
Simulation time 130562482 ps
CPU time 4.39 seconds
Started Aug 10 06:19:05 PM PDT 24
Finished Aug 10 06:19:10 PM PDT 24
Peak memory 221568 kb
Host smart-727dceb9-ab44-4d37-9491-60111c20f7a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3589056928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3589056928
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2666468607
Short name T727
Test name
Test status
Simulation time 97227912 ps
CPU time 1.05 seconds
Started Aug 10 06:19:07 PM PDT 24
Finished Aug 10 06:19:08 PM PDT 24
Peak memory 207648 kb
Host smart-0bcae402-646c-4195-b1cb-201c6bc81dc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666468607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2666468607
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.999686044
Short name T568
Test name
Test status
Simulation time 2727280825 ps
CPU time 19 seconds
Started Aug 10 06:19:05 PM PDT 24
Finished Aug 10 06:19:24 PM PDT 24
Peak memory 217064 kb
Host smart-1713fd5e-7f82-4f52-9220-8de07e3eeb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999686044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.999686044
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.751240163
Short name T369
Test name
Test status
Simulation time 6575353807 ps
CPU time 6.72 seconds
Started Aug 10 06:19:03 PM PDT 24
Finished Aug 10 06:19:09 PM PDT 24
Peak memory 217028 kb
Host smart-2b20dcc6-c86c-4d3c-a719-4479a097481e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751240163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.751240163
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3769302474
Short name T398
Test name
Test status
Simulation time 38256928 ps
CPU time 1.23 seconds
Started Aug 10 06:19:08 PM PDT 24
Finished Aug 10 06:19:10 PM PDT 24
Peak memory 208592 kb
Host smart-95cd7698-dc3f-44c1-8783-b9ab95f4f1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769302474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3769302474
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.101100063
Short name T344
Test name
Test status
Simulation time 198396981 ps
CPU time 0.88 seconds
Started Aug 10 06:19:03 PM PDT 24
Finished Aug 10 06:19:04 PM PDT 24
Peak memory 206556 kb
Host smart-04508ce4-cc4f-477f-8bee-79f428ed09b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101100063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.101100063
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.577791214
Short name T309
Test name
Test status
Simulation time 822184785 ps
CPU time 4.85 seconds
Started Aug 10 06:19:05 PM PDT 24
Finished Aug 10 06:19:10 PM PDT 24
Peak memory 225376 kb
Host smart-8bae405b-4481-49b7-9474-3b8eee6f3c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577791214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.577791214
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3485532499
Short name T1
Test name
Test status
Simulation time 50038931 ps
CPU time 0.69 seconds
Started Aug 10 06:19:10 PM PDT 24
Finished Aug 10 06:19:11 PM PDT 24
Peak memory 205876 kb
Host smart-aa0fa8d8-7e54-41c7-a8ab-1ec7aca539ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485532499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3485532499
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3690392147
Short name T489
Test name
Test status
Simulation time 113129679 ps
CPU time 3.15 seconds
Started Aug 10 06:19:10 PM PDT 24
Finished Aug 10 06:19:13 PM PDT 24
Peak memory 233432 kb
Host smart-9b2c6fda-03d5-49ea-b3e6-994469ca7842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690392147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3690392147
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.421426138
Short name T993
Test name
Test status
Simulation time 14553398 ps
CPU time 0.77 seconds
Started Aug 10 06:19:09 PM PDT 24
Finished Aug 10 06:19:10 PM PDT 24
Peak memory 207088 kb
Host smart-7df20183-118c-4e0c-9e05-a9f77855b161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421426138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.421426138
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1122526174
Short name T263
Test name
Test status
Simulation time 66962714091 ps
CPU time 655.55 seconds
Started Aug 10 06:19:13 PM PDT 24
Finished Aug 10 06:30:08 PM PDT 24
Peak memory 264160 kb
Host smart-acdf504e-c5f0-41d1-91b0-bc7580f7888b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122526174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1122526174
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1806378481
Short name T129
Test name
Test status
Simulation time 175782506364 ps
CPU time 286.1 seconds
Started Aug 10 06:19:12 PM PDT 24
Finished Aug 10 06:23:58 PM PDT 24
Peak memory 252008 kb
Host smart-c5ae1a46-b637-4fb6-9e5a-c42bb33f7008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806378481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1806378481
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1426576354
Short name T871
Test name
Test status
Simulation time 1052759068 ps
CPU time 4.99 seconds
Started Aug 10 06:19:11 PM PDT 24
Finished Aug 10 06:19:16 PM PDT 24
Peak memory 225168 kb
Host smart-36e1519a-f0cb-4b23-8c53-fb64a988cb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426576354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1426576354
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2544981935
Short name T288
Test name
Test status
Simulation time 4979340240 ps
CPU time 13.01 seconds
Started Aug 10 06:19:14 PM PDT 24
Finished Aug 10 06:19:27 PM PDT 24
Peak memory 233484 kb
Host smart-8b5057f1-0f03-499b-872c-8b8dca8d244c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544981935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2544981935
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3989557183
Short name T772
Test name
Test status
Simulation time 714362858 ps
CPU time 4.62 seconds
Started Aug 10 06:19:13 PM PDT 24
Finished Aug 10 06:19:18 PM PDT 24
Peak memory 227920 kb
Host smart-1cc90ce1-100a-4a1e-a811-9ca7dfd54d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989557183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3989557183
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.4118724259
Short name T539
Test name
Test status
Simulation time 14623099 ps
CPU time 1.03 seconds
Started Aug 10 06:19:10 PM PDT 24
Finished Aug 10 06:19:12 PM PDT 24
Peak memory 218452 kb
Host smart-7c2e7b99-aa7a-4ffc-9d70-f55a80b9211d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118724259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.4118724259
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.435660091
Short name T428
Test name
Test status
Simulation time 307606682 ps
CPU time 2.89 seconds
Started Aug 10 06:19:10 PM PDT 24
Finished Aug 10 06:19:13 PM PDT 24
Peak memory 225244 kb
Host smart-f5712191-9833-4289-8b6d-333bd180058e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435660091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.435660091
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3514361144
Short name T739
Test name
Test status
Simulation time 2488586752 ps
CPU time 12.47 seconds
Started Aug 10 06:19:09 PM PDT 24
Finished Aug 10 06:19:22 PM PDT 24
Peak memory 239632 kb
Host smart-23542953-c0b7-4ee4-8ac5-165f9b363ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514361144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3514361144
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3721183188
Short name T526
Test name
Test status
Simulation time 2279775675 ps
CPU time 7.42 seconds
Started Aug 10 06:19:10 PM PDT 24
Finished Aug 10 06:19:18 PM PDT 24
Peak memory 220264 kb
Host smart-3ae5187d-c6c7-4a61-b82a-366d24b7410f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3721183188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3721183188
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3197533320
Short name T579
Test name
Test status
Simulation time 3498897323 ps
CPU time 18.5 seconds
Started Aug 10 06:19:09 PM PDT 24
Finished Aug 10 06:19:28 PM PDT 24
Peak memory 217088 kb
Host smart-6e2685bf-c2fa-4e73-8d68-e5bb84c58902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197533320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3197533320
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.4035805027
Short name T974
Test name
Test status
Simulation time 734521665 ps
CPU time 4.97 seconds
Started Aug 10 06:19:15 PM PDT 24
Finished Aug 10 06:19:20 PM PDT 24
Peak memory 216968 kb
Host smart-187b85b3-7d01-4ad5-a89f-32f72facaf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035805027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4035805027
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.4008196399
Short name T2
Test name
Test status
Simulation time 62113443 ps
CPU time 1.14 seconds
Started Aug 10 06:19:10 PM PDT 24
Finished Aug 10 06:19:11 PM PDT 24
Peak memory 208632 kb
Host smart-2620db5e-7a3d-4122-b1bf-ceec3c6a12f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008196399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.4008196399
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3978170969
Short name T584
Test name
Test status
Simulation time 64294300 ps
CPU time 0.83 seconds
Started Aug 10 06:19:14 PM PDT 24
Finished Aug 10 06:19:14 PM PDT 24
Peak memory 206556 kb
Host smart-8bb82dd7-3901-437b-804b-6343304026b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978170969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3978170969
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1100291541
Short name T980
Test name
Test status
Simulation time 4441250375 ps
CPU time 17.55 seconds
Started Aug 10 06:19:09 PM PDT 24
Finished Aug 10 06:19:27 PM PDT 24
Peak memory 225240 kb
Host smart-c959d43d-bda7-43a4-9da4-67779d3d31c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100291541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1100291541
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1261393518
Short name T996
Test name
Test status
Simulation time 19797742 ps
CPU time 0.75 seconds
Started Aug 10 06:18:17 PM PDT 24
Finished Aug 10 06:18:18 PM PDT 24
Peak memory 206164 kb
Host smart-337a8f74-398d-4d11-bab9-082104a03cd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261393518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
261393518
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3181834289
Short name T544
Test name
Test status
Simulation time 367854814 ps
CPU time 2.45 seconds
Started Aug 10 06:18:17 PM PDT 24
Finished Aug 10 06:18:20 PM PDT 24
Peak memory 225220 kb
Host smart-3f3a8b0e-521d-42a3-99a7-2ab9d77d206c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181834289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3181834289
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3443460642
Short name T822
Test name
Test status
Simulation time 19640997 ps
CPU time 0.81 seconds
Started Aug 10 06:18:08 PM PDT 24
Finished Aug 10 06:18:09 PM PDT 24
Peak memory 207080 kb
Host smart-fbda6ed1-f92b-4852-964b-5283cc53e272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443460642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3443460642
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1922787947
Short name T521
Test name
Test status
Simulation time 71378745576 ps
CPU time 111.71 seconds
Started Aug 10 06:18:20 PM PDT 24
Finished Aug 10 06:20:12 PM PDT 24
Peak memory 257560 kb
Host smart-97f926ee-5da2-4c13-8a31-902a442f1ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922787947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1922787947
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2433983965
Short name T247
Test name
Test status
Simulation time 15961197327 ps
CPU time 65.2 seconds
Started Aug 10 06:18:14 PM PDT 24
Finished Aug 10 06:19:20 PM PDT 24
Peak memory 261900 kb
Host smart-8824fd85-86f0-462b-b125-605aab4c3eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433983965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2433983965
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1320016967
Short name T45
Test name
Test status
Simulation time 44863869480 ps
CPU time 437.27 seconds
Started Aug 10 06:18:17 PM PDT 24
Finished Aug 10 06:25:34 PM PDT 24
Peak memory 263000 kb
Host smart-29272134-a16b-4768-b44e-95a603eed715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320016967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1320016967
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3066968212
Short name T784
Test name
Test status
Simulation time 268864348 ps
CPU time 12.1 seconds
Started Aug 10 06:18:18 PM PDT 24
Finished Aug 10 06:18:30 PM PDT 24
Peak memory 249740 kb
Host smart-f4673ba8-e5d9-46f0-b752-7c312f7f6080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066968212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3066968212
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1739535346
Short name T170
Test name
Test status
Simulation time 16932389132 ps
CPU time 131.99 seconds
Started Aug 10 06:18:14 PM PDT 24
Finished Aug 10 06:20:26 PM PDT 24
Peak memory 250656 kb
Host smart-6d5e9a2a-f97d-48ae-9748-278eccc6aff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739535346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1739535346
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3649447236
Short name T295
Test name
Test status
Simulation time 4545382368 ps
CPU time 18.68 seconds
Started Aug 10 06:18:16 PM PDT 24
Finished Aug 10 06:18:35 PM PDT 24
Peak memory 233480 kb
Host smart-265fb793-136b-49ef-86a7-7e1669894dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649447236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3649447236
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3120508895
Short name T718
Test name
Test status
Simulation time 462294316 ps
CPU time 11.82 seconds
Started Aug 10 06:18:16 PM PDT 24
Finished Aug 10 06:18:28 PM PDT 24
Peak memory 251528 kb
Host smart-912f50d5-36de-4ebf-8fa7-25876ce4ed70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120508895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3120508895
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3576757082
Short name T903
Test name
Test status
Simulation time 38250795 ps
CPU time 1.14 seconds
Started Aug 10 06:18:08 PM PDT 24
Finished Aug 10 06:18:09 PM PDT 24
Peak memory 217188 kb
Host smart-eb4332fe-8ddd-41a3-87ad-ae5d5d0d023c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576757082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3576757082
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2021441778
Short name T962
Test name
Test status
Simulation time 7980206920 ps
CPU time 6.56 seconds
Started Aug 10 06:18:17 PM PDT 24
Finished Aug 10 06:18:23 PM PDT 24
Peak memory 225276 kb
Host smart-d1fb65dd-b6d4-45c2-8ef6-10bb444b6e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021441778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2021441778
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4224582265
Short name T815
Test name
Test status
Simulation time 522445919 ps
CPU time 5.56 seconds
Started Aug 10 06:18:18 PM PDT 24
Finished Aug 10 06:18:23 PM PDT 24
Peak memory 241392 kb
Host smart-98165ffd-882d-4aa4-9670-29afb3c8d7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224582265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4224582265
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3253126942
Short name T497
Test name
Test status
Simulation time 644083631 ps
CPU time 10.54 seconds
Started Aug 10 06:18:17 PM PDT 24
Finished Aug 10 06:18:28 PM PDT 24
Peak memory 219724 kb
Host smart-aae6ccd7-9d7b-4f9f-8202-65e1e234b9e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3253126942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3253126942
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3801020136
Short name T65
Test name
Test status
Simulation time 61413197 ps
CPU time 1.06 seconds
Started Aug 10 06:18:20 PM PDT 24
Finished Aug 10 06:18:21 PM PDT 24
Peak memory 235552 kb
Host smart-7fb9b4fc-6fe9-4ab8-a0c4-42d607213653
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801020136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3801020136
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3446652025
Short name T63
Test name
Test status
Simulation time 67911926 ps
CPU time 0.95 seconds
Started Aug 10 06:18:17 PM PDT 24
Finished Aug 10 06:18:18 PM PDT 24
Peak memory 207224 kb
Host smart-95f21c46-2d75-4fbc-9040-a66a72659829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446652025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3446652025
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.4054994452
Short name T682
Test name
Test status
Simulation time 1138015330 ps
CPU time 5.54 seconds
Started Aug 10 06:18:09 PM PDT 24
Finished Aug 10 06:18:15 PM PDT 24
Peak memory 218920 kb
Host smart-d7d1b123-5457-4594-9e22-8b5bcbd52dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054994452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.4054994452
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.246984656
Short name T775
Test name
Test status
Simulation time 2435153580 ps
CPU time 7.06 seconds
Started Aug 10 06:18:08 PM PDT 24
Finished Aug 10 06:18:16 PM PDT 24
Peak memory 217020 kb
Host smart-115d991b-7d92-4090-9c52-feb2fae4dcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246984656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.246984656
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.312698244
Short name T694
Test name
Test status
Simulation time 78759597 ps
CPU time 1.69 seconds
Started Aug 10 06:18:08 PM PDT 24
Finished Aug 10 06:18:10 PM PDT 24
Peak memory 216996 kb
Host smart-68d70cdf-a3a9-4a6e-beb2-a0bbf1d04ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312698244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.312698244
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1531082033
Short name T712
Test name
Test status
Simulation time 92721785 ps
CPU time 0.9 seconds
Started Aug 10 06:18:08 PM PDT 24
Finished Aug 10 06:18:09 PM PDT 24
Peak memory 206596 kb
Host smart-528cee89-2904-44f1-8ead-ff5a1cf161eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531082033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1531082033
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1814614598
Short name T50
Test name
Test status
Simulation time 1512526584 ps
CPU time 8.14 seconds
Started Aug 10 06:18:20 PM PDT 24
Finished Aug 10 06:18:28 PM PDT 24
Peak memory 240092 kb
Host smart-c0247878-bfc5-46bb-989a-cda9717f6e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814614598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1814614598
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.4276999950
Short name T674
Test name
Test status
Simulation time 42136822 ps
CPU time 0.72 seconds
Started Aug 10 06:19:10 PM PDT 24
Finished Aug 10 06:19:10 PM PDT 24
Peak memory 205284 kb
Host smart-6d07b816-b4a1-4fe2-ad5b-8cb6983f3593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276999950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
4276999950
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1345763750
Short name T594
Test name
Test status
Simulation time 605690323 ps
CPU time 5.39 seconds
Started Aug 10 06:19:10 PM PDT 24
Finished Aug 10 06:19:15 PM PDT 24
Peak memory 233400 kb
Host smart-6f1480ed-ec42-4084-bf8d-3e219ffdd744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345763750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1345763750
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.15964854
Short name T380
Test name
Test status
Simulation time 18145894 ps
CPU time 0.77 seconds
Started Aug 10 06:19:12 PM PDT 24
Finished Aug 10 06:19:13 PM PDT 24
Peak memory 207432 kb
Host smart-77b64027-e2d8-461c-9f98-fbe04ca2defc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15964854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.15964854
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.325426832
Short name T423
Test name
Test status
Simulation time 8080824496 ps
CPU time 59.75 seconds
Started Aug 10 06:19:09 PM PDT 24
Finished Aug 10 06:20:09 PM PDT 24
Peak memory 240824 kb
Host smart-fce40ace-836d-47cb-b28f-b8edda4320b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325426832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.325426832
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.199347616
Short name T631
Test name
Test status
Simulation time 7357684173 ps
CPU time 49.36 seconds
Started Aug 10 06:19:12 PM PDT 24
Finished Aug 10 06:20:02 PM PDT 24
Peak memory 241724 kb
Host smart-1a10b709-9c23-4b59-a8fa-7676d7b26b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199347616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.199347616
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1809947414
Short name T494
Test name
Test status
Simulation time 14421406226 ps
CPU time 37.32 seconds
Started Aug 10 06:19:13 PM PDT 24
Finished Aug 10 06:19:50 PM PDT 24
Peak memory 237780 kb
Host smart-73f87280-d1e3-4707-ab21-b0ab98d494b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809947414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1809947414
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2030644513
Short name T973
Test name
Test status
Simulation time 20239883191 ps
CPU time 66.42 seconds
Started Aug 10 06:19:09 PM PDT 24
Finished Aug 10 06:20:16 PM PDT 24
Peak memory 250700 kb
Host smart-72e41d14-5031-4e1a-bc71-9da582ed8d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030644513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2030644513
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2345620518
Short name T709
Test name
Test status
Simulation time 36864235619 ps
CPU time 248.22 seconds
Started Aug 10 06:19:12 PM PDT 24
Finished Aug 10 06:23:20 PM PDT 24
Peak memory 250560 kb
Host smart-9ea16be8-110d-495e-a4de-c06bf7ec8572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345620518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2345620518
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4184606030
Short name T451
Test name
Test status
Simulation time 674290597 ps
CPU time 6.29 seconds
Started Aug 10 06:19:10 PM PDT 24
Finished Aug 10 06:19:16 PM PDT 24
Peak memory 233496 kb
Host smart-4448cfaf-e71d-4e7d-b00a-f2b9d7c013ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184606030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4184606030
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3277449046
Short name T697
Test name
Test status
Simulation time 44949268042 ps
CPU time 75.93 seconds
Started Aug 10 06:19:11 PM PDT 24
Finished Aug 10 06:20:27 PM PDT 24
Peak memory 225280 kb
Host smart-c0d54f50-f188-428e-83e7-5c394684d7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277449046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3277449046
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1066256646
Short name T522
Test name
Test status
Simulation time 692260564 ps
CPU time 3.51 seconds
Started Aug 10 06:19:10 PM PDT 24
Finished Aug 10 06:19:14 PM PDT 24
Peak memory 225220 kb
Host smart-6364089c-8d73-4099-bc36-44277978686b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066256646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1066256646
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1627859834
Short name T762
Test name
Test status
Simulation time 25953844137 ps
CPU time 8.63 seconds
Started Aug 10 06:19:12 PM PDT 24
Finished Aug 10 06:19:21 PM PDT 24
Peak memory 225252 kb
Host smart-bc8e98e7-bb48-47d0-9417-08709ef69a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627859834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1627859834
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.948104907
Short name T703
Test name
Test status
Simulation time 656580612 ps
CPU time 4.18 seconds
Started Aug 10 06:19:08 PM PDT 24
Finished Aug 10 06:19:13 PM PDT 24
Peak memory 221388 kb
Host smart-80d1dc2b-42c8-4a77-8598-2bb60935688d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=948104907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.948104907
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1567356340
Short name T714
Test name
Test status
Simulation time 22856704947 ps
CPU time 189.11 seconds
Started Aug 10 06:19:13 PM PDT 24
Finished Aug 10 06:22:22 PM PDT 24
Peak memory 254804 kb
Host smart-aceb17b9-f1a9-496d-81ec-576c60ff3284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567356340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1567356340
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.285878132
Short name T505
Test name
Test status
Simulation time 1837942727 ps
CPU time 19.97 seconds
Started Aug 10 06:19:11 PM PDT 24
Finished Aug 10 06:19:31 PM PDT 24
Peak memory 217240 kb
Host smart-3dea4379-a24c-4592-ac77-f6a708f3b1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285878132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.285878132
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.7934074
Short name T675
Test name
Test status
Simulation time 3530870868 ps
CPU time 5.81 seconds
Started Aug 10 06:19:12 PM PDT 24
Finished Aug 10 06:19:18 PM PDT 24
Peak memory 217036 kb
Host smart-af9dadd4-a07a-491c-967f-8dc94251c072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7934074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.7934074
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.448826502
Short name T468
Test name
Test status
Simulation time 142782787 ps
CPU time 1.72 seconds
Started Aug 10 06:19:13 PM PDT 24
Finished Aug 10 06:19:14 PM PDT 24
Peak memory 216988 kb
Host smart-fe84b71c-3d48-4a5d-8641-a9034f030223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448826502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.448826502
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.4189748300
Short name T448
Test name
Test status
Simulation time 94693075 ps
CPU time 0.97 seconds
Started Aug 10 06:19:13 PM PDT 24
Finished Aug 10 06:19:14 PM PDT 24
Peak memory 207620 kb
Host smart-f770f176-14f9-4189-b4fd-a68e64f64f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189748300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4189748300
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.4035631207
Short name T692
Test name
Test status
Simulation time 4631416729 ps
CPU time 8.43 seconds
Started Aug 10 06:19:09 PM PDT 24
Finished Aug 10 06:19:18 PM PDT 24
Peak memory 233508 kb
Host smart-1b08ad94-8ee7-43aa-85a6-47564ad6ff94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035631207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4035631207
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.997188672
Short name T638
Test name
Test status
Simulation time 91166093 ps
CPU time 0.7 seconds
Started Aug 10 06:19:19 PM PDT 24
Finished Aug 10 06:19:20 PM PDT 24
Peak memory 205272 kb
Host smart-9a7640a8-e438-4a3a-902b-8f5f3488ce0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997188672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.997188672
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.749187753
Short name T952
Test name
Test status
Simulation time 496507428 ps
CPU time 4.01 seconds
Started Aug 10 06:19:17 PM PDT 24
Finished Aug 10 06:19:22 PM PDT 24
Peak memory 225228 kb
Host smart-cf3ccf99-cb1b-4862-b738-facb00be452b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749187753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.749187753
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3474307484
Short name T394
Test name
Test status
Simulation time 26549808 ps
CPU time 0.76 seconds
Started Aug 10 06:19:10 PM PDT 24
Finished Aug 10 06:19:11 PM PDT 24
Peak memory 207028 kb
Host smart-fa123fd2-3c59-47d9-9616-517f6ee85d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474307484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3474307484
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.197163390
Short name T912
Test name
Test status
Simulation time 5163685771 ps
CPU time 45.25 seconds
Started Aug 10 06:19:16 PM PDT 24
Finished Aug 10 06:20:02 PM PDT 24
Peak memory 249940 kb
Host smart-e15de5c0-54f4-447a-a850-1a0bd1fa601f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197163390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.197163390
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.880183061
Short name T483
Test name
Test status
Simulation time 989157246 ps
CPU time 18.05 seconds
Started Aug 10 06:19:18 PM PDT 24
Finished Aug 10 06:19:36 PM PDT 24
Peak memory 241664 kb
Host smart-02406311-facb-4c48-9980-75cc5381337b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880183061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.880183061
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1932024868
Short name T725
Test name
Test status
Simulation time 283602616 ps
CPU time 4.69 seconds
Started Aug 10 06:19:23 PM PDT 24
Finished Aug 10 06:19:27 PM PDT 24
Peak memory 241584 kb
Host smart-45317137-a95d-44d5-9ea9-2c4387f75fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932024868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1932024868
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3854036116
Short name T559
Test name
Test status
Simulation time 2159586708 ps
CPU time 16.69 seconds
Started Aug 10 06:19:20 PM PDT 24
Finished Aug 10 06:19:37 PM PDT 24
Peak memory 225320 kb
Host smart-5e09a58e-7d03-4d2e-91d2-02f4bf4b4bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854036116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3854036116
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3691413664
Short name T560
Test name
Test status
Simulation time 235571417 ps
CPU time 5.8 seconds
Started Aug 10 06:19:22 PM PDT 24
Finished Aug 10 06:19:28 PM PDT 24
Peak memory 233320 kb
Host smart-95412665-2032-40ae-ac35-f5da0429f849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691413664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3691413664
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1926585833
Short name T803
Test name
Test status
Simulation time 50966684564 ps
CPU time 65.25 seconds
Started Aug 10 06:19:19 PM PDT 24
Finished Aug 10 06:20:24 PM PDT 24
Peak memory 249440 kb
Host smart-c6913d24-ef3b-4090-957f-5ebeffa1e939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926585833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1926585833
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3561585815
Short name T167
Test name
Test status
Simulation time 41240156056 ps
CPU time 24.36 seconds
Started Aug 10 06:19:20 PM PDT 24
Finished Aug 10 06:19:45 PM PDT 24
Peak memory 225304 kb
Host smart-cc39bd41-2d0a-4322-9a51-0594a9fdd397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561585815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3561585815
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3445855741
Short name T24
Test name
Test status
Simulation time 941324180 ps
CPU time 6.91 seconds
Started Aug 10 06:19:18 PM PDT 24
Finished Aug 10 06:19:25 PM PDT 24
Peak memory 225224 kb
Host smart-36d8196d-08a7-40ca-8502-de8cf6841b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445855741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3445855741
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1932135784
Short name T149
Test name
Test status
Simulation time 14945536505 ps
CPU time 11.62 seconds
Started Aug 10 06:19:20 PM PDT 24
Finished Aug 10 06:19:32 PM PDT 24
Peak memory 219572 kb
Host smart-4dd540ca-b8cc-4e56-81ab-64b4e83a5f72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1932135784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1932135784
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.869239564
Short name T833
Test name
Test status
Simulation time 48664853465 ps
CPU time 382.3 seconds
Started Aug 10 06:19:17 PM PDT 24
Finished Aug 10 06:25:39 PM PDT 24
Peak memory 264528 kb
Host smart-f8cbde5a-4ca6-488e-9823-d74faf829213
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869239564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.869239564
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3360228230
Short name T337
Test name
Test status
Simulation time 753906503 ps
CPU time 11.37 seconds
Started Aug 10 06:19:22 PM PDT 24
Finished Aug 10 06:19:34 PM PDT 24
Peak memory 217164 kb
Host smart-1b89cb7c-0d66-47ee-9fdf-4fa02efc5642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360228230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3360228230
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2386405157
Short name T397
Test name
Test status
Simulation time 1191985406 ps
CPU time 5.8 seconds
Started Aug 10 06:19:23 PM PDT 24
Finished Aug 10 06:19:29 PM PDT 24
Peak memory 216932 kb
Host smart-473c44ef-4a00-4de0-b471-299b888596f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386405157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2386405157
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.156242586
Short name T531
Test name
Test status
Simulation time 13700667 ps
CPU time 0.8 seconds
Started Aug 10 06:19:21 PM PDT 24
Finished Aug 10 06:19:22 PM PDT 24
Peak memory 207112 kb
Host smart-4c69386d-b045-407f-b726-1693e5d5e3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156242586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.156242586
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.356010643
Short name T84
Test name
Test status
Simulation time 48044060 ps
CPU time 0.82 seconds
Started Aug 10 06:19:22 PM PDT 24
Finished Aug 10 06:19:22 PM PDT 24
Peak memory 206524 kb
Host smart-b48b7da8-e921-441d-a9fe-4aff28c3db78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356010643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.356010643
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1240603074
Short name T1001
Test name
Test status
Simulation time 2618302375 ps
CPU time 11.18 seconds
Started Aug 10 06:19:18 PM PDT 24
Finished Aug 10 06:19:29 PM PDT 24
Peak memory 233536 kb
Host smart-ba2b3b82-7106-49ca-9196-c2b6311c76e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240603074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1240603074
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.407147247
Short name T1012
Test name
Test status
Simulation time 38930795 ps
CPU time 0.75 seconds
Started Aug 10 06:19:20 PM PDT 24
Finished Aug 10 06:19:21 PM PDT 24
Peak memory 205868 kb
Host smart-055d556f-e5a8-4751-b788-dd4b57500027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407147247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.407147247
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1530502825
Short name T469
Test name
Test status
Simulation time 3745355495 ps
CPU time 19.89 seconds
Started Aug 10 06:19:22 PM PDT 24
Finished Aug 10 06:19:42 PM PDT 24
Peak memory 233384 kb
Host smart-7df5476a-d1e0-4a69-a377-10055075112f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530502825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1530502825
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3595727921
Short name T686
Test name
Test status
Simulation time 28676474 ps
CPU time 0.76 seconds
Started Aug 10 06:19:22 PM PDT 24
Finished Aug 10 06:19:23 PM PDT 24
Peak memory 207004 kb
Host smart-64c1cdbb-e0ff-4ffa-92d5-ffefa1f37d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595727921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3595727921
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3031440585
Short name T1018
Test name
Test status
Simulation time 179311447887 ps
CPU time 382.43 seconds
Started Aug 10 06:19:21 PM PDT 24
Finished Aug 10 06:25:44 PM PDT 24
Peak memory 266308 kb
Host smart-f227b1ee-53d9-4faf-969c-b7419a09494c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031440585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3031440585
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1567898013
Short name T942
Test name
Test status
Simulation time 22404297691 ps
CPU time 256.03 seconds
Started Aug 10 06:19:19 PM PDT 24
Finished Aug 10 06:23:35 PM PDT 24
Peak memory 262272 kb
Host smart-28d3ef70-ce05-4462-ab84-0ec254ea1c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567898013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1567898013
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3011694359
Short name T896
Test name
Test status
Simulation time 142625488 ps
CPU time 3.23 seconds
Started Aug 10 06:19:17 PM PDT 24
Finished Aug 10 06:19:20 PM PDT 24
Peak memory 233436 kb
Host smart-da1b6aed-644f-413f-ae07-a8389b9b2bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011694359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3011694359
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1926430614
Short name T789
Test name
Test status
Simulation time 1285512997 ps
CPU time 12.91 seconds
Started Aug 10 06:19:19 PM PDT 24
Finished Aug 10 06:19:32 PM PDT 24
Peak memory 233464 kb
Host smart-d0483dfe-9aa0-46fb-9d15-963bae0a5b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926430614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1926430614
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2155527249
Short name T645
Test name
Test status
Simulation time 5281015725 ps
CPU time 29.44 seconds
Started Aug 10 06:19:19 PM PDT 24
Finished Aug 10 06:19:49 PM PDT 24
Peak memory 234512 kb
Host smart-0fb8870a-380f-4c96-b593-e8ad462e9e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155527249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2155527249
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.19524366
Short name T209
Test name
Test status
Simulation time 221039602 ps
CPU time 4.3 seconds
Started Aug 10 06:19:21 PM PDT 24
Finished Aug 10 06:19:25 PM PDT 24
Peak memory 225208 kb
Host smart-46422f11-f318-417a-8502-7e4102828c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19524366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.19524366
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2889654692
Short name T877
Test name
Test status
Simulation time 2093331776 ps
CPU time 15.09 seconds
Started Aug 10 06:19:21 PM PDT 24
Finished Aug 10 06:19:36 PM PDT 24
Peak memory 220704 kb
Host smart-22ed589e-4065-4707-a6bd-383b1750c9c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2889654692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2889654692
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2508365886
Short name T528
Test name
Test status
Simulation time 32200529216 ps
CPU time 40.04 seconds
Started Aug 10 06:19:20 PM PDT 24
Finished Aug 10 06:20:00 PM PDT 24
Peak memory 217004 kb
Host smart-f092fe94-5f17-4f5b-b104-976b8a530926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508365886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2508365886
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.872055249
Short name T643
Test name
Test status
Simulation time 2081509690 ps
CPU time 5.8 seconds
Started Aug 10 06:19:19 PM PDT 24
Finished Aug 10 06:19:25 PM PDT 24
Peak memory 216976 kb
Host smart-93a7bade-1ab1-431c-886a-0e0cd8609ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872055249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.872055249
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2993731060
Short name T401
Test name
Test status
Simulation time 16751724 ps
CPU time 0.74 seconds
Started Aug 10 06:19:21 PM PDT 24
Finished Aug 10 06:19:21 PM PDT 24
Peak memory 206600 kb
Host smart-306b2426-c59e-402f-b1c2-34115ee4ab2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993731060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2993731060
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1386606240
Short name T920
Test name
Test status
Simulation time 721509881 ps
CPU time 0.96 seconds
Started Aug 10 06:19:18 PM PDT 24
Finished Aug 10 06:19:19 PM PDT 24
Peak memory 207564 kb
Host smart-0642c0e6-d623-4395-9c28-8bde428c8bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386606240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1386606240
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1978625172
Short name T745
Test name
Test status
Simulation time 5687993130 ps
CPU time 17.67 seconds
Started Aug 10 06:19:20 PM PDT 24
Finished Aug 10 06:19:38 PM PDT 24
Peak memory 234584 kb
Host smart-e63be031-db79-41c4-a813-ecb0c7bd32ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978625172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1978625172
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3774379008
Short name T475
Test name
Test status
Simulation time 20203597 ps
CPU time 0.7 seconds
Started Aug 10 06:19:26 PM PDT 24
Finished Aug 10 06:19:26 PM PDT 24
Peak memory 205840 kb
Host smart-6909ab8c-b5cd-435d-af0b-1ac1e50d19bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774379008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3774379008
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2818976483
Short name T634
Test name
Test status
Simulation time 150534802 ps
CPU time 4.27 seconds
Started Aug 10 06:19:23 PM PDT 24
Finished Aug 10 06:19:28 PM PDT 24
Peak memory 225236 kb
Host smart-ccf65928-f7e5-494d-9e8d-239b03bdfdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818976483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2818976483
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.540322030
Short name T667
Test name
Test status
Simulation time 16428959 ps
CPU time 0.78 seconds
Started Aug 10 06:19:22 PM PDT 24
Finished Aug 10 06:19:23 PM PDT 24
Peak memory 206048 kb
Host smart-4af51e7b-2ed9-4f13-82e7-92c07c01508b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540322030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.540322030
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3436952320
Short name T656
Test name
Test status
Simulation time 55275087815 ps
CPU time 216.09 seconds
Started Aug 10 06:19:21 PM PDT 24
Finished Aug 10 06:22:57 PM PDT 24
Peak memory 257332 kb
Host smart-dbb435c8-2459-48e7-81c6-9ef25cea2f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436952320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3436952320
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1255939926
Short name T291
Test name
Test status
Simulation time 2367736576 ps
CPU time 28.29 seconds
Started Aug 10 06:19:24 PM PDT 24
Finished Aug 10 06:19:53 PM PDT 24
Peak memory 239896 kb
Host smart-a96fb6d0-a836-4e94-a91a-e4d614f399bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255939926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1255939926
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.11620849
Short name T853
Test name
Test status
Simulation time 4314775521 ps
CPU time 94.18 seconds
Started Aug 10 06:19:25 PM PDT 24
Finished Aug 10 06:21:00 PM PDT 24
Peak memory 265900 kb
Host smart-c72cb417-2d19-4854-940b-82ce9a4274b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11620849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.11620849
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1316940225
Short name T326
Test name
Test status
Simulation time 288369351 ps
CPU time 10.28 seconds
Started Aug 10 06:19:21 PM PDT 24
Finished Aug 10 06:19:31 PM PDT 24
Peak memory 235596 kb
Host smart-641ca0b0-5c21-4541-84e8-1af6dafcf3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316940225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1316940225
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.270581372
Short name T810
Test name
Test status
Simulation time 1894262238 ps
CPU time 20.04 seconds
Started Aug 10 06:19:18 PM PDT 24
Finished Aug 10 06:19:38 PM PDT 24
Peak memory 225200 kb
Host smart-732d6a79-0fdc-4e23-813a-e70631f8f61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270581372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.270581372
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2186472112
Short name T319
Test name
Test status
Simulation time 1325952943 ps
CPU time 5.68 seconds
Started Aug 10 06:19:19 PM PDT 24
Finished Aug 10 06:19:25 PM PDT 24
Peak memory 225232 kb
Host smart-17ba6655-90aa-436d-98ea-8444d1bbf21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186472112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2186472112
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1200286687
Short name T749
Test name
Test status
Simulation time 2236825132 ps
CPU time 8.84 seconds
Started Aug 10 06:19:19 PM PDT 24
Finished Aug 10 06:19:28 PM PDT 24
Peak memory 241672 kb
Host smart-6195e2f8-ca84-42ae-9f9d-2e97958eca5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200286687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1200286687
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3958670312
Short name T296
Test name
Test status
Simulation time 426304936 ps
CPU time 2.66 seconds
Started Aug 10 06:19:22 PM PDT 24
Finished Aug 10 06:19:25 PM PDT 24
Peak memory 225160 kb
Host smart-f5d4aff5-823e-4554-b37a-608162669ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958670312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3958670312
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1853833936
Short name T543
Test name
Test status
Simulation time 607873653 ps
CPU time 4.32 seconds
Started Aug 10 06:19:19 PM PDT 24
Finished Aug 10 06:19:23 PM PDT 24
Peak memory 223212 kb
Host smart-cc9106d5-5895-46c0-8e98-0e095759e727
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1853833936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1853833936
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.541965542
Short name T1019
Test name
Test status
Simulation time 2424923032 ps
CPU time 56.68 seconds
Started Aug 10 06:19:26 PM PDT 24
Finished Aug 10 06:20:22 PM PDT 24
Peak memory 253928 kb
Host smart-0a24c355-fa6b-4b32-8ee2-fe483e0eb06d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541965542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.541965542
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1617765563
Short name T577
Test name
Test status
Simulation time 34057756 ps
CPU time 0.69 seconds
Started Aug 10 06:19:18 PM PDT 24
Finished Aug 10 06:19:19 PM PDT 24
Peak memory 206184 kb
Host smart-e09f7831-d16a-4b99-9be0-1be0cff6365d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617765563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1617765563
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3009187762
Short name T71
Test name
Test status
Simulation time 4363936519 ps
CPU time 3.64 seconds
Started Aug 10 06:19:18 PM PDT 24
Finished Aug 10 06:19:21 PM PDT 24
Peak memory 208664 kb
Host smart-78599a95-ef49-4f6a-8cd9-408ed7c21c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009187762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3009187762
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2275265643
Short name T875
Test name
Test status
Simulation time 58636045 ps
CPU time 2.72 seconds
Started Aug 10 06:19:18 PM PDT 24
Finished Aug 10 06:19:21 PM PDT 24
Peak memory 217008 kb
Host smart-8c5d45c8-67ca-4511-8f0e-37f29b36d69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275265643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2275265643
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1683352011
Short name T447
Test name
Test status
Simulation time 72653559 ps
CPU time 0.96 seconds
Started Aug 10 06:19:18 PM PDT 24
Finished Aug 10 06:19:19 PM PDT 24
Peak memory 207600 kb
Host smart-abea591b-e346-4de8-94ed-744865943e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683352011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1683352011
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.361189302
Short name T668
Test name
Test status
Simulation time 16313098405 ps
CPU time 15.57 seconds
Started Aug 10 06:19:22 PM PDT 24
Finished Aug 10 06:19:38 PM PDT 24
Peak memory 233536 kb
Host smart-f52d45a1-bc25-432f-8e9c-d4f8108d5ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361189302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.361189302
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.579371689
Short name T541
Test name
Test status
Simulation time 13843711 ps
CPU time 0.7 seconds
Started Aug 10 06:19:25 PM PDT 24
Finished Aug 10 06:19:26 PM PDT 24
Peak memory 206232 kb
Host smart-756be936-967b-4318-ad91-eaa05fb02660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579371689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.579371689
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2213332058
Short name T807
Test name
Test status
Simulation time 329899272 ps
CPU time 3.17 seconds
Started Aug 10 06:19:23 PM PDT 24
Finished Aug 10 06:19:27 PM PDT 24
Peak memory 233364 kb
Host smart-e8a2e816-3e80-4d2b-a5d2-aecfbb3f7465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213332058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2213332058
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.4191382948
Short name T466
Test name
Test status
Simulation time 15221684 ps
CPU time 0.77 seconds
Started Aug 10 06:19:27 PM PDT 24
Finished Aug 10 06:19:28 PM PDT 24
Peak memory 207340 kb
Host smart-335b21d6-9e9b-4462-89b4-4daff0c8a17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191382948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.4191382948
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1475484169
Short name T510
Test name
Test status
Simulation time 63307890780 ps
CPU time 90.09 seconds
Started Aug 10 06:19:31 PM PDT 24
Finished Aug 10 06:21:02 PM PDT 24
Peak memory 249960 kb
Host smart-55110bf4-3f82-44da-9f58-7132c41dbc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475484169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1475484169
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3645474982
Short name T316
Test name
Test status
Simulation time 115041926299 ps
CPU time 306.87 seconds
Started Aug 10 06:19:31 PM PDT 24
Finished Aug 10 06:24:38 PM PDT 24
Peak memory 249976 kb
Host smart-c8a3a493-2808-47a0-a598-ff0c4a1edf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645474982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3645474982
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.4148138965
Short name T1020
Test name
Test status
Simulation time 3773377636 ps
CPU time 16.49 seconds
Started Aug 10 06:19:25 PM PDT 24
Finished Aug 10 06:19:42 PM PDT 24
Peak memory 233572 kb
Host smart-b61efda7-1af0-4045-977d-0f15ed272f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148138965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.4148138965
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1498085829
Short name T1003
Test name
Test status
Simulation time 1930086670 ps
CPU time 24.16 seconds
Started Aug 10 06:19:24 PM PDT 24
Finished Aug 10 06:19:49 PM PDT 24
Peak memory 241672 kb
Host smart-b5e9dbad-bcc5-48dd-b5bc-cbfa72e1baef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498085829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1498085829
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3404754425
Short name T196
Test name
Test status
Simulation time 2082096897 ps
CPU time 12.69 seconds
Started Aug 10 06:19:32 PM PDT 24
Finished Aug 10 06:19:44 PM PDT 24
Peak memory 225304 kb
Host smart-339df4ac-9720-4e5f-90ec-4d01e57360ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404754425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3404754425
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1456673950
Short name T706
Test name
Test status
Simulation time 1649901873 ps
CPU time 11.49 seconds
Started Aug 10 06:19:25 PM PDT 24
Finished Aug 10 06:19:36 PM PDT 24
Peak memory 233448 kb
Host smart-a4598dbd-85d9-4d9d-a41b-2ee39916504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456673950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1456673950
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.748947052
Short name T290
Test name
Test status
Simulation time 1411890792 ps
CPU time 8.33 seconds
Started Aug 10 06:19:24 PM PDT 24
Finished Aug 10 06:19:32 PM PDT 24
Peak memory 241136 kb
Host smart-3c27cd05-f837-4881-a56f-b5aa58b921c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748947052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.748947052
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.840222632
Short name T470
Test name
Test status
Simulation time 880855868 ps
CPU time 4.81 seconds
Started Aug 10 06:19:25 PM PDT 24
Finished Aug 10 06:19:30 PM PDT 24
Peak memory 233444 kb
Host smart-42e7ba2b-cd1f-4e11-b65d-524a62b8871a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840222632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.840222632
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4198847090
Short name T567
Test name
Test status
Simulation time 262029912 ps
CPU time 4.71 seconds
Started Aug 10 06:19:29 PM PDT 24
Finished Aug 10 06:19:34 PM PDT 24
Peak memory 220796 kb
Host smart-1858873b-293e-48f6-ad24-0a0c1f28b87b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4198847090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4198847090
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2415343175
Short name T163
Test name
Test status
Simulation time 310251335 ps
CPU time 1.18 seconds
Started Aug 10 06:19:31 PM PDT 24
Finished Aug 10 06:19:32 PM PDT 24
Peak memory 208224 kb
Host smart-6d47fa58-548b-4120-b90e-c7dacd047dd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415343175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2415343175
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3702878133
Short name T591
Test name
Test status
Simulation time 733634853 ps
CPU time 5.76 seconds
Started Aug 10 06:19:27 PM PDT 24
Finished Aug 10 06:19:33 PM PDT 24
Peak memory 216996 kb
Host smart-688dd023-6e47-4d04-b79c-97bec58b8248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702878133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3702878133
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1177538956
Short name T624
Test name
Test status
Simulation time 8840844526 ps
CPU time 6.43 seconds
Started Aug 10 06:19:26 PM PDT 24
Finished Aug 10 06:19:33 PM PDT 24
Peak memory 217028 kb
Host smart-430d6843-272d-4812-9a78-8cd3642f0607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177538956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1177538956
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.140311568
Short name T827
Test name
Test status
Simulation time 428658695 ps
CPU time 2.19 seconds
Started Aug 10 06:19:29 PM PDT 24
Finished Aug 10 06:19:31 PM PDT 24
Peak memory 216804 kb
Host smart-8becd0ce-277e-449c-8aa0-cdd2db91e7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140311568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.140311568
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.926002119
Short name T33
Test name
Test status
Simulation time 22276704 ps
CPU time 0.77 seconds
Started Aug 10 06:19:31 PM PDT 24
Finished Aug 10 06:19:32 PM PDT 24
Peak memory 206592 kb
Host smart-700a7ca6-d880-4859-ab07-2b27dbce2a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926002119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.926002119
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.363450831
Short name T601
Test name
Test status
Simulation time 33841283 ps
CPU time 2.42 seconds
Started Aug 10 06:19:32 PM PDT 24
Finished Aug 10 06:19:35 PM PDT 24
Peak memory 233428 kb
Host smart-18ab02f9-4570-4d2e-b8fb-b6b3e8788088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363450831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.363450831
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3315207104
Short name T921
Test name
Test status
Simulation time 51801928 ps
CPU time 0.8 seconds
Started Aug 10 06:19:32 PM PDT 24
Finished Aug 10 06:19:33 PM PDT 24
Peak memory 205288 kb
Host smart-f0cb22b8-5c38-43c0-9ce0-af164d5051bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315207104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3315207104
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2906332103
Short name T175
Test name
Test status
Simulation time 629192119 ps
CPU time 7.9 seconds
Started Aug 10 06:19:26 PM PDT 24
Finished Aug 10 06:19:34 PM PDT 24
Peak memory 233436 kb
Host smart-cefa6387-01ae-4226-8817-b78fbfc0a830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906332103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2906332103
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.324715232
Short name T613
Test name
Test status
Simulation time 20582596 ps
CPU time 0.78 seconds
Started Aug 10 06:19:32 PM PDT 24
Finished Aug 10 06:19:33 PM PDT 24
Peak memory 206064 kb
Host smart-616a6e68-f8d3-4ba7-819d-0e6a58bedfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324715232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.324715232
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3145115253
Short name T970
Test name
Test status
Simulation time 86034925 ps
CPU time 0.73 seconds
Started Aug 10 06:19:24 PM PDT 24
Finished Aug 10 06:19:25 PM PDT 24
Peak memory 216460 kb
Host smart-78b60d53-c654-4d66-97d0-ddb10aa19eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145115253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3145115253
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.300510830
Short name T654
Test name
Test status
Simulation time 17539983630 ps
CPU time 157.85 seconds
Started Aug 10 06:19:27 PM PDT 24
Finished Aug 10 06:22:05 PM PDT 24
Peak memory 249972 kb
Host smart-896a23d7-d920-4c04-9dcd-173bb788a8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300510830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.300510830
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2348654491
Short name T328
Test name
Test status
Simulation time 8327431290 ps
CPU time 12.9 seconds
Started Aug 10 06:19:26 PM PDT 24
Finished Aug 10 06:19:39 PM PDT 24
Peak memory 225288 kb
Host smart-ab4ac31c-5be4-4f60-9195-b6541124c2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348654491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2348654491
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1056820556
Short name T767
Test name
Test status
Simulation time 25563266936 ps
CPU time 53.94 seconds
Started Aug 10 06:19:32 PM PDT 24
Finished Aug 10 06:20:26 PM PDT 24
Peak memory 241728 kb
Host smart-c5c5a31b-8bfc-4b44-af7c-3dba5ab37659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056820556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1056820556
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1504246230
Short name T114
Test name
Test status
Simulation time 408893164 ps
CPU time 5.33 seconds
Started Aug 10 06:19:25 PM PDT 24
Finished Aug 10 06:19:30 PM PDT 24
Peak memory 225224 kb
Host smart-1a5a3eb3-771c-41e3-a7aa-6a80dda218e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504246230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1504246230
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.894063989
Short name T893
Test name
Test status
Simulation time 1283239852 ps
CPU time 24.36 seconds
Started Aug 10 06:19:24 PM PDT 24
Finished Aug 10 06:19:49 PM PDT 24
Peak memory 241324 kb
Host smart-66c7a9a2-7873-4386-87bf-f07c4c0ce81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894063989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.894063989
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2090769046
Short name T446
Test name
Test status
Simulation time 270415687 ps
CPU time 2.55 seconds
Started Aug 10 06:19:24 PM PDT 24
Finished Aug 10 06:19:27 PM PDT 24
Peak memory 225216 kb
Host smart-702c8946-d4c8-43b5-9ac2-916e051b38ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090769046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2090769046
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.145021195
Short name T985
Test name
Test status
Simulation time 503347433 ps
CPU time 4.98 seconds
Started Aug 10 06:19:25 PM PDT 24
Finished Aug 10 06:19:30 PM PDT 24
Peak memory 241568 kb
Host smart-57995935-8a7d-45ad-99d6-939c07724c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145021195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.145021195
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4123764829
Short name T130
Test name
Test status
Simulation time 425230884 ps
CPU time 5.08 seconds
Started Aug 10 06:19:25 PM PDT 24
Finished Aug 10 06:19:31 PM PDT 24
Peak memory 219436 kb
Host smart-27463898-8da1-4e08-bd7e-f691bd5d97a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4123764829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4123764829
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.661472464
Short name T4
Test name
Test status
Simulation time 13615254778 ps
CPU time 75.05 seconds
Started Aug 10 06:19:26 PM PDT 24
Finished Aug 10 06:20:41 PM PDT 24
Peak memory 266152 kb
Host smart-fe768319-1c41-41b6-b70e-fe8f931dd584
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661472464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.661472464
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4050333151
Short name T343
Test name
Test status
Simulation time 2690247559 ps
CPU time 23.81 seconds
Started Aug 10 06:19:24 PM PDT 24
Finished Aug 10 06:19:48 PM PDT 24
Peak memory 217040 kb
Host smart-e62d8b06-6bbe-4b23-8d8c-74d89e122879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050333151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4050333151
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1724266556
Short name T609
Test name
Test status
Simulation time 8177234107 ps
CPU time 20.98 seconds
Started Aug 10 06:19:29 PM PDT 24
Finished Aug 10 06:19:51 PM PDT 24
Peak memory 216880 kb
Host smart-fb55bc9e-c2d3-41c5-a7f0-da052c7a5c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724266556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1724266556
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1700490257
Short name T435
Test name
Test status
Simulation time 3056067721 ps
CPU time 8.74 seconds
Started Aug 10 06:19:27 PM PDT 24
Finished Aug 10 06:19:36 PM PDT 24
Peak memory 217004 kb
Host smart-3fa43ca8-1cbe-40d0-8215-01663ea7c716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700490257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1700490257
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.338100287
Short name T946
Test name
Test status
Simulation time 270260239 ps
CPU time 0.96 seconds
Started Aug 10 06:19:31 PM PDT 24
Finished Aug 10 06:19:32 PM PDT 24
Peak memory 207620 kb
Host smart-fec9bcc6-eae1-47c1-8b14-8cf153c827a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338100287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.338100287
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2503571465
Short name T841
Test name
Test status
Simulation time 1059653525 ps
CPU time 4.85 seconds
Started Aug 10 06:19:25 PM PDT 24
Finished Aug 10 06:19:30 PM PDT 24
Peak memory 225264 kb
Host smart-bccc6003-6785-44e5-81ec-920c7165f267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503571465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2503571465
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.403434478
Short name T393
Test name
Test status
Simulation time 12665182 ps
CPU time 0.71 seconds
Started Aug 10 06:19:32 PM PDT 24
Finished Aug 10 06:19:33 PM PDT 24
Peak memory 205868 kb
Host smart-1c8eeee7-ec3f-4986-acd2-2e5063a10142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403434478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.403434478
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3717367161
Short name T384
Test name
Test status
Simulation time 138349624 ps
CPU time 2.51 seconds
Started Aug 10 06:19:33 PM PDT 24
Finished Aug 10 06:19:35 PM PDT 24
Peak memory 233492 kb
Host smart-2506f0ee-4a07-488f-ab26-34a728a4f472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717367161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3717367161
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1200811701
Short name T548
Test name
Test status
Simulation time 249959027 ps
CPU time 0.82 seconds
Started Aug 10 06:19:29 PM PDT 24
Finished Aug 10 06:19:30 PM PDT 24
Peak memory 206920 kb
Host smart-8dd377b9-50f4-450a-afd2-e05a9fce3dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200811701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1200811701
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3287542766
Short name T516
Test name
Test status
Simulation time 12813431 ps
CPU time 0.74 seconds
Started Aug 10 06:19:32 PM PDT 24
Finished Aug 10 06:19:33 PM PDT 24
Peak memory 216452 kb
Host smart-b91a4701-dd65-405d-a43b-770dce632e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287542766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3287542766
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2063916329
Short name T685
Test name
Test status
Simulation time 25914675523 ps
CPU time 72.18 seconds
Started Aug 10 06:19:35 PM PDT 24
Finished Aug 10 06:20:47 PM PDT 24
Peak memory 237560 kb
Host smart-514e3bfe-738a-4340-86dd-c1b52b629cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063916329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2063916329
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.688067504
Short name T28
Test name
Test status
Simulation time 16606248759 ps
CPU time 129.97 seconds
Started Aug 10 06:19:31 PM PDT 24
Finished Aug 10 06:21:41 PM PDT 24
Peak memory 273484 kb
Host smart-bf338d1b-738c-4f08-8504-773f776c2005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688067504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.688067504
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1573958667
Short name T607
Test name
Test status
Simulation time 383917809 ps
CPU time 9.71 seconds
Started Aug 10 06:19:35 PM PDT 24
Finished Aug 10 06:19:44 PM PDT 24
Peak memory 239820 kb
Host smart-fccc44b7-c5ff-4262-b15f-e31d403fe237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573958667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1573958667
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3548903657
Short name T87
Test name
Test status
Simulation time 91628071527 ps
CPU time 142.16 seconds
Started Aug 10 06:19:32 PM PDT 24
Finished Aug 10 06:21:54 PM PDT 24
Peak memory 252792 kb
Host smart-0b1d4571-08c6-4e01-8f89-31ac065f3a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548903657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3548903657
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1829700224
Short name T666
Test name
Test status
Simulation time 14696634365 ps
CPU time 23.7 seconds
Started Aug 10 06:19:33 PM PDT 24
Finished Aug 10 06:19:56 PM PDT 24
Peak memory 225264 kb
Host smart-b9400634-2e5b-49e1-bb66-62430d609171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829700224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1829700224
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.198507296
Short name T29
Test name
Test status
Simulation time 1017413752 ps
CPU time 13.4 seconds
Started Aug 10 06:19:34 PM PDT 24
Finished Aug 10 06:19:47 PM PDT 24
Peak memory 239696 kb
Host smart-098e0fd9-4e26-4286-81a4-014c48fb9890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198507296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.198507296
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.206725766
Short name T192
Test name
Test status
Simulation time 8137390300 ps
CPU time 9.27 seconds
Started Aug 10 06:19:32 PM PDT 24
Finished Aug 10 06:19:41 PM PDT 24
Peak memory 233576 kb
Host smart-8171da6f-72d0-4dbe-bef3-baa7a6e5b5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206725766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.206725766
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.501816624
Short name T285
Test name
Test status
Simulation time 3555108236 ps
CPU time 15.21 seconds
Started Aug 10 06:19:39 PM PDT 24
Finished Aug 10 06:19:54 PM PDT 24
Peak memory 225332 kb
Host smart-1ccf41f7-66fc-4706-b8f8-553ceadfaae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501816624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.501816624
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.933663138
Short name T383
Test name
Test status
Simulation time 2693949938 ps
CPU time 7.07 seconds
Started Aug 10 06:19:32 PM PDT 24
Finished Aug 10 06:19:39 PM PDT 24
Peak memory 220024 kb
Host smart-11811676-2dc6-4be0-babe-45f730052e0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=933663138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.933663138
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1073753108
Short name T757
Test name
Test status
Simulation time 186004783 ps
CPU time 1.01 seconds
Started Aug 10 06:19:36 PM PDT 24
Finished Aug 10 06:19:37 PM PDT 24
Peak memory 207480 kb
Host smart-e1091ea6-60bc-42c2-aa93-848402616e9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073753108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1073753108
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2116197906
Short name T561
Test name
Test status
Simulation time 11310936580 ps
CPU time 8.16 seconds
Started Aug 10 06:19:26 PM PDT 24
Finished Aug 10 06:19:34 PM PDT 24
Peak memory 216936 kb
Host smart-503fdcae-d25d-4910-b751-1e3eab568618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116197906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2116197906
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4221095774
Short name T934
Test name
Test status
Simulation time 2541793839 ps
CPU time 4.73 seconds
Started Aug 10 06:19:32 PM PDT 24
Finished Aug 10 06:19:36 PM PDT 24
Peak memory 217088 kb
Host smart-7f94debe-4310-432a-ae23-af7376e14ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221095774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4221095774
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2817593522
Short name T969
Test name
Test status
Simulation time 81018597 ps
CPU time 0.93 seconds
Started Aug 10 06:19:34 PM PDT 24
Finished Aug 10 06:19:36 PM PDT 24
Peak memory 207592 kb
Host smart-8b1a2c18-4ae9-4b5d-9a65-1a729b051194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817593522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2817593522
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3678134104
Short name T913
Test name
Test status
Simulation time 29881363 ps
CPU time 0.71 seconds
Started Aug 10 06:19:25 PM PDT 24
Finished Aug 10 06:19:25 PM PDT 24
Peak memory 206572 kb
Host smart-85f5c5c1-498a-4b7a-a3ce-317e21413d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678134104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3678134104
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2753006866
Short name T305
Test name
Test status
Simulation time 11535193108 ps
CPU time 10.35 seconds
Started Aug 10 06:19:32 PM PDT 24
Finished Aug 10 06:19:43 PM PDT 24
Peak memory 225296 kb
Host smart-63d56288-3d1d-43a9-bf6b-dfff6822e2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753006866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2753006866
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4233606978
Short name T603
Test name
Test status
Simulation time 13729920 ps
CPU time 0.71 seconds
Started Aug 10 06:19:33 PM PDT 24
Finished Aug 10 06:19:34 PM PDT 24
Peak memory 206164 kb
Host smart-af1f1f1a-9ed5-43cc-bf79-28cf54794e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233606978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4233606978
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.991238766
Short name T554
Test name
Test status
Simulation time 1435244790 ps
CPU time 5.28 seconds
Started Aug 10 06:19:34 PM PDT 24
Finished Aug 10 06:19:40 PM PDT 24
Peak memory 233380 kb
Host smart-98a25894-7a86-4c96-8f0e-899fdad58a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991238766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.991238766
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1897910105
Short name T880
Test name
Test status
Simulation time 20266301 ps
CPU time 0.74 seconds
Started Aug 10 06:19:35 PM PDT 24
Finished Aug 10 06:19:35 PM PDT 24
Peak memory 206012 kb
Host smart-53446b8a-32e6-40ab-90ba-7a76e0fa63ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897910105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1897910105
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1800715777
Short name T182
Test name
Test status
Simulation time 52104446477 ps
CPU time 67.81 seconds
Started Aug 10 06:19:31 PM PDT 24
Finished Aug 10 06:20:39 PM PDT 24
Peak memory 255636 kb
Host smart-3404a52b-12d2-4ff1-a48a-9200613f5bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800715777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1800715777
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2052524793
Short name T979
Test name
Test status
Simulation time 2837846389 ps
CPU time 30.85 seconds
Started Aug 10 06:19:34 PM PDT 24
Finished Aug 10 06:20:05 PM PDT 24
Peak memory 225380 kb
Host smart-e034aec7-65bd-4e1c-b5ec-8b4603fd0444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052524793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2052524793
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2102311506
Short name T817
Test name
Test status
Simulation time 1103088282 ps
CPU time 6.25 seconds
Started Aug 10 06:19:34 PM PDT 24
Finished Aug 10 06:19:41 PM PDT 24
Peak memory 225284 kb
Host smart-cef5f8d4-98cb-4332-bfb3-1c923813cd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102311506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2102311506
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2152816152
Short name T595
Test name
Test status
Simulation time 23180003115 ps
CPU time 14.61 seconds
Started Aug 10 06:19:34 PM PDT 24
Finished Aug 10 06:19:49 PM PDT 24
Peak memory 225292 kb
Host smart-1f2db738-89f3-41e9-b0ac-ad68598245bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152816152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2152816152
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2054290134
Short name T838
Test name
Test status
Simulation time 1037630058 ps
CPU time 18 seconds
Started Aug 10 06:19:37 PM PDT 24
Finished Aug 10 06:19:55 PM PDT 24
Peak memory 233480 kb
Host smart-aba5bf01-289c-45ec-a655-21a7d78637a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054290134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2054290134
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1926813754
Short name T950
Test name
Test status
Simulation time 4172579465 ps
CPU time 12.11 seconds
Started Aug 10 06:19:34 PM PDT 24
Finished Aug 10 06:19:47 PM PDT 24
Peak memory 233564 kb
Host smart-9508f91d-5a1f-4cc6-aea6-4ac8730eab84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926813754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1926813754
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4139473301
Short name T883
Test name
Test status
Simulation time 69973645 ps
CPU time 2.79 seconds
Started Aug 10 06:19:33 PM PDT 24
Finished Aug 10 06:19:36 PM PDT 24
Peak memory 233400 kb
Host smart-48d150e6-8628-44e5-83ce-c8a6c30a9b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139473301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4139473301
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3662061390
Short name T943
Test name
Test status
Simulation time 439303639 ps
CPU time 4.32 seconds
Started Aug 10 06:19:34 PM PDT 24
Finished Aug 10 06:19:39 PM PDT 24
Peak memory 223504 kb
Host smart-e944b24a-8aae-4c5e-91fd-8b084bb29239
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3662061390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3662061390
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1585533375
Short name T340
Test name
Test status
Simulation time 1510911519 ps
CPU time 6.87 seconds
Started Aug 10 06:19:34 PM PDT 24
Finished Aug 10 06:19:41 PM PDT 24
Peak memory 219056 kb
Host smart-39eb9b3d-a7e6-459f-96e3-30599b33f4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585533375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1585533375
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3933957972
Short name T535
Test name
Test status
Simulation time 599869898 ps
CPU time 5.27 seconds
Started Aug 10 06:19:29 PM PDT 24
Finished Aug 10 06:19:34 PM PDT 24
Peak memory 216932 kb
Host smart-7ded2fe2-418a-4eea-adf5-6f925467f623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933957972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3933957972
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3445010393
Short name T537
Test name
Test status
Simulation time 127551911 ps
CPU time 1.76 seconds
Started Aug 10 06:19:37 PM PDT 24
Finished Aug 10 06:19:39 PM PDT 24
Peak memory 216976 kb
Host smart-674d5ed2-3e25-412c-9b76-2bec8603bf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445010393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3445010393
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3489679051
Short name T963
Test name
Test status
Simulation time 104019720 ps
CPU time 0.79 seconds
Started Aug 10 06:19:32 PM PDT 24
Finished Aug 10 06:19:33 PM PDT 24
Peak memory 206680 kb
Host smart-51a42a60-f549-46bd-8c32-b7581d3d4570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489679051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3489679051
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3999845009
Short name T847
Test name
Test status
Simulation time 107446433 ps
CPU time 2.15 seconds
Started Aug 10 06:19:34 PM PDT 24
Finished Aug 10 06:19:36 PM PDT 24
Peak memory 224448 kb
Host smart-5864d313-6cf3-463e-a29a-cf9c2e288773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999845009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3999845009
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3374297588
Short name T485
Test name
Test status
Simulation time 11080010 ps
CPU time 0.74 seconds
Started Aug 10 06:19:44 PM PDT 24
Finished Aug 10 06:19:45 PM PDT 24
Peak memory 205312 kb
Host smart-5a0c74ba-ef68-43e0-84da-3d2e32cc2355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374297588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3374297588
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2194235821
Short name T488
Test name
Test status
Simulation time 2317048275 ps
CPU time 7.97 seconds
Started Aug 10 06:19:42 PM PDT 24
Finished Aug 10 06:19:50 PM PDT 24
Peak memory 225280 kb
Host smart-970f2f8d-bc8c-4e29-bcb1-faf4ea0e1d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194235821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2194235821
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.694012974
Short name T1022
Test name
Test status
Simulation time 18930465 ps
CPU time 0.78 seconds
Started Aug 10 06:19:37 PM PDT 24
Finished Aug 10 06:19:38 PM PDT 24
Peak memory 207080 kb
Host smart-6d821ebc-e35f-48f1-92a7-afbc524b5f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694012974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.694012974
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1394393977
Short name T14
Test name
Test status
Simulation time 3003466602 ps
CPU time 56.34 seconds
Started Aug 10 06:19:41 PM PDT 24
Finished Aug 10 06:20:37 PM PDT 24
Peak memory 256140 kb
Host smart-47cab363-1df3-4997-bb85-1999620a595d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394393977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1394393977
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4237687659
Short name T823
Test name
Test status
Simulation time 2344192676 ps
CPU time 14.24 seconds
Started Aug 10 06:19:40 PM PDT 24
Finished Aug 10 06:19:54 PM PDT 24
Peak memory 237700 kb
Host smart-91e6c051-e941-4d6c-ac55-17ed50a85464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237687659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4237687659
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2813302167
Short name T684
Test name
Test status
Simulation time 147113725 ps
CPU time 4.55 seconds
Started Aug 10 06:19:39 PM PDT 24
Finished Aug 10 06:19:44 PM PDT 24
Peak memory 233448 kb
Host smart-9008c184-02b4-4ebe-bcd8-0e8734107ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813302167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2813302167
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.394912873
Short name T211
Test name
Test status
Simulation time 19683061919 ps
CPU time 82.96 seconds
Started Aug 10 06:19:39 PM PDT 24
Finished Aug 10 06:21:02 PM PDT 24
Peak memory 265664 kb
Host smart-940f711e-a448-46fe-a4c2-99480a8ef501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394912873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.394912873
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3483192246
Short name T190
Test name
Test status
Simulation time 1826353161 ps
CPU time 13.59 seconds
Started Aug 10 06:19:40 PM PDT 24
Finished Aug 10 06:19:54 PM PDT 24
Peak memory 225064 kb
Host smart-2680cb29-ccbf-461c-a5a7-3cfb5097bba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483192246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3483192246
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.4098698827
Short name T75
Test name
Test status
Simulation time 2960036205 ps
CPU time 25.09 seconds
Started Aug 10 06:19:38 PM PDT 24
Finished Aug 10 06:20:03 PM PDT 24
Peak memory 233524 kb
Host smart-9d112f5a-12ff-45af-9943-6b922d904cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098698827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4098698827
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2187428788
Short name T208
Test name
Test status
Simulation time 4371842863 ps
CPU time 6.98 seconds
Started Aug 10 06:19:38 PM PDT 24
Finished Aug 10 06:19:45 PM PDT 24
Peak memory 233504 kb
Host smart-061b60ef-0d3d-4fc7-b848-b4669d206d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187428788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2187428788
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2819631547
Short name T437
Test name
Test status
Simulation time 1342966714 ps
CPU time 9.37 seconds
Started Aug 10 06:19:42 PM PDT 24
Finished Aug 10 06:19:51 PM PDT 24
Peak memory 233480 kb
Host smart-6344b431-5251-410f-be5c-6c17f3515b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819631547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2819631547
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1488682992
Short name T495
Test name
Test status
Simulation time 2470916109 ps
CPU time 12.44 seconds
Started Aug 10 06:19:40 PM PDT 24
Finished Aug 10 06:19:53 PM PDT 24
Peak memory 219476 kb
Host smart-a52077ec-5102-4ff1-8ae8-5f8dab99e0c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1488682992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1488682992
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.4225987803
Short name T17
Test name
Test status
Simulation time 1048432695 ps
CPU time 11.29 seconds
Started Aug 10 06:19:38 PM PDT 24
Finished Aug 10 06:19:50 PM PDT 24
Peak memory 225236 kb
Host smart-0d685545-c510-4bc5-8cb6-676a94a27aeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225987803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.4225987803
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3008833622
Short name T1014
Test name
Test status
Simulation time 45538200 ps
CPU time 0.72 seconds
Started Aug 10 06:19:34 PM PDT 24
Finished Aug 10 06:19:35 PM PDT 24
Peak memory 206100 kb
Host smart-78a640e6-4696-4bad-9422-ea5ff250aee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008833622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3008833622
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3633637744
Short name T958
Test name
Test status
Simulation time 11973368 ps
CPU time 0.69 seconds
Started Aug 10 06:19:32 PM PDT 24
Finished Aug 10 06:19:33 PM PDT 24
Peak memory 206188 kb
Host smart-d5aa8882-cab4-43b3-acd4-d3cc5d7efc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633637744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3633637744
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1459003604
Short name T915
Test name
Test status
Simulation time 161123746 ps
CPU time 1.04 seconds
Started Aug 10 06:19:40 PM PDT 24
Finished Aug 10 06:19:41 PM PDT 24
Peak memory 207824 kb
Host smart-d4e35e55-b024-42d6-9dad-a8d56a058ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459003604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1459003604
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3679039163
Short name T478
Test name
Test status
Simulation time 62226010 ps
CPU time 0.88 seconds
Started Aug 10 06:19:39 PM PDT 24
Finished Aug 10 06:19:40 PM PDT 24
Peak memory 206584 kb
Host smart-9953b02f-ac97-4716-94bb-3cef22fa72c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679039163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3679039163
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1231438137
Short name T787
Test name
Test status
Simulation time 405397455 ps
CPU time 3.68 seconds
Started Aug 10 06:19:40 PM PDT 24
Finished Aug 10 06:19:44 PM PDT 24
Peak memory 225260 kb
Host smart-d17d797a-e5d3-4161-a013-144f38acc7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231438137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1231438137
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2319727219
Short name T352
Test name
Test status
Simulation time 40332169 ps
CPU time 0.71 seconds
Started Aug 10 06:19:43 PM PDT 24
Finished Aug 10 06:19:44 PM PDT 24
Peak memory 205288 kb
Host smart-7508376b-a065-4b54-8055-5e2170384ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319727219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2319727219
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.4024344471
Short name T785
Test name
Test status
Simulation time 2112987864 ps
CPU time 8.14 seconds
Started Aug 10 06:19:37 PM PDT 24
Finished Aug 10 06:19:46 PM PDT 24
Peak memory 225236 kb
Host smart-2e414033-4227-48e0-95d9-d6711145ef64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024344471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.4024344471
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.654335638
Short name T763
Test name
Test status
Simulation time 17640333 ps
CPU time 0.78 seconds
Started Aug 10 06:19:40 PM PDT 24
Finished Aug 10 06:19:41 PM PDT 24
Peak memory 207368 kb
Host smart-ceadfea1-aba7-46cb-a534-768973abec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654335638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.654335638
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.599230170
Short name T995
Test name
Test status
Simulation time 38035238139 ps
CPU time 84.56 seconds
Started Aug 10 06:19:41 PM PDT 24
Finished Aug 10 06:21:06 PM PDT 24
Peak memory 266320 kb
Host smart-a0f69b94-9ef9-4fb7-bafa-1d99988d1f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599230170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.599230170
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.216660918
Short name T241
Test name
Test status
Simulation time 2733514227 ps
CPU time 22.79 seconds
Started Aug 10 06:19:40 PM PDT 24
Finished Aug 10 06:20:03 PM PDT 24
Peak memory 249928 kb
Host smart-d2bf89d3-c881-4b2a-97fb-4e3f8323c85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216660918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.216660918
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.653868659
Short name T233
Test name
Test status
Simulation time 4706778925 ps
CPU time 47.51 seconds
Started Aug 10 06:19:42 PM PDT 24
Finished Aug 10 06:20:29 PM PDT 24
Peak memory 249984 kb
Host smart-046a170a-27bd-422e-a39f-f16c0212e1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653868659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.653868659
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2246890396
Short name T329
Test name
Test status
Simulation time 213534141 ps
CPU time 8.06 seconds
Started Aug 10 06:19:40 PM PDT 24
Finished Aug 10 06:19:48 PM PDT 24
Peak memory 241644 kb
Host smart-05e2da3f-498b-4838-82f6-bf1525c191c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246890396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2246890396
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3052640141
Short name T356
Test name
Test status
Simulation time 21360233 ps
CPU time 0.74 seconds
Started Aug 10 06:19:39 PM PDT 24
Finished Aug 10 06:19:40 PM PDT 24
Peak memory 216320 kb
Host smart-051d0591-dc08-49b1-81c7-007134f17755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052640141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3052640141
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1735382435
Short name T899
Test name
Test status
Simulation time 2424078571 ps
CPU time 12.21 seconds
Started Aug 10 06:19:40 PM PDT 24
Finished Aug 10 06:19:53 PM PDT 24
Peak memory 225276 kb
Host smart-c5f6caa7-b749-4c9a-9f2e-ba013578ed55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735382435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1735382435
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1033859363
Short name T72
Test name
Test status
Simulation time 8725018652 ps
CPU time 27.31 seconds
Started Aug 10 06:19:42 PM PDT 24
Finished Aug 10 06:20:09 PM PDT 24
Peak memory 237432 kb
Host smart-626c9676-5f43-467b-920c-50e0e29d6db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033859363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1033859363
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.4195992854
Short name T214
Test name
Test status
Simulation time 9834917863 ps
CPU time 29.36 seconds
Started Aug 10 06:19:40 PM PDT 24
Finished Aug 10 06:20:10 PM PDT 24
Peak memory 233456 kb
Host smart-4ce3cb28-ae50-4249-a281-0ff60974b987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195992854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.4195992854
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1325559764
Short name T636
Test name
Test status
Simulation time 5002727064 ps
CPU time 16.74 seconds
Started Aug 10 06:19:44 PM PDT 24
Finished Aug 10 06:20:01 PM PDT 24
Peak memory 233556 kb
Host smart-74060fdd-fb40-4a77-bab9-96ae8035d379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325559764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1325559764
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3223891978
Short name T53
Test name
Test status
Simulation time 731038436 ps
CPU time 4.76 seconds
Started Aug 10 06:19:41 PM PDT 24
Finished Aug 10 06:19:46 PM PDT 24
Peak memory 221324 kb
Host smart-569b834b-cd5d-4329-8df8-18a6de28f388
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3223891978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3223891978
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.508292078
Short name T162
Test name
Test status
Simulation time 68954178925 ps
CPU time 315.38 seconds
Started Aug 10 06:19:43 PM PDT 24
Finished Aug 10 06:24:59 PM PDT 24
Peak memory 258172 kb
Host smart-e5dfc51f-9deb-4b9b-a11b-1045fe7d4fcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508292078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.508292078
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.534136089
Short name T421
Test name
Test status
Simulation time 653001961 ps
CPU time 5.05 seconds
Started Aug 10 06:19:43 PM PDT 24
Finished Aug 10 06:19:48 PM PDT 24
Peak memory 217216 kb
Host smart-034d9434-ed24-45fd-8c3e-b323cdf54c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534136089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.534136089
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2446503639
Short name T1009
Test name
Test status
Simulation time 11227703329 ps
CPU time 10.44 seconds
Started Aug 10 06:19:39 PM PDT 24
Finished Aug 10 06:19:50 PM PDT 24
Peak memory 217116 kb
Host smart-d5c7d269-17cf-43bd-ba42-3b5b8980f726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446503639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2446503639
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3099837753
Short name T409
Test name
Test status
Simulation time 57272630 ps
CPU time 1.65 seconds
Started Aug 10 06:19:44 PM PDT 24
Finished Aug 10 06:19:46 PM PDT 24
Peak memory 217028 kb
Host smart-ae894a30-2f1f-466a-a139-a2592a8976ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099837753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3099837753
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.978694910
Short name T405
Test name
Test status
Simulation time 15904372 ps
CPU time 0.74 seconds
Started Aug 10 06:19:38 PM PDT 24
Finished Aug 10 06:19:39 PM PDT 24
Peak memory 206568 kb
Host smart-5473088a-7496-475c-a027-172e7093bad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978694910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.978694910
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3611605155
Short name T994
Test name
Test status
Simulation time 17181132860 ps
CPU time 9.14 seconds
Started Aug 10 06:19:40 PM PDT 24
Finished Aug 10 06:19:49 PM PDT 24
Peak memory 233492 kb
Host smart-4b156a8c-fcef-4426-a466-201dc54836b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611605155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3611605155
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.665302826
Short name T572
Test name
Test status
Simulation time 12447656 ps
CPU time 0.73 seconds
Started Aug 10 06:18:16 PM PDT 24
Finished Aug 10 06:18:17 PM PDT 24
Peak memory 205220 kb
Host smart-1c310b65-5003-45d2-a2d9-37afad33b290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665302826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.665302826
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1387887768
Short name T444
Test name
Test status
Simulation time 156151870 ps
CPU time 3.44 seconds
Started Aug 10 06:18:18 PM PDT 24
Finished Aug 10 06:18:21 PM PDT 24
Peak memory 225296 kb
Host smart-911d30aa-c008-4bee-a826-c6603b86770d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387887768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1387887768
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2502577205
Short name T547
Test name
Test status
Simulation time 64095633 ps
CPU time 0.8 seconds
Started Aug 10 06:18:16 PM PDT 24
Finished Aug 10 06:18:17 PM PDT 24
Peak memory 207056 kb
Host smart-6498b010-7cc2-44be-99d6-a6df7dc84494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502577205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2502577205
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.50688174
Short name T239
Test name
Test status
Simulation time 166167253520 ps
CPU time 133.26 seconds
Started Aug 10 06:18:20 PM PDT 24
Finished Aug 10 06:20:33 PM PDT 24
Peak memory 249976 kb
Host smart-fe076cab-a0bb-486d-ae6d-b7d223f7298b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50688174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.50688174
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4005292907
Short name T256
Test name
Test status
Simulation time 14984502556 ps
CPU time 82.39 seconds
Started Aug 10 06:18:19 PM PDT 24
Finished Aug 10 06:19:41 PM PDT 24
Peak memory 254084 kb
Host smart-cca89cc8-9cd0-40ef-a158-ef0c26d6d9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005292907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4005292907
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.725942286
Short name T431
Test name
Test status
Simulation time 2974226908 ps
CPU time 57.84 seconds
Started Aug 10 06:18:17 PM PDT 24
Finished Aug 10 06:19:16 PM PDT 24
Peak memory 258196 kb
Host smart-5ba17267-c33c-4ff7-a11e-3cd757c60e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725942286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
725942286
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.4082885683
Short name T941
Test name
Test status
Simulation time 955257036 ps
CPU time 24.79 seconds
Started Aug 10 06:18:18 PM PDT 24
Finished Aug 10 06:18:43 PM PDT 24
Peak memory 249864 kb
Host smart-c02a1055-bada-47a7-87ad-0fd9d90c52d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082885683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.4082885683
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.3063778840
Short name T242
Test name
Test status
Simulation time 36186417118 ps
CPU time 161.23 seconds
Started Aug 10 06:18:17 PM PDT 24
Finished Aug 10 06:20:59 PM PDT 24
Peak memory 253212 kb
Host smart-24906ce9-35ff-4629-a88a-b3749d5c33c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063778840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.3063778840
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1078998532
Short name T10
Test name
Test status
Simulation time 993736985 ps
CPU time 4.99 seconds
Started Aug 10 06:18:18 PM PDT 24
Finished Aug 10 06:18:23 PM PDT 24
Peak memory 225176 kb
Host smart-83da106b-157c-4949-a2bd-2a29eb4934d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078998532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1078998532
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1009580363
Short name T626
Test name
Test status
Simulation time 6868344638 ps
CPU time 73.32 seconds
Started Aug 10 06:18:17 PM PDT 24
Finished Aug 10 06:19:31 PM PDT 24
Peak memory 239308 kb
Host smart-fc33e21c-4478-4cbc-bed2-f80e1b9ce3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009580363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1009580363
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2983259164
Short name T530
Test name
Test status
Simulation time 123702456 ps
CPU time 1.09 seconds
Started Aug 10 06:18:17 PM PDT 24
Finished Aug 10 06:18:19 PM PDT 24
Peak memory 217212 kb
Host smart-78962e96-f89b-42f8-a70d-55b313d78b42
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983259164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2983259164
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2348668409
Short name T363
Test name
Test status
Simulation time 35059141 ps
CPU time 2.45 seconds
Started Aug 10 06:18:17 PM PDT 24
Finished Aug 10 06:18:20 PM PDT 24
Peak memory 233108 kb
Host smart-c5ba1c17-6ce8-468d-8c7f-582a6e3b895f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348668409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2348668409
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.71878694
Short name T207
Test name
Test status
Simulation time 13522668874 ps
CPU time 39.24 seconds
Started Aug 10 06:18:15 PM PDT 24
Finished Aug 10 06:18:54 PM PDT 24
Peak memory 241216 kb
Host smart-483bec2a-50f5-4b3b-a960-605b15afa761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71878694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.71878694
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.4141580719
Short name T153
Test name
Test status
Simulation time 321852489 ps
CPU time 4.06 seconds
Started Aug 10 06:18:18 PM PDT 24
Finished Aug 10 06:18:22 PM PDT 24
Peak memory 220648 kb
Host smart-8cd1b220-d3c7-48fb-bfe7-2f36ba122e0c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4141580719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.4141580719
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2517891984
Short name T335
Test name
Test status
Simulation time 1561328428 ps
CPU time 15.87 seconds
Started Aug 10 06:18:20 PM PDT 24
Finished Aug 10 06:18:36 PM PDT 24
Peak memory 220536 kb
Host smart-414f0356-bb60-4534-a0a0-4e284ecbe42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517891984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2517891984
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1308139681
Short name T76
Test name
Test status
Simulation time 2487188279 ps
CPU time 4.28 seconds
Started Aug 10 06:18:17 PM PDT 24
Finished Aug 10 06:18:22 PM PDT 24
Peak memory 217060 kb
Host smart-96fcb5b8-8510-47b7-a866-df71e0708d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308139681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1308139681
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1070897040
Short name T417
Test name
Test status
Simulation time 80042450 ps
CPU time 1.32 seconds
Started Aug 10 06:18:18 PM PDT 24
Finished Aug 10 06:18:19 PM PDT 24
Peak memory 216976 kb
Host smart-79d9dc0e-37e9-4cf0-b845-0a0f563a9b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070897040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1070897040
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.191964866
Short name T728
Test name
Test status
Simulation time 24496210 ps
CPU time 0.77 seconds
Started Aug 10 06:18:15 PM PDT 24
Finished Aug 10 06:18:16 PM PDT 24
Peak memory 206592 kb
Host smart-e6f2dbd1-5604-4df5-879a-410387daf22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191964866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.191964866
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1002685685
Short name T183
Test name
Test status
Simulation time 509272531 ps
CPU time 2.74 seconds
Started Aug 10 06:18:20 PM PDT 24
Finished Aug 10 06:18:22 PM PDT 24
Peak memory 225264 kb
Host smart-bd5797c6-2f1a-4396-a8cb-5affcfaf8e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002685685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1002685685
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3391659387
Short name T347
Test name
Test status
Simulation time 17789343 ps
CPU time 0.76 seconds
Started Aug 10 06:19:47 PM PDT 24
Finished Aug 10 06:19:48 PM PDT 24
Peak memory 206192 kb
Host smart-a2aced64-ece0-4a70-b77d-e3b2c3e3a188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391659387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3391659387
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1693614221
Short name T306
Test name
Test status
Simulation time 108806949 ps
CPU time 2.92 seconds
Started Aug 10 06:19:47 PM PDT 24
Finished Aug 10 06:19:50 PM PDT 24
Peak memory 233608 kb
Host smart-299c15c4-ece3-433d-82ae-5e830ba8a5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693614221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1693614221
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3856267423
Short name T404
Test name
Test status
Simulation time 19192296 ps
CPU time 0.8 seconds
Started Aug 10 06:19:39 PM PDT 24
Finished Aug 10 06:19:40 PM PDT 24
Peak memory 207088 kb
Host smart-2718c32b-3644-4927-bd5c-c95c863f0394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856267423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3856267423
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3583764809
Short name T482
Test name
Test status
Simulation time 44608180367 ps
CPU time 81.67 seconds
Started Aug 10 06:19:47 PM PDT 24
Finished Aug 10 06:21:09 PM PDT 24
Peak memory 249944 kb
Host smart-e7b528f3-1b31-49ba-b368-bcb4027561be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583764809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3583764809
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2006025574
Short name T615
Test name
Test status
Simulation time 1102088623 ps
CPU time 5.71 seconds
Started Aug 10 06:19:47 PM PDT 24
Finished Aug 10 06:19:52 PM PDT 24
Peak memory 225292 kb
Host smart-5cf3d2cf-62b3-4adf-b80d-9970b1eeb9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006025574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2006025574
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2957213733
Short name T472
Test name
Test status
Simulation time 2874887592 ps
CPU time 22.11 seconds
Started Aug 10 06:19:54 PM PDT 24
Finished Aug 10 06:20:16 PM PDT 24
Peak memory 250368 kb
Host smart-52c1cfbc-1e8e-4e98-ba45-3ae53e640c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957213733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2957213733
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3663616161
Short name T908
Test name
Test status
Simulation time 59493560154 ps
CPU time 86.1 seconds
Started Aug 10 06:19:46 PM PDT 24
Finished Aug 10 06:21:12 PM PDT 24
Peak memory 241676 kb
Host smart-2875c176-9289-434c-b3ee-723a0f431f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663616161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3663616161
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2577268751
Short name T972
Test name
Test status
Simulation time 1380203843 ps
CPU time 12.52 seconds
Started Aug 10 06:19:47 PM PDT 24
Finished Aug 10 06:20:00 PM PDT 24
Peak memory 225280 kb
Host smart-ae3f75a7-b8f7-4e18-bdd4-1489352598d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577268751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2577268751
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3948486597
Short name T989
Test name
Test status
Simulation time 2079162455 ps
CPU time 8.54 seconds
Started Aug 10 06:19:54 PM PDT 24
Finished Aug 10 06:20:02 PM PDT 24
Peak memory 225080 kb
Host smart-186ec136-cbe0-4d6e-a1bc-a3a5d1a0487b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948486597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3948486597
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.761416001
Short name T222
Test name
Test status
Simulation time 114222940926 ps
CPU time 23.11 seconds
Started Aug 10 06:19:46 PM PDT 24
Finished Aug 10 06:20:10 PM PDT 24
Peak memory 233480 kb
Host smart-3b5b619e-4e86-4c2b-b2f8-f2d0c842d7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761416001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.761416001
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2323349127
Short name T760
Test name
Test status
Simulation time 9140513641 ps
CPU time 19.99 seconds
Started Aug 10 06:19:47 PM PDT 24
Finished Aug 10 06:20:07 PM PDT 24
Peak memory 241616 kb
Host smart-3415aaff-676a-4975-85ba-5e9b4b7047bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323349127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2323349127
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3063498969
Short name T1024
Test name
Test status
Simulation time 599731624 ps
CPU time 7.65 seconds
Started Aug 10 06:19:47 PM PDT 24
Finished Aug 10 06:19:54 PM PDT 24
Peak memory 222596 kb
Host smart-ce3f5cb1-610d-4c15-a126-a92a2d7706fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3063498969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3063498969
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2895933776
Short name T741
Test name
Test status
Simulation time 6973208680 ps
CPU time 70.28 seconds
Started Aug 10 06:19:55 PM PDT 24
Finished Aug 10 06:21:05 PM PDT 24
Peak memory 249924 kb
Host smart-dedaf833-a0fe-4956-b907-a9aae007e0bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895933776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2895933776
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2952271003
Short name T829
Test name
Test status
Simulation time 7694209057 ps
CPU time 20.31 seconds
Started Aug 10 06:19:42 PM PDT 24
Finished Aug 10 06:20:03 PM PDT 24
Peak memory 217272 kb
Host smart-2a7b1394-91fc-4aaa-8545-b874761425a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952271003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2952271003
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3453967539
Short name T429
Test name
Test status
Simulation time 356350626 ps
CPU time 3.56 seconds
Started Aug 10 06:19:39 PM PDT 24
Finished Aug 10 06:19:43 PM PDT 24
Peak memory 216884 kb
Host smart-7772226d-47ca-4d7e-881f-4b419650d515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453967539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3453967539
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3368614103
Short name T795
Test name
Test status
Simulation time 61603768 ps
CPU time 0.89 seconds
Started Aug 10 06:19:47 PM PDT 24
Finished Aug 10 06:19:48 PM PDT 24
Peak memory 207560 kb
Host smart-42c7670a-f2f8-473c-afd9-88908ef47655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368614103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3368614103
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3248050548
Short name T748
Test name
Test status
Simulation time 230250826 ps
CPU time 0.78 seconds
Started Aug 10 06:19:49 PM PDT 24
Finished Aug 10 06:19:50 PM PDT 24
Peak memory 206568 kb
Host smart-e7c2ca22-e241-4e5f-9acd-934b48fbc136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248050548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3248050548
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.446945326
Short name T778
Test name
Test status
Simulation time 2944947802 ps
CPU time 9.22 seconds
Started Aug 10 06:19:45 PM PDT 24
Finished Aug 10 06:19:54 PM PDT 24
Peak memory 249884 kb
Host smart-5a123ba5-a114-4638-a0b3-6f52c28326e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446945326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.446945326
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.6540691
Short name T351
Test name
Test status
Simulation time 45950512 ps
CPU time 0.71 seconds
Started Aug 10 06:19:46 PM PDT 24
Finished Aug 10 06:19:47 PM PDT 24
Peak memory 205460 kb
Host smart-5c6cae5b-dea2-4676-ad9a-4698c38a7936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6540691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.6540691
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3291764562
Short name T949
Test name
Test status
Simulation time 6478817719 ps
CPU time 11.52 seconds
Started Aug 10 06:19:45 PM PDT 24
Finished Aug 10 06:19:57 PM PDT 24
Peak memory 233468 kb
Host smart-8862c826-691d-45b0-b4ee-252ff6b91e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291764562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3291764562
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1722584431
Short name T348
Test name
Test status
Simulation time 28757358 ps
CPU time 0.75 seconds
Started Aug 10 06:19:49 PM PDT 24
Finished Aug 10 06:19:50 PM PDT 24
Peak memory 207004 kb
Host smart-c2651423-2134-4132-8a3e-64ff6d9a1cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722584431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1722584431
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.849536925
Short name T250
Test name
Test status
Simulation time 49193623806 ps
CPU time 53.87 seconds
Started Aug 10 06:19:48 PM PDT 24
Finished Aug 10 06:20:42 PM PDT 24
Peak memory 249924 kb
Host smart-8217da9a-03cd-4d4d-8d0e-0cf959d62100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849536925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.849536925
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3128113210
Short name T796
Test name
Test status
Simulation time 31679444437 ps
CPU time 129.93 seconds
Started Aug 10 06:19:49 PM PDT 24
Finished Aug 10 06:21:59 PM PDT 24
Peak memory 249928 kb
Host smart-aeb8d656-54b3-4a34-a38d-b4d01f1af71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128113210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3128113210
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2948045282
Short name T837
Test name
Test status
Simulation time 226066658 ps
CPU time 4.8 seconds
Started Aug 10 06:19:55 PM PDT 24
Finished Aug 10 06:20:00 PM PDT 24
Peak memory 219172 kb
Host smart-edb06933-0005-4528-aaeb-0bf812b90c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948045282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2948045282
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.386668593
Short name T321
Test name
Test status
Simulation time 675789426 ps
CPU time 16.92 seconds
Started Aug 10 06:19:48 PM PDT 24
Finished Aug 10 06:20:05 PM PDT 24
Peak memory 233432 kb
Host smart-b1e324fb-ec8c-461c-b6ea-24bbe9d0da24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386668593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.386668593
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4070706473
Short name T961
Test name
Test status
Simulation time 1989587012 ps
CPU time 11.67 seconds
Started Aug 10 06:19:47 PM PDT 24
Finished Aug 10 06:19:59 PM PDT 24
Peak memory 233492 kb
Host smart-22cb79e7-d0b6-492e-b031-9e3b5de9eabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070706473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4070706473
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2057013092
Short name T882
Test name
Test status
Simulation time 732621132 ps
CPU time 4.51 seconds
Started Aug 10 06:19:57 PM PDT 24
Finished Aug 10 06:20:01 PM PDT 24
Peak memory 233412 kb
Host smart-dc4ce60b-9c19-47fd-8960-a348a7f4b063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057013092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2057013092
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1054909476
Short name T518
Test name
Test status
Simulation time 1041548682 ps
CPU time 5.94 seconds
Started Aug 10 06:19:54 PM PDT 24
Finished Aug 10 06:20:00 PM PDT 24
Peak memory 233344 kb
Host smart-a9e94773-c329-4587-a902-90464286a2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054909476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1054909476
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.867905159
Short name T687
Test name
Test status
Simulation time 10878880080 ps
CPU time 30.96 seconds
Started Aug 10 06:19:45 PM PDT 24
Finished Aug 10 06:20:16 PM PDT 24
Peak memory 234568 kb
Host smart-5744b9a4-5bfe-4dc8-ac87-7102c0fed9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867905159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.867905159
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2964802211
Short name T710
Test name
Test status
Simulation time 306614384 ps
CPU time 4.72 seconds
Started Aug 10 06:19:47 PM PDT 24
Finished Aug 10 06:19:51 PM PDT 24
Peak memory 221096 kb
Host smart-6a724ec0-6bd4-467c-929d-cc5179741ac1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2964802211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2964802211
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3370465429
Short name T255
Test name
Test status
Simulation time 78608233018 ps
CPU time 218.69 seconds
Started Aug 10 06:19:46 PM PDT 24
Finished Aug 10 06:23:25 PM PDT 24
Peak memory 257616 kb
Host smart-d2a180ae-0555-4211-bd25-fdd76ca2b9ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370465429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3370465429
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.775023175
Short name T524
Test name
Test status
Simulation time 7370466116 ps
CPU time 23.55 seconds
Started Aug 10 06:19:52 PM PDT 24
Finished Aug 10 06:20:16 PM PDT 24
Peak memory 217080 kb
Host smart-6a944381-f2ae-4b64-a726-2913a997d762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775023175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.775023175
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4073213458
Short name T386
Test name
Test status
Simulation time 451636163 ps
CPU time 1.59 seconds
Started Aug 10 06:19:48 PM PDT 24
Finished Aug 10 06:19:49 PM PDT 24
Peak memory 208564 kb
Host smart-178b5953-2b55-41cf-b9a5-f210fb208c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073213458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4073213458
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.72973928
Short name T825
Test name
Test status
Simulation time 94287755 ps
CPU time 4.64 seconds
Started Aug 10 06:19:52 PM PDT 24
Finished Aug 10 06:19:57 PM PDT 24
Peak memory 216976 kb
Host smart-ad6f3193-37e5-4be3-9097-3b8242a71a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72973928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.72973928
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1384865560
Short name T652
Test name
Test status
Simulation time 427485428 ps
CPU time 0.87 seconds
Started Aug 10 06:19:54 PM PDT 24
Finished Aug 10 06:19:55 PM PDT 24
Peak memory 206516 kb
Host smart-3282fa4f-7326-475d-af85-34f60b428676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384865560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1384865560
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3821386839
Short name T891
Test name
Test status
Simulation time 533887570 ps
CPU time 3.9 seconds
Started Aug 10 06:19:46 PM PDT 24
Finished Aug 10 06:19:50 PM PDT 24
Peak memory 225280 kb
Host smart-4786b62a-ca9e-4051-9a1f-72dda0023188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821386839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3821386839
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3426449362
Short name T61
Test name
Test status
Simulation time 31951883 ps
CPU time 0.71 seconds
Started Aug 10 06:19:53 PM PDT 24
Finished Aug 10 06:19:54 PM PDT 24
Peak memory 206192 kb
Host smart-ab728f93-1efe-4408-bf6d-da086e3222a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426449362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3426449362
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3889175418
Short name T919
Test name
Test status
Simulation time 1306837255 ps
CPU time 4.54 seconds
Started Aug 10 06:19:55 PM PDT 24
Finished Aug 10 06:20:00 PM PDT 24
Peak memory 233428 kb
Host smart-cf7e42bd-4e69-4670-a95a-69ee23df0b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889175418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3889175418
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3337393120
Short name T410
Test name
Test status
Simulation time 38126910 ps
CPU time 0.75 seconds
Started Aug 10 06:19:48 PM PDT 24
Finished Aug 10 06:19:49 PM PDT 24
Peak memory 207408 kb
Host smart-10cbe700-0343-4c86-b47b-6937415e2dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337393120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3337393120
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3480710206
Short name T200
Test name
Test status
Simulation time 12218293951 ps
CPU time 85.41 seconds
Started Aug 10 06:19:54 PM PDT 24
Finished Aug 10 06:21:19 PM PDT 24
Peak memory 249888 kb
Host smart-81c4820e-ed54-49d4-a320-efa2c15c2b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480710206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3480710206
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2165522951
Short name T174
Test name
Test status
Simulation time 22862259026 ps
CPU time 40.89 seconds
Started Aug 10 06:19:55 PM PDT 24
Finished Aug 10 06:20:36 PM PDT 24
Peak memory 257928 kb
Host smart-82fd6aac-670c-4559-b962-1819cf0868e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165522951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2165522951
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.4122017012
Short name T254
Test name
Test status
Simulation time 88420094239 ps
CPU time 219.23 seconds
Started Aug 10 06:19:55 PM PDT 24
Finished Aug 10 06:23:34 PM PDT 24
Peak memory 254932 kb
Host smart-f3851d8d-f0a8-477a-9397-85ceb1a2f28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122017012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.4122017012
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.97917684
Short name T150
Test name
Test status
Simulation time 680171577 ps
CPU time 7.8 seconds
Started Aug 10 06:19:53 PM PDT 24
Finished Aug 10 06:20:01 PM PDT 24
Peak memory 233508 kb
Host smart-e8d1ebb7-1bf5-4b7d-81ce-3202fc6b9925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97917684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.97917684
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2917221557
Short name T648
Test name
Test status
Simulation time 3922636881 ps
CPU time 12.47 seconds
Started Aug 10 06:19:53 PM PDT 24
Finished Aug 10 06:20:06 PM PDT 24
Peak memory 225224 kb
Host smart-00e237c3-9d84-401b-bdb6-1e75d322976f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917221557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2917221557
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2989750085
Short name T177
Test name
Test status
Simulation time 1713805111 ps
CPU time 16.74 seconds
Started Aug 10 06:19:52 PM PDT 24
Finished Aug 10 06:20:09 PM PDT 24
Peak memory 233500 kb
Host smart-a87ed162-d26b-4010-8c5f-768175589a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989750085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2989750085
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3327843907
Short name T647
Test name
Test status
Simulation time 12797572987 ps
CPU time 53.07 seconds
Started Aug 10 06:19:53 PM PDT 24
Finished Aug 10 06:20:46 PM PDT 24
Peak memory 233464 kb
Host smart-f6b4d426-0949-47ac-b355-20658174f816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327843907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3327843907
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2951222102
Short name T235
Test name
Test status
Simulation time 7677425101 ps
CPU time 6.27 seconds
Started Aug 10 06:19:54 PM PDT 24
Finished Aug 10 06:20:01 PM PDT 24
Peak memory 225280 kb
Host smart-b5c46b1c-232b-4a94-9d17-b5ae25de7235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951222102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2951222102
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.745602097
Short name T846
Test name
Test status
Simulation time 12780550578 ps
CPU time 22.84 seconds
Started Aug 10 06:19:55 PM PDT 24
Finished Aug 10 06:20:18 PM PDT 24
Peak memory 225240 kb
Host smart-afef5429-e64a-47c8-bc29-028a0d633688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745602097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.745602097
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2192736566
Short name T761
Test name
Test status
Simulation time 2942706135 ps
CPU time 10.3 seconds
Started Aug 10 06:19:56 PM PDT 24
Finished Aug 10 06:20:06 PM PDT 24
Peak memory 221508 kb
Host smart-44f8ca63-5352-4241-9fa1-34ab961b6fbd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2192736566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2192736566
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1618277144
Short name T21
Test name
Test status
Simulation time 92847395558 ps
CPU time 383.12 seconds
Started Aug 10 06:19:53 PM PDT 24
Finished Aug 10 06:26:17 PM PDT 24
Peak memory 257296 kb
Host smart-af659d11-a677-469e-a168-2c2280585011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618277144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1618277144
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.4217533005
Short name T981
Test name
Test status
Simulation time 2631023660 ps
CPU time 8.06 seconds
Started Aug 10 06:19:47 PM PDT 24
Finished Aug 10 06:19:55 PM PDT 24
Peak memory 217128 kb
Host smart-9571eb03-057d-4181-8829-2c9365874094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217533005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.4217533005
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1168240108
Short name T786
Test name
Test status
Simulation time 79630778416 ps
CPU time 18.78 seconds
Started Aug 10 06:19:52 PM PDT 24
Finished Aug 10 06:20:11 PM PDT 24
Peak memory 217052 kb
Host smart-8dfc7ec9-b7e8-4ce9-8e80-3a7ab186851d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168240108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1168240108
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1654735227
Short name T681
Test name
Test status
Simulation time 88170521 ps
CPU time 1.43 seconds
Started Aug 10 06:19:53 PM PDT 24
Finished Aug 10 06:19:54 PM PDT 24
Peak memory 217004 kb
Host smart-b836ad22-49ae-4787-9614-37a5d13cb9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654735227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1654735227
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1974919165
Short name T1027
Test name
Test status
Simulation time 187014684 ps
CPU time 0.86 seconds
Started Aug 10 06:19:55 PM PDT 24
Finished Aug 10 06:19:56 PM PDT 24
Peak memory 206512 kb
Host smart-f02e2bbf-c6e6-4370-bb36-e54fa13ed5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974919165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1974919165
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.284310003
Short name T931
Test name
Test status
Simulation time 1003933220 ps
CPU time 4.17 seconds
Started Aug 10 06:19:54 PM PDT 24
Finished Aug 10 06:19:58 PM PDT 24
Peak memory 225188 kb
Host smart-8bbbb44e-80e1-4b88-b608-f295cf9cbe1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284310003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.284310003
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1305808953
Short name T570
Test name
Test status
Simulation time 21631236 ps
CPU time 0.69 seconds
Started Aug 10 06:20:01 PM PDT 24
Finished Aug 10 06:20:01 PM PDT 24
Peak memory 205320 kb
Host smart-9b231170-7036-4bab-ad04-93d4ec847c36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305808953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1305808953
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.389382585
Short name T711
Test name
Test status
Simulation time 473246171 ps
CPU time 3.02 seconds
Started Aug 10 06:19:56 PM PDT 24
Finished Aug 10 06:19:59 PM PDT 24
Peak memory 233408 kb
Host smart-4b7c0fbd-5962-421b-9480-a3cea16ed487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389382585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.389382585
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3149304981
Short name T816
Test name
Test status
Simulation time 60906174 ps
CPU time 0.8 seconds
Started Aug 10 06:19:55 PM PDT 24
Finished Aug 10 06:19:56 PM PDT 24
Peak memory 207064 kb
Host smart-977166a4-64e6-4d00-bdac-9423566a0c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149304981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3149304981
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3992257590
Short name T759
Test name
Test status
Simulation time 1317679451 ps
CPU time 6 seconds
Started Aug 10 06:19:52 PM PDT 24
Finished Aug 10 06:19:58 PM PDT 24
Peak memory 234508 kb
Host smart-42999b0f-a90a-452d-b541-1a32ad0abfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992257590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3992257590
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.32644903
Short name T563
Test name
Test status
Simulation time 55943396979 ps
CPU time 75.78 seconds
Started Aug 10 06:20:02 PM PDT 24
Finished Aug 10 06:21:19 PM PDT 24
Peak memory 239988 kb
Host smart-bba51afd-a63b-4696-9e59-0c4a17d65fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32644903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.32644903
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.4265335137
Short name T770
Test name
Test status
Simulation time 824683997 ps
CPU time 7.86 seconds
Started Aug 10 06:19:58 PM PDT 24
Finished Aug 10 06:20:07 PM PDT 24
Peak memory 225284 kb
Host smart-906910e7-084c-478d-ac79-b760efae5445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265335137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.4265335137
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.4150037261
Short name T679
Test name
Test status
Simulation time 9394968878 ps
CPU time 67.48 seconds
Started Aug 10 06:19:55 PM PDT 24
Finished Aug 10 06:21:02 PM PDT 24
Peak memory 241452 kb
Host smart-fa79e542-fd75-47ca-bd76-7d1f1d0f1f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150037261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.4150037261
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.379593375
Short name T932
Test name
Test status
Simulation time 2738512934 ps
CPU time 25.24 seconds
Started Aug 10 06:19:53 PM PDT 24
Finished Aug 10 06:20:19 PM PDT 24
Peak memory 225264 kb
Host smart-ff200221-9d39-4f41-bc0f-906fd1bdede8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379593375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.379593375
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.189407596
Short name T186
Test name
Test status
Simulation time 361137014 ps
CPU time 2.8 seconds
Started Aug 10 06:19:55 PM PDT 24
Finished Aug 10 06:19:57 PM PDT 24
Peak memory 233420 kb
Host smart-8a8a0c6c-a5f8-4f50-b57c-c65da998b66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189407596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.189407596
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1418852972
Short name T695
Test name
Test status
Simulation time 1396154252 ps
CPU time 8.54 seconds
Started Aug 10 06:19:55 PM PDT 24
Finished Aug 10 06:20:03 PM PDT 24
Peak memory 233460 kb
Host smart-ccd2944a-4f20-4a2e-ab23-6c1f012da958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418852972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1418852972
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2133461219
Short name T811
Test name
Test status
Simulation time 151530753 ps
CPU time 2.61 seconds
Started Aug 10 06:19:51 PM PDT 24
Finished Aug 10 06:19:54 PM PDT 24
Peak memory 225168 kb
Host smart-7bcb7470-8f65-4a55-b6e9-de0f07490887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133461219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2133461219
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.136461666
Short name T587
Test name
Test status
Simulation time 960051572 ps
CPU time 8.45 seconds
Started Aug 10 06:19:54 PM PDT 24
Finished Aug 10 06:20:02 PM PDT 24
Peak memory 222584 kb
Host smart-4f956916-afbd-43f7-a660-65a4cf0a0a76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=136461666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.136461666
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1323966834
Short name T267
Test name
Test status
Simulation time 18285916783 ps
CPU time 161.28 seconds
Started Aug 10 06:20:01 PM PDT 24
Finished Aug 10 06:22:43 PM PDT 24
Peak memory 269776 kb
Host smart-dcec4c9d-8d9a-4f25-b37c-88d852b6b185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323966834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1323966834
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.21009506
Short name T574
Test name
Test status
Simulation time 4462987138 ps
CPU time 6.21 seconds
Started Aug 10 06:19:54 PM PDT 24
Finished Aug 10 06:20:01 PM PDT 24
Peak memory 217064 kb
Host smart-dde5329b-ba0b-486f-94f6-675839668f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21009506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.21009506
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1754540613
Short name T657
Test name
Test status
Simulation time 3184113649 ps
CPU time 2.9 seconds
Started Aug 10 06:19:53 PM PDT 24
Finished Aug 10 06:19:56 PM PDT 24
Peak memory 216844 kb
Host smart-c69a4a59-6bab-4a04-a0d7-f29f0818bdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754540613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1754540613
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4046757259
Short name T341
Test name
Test status
Simulation time 259148544 ps
CPU time 1.1 seconds
Started Aug 10 06:19:54 PM PDT 24
Finished Aug 10 06:19:55 PM PDT 24
Peak memory 207820 kb
Host smart-b8a30adc-cfd5-4820-9620-2efadb014891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046757259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4046757259
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3647784268
Short name T629
Test name
Test status
Simulation time 157822168 ps
CPU time 0.93 seconds
Started Aug 10 06:19:53 PM PDT 24
Finished Aug 10 06:19:54 PM PDT 24
Peak memory 206968 kb
Host smart-4167c385-7256-4d51-8eab-97210bf1d9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647784268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3647784268
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2326274681
Short name T805
Test name
Test status
Simulation time 2885284937 ps
CPU time 11.37 seconds
Started Aug 10 06:19:55 PM PDT 24
Finished Aug 10 06:20:06 PM PDT 24
Peak memory 233552 kb
Host smart-0b6fa3d1-abe1-45f7-9e71-40b77740085b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326274681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2326274681
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2359367886
Short name T691
Test name
Test status
Simulation time 37489385 ps
CPU time 0.7 seconds
Started Aug 10 06:20:01 PM PDT 24
Finished Aug 10 06:20:01 PM PDT 24
Peak memory 205828 kb
Host smart-58df5484-2ccb-483b-8e4e-b5b137240193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359367886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2359367886
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3939323030
Short name T402
Test name
Test status
Simulation time 648456946 ps
CPU time 3.42 seconds
Started Aug 10 06:20:02 PM PDT 24
Finished Aug 10 06:20:06 PM PDT 24
Peak memory 225232 kb
Host smart-c400f9ba-ed84-4837-ae6a-2c111c0cec69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939323030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3939323030
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3996203357
Short name T676
Test name
Test status
Simulation time 52697596 ps
CPU time 0.75 seconds
Started Aug 10 06:19:59 PM PDT 24
Finished Aug 10 06:20:00 PM PDT 24
Peak memory 206080 kb
Host smart-bb61d165-d36d-44df-a38b-e88254403ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996203357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3996203357
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.564954824
Short name T758
Test name
Test status
Simulation time 41141540 ps
CPU time 0.87 seconds
Started Aug 10 06:20:00 PM PDT 24
Finished Aug 10 06:20:01 PM PDT 24
Peak memory 216704 kb
Host smart-15034e90-2fd3-4023-973a-8751b9eb2289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564954824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.564954824
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1198555261
Short name T533
Test name
Test status
Simulation time 21700950560 ps
CPU time 14.96 seconds
Started Aug 10 06:20:04 PM PDT 24
Finished Aug 10 06:20:19 PM PDT 24
Peak memory 225420 kb
Host smart-c76fbf9c-9e75-4466-934d-9b1b2c4c5166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198555261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1198555261
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.4154250681
Short name T845
Test name
Test status
Simulation time 13107435450 ps
CPU time 78.58 seconds
Started Aug 10 06:20:01 PM PDT 24
Finished Aug 10 06:21:20 PM PDT 24
Peak memory 250180 kb
Host smart-a09f92ca-338a-4802-85e6-5ebd5bd7f1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154250681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.4154250681
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1117515458
Short name T854
Test name
Test status
Simulation time 279440698 ps
CPU time 7.33 seconds
Started Aug 10 06:19:58 PM PDT 24
Finished Aug 10 06:20:06 PM PDT 24
Peak memory 233488 kb
Host smart-21b05f5e-9eb4-4316-9059-a246d3e1d966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117515458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1117515458
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3316651437
Short name T49
Test name
Test status
Simulation time 1861490546 ps
CPU time 32.29 seconds
Started Aug 10 06:20:00 PM PDT 24
Finished Aug 10 06:20:32 PM PDT 24
Peak memory 241660 kb
Host smart-ee6745fe-5d19-4e89-ace0-1401a6d4299d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316651437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3316651437
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2745498765
Short name T202
Test name
Test status
Simulation time 13435338144 ps
CPU time 13.42 seconds
Started Aug 10 06:20:02 PM PDT 24
Finished Aug 10 06:20:16 PM PDT 24
Peak memory 233512 kb
Host smart-9e7baa80-f620-4f82-86c4-4da09be5f6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745498765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2745498765
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.380959310
Short name T990
Test name
Test status
Simulation time 8828463535 ps
CPU time 32.23 seconds
Started Aug 10 06:20:04 PM PDT 24
Finished Aug 10 06:20:36 PM PDT 24
Peak memory 249852 kb
Host smart-30dd36e2-9634-49ae-81d0-9faa66983931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380959310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.380959310
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4020985521
Short name T205
Test name
Test status
Simulation time 741515089 ps
CPU time 5.27 seconds
Started Aug 10 06:20:03 PM PDT 24
Finished Aug 10 06:20:08 PM PDT 24
Peak memory 225208 kb
Host smart-c5b54608-fc00-45fb-a063-a3b2bbd3c0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020985521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4020985521
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1080228026
Short name T504
Test name
Test status
Simulation time 10522170864 ps
CPU time 12.59 seconds
Started Aug 10 06:20:09 PM PDT 24
Finished Aug 10 06:20:22 PM PDT 24
Peak memory 233492 kb
Host smart-662a0d5c-5ae4-4576-adfa-453accd36710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080228026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1080228026
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.4216751877
Short name T392
Test name
Test status
Simulation time 266858884 ps
CPU time 3.51 seconds
Started Aug 10 06:20:10 PM PDT 24
Finished Aug 10 06:20:13 PM PDT 24
Peak memory 223804 kb
Host smart-721ed0a4-dc59-479d-baa1-dfbe8e1ae861
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4216751877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.4216751877
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1735696757
Short name T16
Test name
Test status
Simulation time 57369229 ps
CPU time 1.13 seconds
Started Aug 10 06:20:04 PM PDT 24
Finished Aug 10 06:20:05 PM PDT 24
Peak memory 207552 kb
Host smart-f02d38fa-879a-4780-bc45-078d8f73c7a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735696757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1735696757
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.488043808
Short name T610
Test name
Test status
Simulation time 4599673329 ps
CPU time 18.89 seconds
Started Aug 10 06:20:02 PM PDT 24
Finished Aug 10 06:20:21 PM PDT 24
Peak memory 217184 kb
Host smart-aa927cf7-5da6-4bb3-afab-4994c73c0484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488043808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.488043808
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.397357392
Short name T385
Test name
Test status
Simulation time 5867800667 ps
CPU time 18.61 seconds
Started Aug 10 06:19:59 PM PDT 24
Finished Aug 10 06:20:17 PM PDT 24
Peak memory 217048 kb
Host smart-6aa83ca6-8041-4842-8c1e-53107fe3675a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397357392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.397357392
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2398645244
Short name T693
Test name
Test status
Simulation time 252836384 ps
CPU time 1.71 seconds
Started Aug 10 06:20:00 PM PDT 24
Finished Aug 10 06:20:01 PM PDT 24
Peak memory 216912 kb
Host smart-e31ddfaa-f2f7-4946-9995-8fec30187209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398645244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2398645244
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3102392670
Short name T700
Test name
Test status
Simulation time 33248633 ps
CPU time 0.81 seconds
Started Aug 10 06:20:03 PM PDT 24
Finished Aug 10 06:20:04 PM PDT 24
Peak memory 206608 kb
Host smart-7ec47da1-9aed-467c-ae9c-f0b1f12d158c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102392670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3102392670
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2681313051
Short name T210
Test name
Test status
Simulation time 362466037 ps
CPU time 3.28 seconds
Started Aug 10 06:19:59 PM PDT 24
Finished Aug 10 06:20:02 PM PDT 24
Peak memory 225224 kb
Host smart-617ccbd9-27a3-4f83-a72d-610832bee534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681313051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2681313051
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1112951453
Short name T62
Test name
Test status
Simulation time 14844695 ps
CPU time 0.75 seconds
Started Aug 10 06:20:03 PM PDT 24
Finished Aug 10 06:20:04 PM PDT 24
Peak memory 205284 kb
Host smart-521ee610-72d6-45b7-bb51-8a6e04e1b1da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112951453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1112951453
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.797125338
Short name T800
Test name
Test status
Simulation time 159289684 ps
CPU time 4.33 seconds
Started Aug 10 06:20:02 PM PDT 24
Finished Aug 10 06:20:06 PM PDT 24
Peak memory 233480 kb
Host smart-eb843ec1-968e-475d-a360-c4bf79fc12b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797125338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.797125338
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.486432645
Short name T403
Test name
Test status
Simulation time 18258882 ps
CPU time 0.79 seconds
Started Aug 10 06:19:58 PM PDT 24
Finished Aug 10 06:19:59 PM PDT 24
Peak memory 207032 kb
Host smart-37ae4b7a-485a-4710-8a38-b3a802cd0880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486432645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.486432645
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.4108295070
Short name T641
Test name
Test status
Simulation time 2822730324 ps
CPU time 40.52 seconds
Started Aug 10 06:20:00 PM PDT 24
Finished Aug 10 06:20:41 PM PDT 24
Peak memory 249932 kb
Host smart-863589ac-c279-4dd2-95f7-363b336daf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108295070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.4108295070
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2667656534
Short name T336
Test name
Test status
Simulation time 2887786457 ps
CPU time 44.06 seconds
Started Aug 10 06:20:03 PM PDT 24
Finished Aug 10 06:20:47 PM PDT 24
Peak memory 241404 kb
Host smart-14647a23-16a1-4df3-a4ce-9f72efb7186e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667656534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2667656534
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3047513573
Short name T439
Test name
Test status
Simulation time 2247598410 ps
CPU time 53.26 seconds
Started Aug 10 06:20:02 PM PDT 24
Finished Aug 10 06:20:56 PM PDT 24
Peak memory 266376 kb
Host smart-588b31b5-d8d8-4d12-95d9-944288205df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047513573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3047513573
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3254581359
Short name T12
Test name
Test status
Simulation time 187418915 ps
CPU time 4.57 seconds
Started Aug 10 06:19:59 PM PDT 24
Finished Aug 10 06:20:04 PM PDT 24
Peak memory 233420 kb
Host smart-07f87d62-7345-4ed3-be09-32f07c389bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254581359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3254581359
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3482726630
Short name T501
Test name
Test status
Simulation time 948044434 ps
CPU time 12.81 seconds
Started Aug 10 06:20:02 PM PDT 24
Finished Aug 10 06:20:15 PM PDT 24
Peak memory 249848 kb
Host smart-b205bd13-4a9d-4b9b-9ba1-a4a6756b19dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482726630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3482726630
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.780463995
Short name T649
Test name
Test status
Simulation time 6767319516 ps
CPU time 13.37 seconds
Started Aug 10 06:19:59 PM PDT 24
Finished Aug 10 06:20:13 PM PDT 24
Peak memory 233548 kb
Host smart-15d9fe54-40c5-4045-bc2c-085ff9246844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780463995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.780463995
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.41957250
Short name T520
Test name
Test status
Simulation time 4904125039 ps
CPU time 55.48 seconds
Started Aug 10 06:19:58 PM PDT 24
Finished Aug 10 06:20:54 PM PDT 24
Peak memory 235348 kb
Host smart-eb733099-c942-43cf-b026-070a046208ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41957250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.41957250
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1709563620
Short name T452
Test name
Test status
Simulation time 6561361921 ps
CPU time 14.05 seconds
Started Aug 10 06:20:00 PM PDT 24
Finished Aug 10 06:20:14 PM PDT 24
Peak memory 240452 kb
Host smart-7882d8be-e571-4fdd-99df-1c8a1fed36bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709563620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1709563620
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2936236520
Short name T1015
Test name
Test status
Simulation time 1167888229 ps
CPU time 4.81 seconds
Started Aug 10 06:20:01 PM PDT 24
Finished Aug 10 06:20:06 PM PDT 24
Peak memory 225292 kb
Host smart-eb58c7b4-a6e1-4b1b-88d5-05b2acb8f878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936236520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2936236520
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1223597955
Short name T378
Test name
Test status
Simulation time 219117152 ps
CPU time 4.12 seconds
Started Aug 10 06:19:57 PM PDT 24
Finished Aug 10 06:20:02 PM PDT 24
Peak memory 223264 kb
Host smart-c205fe9d-0dc3-4811-9789-13f56c2a42cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1223597955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1223597955
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3675183908
Short name T768
Test name
Test status
Simulation time 41693094956 ps
CPU time 167.43 seconds
Started Aug 10 06:20:02 PM PDT 24
Finished Aug 10 06:22:49 PM PDT 24
Peak memory 263840 kb
Host smart-fff13ea9-d9ae-42b6-9d4d-5a3d98ac7210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675183908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3675183908
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3163739116
Short name T956
Test name
Test status
Simulation time 4777836428 ps
CPU time 23.53 seconds
Started Aug 10 06:20:01 PM PDT 24
Finished Aug 10 06:20:25 PM PDT 24
Peak memory 217112 kb
Host smart-6c27444b-0d4d-4d40-9ea6-e4887d958aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163739116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3163739116
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.871528126
Short name T662
Test name
Test status
Simulation time 1555186133 ps
CPU time 4.95 seconds
Started Aug 10 06:20:09 PM PDT 24
Finished Aug 10 06:20:14 PM PDT 24
Peak memory 216940 kb
Host smart-f6f5c4ca-bea0-40ce-a9ef-3c937650f445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871528126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.871528126
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1223149067
Short name T358
Test name
Test status
Simulation time 24198234 ps
CPU time 0.73 seconds
Started Aug 10 06:20:09 PM PDT 24
Finished Aug 10 06:20:10 PM PDT 24
Peak memory 206584 kb
Host smart-8ea4daf7-30bf-4bff-b62c-e9f0c48f8520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223149067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1223149067
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3500604956
Short name T586
Test name
Test status
Simulation time 17254541 ps
CPU time 0.7 seconds
Started Aug 10 06:20:02 PM PDT 24
Finished Aug 10 06:20:02 PM PDT 24
Peak memory 206548 kb
Host smart-9ae8fcb5-1c04-4c24-8772-12cef8fbf54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500604956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3500604956
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1797449469
Short name T898
Test name
Test status
Simulation time 3283316160 ps
CPU time 12.01 seconds
Started Aug 10 06:20:02 PM PDT 24
Finished Aug 10 06:20:14 PM PDT 24
Peak memory 225292 kb
Host smart-a136577c-a4c9-4c94-9555-1b6c56e3c3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797449469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1797449469
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.283370520
Short name T982
Test name
Test status
Simulation time 23256838 ps
CPU time 0.74 seconds
Started Aug 10 06:20:11 PM PDT 24
Finished Aug 10 06:20:12 PM PDT 24
Peak memory 205280 kb
Host smart-4f209522-7e6b-460f-a17f-7d7bc9e0324a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283370520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.283370520
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3764291572
Short name T199
Test name
Test status
Simulation time 1866172951 ps
CPU time 12.12 seconds
Started Aug 10 06:20:13 PM PDT 24
Finished Aug 10 06:20:25 PM PDT 24
Peak memory 225236 kb
Host smart-ddc21056-8977-4e38-9898-081fb0aab960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764291572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3764291572
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.465791006
Short name T377
Test name
Test status
Simulation time 17113733 ps
CPU time 0.83 seconds
Started Aug 10 06:20:10 PM PDT 24
Finished Aug 10 06:20:11 PM PDT 24
Peak memory 206048 kb
Host smart-256ac692-1d8e-4b3c-8593-b06e0338b634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465791006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.465791006
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1698973336
Short name T253
Test name
Test status
Simulation time 2264930993 ps
CPU time 46.57 seconds
Started Aug 10 06:20:12 PM PDT 24
Finished Aug 10 06:20:58 PM PDT 24
Peak memory 265172 kb
Host smart-4d0bed0c-4cca-4948-855b-e0a2f0186c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698973336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1698973336
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3060157940
Short name T550
Test name
Test status
Simulation time 5256592988 ps
CPU time 8.91 seconds
Started Aug 10 06:20:11 PM PDT 24
Finished Aug 10 06:20:20 PM PDT 24
Peak memory 218352 kb
Host smart-8ca75e95-5668-4f38-87c0-c42de58aa362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060157940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3060157940
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3328102745
Short name T286
Test name
Test status
Simulation time 108691562480 ps
CPU time 121.94 seconds
Started Aug 10 06:20:11 PM PDT 24
Finished Aug 10 06:22:13 PM PDT 24
Peak memory 250988 kb
Host smart-2962e77f-4f11-4c13-9227-050d56ab9f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328102745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3328102745
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3892145174
Short name T991
Test name
Test status
Simulation time 5455048691 ps
CPU time 10.61 seconds
Started Aug 10 06:20:14 PM PDT 24
Finished Aug 10 06:20:25 PM PDT 24
Peak memory 234588 kb
Host smart-8f648323-d04b-45a1-8e21-8d97edef2ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892145174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3892145174
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3202633079
Short name T359
Test name
Test status
Simulation time 9256191760 ps
CPU time 17.89 seconds
Started Aug 10 06:20:11 PM PDT 24
Finished Aug 10 06:20:29 PM PDT 24
Peak memory 219788 kb
Host smart-8ab3310c-6870-481b-89a1-e14bb2c29acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202633079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3202633079
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2989554754
Short name T300
Test name
Test status
Simulation time 7650305692 ps
CPU time 10.17 seconds
Started Aug 10 06:20:11 PM PDT 24
Finished Aug 10 06:20:22 PM PDT 24
Peak memory 233360 kb
Host smart-dd3030e7-1434-45a8-9b2e-246c2db03755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989554754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2989554754
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3957311388
Short name T88
Test name
Test status
Simulation time 29423968413 ps
CPU time 63.4 seconds
Started Aug 10 06:20:12 PM PDT 24
Finished Aug 10 06:21:16 PM PDT 24
Peak memory 233504 kb
Host smart-38201a98-3623-489a-91b9-1f44719fb910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957311388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3957311388
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1377839392
Short name T69
Test name
Test status
Simulation time 8799156794 ps
CPU time 15.09 seconds
Started Aug 10 06:20:09 PM PDT 24
Finished Aug 10 06:20:24 PM PDT 24
Peak memory 241668 kb
Host smart-2e4383d9-73c4-422f-a5b8-fd3f4118e7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377839392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1377839392
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1355483085
Short name T223
Test name
Test status
Simulation time 3829317984 ps
CPU time 13.37 seconds
Started Aug 10 06:20:10 PM PDT 24
Finished Aug 10 06:20:24 PM PDT 24
Peak memory 241224 kb
Host smart-9da41a0b-aeac-43da-9f17-b654997ee069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355483085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1355483085
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.333991766
Short name T746
Test name
Test status
Simulation time 1480332276 ps
CPU time 6.29 seconds
Started Aug 10 06:20:10 PM PDT 24
Finished Aug 10 06:20:16 PM PDT 24
Peak memory 223176 kb
Host smart-9b5ac7f7-81a3-4d50-9996-cedb430ca283
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=333991766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.333991766
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2981017664
Short name T159
Test name
Test status
Simulation time 1192416739 ps
CPU time 22.18 seconds
Started Aug 10 06:20:11 PM PDT 24
Finished Aug 10 06:20:33 PM PDT 24
Peak memory 252268 kb
Host smart-a003c1f3-8a8a-4b97-8566-f50e3c4b5bcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981017664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2981017664
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2979510219
Short name T627
Test name
Test status
Simulation time 6588613923 ps
CPU time 22.22 seconds
Started Aug 10 06:20:10 PM PDT 24
Finished Aug 10 06:20:32 PM PDT 24
Peak memory 217056 kb
Host smart-f89566c0-1675-4bad-bad1-b8efd134739d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979510219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2979510219
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1263438139
Short name T353
Test name
Test status
Simulation time 849493806 ps
CPU time 2.7 seconds
Started Aug 10 06:20:09 PM PDT 24
Finished Aug 10 06:20:12 PM PDT 24
Peak memory 208556 kb
Host smart-a41c1b8f-9117-47c9-a7ca-1eed7aa6dc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263438139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1263438139
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.4176063728
Short name T869
Test name
Test status
Simulation time 311546354 ps
CPU time 1.2 seconds
Started Aug 10 06:20:11 PM PDT 24
Finished Aug 10 06:20:12 PM PDT 24
Peak memory 208552 kb
Host smart-4b01a6e8-9a53-4ec4-8565-48a3929cc2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176063728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4176063728
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2506084168
Short name T345
Test name
Test status
Simulation time 71314831 ps
CPU time 0.96 seconds
Started Aug 10 06:20:10 PM PDT 24
Finished Aug 10 06:20:11 PM PDT 24
Peak memory 206520 kb
Host smart-6a345a6a-72e4-483b-a2d1-e3e69158f8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506084168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2506084168
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2624857530
Short name T623
Test name
Test status
Simulation time 2274902020 ps
CPU time 5.01 seconds
Started Aug 10 06:20:12 PM PDT 24
Finished Aug 10 06:20:17 PM PDT 24
Peak memory 225344 kb
Host smart-7dd13223-a2b6-4c41-8854-2ae50e27c4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624857530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2624857530
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3368946966
Short name T892
Test name
Test status
Simulation time 146637792 ps
CPU time 0.67 seconds
Started Aug 10 06:20:10 PM PDT 24
Finished Aug 10 06:20:11 PM PDT 24
Peak memory 205272 kb
Host smart-099fceb9-6608-41b3-bc1c-a25e556f0ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368946966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3368946966
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.255620918
Short name T511
Test name
Test status
Simulation time 6338618394 ps
CPU time 26.45 seconds
Started Aug 10 06:20:10 PM PDT 24
Finished Aug 10 06:20:36 PM PDT 24
Peak memory 225264 kb
Host smart-60658b22-6362-44c1-8f6d-f1234593234c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255620918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.255620918
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2149838606
Short name T34
Test name
Test status
Simulation time 75300125 ps
CPU time 0.78 seconds
Started Aug 10 06:20:12 PM PDT 24
Finished Aug 10 06:20:12 PM PDT 24
Peak memory 207056 kb
Host smart-e641bc2f-162a-4e6a-91e5-451e09eb6422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149838606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2149838606
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.133919075
Short name T986
Test name
Test status
Simulation time 9409980406 ps
CPU time 69.41 seconds
Started Aug 10 06:20:17 PM PDT 24
Finished Aug 10 06:21:27 PM PDT 24
Peak memory 241732 kb
Host smart-cb308518-7710-4d10-90ec-b62762fcdc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133919075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.133919075
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1737145600
Short name T1017
Test name
Test status
Simulation time 15313740198 ps
CPU time 184.38 seconds
Started Aug 10 06:20:12 PM PDT 24
Finished Aug 10 06:23:17 PM PDT 24
Peak memory 249992 kb
Host smart-ad2ad42f-2fa7-411b-b8b0-b0ae667e326a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737145600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1737145600
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1874701260
Short name T58
Test name
Test status
Simulation time 33542066609 ps
CPU time 336.71 seconds
Started Aug 10 06:20:14 PM PDT 24
Finished Aug 10 06:25:51 PM PDT 24
Peak memory 256784 kb
Host smart-28dbd222-9c38-42fd-9c94-67fa5f042327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874701260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1874701260
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3793781621
Short name T297
Test name
Test status
Simulation time 893621544 ps
CPU time 4.94 seconds
Started Aug 10 06:20:10 PM PDT 24
Finished Aug 10 06:20:15 PM PDT 24
Peak memory 234536 kb
Host smart-08128f1b-ceba-41d1-9178-0c18f17ffc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793781621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3793781621
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2386116534
Short name T798
Test name
Test status
Simulation time 22073950616 ps
CPU time 177.74 seconds
Started Aug 10 06:20:11 PM PDT 24
Finished Aug 10 06:23:09 PM PDT 24
Peak memory 251664 kb
Host smart-10118ee3-6251-40d7-af95-d91997b4f981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386116534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2386116534
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3011179337
Short name T628
Test name
Test status
Simulation time 2355342253 ps
CPU time 12.69 seconds
Started Aug 10 06:20:16 PM PDT 24
Finished Aug 10 06:20:29 PM PDT 24
Peak memory 233528 kb
Host smart-dbea4caa-a06b-4f55-a19d-54b5671b7a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011179337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3011179337
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.239687012
Short name T790
Test name
Test status
Simulation time 2151142219 ps
CPU time 33.94 seconds
Started Aug 10 06:20:09 PM PDT 24
Finished Aug 10 06:20:43 PM PDT 24
Peak memory 235532 kb
Host smart-4c22cd86-e401-4f92-9104-980b35d1c71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239687012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.239687012
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3785685992
Short name T228
Test name
Test status
Simulation time 3218196590 ps
CPU time 11.8 seconds
Started Aug 10 06:20:10 PM PDT 24
Finished Aug 10 06:20:22 PM PDT 24
Peak memory 238064 kb
Host smart-bae55e8f-f31c-4152-9d59-8ae7d7cabb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785685992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3785685992
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3182846028
Short name T89
Test name
Test status
Simulation time 511126807 ps
CPU time 3.62 seconds
Started Aug 10 06:20:11 PM PDT 24
Finished Aug 10 06:20:15 PM PDT 24
Peak memory 232800 kb
Host smart-5e8f0b8d-95c9-41d7-b73d-81dd6be9a2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182846028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3182846028
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3732011716
Short name T809
Test name
Test status
Simulation time 320053867 ps
CPU time 3.94 seconds
Started Aug 10 06:20:08 PM PDT 24
Finished Aug 10 06:20:12 PM PDT 24
Peak memory 223916 kb
Host smart-3beca442-4832-4f56-8a4a-e99b261f3ee2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3732011716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3732011716
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.280772633
Short name T878
Test name
Test status
Simulation time 1712275848 ps
CPU time 17.11 seconds
Started Aug 10 06:20:18 PM PDT 24
Finished Aug 10 06:20:36 PM PDT 24
Peak memory 225296 kb
Host smart-622a6d73-a765-4e7d-8031-56c4dfbfed5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280772633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.280772633
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2255170910
Short name T338
Test name
Test status
Simulation time 3853065294 ps
CPU time 19.33 seconds
Started Aug 10 06:20:08 PM PDT 24
Finished Aug 10 06:20:28 PM PDT 24
Peak memory 217052 kb
Host smart-b4843636-c268-4068-9232-352ddf604241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255170910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2255170910
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.720146568
Short name T408
Test name
Test status
Simulation time 52160010830 ps
CPU time 19.91 seconds
Started Aug 10 06:20:19 PM PDT 24
Finished Aug 10 06:20:39 PM PDT 24
Peak memory 217040 kb
Host smart-18aa2bea-7b97-4b80-bfc7-381f59768edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720146568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.720146568
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2503891907
Short name T858
Test name
Test status
Simulation time 739991898 ps
CPU time 4.15 seconds
Started Aug 10 06:20:12 PM PDT 24
Finished Aug 10 06:20:16 PM PDT 24
Peak memory 216972 kb
Host smart-1669a7fb-ac41-446e-9bf0-2b2ea865fd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503891907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2503891907
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.760124156
Short name T588
Test name
Test status
Simulation time 80337085 ps
CPU time 0.9 seconds
Started Aug 10 06:20:09 PM PDT 24
Finished Aug 10 06:20:10 PM PDT 24
Peak memory 206508 kb
Host smart-13ce53f4-2865-4b2c-80c4-849b901d257c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760124156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.760124156
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.4121850113
Short name T450
Test name
Test status
Simulation time 1266000881 ps
CPU time 6.16 seconds
Started Aug 10 06:20:10 PM PDT 24
Finished Aug 10 06:20:16 PM PDT 24
Peak memory 233380 kb
Host smart-b41f0752-a11a-4267-9b06-2f50f06d3d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121850113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.4121850113
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.9775137
Short name T754
Test name
Test status
Simulation time 41448472 ps
CPU time 0.71 seconds
Started Aug 10 06:20:24 PM PDT 24
Finished Aug 10 06:20:24 PM PDT 24
Peak memory 205280 kb
Host smart-86b30c15-9e07-4b1e-b9b4-f5d492cc7312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9775137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.9775137
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3119569518
Short name T769
Test name
Test status
Simulation time 152973842 ps
CPU time 2.53 seconds
Started Aug 10 06:20:22 PM PDT 24
Finished Aug 10 06:20:25 PM PDT 24
Peak memory 233424 kb
Host smart-2c25b6d3-3fcb-4dc5-b25f-53a9d1652c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119569518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3119569518
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1693789600
Short name T604
Test name
Test status
Simulation time 34771034 ps
CPU time 0.73 seconds
Started Aug 10 06:20:12 PM PDT 24
Finished Aug 10 06:20:13 PM PDT 24
Peak memory 206348 kb
Host smart-040aa32b-f96b-4b0a-9163-f3dc638df3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693789600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1693789600
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3580314365
Short name T776
Test name
Test status
Simulation time 7394024330 ps
CPU time 51.22 seconds
Started Aug 10 06:20:22 PM PDT 24
Finished Aug 10 06:21:13 PM PDT 24
Peak memory 250320 kb
Host smart-ae4064fe-4808-4b5c-bb96-d9be843f0e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580314365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3580314365
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.88951910
Short name T917
Test name
Test status
Simulation time 2846060045 ps
CPU time 19.54 seconds
Started Aug 10 06:20:22 PM PDT 24
Finished Aug 10 06:20:42 PM PDT 24
Peak memory 236784 kb
Host smart-066a3d02-a8e7-4abc-8222-aba823e2c17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88951910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.88951910
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.253069941
Short name T396
Test name
Test status
Simulation time 3512409870 ps
CPU time 7.87 seconds
Started Aug 10 06:20:21 PM PDT 24
Finished Aug 10 06:20:29 PM PDT 24
Peak memory 233492 kb
Host smart-ddacbb7c-20e2-4282-b1e4-6ca058c6af3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253069941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.253069941
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2633031859
Short name T677
Test name
Test status
Simulation time 26775908507 ps
CPU time 182.52 seconds
Started Aug 10 06:20:26 PM PDT 24
Finished Aug 10 06:23:29 PM PDT 24
Peak memory 251516 kb
Host smart-04c1c8e4-5312-4770-a155-709416caebd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633031859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2633031859
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1688753890
Short name T302
Test name
Test status
Simulation time 4608289257 ps
CPU time 10.42 seconds
Started Aug 10 06:20:21 PM PDT 24
Finished Aug 10 06:20:31 PM PDT 24
Peak memory 225360 kb
Host smart-9eaaf14f-6470-48d6-849d-93ba95f252f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688753890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1688753890
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1490179949
Short name T801
Test name
Test status
Simulation time 2549982773 ps
CPU time 23.43 seconds
Started Aug 10 06:20:24 PM PDT 24
Finished Aug 10 06:20:47 PM PDT 24
Peak memory 225304 kb
Host smart-37db95c7-5b35-4e1b-9930-702b1ea2ae0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490179949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1490179949
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3995013123
Short name T357
Test name
Test status
Simulation time 1655948486 ps
CPU time 4.87 seconds
Started Aug 10 06:20:25 PM PDT 24
Finished Aug 10 06:20:30 PM PDT 24
Peak memory 233500 kb
Host smart-1d006637-4393-410e-add8-110b5b48d81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995013123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3995013123
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2324346090
Short name T755
Test name
Test status
Simulation time 1263987814 ps
CPU time 10.49 seconds
Started Aug 10 06:20:25 PM PDT 24
Finished Aug 10 06:20:35 PM PDT 24
Peak memory 241512 kb
Host smart-2bf5b3cd-37ee-408c-bd6a-73534f196415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324346090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2324346090
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3629039990
Short name T145
Test name
Test status
Simulation time 5044062976 ps
CPU time 11.38 seconds
Started Aug 10 06:20:24 PM PDT 24
Finished Aug 10 06:20:36 PM PDT 24
Peak memory 221168 kb
Host smart-9c3e041e-0e93-4fa1-b8ed-e62cb4dcedf7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3629039990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3629039990
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.474804692
Short name T793
Test name
Test status
Simulation time 72743594739 ps
CPU time 212.59 seconds
Started Aug 10 06:20:21 PM PDT 24
Finished Aug 10 06:23:54 PM PDT 24
Peak memory 258316 kb
Host smart-1e6f7206-eb58-4f8f-80c3-1fb478cdc30d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474804692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.474804692
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.655547740
Short name T1010
Test name
Test status
Simulation time 2065325176 ps
CPU time 9.95 seconds
Started Aug 10 06:20:21 PM PDT 24
Finished Aug 10 06:20:31 PM PDT 24
Peak memory 216984 kb
Host smart-01aff6f2-8c25-4d48-8360-1e627cc6042d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655547740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.655547740
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.898390756
Short name T857
Test name
Test status
Simulation time 622415921 ps
CPU time 3.63 seconds
Started Aug 10 06:20:21 PM PDT 24
Finished Aug 10 06:20:25 PM PDT 24
Peak memory 217008 kb
Host smart-01e2d46c-4a80-4094-a96b-66c2360060bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898390756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.898390756
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3104349384
Short name T820
Test name
Test status
Simulation time 117395463 ps
CPU time 1.15 seconds
Started Aug 10 06:20:21 PM PDT 24
Finished Aug 10 06:20:22 PM PDT 24
Peak memory 208588 kb
Host smart-4e68fc27-52ee-4bf3-b8d0-3b214d3a7a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104349384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3104349384
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.822248816
Short name T592
Test name
Test status
Simulation time 45116504 ps
CPU time 0.77 seconds
Started Aug 10 06:20:25 PM PDT 24
Finished Aug 10 06:20:26 PM PDT 24
Peak memory 206596 kb
Host smart-94010863-2eaa-4611-9a42-74aad8a16fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822248816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.822248816
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2497907180
Short name T172
Test name
Test status
Simulation time 1825604794 ps
CPU time 12.31 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:20:36 PM PDT 24
Peak memory 233484 kb
Host smart-3358db5a-7b55-4ad0-b654-8180b3813aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497907180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2497907180
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1250132369
Short name T458
Test name
Test status
Simulation time 43769773 ps
CPU time 0.75 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:20:24 PM PDT 24
Peak memory 205260 kb
Host smart-01afab86-2b08-4aa1-bd9d-94521f41855f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250132369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1250132369
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3742206213
Short name T731
Test name
Test status
Simulation time 1299451970 ps
CPU time 6.12 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:20:29 PM PDT 24
Peak memory 225248 kb
Host smart-6aab5163-f1f3-477c-9bc9-68260c64bd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742206213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3742206213
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1108277950
Short name T596
Test name
Test status
Simulation time 18271796 ps
CPU time 0.73 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:20:24 PM PDT 24
Peak memory 206060 kb
Host smart-c2b09810-ee58-4108-a07c-48a98267d85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108277950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1108277950
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.970346822
Short name T8
Test name
Test status
Simulation time 70191715054 ps
CPU time 127.58 seconds
Started Aug 10 06:20:22 PM PDT 24
Finished Aug 10 06:22:30 PM PDT 24
Peak memory 252600 kb
Host smart-a17c5bf7-484e-4a61-b413-fdd325e1e22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970346822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.970346822
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1759198203
Short name T453
Test name
Test status
Simulation time 14488914688 ps
CPU time 119.27 seconds
Started Aug 10 06:20:25 PM PDT 24
Finished Aug 10 06:22:24 PM PDT 24
Peak memory 254840 kb
Host smart-2039e172-aeaa-4b5c-8d83-028e9a284aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759198203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1759198203
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1431304825
Short name T26
Test name
Test status
Simulation time 21487606674 ps
CPU time 81.61 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:21:45 PM PDT 24
Peak memory 250980 kb
Host smart-1963ba7a-2052-4703-a7d6-c5128bd133c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431304825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1431304825
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.458487944
Short name T280
Test name
Test status
Simulation time 12934327606 ps
CPU time 17.58 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:20:41 PM PDT 24
Peak memory 236628 kb
Host smart-d69a17a4-6d4a-47ba-a3ab-50959d7bab10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458487944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.458487944
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.775991924
Short name T301
Test name
Test status
Simulation time 477829099 ps
CPU time 4.91 seconds
Started Aug 10 06:20:19 PM PDT 24
Finished Aug 10 06:20:24 PM PDT 24
Peak memory 233428 kb
Host smart-78abbc66-9ab6-4e34-8bcf-d817248cd2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775991924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.775991924
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1947509244
Short name T213
Test name
Test status
Simulation time 44774269270 ps
CPU time 125.04 seconds
Started Aug 10 06:20:22 PM PDT 24
Finished Aug 10 06:22:27 PM PDT 24
Peak memory 225328 kb
Host smart-d9a95434-cc27-4d42-8bc6-a0b80cfaab4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947509244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1947509244
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1400371760
Short name T216
Test name
Test status
Simulation time 4768773707 ps
CPU time 12.27 seconds
Started Aug 10 06:20:22 PM PDT 24
Finished Aug 10 06:20:35 PM PDT 24
Peak memory 233500 kb
Host smart-a5d54f2c-df27-44bb-a560-f718dc472221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400371760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1400371760
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2168434142
Short name T713
Test name
Test status
Simulation time 13569473053 ps
CPU time 12.35 seconds
Started Aug 10 06:20:24 PM PDT 24
Finished Aug 10 06:20:37 PM PDT 24
Peak memory 240028 kb
Host smart-b9af1374-8024-4cdd-9ca0-83125e1c2303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168434142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2168434142
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.823151304
Short name T585
Test name
Test status
Simulation time 1092230073 ps
CPU time 13.73 seconds
Started Aug 10 06:20:25 PM PDT 24
Finished Aug 10 06:20:39 PM PDT 24
Peak memory 223572 kb
Host smart-3835999b-7ef2-4e49-9f0c-7d906498a03c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=823151304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.823151304
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1245057553
Short name T160
Test name
Test status
Simulation time 237321452 ps
CPU time 1.13 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:20:24 PM PDT 24
Peak memory 207648 kb
Host smart-c7d01e48-34af-43c5-bed2-1481aaf9e280
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245057553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1245057553
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3911364792
Short name T608
Test name
Test status
Simulation time 1631748419 ps
CPU time 10.53 seconds
Started Aug 10 06:20:25 PM PDT 24
Finished Aug 10 06:20:35 PM PDT 24
Peak memory 217324 kb
Host smart-b5ec22cb-2f38-496b-90fe-37f200dd87df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911364792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3911364792
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1759304795
Short name T614
Test name
Test status
Simulation time 1311996942 ps
CPU time 8.21 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:20:31 PM PDT 24
Peak memory 216964 kb
Host smart-337f3b5c-b29f-4149-8f9e-cd9fd69843cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759304795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1759304795
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3830045091
Short name T427
Test name
Test status
Simulation time 23752557 ps
CPU time 0.95 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:20:24 PM PDT 24
Peak memory 207992 kb
Host smart-14809557-eab4-4aa4-9ba9-2adddb93819b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830045091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3830045091
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1947563657
Short name T867
Test name
Test status
Simulation time 55610401 ps
CPU time 0.81 seconds
Started Aug 10 06:20:22 PM PDT 24
Finished Aug 10 06:20:23 PM PDT 24
Peak memory 206528 kb
Host smart-9d8e6d59-8cd6-4296-8cd7-732694209a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947563657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1947563657
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.41621800
Short name T766
Test name
Test status
Simulation time 3746808815 ps
CPU time 12.58 seconds
Started Aug 10 06:20:25 PM PDT 24
Finished Aug 10 06:20:38 PM PDT 24
Peak memory 225160 kb
Host smart-03a6fb8a-d5a2-43bc-b6b5-23ed2189fdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41621800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.41621800
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2961675010
Short name T814
Test name
Test status
Simulation time 49488528 ps
CPU time 0.69 seconds
Started Aug 10 06:18:24 PM PDT 24
Finished Aug 10 06:18:25 PM PDT 24
Peak memory 205856 kb
Host smart-f55c8a25-e07e-4d20-b0f6-7ea029c3352d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961675010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
961675010
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2479341642
Short name T720
Test name
Test status
Simulation time 249179048 ps
CPU time 2.87 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:18:35 PM PDT 24
Peak memory 233380 kb
Host smart-b9452d67-88be-4c10-9c46-1bbfdf3a40f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479341642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2479341642
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2988448850
Short name T887
Test name
Test status
Simulation time 28443012 ps
CPU time 0.76 seconds
Started Aug 10 06:18:19 PM PDT 24
Finished Aug 10 06:18:19 PM PDT 24
Peak memory 207104 kb
Host smart-22afa1af-cc4e-4d1c-b04b-f0c4a40af781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988448850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2988448850
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1066439751
Short name T187
Test name
Test status
Simulation time 108649565476 ps
CPU time 183.5 seconds
Started Aug 10 06:18:22 PM PDT 24
Finished Aug 10 06:21:25 PM PDT 24
Peak memory 254820 kb
Host smart-b7d49d21-6c7f-4aaa-9065-4c469dc90fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066439751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1066439751
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3656551927
Short name T414
Test name
Test status
Simulation time 9273640478 ps
CPU time 93 seconds
Started Aug 10 06:18:30 PM PDT 24
Finished Aug 10 06:20:03 PM PDT 24
Peak memory 251356 kb
Host smart-04ef1de5-bc77-4884-8d8a-52075e8e097e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656551927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3656551927
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2346644073
Short name T916
Test name
Test status
Simulation time 6697280024 ps
CPU time 71.06 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:19:43 PM PDT 24
Peak memory 256996 kb
Host smart-ad439fad-873a-4311-9b56-901e0a74c416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346644073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2346644073
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.186966453
Short name T55
Test name
Test status
Simulation time 46276524 ps
CPU time 2.76 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:18:35 PM PDT 24
Peak memory 233480 kb
Host smart-556ae784-8027-4afd-a99b-c492b7cf1c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186966453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.186966453
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1174663425
Short name T257
Test name
Test status
Simulation time 5159134913 ps
CPU time 68.91 seconds
Started Aug 10 06:18:24 PM PDT 24
Finished Aug 10 06:19:33 PM PDT 24
Peak memory 249884 kb
Host smart-605532bb-4e6c-403a-be99-fd44b852a01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174663425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1174663425
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.60360687
Short name T997
Test name
Test status
Simulation time 276898072 ps
CPU time 4.09 seconds
Started Aug 10 06:18:18 PM PDT 24
Finished Aug 10 06:18:22 PM PDT 24
Peak memory 225236 kb
Host smart-a30ee34e-a0b8-489b-8f9e-884bdf864808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60360687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.60360687
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2670450047
Short name T197
Test name
Test status
Simulation time 4662822936 ps
CPU time 45.44 seconds
Started Aug 10 06:18:31 PM PDT 24
Finished Aug 10 06:19:16 PM PDT 24
Peak memory 250028 kb
Host smart-e2474b1a-7a3e-414f-aa9a-dbc93fa86ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670450047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2670450047
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1426585163
Short name T698
Test name
Test status
Simulation time 53366053 ps
CPU time 1.02 seconds
Started Aug 10 06:18:18 PM PDT 24
Finished Aug 10 06:18:19 PM PDT 24
Peak memory 218436 kb
Host smart-4a6c08e7-80e5-4373-8942-b735717abee5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426585163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1426585163
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1760962745
Short name T314
Test name
Test status
Simulation time 519970365 ps
CPU time 4.14 seconds
Started Aug 10 06:18:17 PM PDT 24
Finished Aug 10 06:18:21 PM PDT 24
Peak memory 225216 kb
Host smart-c99c1e91-8021-4ced-bdbc-21899fbc8ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760962745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1760962745
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2547649932
Short name T212
Test name
Test status
Simulation time 1429775429 ps
CPU time 4.96 seconds
Started Aug 10 06:18:18 PM PDT 24
Finished Aug 10 06:18:23 PM PDT 24
Peak memory 233512 kb
Host smart-3601c900-24db-4e3b-83f9-942becd4fbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547649932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2547649932
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3727306522
Short name T11
Test name
Test status
Simulation time 611381521 ps
CPU time 8.72 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:18:42 PM PDT 24
Peak memory 223664 kb
Host smart-090b2063-550a-4e7a-a039-dd65fa07a3b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3727306522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3727306522
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2256175456
Short name T67
Test name
Test status
Simulation time 76653944 ps
CPU time 1.13 seconds
Started Aug 10 06:18:30 PM PDT 24
Finished Aug 10 06:18:31 PM PDT 24
Peak memory 235964 kb
Host smart-689edc98-8fa2-4a5c-8b84-546affeca39f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256175456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2256175456
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3610866448
Short name T959
Test name
Test status
Simulation time 715139591 ps
CPU time 9.49 seconds
Started Aug 10 06:18:19 PM PDT 24
Finished Aug 10 06:18:28 PM PDT 24
Peak memory 217080 kb
Host smart-bb39601c-3114-4d04-bf00-fa2273b8b645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610866448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3610866448
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3943546521
Short name T433
Test name
Test status
Simulation time 4862751575 ps
CPU time 13.33 seconds
Started Aug 10 06:18:20 PM PDT 24
Finished Aug 10 06:18:34 PM PDT 24
Peak memory 216576 kb
Host smart-937a3bb4-8ac3-4acc-b98d-31161179658e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943546521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3943546521
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.299839782
Short name T771
Test name
Test status
Simulation time 735072725 ps
CPU time 1.83 seconds
Started Aug 10 06:18:19 PM PDT 24
Finished Aug 10 06:18:21 PM PDT 24
Peak memory 216940 kb
Host smart-f4de702b-a7ad-48bc-ae44-bf227b4bb5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299839782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.299839782
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3985548504
Short name T37
Test name
Test status
Simulation time 111676288 ps
CPU time 0.9 seconds
Started Aug 10 06:18:17 PM PDT 24
Finished Aug 10 06:18:18 PM PDT 24
Peak memory 207616 kb
Host smart-9ea732c4-ff89-4154-9fd1-27d7562ef12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985548504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3985548504
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1225882121
Short name T416
Test name
Test status
Simulation time 7678589149 ps
CPU time 4.23 seconds
Started Aug 10 06:18:23 PM PDT 24
Finished Aug 10 06:18:27 PM PDT 24
Peak memory 225256 kb
Host smart-2fbbd2b6-3476-4872-a6b2-d62669673375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225882121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1225882121
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.112510463
Short name T937
Test name
Test status
Simulation time 12093582 ps
CPU time 0.68 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:20:24 PM PDT 24
Peak memory 205792 kb
Host smart-cfe4a3d9-d29c-4874-b782-055f3dc57e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112510463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.112510463
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.639239263
Short name T826
Test name
Test status
Simulation time 285695204 ps
CPU time 2.69 seconds
Started Aug 10 06:20:26 PM PDT 24
Finished Aug 10 06:20:29 PM PDT 24
Peak memory 225308 kb
Host smart-09670439-95fe-4bd1-a173-aaf2a12ae76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639239263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.639239263
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4045436264
Short name T360
Test name
Test status
Simulation time 15342255 ps
CPU time 0.76 seconds
Started Aug 10 06:20:27 PM PDT 24
Finished Aug 10 06:20:28 PM PDT 24
Peak memory 206392 kb
Host smart-7097209d-dfa8-4989-9f6a-465fa94e0aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045436264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4045436264
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3662110574
Short name T747
Test name
Test status
Simulation time 9128323888 ps
CPU time 83.09 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:21:46 PM PDT 24
Peak memory 233520 kb
Host smart-604fa2d5-7284-49ff-939f-403b12675c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662110574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3662110574
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2832394952
Short name T252
Test name
Test status
Simulation time 16741044458 ps
CPU time 40.39 seconds
Started Aug 10 06:20:20 PM PDT 24
Finished Aug 10 06:21:01 PM PDT 24
Peak memory 241652 kb
Host smart-4e44d1f7-65d7-4672-ad05-5bc39aa2f928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832394952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2832394952
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.311784259
Short name T794
Test name
Test status
Simulation time 3441357225 ps
CPU time 34.48 seconds
Started Aug 10 06:20:25 PM PDT 24
Finished Aug 10 06:21:00 PM PDT 24
Peak memory 233600 kb
Host smart-0f4b82e8-e267-46b8-a132-2044aa2af8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311784259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.311784259
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1663322173
Short name T650
Test name
Test status
Simulation time 4495545117 ps
CPU time 17.57 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:20:41 PM PDT 24
Peak memory 234836 kb
Host smart-959932c9-0475-4f85-918f-6e0ac3133d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663322173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1663322173
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.999352065
Short name T473
Test name
Test status
Simulation time 632662370 ps
CPU time 2.68 seconds
Started Aug 10 06:20:25 PM PDT 24
Finished Aug 10 06:20:28 PM PDT 24
Peak memory 233272 kb
Host smart-b60e66c0-14dc-4556-aacd-21c9324be19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999352065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.999352065
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4023637063
Short name T620
Test name
Test status
Simulation time 29888781 ps
CPU time 2.05 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:20:25 PM PDT 24
Peak memory 224528 kb
Host smart-945be0e4-06b0-4312-bd6d-7e43cac658b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023637063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4023637063
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.4100667250
Short name T659
Test name
Test status
Simulation time 11242786669 ps
CPU time 9.71 seconds
Started Aug 10 06:20:25 PM PDT 24
Finished Aug 10 06:20:35 PM PDT 24
Peak memory 233532 kb
Host smart-98f23bfe-594d-4098-9b2e-4b36b1e42d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100667250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.4100667250
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3392466950
Short name T884
Test name
Test status
Simulation time 7857259406 ps
CPU time 6.44 seconds
Started Aug 10 06:20:24 PM PDT 24
Finished Aug 10 06:20:31 PM PDT 24
Peak memory 241560 kb
Host smart-5d8d9d30-853b-406f-bfc3-42d31b200213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392466950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3392466950
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2249015544
Short name T372
Test name
Test status
Simulation time 4669280421 ps
CPU time 9.06 seconds
Started Aug 10 06:20:27 PM PDT 24
Finished Aug 10 06:20:36 PM PDT 24
Peak memory 219608 kb
Host smart-645bfb44-bd32-47d3-9998-fdbbbcea9f78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2249015544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2249015544
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1903826242
Short name T861
Test name
Test status
Simulation time 25101382095 ps
CPU time 223.18 seconds
Started Aug 10 06:20:24 PM PDT 24
Finished Aug 10 06:24:08 PM PDT 24
Peak memory 252820 kb
Host smart-56910c43-5aa0-4e68-b56c-9dc959d32b39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903826242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1903826242
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2495999729
Short name T35
Test name
Test status
Simulation time 28222266451 ps
CPU time 31.96 seconds
Started Aug 10 06:20:19 PM PDT 24
Finished Aug 10 06:20:51 PM PDT 24
Peak memory 217048 kb
Host smart-130db989-464c-4606-9baf-f94b4d207c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495999729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2495999729
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3723673110
Short name T1005
Test name
Test status
Simulation time 7611959153 ps
CPU time 6.42 seconds
Started Aug 10 06:20:23 PM PDT 24
Finished Aug 10 06:20:30 PM PDT 24
Peak memory 216872 kb
Host smart-18114b59-9a00-4f37-bf5d-ad82b8f26d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723673110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3723673110
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4204556081
Short name T940
Test name
Test status
Simulation time 37994201 ps
CPU time 0.73 seconds
Started Aug 10 06:20:25 PM PDT 24
Finished Aug 10 06:20:26 PM PDT 24
Peak memory 205936 kb
Host smart-1c76b5cd-f20f-4093-81de-346d1fde43e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204556081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4204556081
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2212775973
Short name T36
Test name
Test status
Simulation time 13422682 ps
CPU time 0.7 seconds
Started Aug 10 06:20:21 PM PDT 24
Finished Aug 10 06:20:22 PM PDT 24
Peak memory 206588 kb
Host smart-2b5fef73-1969-4046-8ade-2d339d9f135d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212775973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2212775973
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.533895350
Short name T500
Test name
Test status
Simulation time 7816999683 ps
CPU time 8.52 seconds
Started Aug 10 06:20:22 PM PDT 24
Finished Aug 10 06:20:31 PM PDT 24
Peak memory 225424 kb
Host smart-815ee377-b202-4cd8-a670-a593f53821f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533895350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.533895350
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3232140634
Short name T839
Test name
Test status
Simulation time 19940892 ps
CPU time 0.71 seconds
Started Aug 10 06:20:38 PM PDT 24
Finished Aug 10 06:20:39 PM PDT 24
Peak memory 206220 kb
Host smart-1827b9ac-e4da-4d4b-adcf-32dbc0fee590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232140634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3232140634
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2008092464
Short name T849
Test name
Test status
Simulation time 351271433 ps
CPU time 4.19 seconds
Started Aug 10 06:20:39 PM PDT 24
Finished Aug 10 06:20:43 PM PDT 24
Peak memory 233424 kb
Host smart-1eca1e52-c412-497f-a3df-2474ea0798f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008092464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2008092464
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1185219570
Short name T366
Test name
Test status
Simulation time 42123740 ps
CPU time 0.82 seconds
Started Aug 10 06:20:24 PM PDT 24
Finished Aug 10 06:20:25 PM PDT 24
Peak memory 207080 kb
Host smart-bdab389b-745a-44ce-b508-b34197cb8534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185219570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1185219570
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3542082184
Short name T680
Test name
Test status
Simulation time 12312405983 ps
CPU time 75.48 seconds
Started Aug 10 06:20:39 PM PDT 24
Finished Aug 10 06:21:54 PM PDT 24
Peak memory 241732 kb
Host smart-f7759613-492e-469c-82d1-bd97b8872f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542082184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3542082184
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3957247795
Short name T184
Test name
Test status
Simulation time 458475388136 ps
CPU time 446.2 seconds
Started Aug 10 06:20:36 PM PDT 24
Finished Aug 10 06:28:02 PM PDT 24
Peak memory 264236 kb
Host smart-6f5d3d04-0550-43ae-8aa8-e6812ea3cd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957247795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3957247795
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2998225039
Short name T262
Test name
Test status
Simulation time 19949333423 ps
CPU time 187.72 seconds
Started Aug 10 06:20:38 PM PDT 24
Finished Aug 10 06:23:46 PM PDT 24
Peak memory 241812 kb
Host smart-252d6854-ad34-436b-b0d8-3099fff3add0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998225039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2998225039
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2872386406
Short name T323
Test name
Test status
Simulation time 1015814437 ps
CPU time 15.1 seconds
Started Aug 10 06:20:33 PM PDT 24
Finished Aug 10 06:20:48 PM PDT 24
Peak memory 225272 kb
Host smart-abd38ffe-7aec-4ed3-bb93-91b18ecb513f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872386406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2872386406
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.906346
Short name T491
Test name
Test status
Simulation time 24994605374 ps
CPU time 34.42 seconds
Started Aug 10 06:20:37 PM PDT 24
Finished Aug 10 06:21:12 PM PDT 24
Peak memory 235520 kb
Host smart-d946b434-5fc4-4353-a1f0-46ce019a537a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.906346
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1937976617
Short name T307
Test name
Test status
Simulation time 1073661650 ps
CPU time 6.52 seconds
Started Aug 10 06:20:37 PM PDT 24
Finished Aug 10 06:20:44 PM PDT 24
Peak memory 233460 kb
Host smart-fe8cc8c0-fdf6-4d48-a920-34301c0687e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937976617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1937976617
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.921118278
Short name T855
Test name
Test status
Simulation time 18822112643 ps
CPU time 28.59 seconds
Started Aug 10 06:20:36 PM PDT 24
Finished Aug 10 06:21:05 PM PDT 24
Peak memory 235076 kb
Host smart-eedc48b1-90e3-4d4c-a4c3-9c6a22400fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921118278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.921118278
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2581474738
Short name T658
Test name
Test status
Simulation time 4541674636 ps
CPU time 7.56 seconds
Started Aug 10 06:20:39 PM PDT 24
Finished Aug 10 06:20:47 PM PDT 24
Peak memory 233504 kb
Host smart-fadd8f8f-0742-4300-902c-27c44ad6e20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581474738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2581474738
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1607733938
Short name T498
Test name
Test status
Simulation time 483683884 ps
CPU time 5.5 seconds
Started Aug 10 06:20:37 PM PDT 24
Finished Aug 10 06:20:43 PM PDT 24
Peak memory 233464 kb
Host smart-264599ae-362a-4af2-b249-b7125a46c5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607733938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1607733938
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.4047670932
Short name T399
Test name
Test status
Simulation time 2966726930 ps
CPU time 5.36 seconds
Started Aug 10 06:20:35 PM PDT 24
Finished Aug 10 06:20:41 PM PDT 24
Peak memory 223740 kb
Host smart-d2939da1-2a13-4b65-b750-a3aea2edeeb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4047670932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.4047670932
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3090730240
Short name T161
Test name
Test status
Simulation time 55006285730 ps
CPU time 289.71 seconds
Started Aug 10 06:20:39 PM PDT 24
Finished Aug 10 06:25:29 PM PDT 24
Peak memory 266156 kb
Host smart-77fbb102-ae5e-4a0a-b933-fecbffedff24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090730240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3090730240
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.322050888
Short name T589
Test name
Test status
Simulation time 5975585168 ps
CPU time 29.18 seconds
Started Aug 10 06:20:36 PM PDT 24
Finished Aug 10 06:21:05 PM PDT 24
Peak memory 217172 kb
Host smart-e9e4afa6-b88a-424b-b3b9-57a0d3f46c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322050888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.322050888
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3138869839
Short name T374
Test name
Test status
Simulation time 15012699 ps
CPU time 0.7 seconds
Started Aug 10 06:20:34 PM PDT 24
Finished Aug 10 06:20:35 PM PDT 24
Peak memory 206180 kb
Host smart-32144cd1-2f03-44b8-88a8-fe7883072a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138869839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3138869839
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3602703684
Short name T376
Test name
Test status
Simulation time 20053526 ps
CPU time 0.85 seconds
Started Aug 10 06:20:37 PM PDT 24
Finished Aug 10 06:20:38 PM PDT 24
Peak memory 206608 kb
Host smart-db143591-0cec-47e9-889e-2dcfbabb4fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602703684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3602703684
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3161027810
Short name T708
Test name
Test status
Simulation time 37767851 ps
CPU time 0.79 seconds
Started Aug 10 06:20:37 PM PDT 24
Finished Aug 10 06:20:37 PM PDT 24
Peak memory 206592 kb
Host smart-6ece3021-6f82-43aa-979f-ad1ae2a889a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161027810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3161027810
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.97028713
Short name T582
Test name
Test status
Simulation time 392079955 ps
CPU time 7.46 seconds
Started Aug 10 06:20:38 PM PDT 24
Finished Aug 10 06:20:46 PM PDT 24
Peak memory 233432 kb
Host smart-6a770c83-8e39-4383-8649-6c6ae7aa5de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97028713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.97028713
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2848844002
Short name T519
Test name
Test status
Simulation time 23951845 ps
CPU time 0.77 seconds
Started Aug 10 06:20:40 PM PDT 24
Finished Aug 10 06:20:41 PM PDT 24
Peak memory 205292 kb
Host smart-2a62463e-c396-49e2-bf06-6808dfcb97c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848844002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2848844002
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3372467330
Short name T653
Test name
Test status
Simulation time 327621868 ps
CPU time 5.94 seconds
Started Aug 10 06:20:37 PM PDT 24
Finished Aug 10 06:20:43 PM PDT 24
Peak memory 233428 kb
Host smart-e65a898e-a415-4f3a-ae1e-683b9bbfd58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372467330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3372467330
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1005811473
Short name T870
Test name
Test status
Simulation time 332580302 ps
CPU time 0.82 seconds
Started Aug 10 06:20:38 PM PDT 24
Finished Aug 10 06:20:39 PM PDT 24
Peak memory 207076 kb
Host smart-338fc93b-d955-44b4-9ff9-b49a36c4ece1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005811473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1005811473
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.72043996
Short name T529
Test name
Test status
Simulation time 25092564947 ps
CPU time 46.51 seconds
Started Aug 10 06:20:38 PM PDT 24
Finished Aug 10 06:21:25 PM PDT 24
Peak memory 238704 kb
Host smart-70b7c3f2-ee48-442b-8da4-29100aa79ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72043996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.72043996
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2155259893
Short name T843
Test name
Test status
Simulation time 3092488678 ps
CPU time 36.48 seconds
Started Aug 10 06:20:36 PM PDT 24
Finished Aug 10 06:21:13 PM PDT 24
Peak memory 249992 kb
Host smart-c754ae29-7f9d-4fa2-8bbb-545d4f141ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155259893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2155259893
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1771454099
Short name T911
Test name
Test status
Simulation time 4633183957 ps
CPU time 7.55 seconds
Started Aug 10 06:20:36 PM PDT 24
Finished Aug 10 06:20:43 PM PDT 24
Peak memory 225340 kb
Host smart-aafae671-7f6c-4147-8a76-94920f4b438f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771454099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1771454099
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3997306819
Short name T918
Test name
Test status
Simulation time 19555580438 ps
CPU time 128.83 seconds
Started Aug 10 06:20:35 PM PDT 24
Finished Aug 10 06:22:44 PM PDT 24
Peak memory 265124 kb
Host smart-138c321c-168b-4577-929c-5023f0c53e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997306819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3997306819
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3739655620
Short name T836
Test name
Test status
Simulation time 29477343 ps
CPU time 2.36 seconds
Started Aug 10 06:20:35 PM PDT 24
Finished Aug 10 06:20:38 PM PDT 24
Peak memory 233080 kb
Host smart-916b2b1f-f05b-45af-b6d1-c4df23687aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739655620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3739655620
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1966088008
Short name T999
Test name
Test status
Simulation time 6654835591 ps
CPU time 67.61 seconds
Started Aug 10 06:20:37 PM PDT 24
Finished Aug 10 06:21:45 PM PDT 24
Peak memory 225324 kb
Host smart-d992b7c3-5c94-46b2-99b0-f4e065bcbac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966088008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1966088008
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1186821131
Short name T642
Test name
Test status
Simulation time 3785482892 ps
CPU time 14.4 seconds
Started Aug 10 06:20:36 PM PDT 24
Finished Aug 10 06:20:50 PM PDT 24
Peak memory 241668 kb
Host smart-0f216e7c-7682-498a-8551-362cc34d1466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186821131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1186821131
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1660074589
Short name T616
Test name
Test status
Simulation time 62093110 ps
CPU time 2.29 seconds
Started Aug 10 06:20:38 PM PDT 24
Finished Aug 10 06:20:40 PM PDT 24
Peak memory 233468 kb
Host smart-db25aa2d-0020-4692-8be7-2561ea67350d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660074589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1660074589
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2831765946
Short name T948
Test name
Test status
Simulation time 1047884078 ps
CPU time 4.42 seconds
Started Aug 10 06:20:37 PM PDT 24
Finished Aug 10 06:20:41 PM PDT 24
Peak memory 219288 kb
Host smart-5f484f2f-4e8c-4c35-9a6c-29a8f142be84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2831765946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2831765946
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3250155914
Short name T1011
Test name
Test status
Simulation time 4311719880 ps
CPU time 7.56 seconds
Started Aug 10 06:20:36 PM PDT 24
Finished Aug 10 06:20:44 PM PDT 24
Peak memory 224412 kb
Host smart-75efe192-f5d8-4939-860f-41f6d6a06eae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250155914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3250155914
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1344804014
Short name T928
Test name
Test status
Simulation time 5674412928 ps
CPU time 14.8 seconds
Started Aug 10 06:20:36 PM PDT 24
Finished Aug 10 06:20:51 PM PDT 24
Peak memory 217084 kb
Host smart-802b5efc-7c5d-4335-8dc4-42a40f51aa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344804014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1344804014
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2213230577
Short name T966
Test name
Test status
Simulation time 1598307496 ps
CPU time 5.18 seconds
Started Aug 10 06:20:37 PM PDT 24
Finished Aug 10 06:20:43 PM PDT 24
Peak memory 217000 kb
Host smart-7c998b2c-9221-46da-a6a3-db25c4b4f97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213230577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2213230577
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.912047032
Short name T813
Test name
Test status
Simulation time 233362602 ps
CPU time 2.31 seconds
Started Aug 10 06:20:38 PM PDT 24
Finished Aug 10 06:20:40 PM PDT 24
Peak memory 216996 kb
Host smart-31c40e50-c1e5-41a8-8f43-67b004901192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912047032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.912047032
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.839388510
Short name T573
Test name
Test status
Simulation time 66587333 ps
CPU time 0.93 seconds
Started Aug 10 06:20:39 PM PDT 24
Finished Aug 10 06:20:40 PM PDT 24
Peak memory 206548 kb
Host smart-3910f110-8536-489d-a9ba-7dcb37728df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839388510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.839388510
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2116001642
Short name T134
Test name
Test status
Simulation time 269132214 ps
CPU time 2.36 seconds
Started Aug 10 06:20:38 PM PDT 24
Finished Aug 10 06:20:40 PM PDT 24
Peak memory 225272 kb
Host smart-bdc77406-3e6c-4841-b8bd-1945bbaedc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116001642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2116001642
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.961286927
Short name T744
Test name
Test status
Simulation time 21158147 ps
CPU time 0.69 seconds
Started Aug 10 06:20:38 PM PDT 24
Finished Aug 10 06:20:38 PM PDT 24
Peak memory 205856 kb
Host smart-e5663d42-25df-4636-b108-e39a4de8d878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961286927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.961286927
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.957998487
Short name T390
Test name
Test status
Simulation time 1493284124 ps
CPU time 2.77 seconds
Started Aug 10 06:20:35 PM PDT 24
Finished Aug 10 06:20:38 PM PDT 24
Peak memory 225272 kb
Host smart-f9e306b1-8b43-4eb2-a971-41773496aa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957998487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.957998487
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1187952171
Short name T580
Test name
Test status
Simulation time 27168245 ps
CPU time 0.8 seconds
Started Aug 10 06:20:37 PM PDT 24
Finished Aug 10 06:20:38 PM PDT 24
Peak memory 207068 kb
Host smart-7cae671d-f836-472e-b4e1-108a8c9777cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187952171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1187952171
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1819544113
Short name T195
Test name
Test status
Simulation time 172132151734 ps
CPU time 297.13 seconds
Started Aug 10 06:20:38 PM PDT 24
Finished Aug 10 06:25:35 PM PDT 24
Peak memory 257556 kb
Host smart-c07abe9a-de85-4909-a4d6-cd4a3c895ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819544113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1819544113
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1052014232
Short name T734
Test name
Test status
Simulation time 9185991771 ps
CPU time 76.19 seconds
Started Aug 10 06:20:40 PM PDT 24
Finished Aug 10 06:21:56 PM PDT 24
Peak memory 250024 kb
Host smart-01be5109-f257-4590-9b4d-3007b639f080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052014232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1052014232
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1810827630
Short name T139
Test name
Test status
Simulation time 6931195367 ps
CPU time 98.21 seconds
Started Aug 10 06:20:39 PM PDT 24
Finished Aug 10 06:22:17 PM PDT 24
Peak memory 265992 kb
Host smart-3406a911-4a7f-4442-b417-206efff68ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810827630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1810827630
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3004315737
Short name T618
Test name
Test status
Simulation time 691397525 ps
CPU time 12.17 seconds
Started Aug 10 06:20:35 PM PDT 24
Finished Aug 10 06:20:48 PM PDT 24
Peak memory 237664 kb
Host smart-07113d97-638c-424d-92f4-24dc5cde581a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004315737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3004315737
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1498386902
Short name T639
Test name
Test status
Simulation time 87265932 ps
CPU time 3.25 seconds
Started Aug 10 06:20:37 PM PDT 24
Finished Aug 10 06:20:40 PM PDT 24
Peak memory 225224 kb
Host smart-03740e81-51fa-4c3e-a68b-6de174dc696d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498386902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1498386902
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.913263075
Short name T457
Test name
Test status
Simulation time 1624839719 ps
CPU time 8 seconds
Started Aug 10 06:20:38 PM PDT 24
Finished Aug 10 06:20:47 PM PDT 24
Peak memory 225308 kb
Host smart-c0e9a92b-784b-4037-83ac-ee0f873119c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913263075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.913263075
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1148855704
Short name T113
Test name
Test status
Simulation time 2105369607 ps
CPU time 5.16 seconds
Started Aug 10 06:20:38 PM PDT 24
Finished Aug 10 06:20:43 PM PDT 24
Peak memory 233316 kb
Host smart-4e9f4882-4b33-4d21-8119-82d375ea2209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148855704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1148855704
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3808686416
Short name T1021
Test name
Test status
Simulation time 8556331205 ps
CPU time 12.12 seconds
Started Aug 10 06:20:36 PM PDT 24
Finished Aug 10 06:20:49 PM PDT 24
Peak memory 233500 kb
Host smart-8d0c2228-4cb6-48a0-8040-7cd372be75ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808686416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3808686416
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1170949848
Short name T152
Test name
Test status
Simulation time 1220778700 ps
CPU time 14.69 seconds
Started Aug 10 06:20:35 PM PDT 24
Finished Aug 10 06:20:50 PM PDT 24
Peak memory 222888 kb
Host smart-84d5e603-2036-467f-999e-ee549d0bb6e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1170949848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1170949848
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4279246564
Short name T716
Test name
Test status
Simulation time 57213390 ps
CPU time 1.15 seconds
Started Aug 10 06:20:37 PM PDT 24
Finished Aug 10 06:20:39 PM PDT 24
Peak memory 207604 kb
Host smart-7f990b7f-78dc-4766-843d-3bb6ee573db3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279246564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4279246564
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.452435189
Short name T456
Test name
Test status
Simulation time 2743032065 ps
CPU time 19.47 seconds
Started Aug 10 06:20:35 PM PDT 24
Finished Aug 10 06:20:55 PM PDT 24
Peak memory 216980 kb
Host smart-2a5d5348-2eb6-4d3d-8941-364c95bc6c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452435189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.452435189
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3755480447
Short name T865
Test name
Test status
Simulation time 5285901745 ps
CPU time 2.29 seconds
Started Aug 10 06:20:35 PM PDT 24
Finished Aug 10 06:20:38 PM PDT 24
Peak memory 208784 kb
Host smart-47ec3539-b5ee-4310-973c-b2bdc73ed1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755480447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3755480447
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4105711704
Short name T1008
Test name
Test status
Simulation time 1229862622 ps
CPU time 3.3 seconds
Started Aug 10 06:20:38 PM PDT 24
Finished Aug 10 06:20:41 PM PDT 24
Peak memory 217056 kb
Host smart-b6f4f797-949a-4c45-be47-58a9f902b87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105711704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4105711704
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4094357654
Short name T502
Test name
Test status
Simulation time 32392775 ps
CPU time 0.87 seconds
Started Aug 10 06:20:36 PM PDT 24
Finished Aug 10 06:20:37 PM PDT 24
Peak memory 206608 kb
Host smart-b10410d3-2093-4194-b801-71ec3d3ba274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094357654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4094357654
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2073462000
Short name T204
Test name
Test status
Simulation time 7416002930 ps
CPU time 13.26 seconds
Started Aug 10 06:20:35 PM PDT 24
Finished Aug 10 06:20:49 PM PDT 24
Peak memory 233428 kb
Host smart-d7a1e77c-3bd0-4746-9bc7-11b2a1c08b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073462000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2073462000
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.726566802
Short name T751
Test name
Test status
Simulation time 43289666 ps
CPU time 0.77 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:20:54 PM PDT 24
Peak memory 206220 kb
Host smart-f40d801b-c50c-42ed-a03e-d436b1272c63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726566802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.726566802
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2742593211
Short name T863
Test name
Test status
Simulation time 2497439024 ps
CPU time 11.92 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:21:03 PM PDT 24
Peak memory 225288 kb
Host smart-67f25553-747b-4420-8ead-1ebd19090e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742593211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2742593211
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2066322800
Short name T598
Test name
Test status
Simulation time 41271970 ps
CPU time 0.85 seconds
Started Aug 10 06:20:36 PM PDT 24
Finished Aug 10 06:20:37 PM PDT 24
Peak memory 207032 kb
Host smart-e6ad5ea1-02fc-4539-a8ff-af755c25d3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066322800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2066322800
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1047054333
Short name T266
Test name
Test status
Simulation time 11708902339 ps
CPU time 79.17 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:22:14 PM PDT 24
Peak memory 274380 kb
Host smart-44643e70-7bf3-4a24-bc65-a1133491413b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047054333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1047054333
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2632089545
Short name T269
Test name
Test status
Simulation time 11388172124 ps
CPU time 70.99 seconds
Started Aug 10 06:20:52 PM PDT 24
Finished Aug 10 06:22:03 PM PDT 24
Peak memory 257228 kb
Host smart-46efa0dc-7e8f-47a6-a29a-467f7d7d75b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632089545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2632089545
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.327786567
Short name T298
Test name
Test status
Simulation time 1932917653 ps
CPU time 45.84 seconds
Started Aug 10 06:20:50 PM PDT 24
Finished Aug 10 06:21:36 PM PDT 24
Peak memory 254408 kb
Host smart-64dd4d70-f19d-4d4c-aeb8-b41873780a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327786567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.327786567
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.4005947505
Short name T463
Test name
Test status
Simulation time 196372179 ps
CPU time 5.01 seconds
Started Aug 10 06:20:52 PM PDT 24
Finished Aug 10 06:20:57 PM PDT 24
Peak memory 225208 kb
Host smart-b36355a3-8ab2-40a7-a359-a72ea50eac29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005947505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4005947505
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3107930351
Short name T804
Test name
Test status
Simulation time 6585420368 ps
CPU time 34.93 seconds
Started Aug 10 06:20:53 PM PDT 24
Finished Aug 10 06:21:28 PM PDT 24
Peak memory 240632 kb
Host smart-83028896-84a0-42ef-8b5d-66c021274970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107930351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3107930351
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.514148224
Short name T683
Test name
Test status
Simulation time 113905949 ps
CPU time 4.58 seconds
Started Aug 10 06:20:52 PM PDT 24
Finished Aug 10 06:20:56 PM PDT 24
Peak memory 230356 kb
Host smart-970954df-183b-4e2e-884d-a27a6d128a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514148224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.514148224
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.890231277
Short name T499
Test name
Test status
Simulation time 2020849475 ps
CPU time 10.26 seconds
Started Aug 10 06:20:49 PM PDT 24
Finished Aug 10 06:20:59 PM PDT 24
Peak memory 233408 kb
Host smart-4c4f4205-4e67-4e6e-8e3c-712b1c183168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890231277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.890231277
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.383606393
Short name T705
Test name
Test status
Simulation time 5212611431 ps
CPU time 10.03 seconds
Started Aug 10 06:20:50 PM PDT 24
Finished Aug 10 06:21:00 PM PDT 24
Peak memory 225296 kb
Host smart-f66113d0-db67-4881-9a94-07c2865508ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383606393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.383606393
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1814406437
Short name T926
Test name
Test status
Simulation time 1591779442 ps
CPU time 9.89 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:21:04 PM PDT 24
Peak memory 225228 kb
Host smart-14bea30f-bb34-4191-a517-e142840ffe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814406437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1814406437
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3847108013
Short name T888
Test name
Test status
Simulation time 323896848 ps
CPU time 3.61 seconds
Started Aug 10 06:20:49 PM PDT 24
Finished Aug 10 06:20:53 PM PDT 24
Peak memory 220836 kb
Host smart-774fe97e-c672-4585-ad38-0fabb5971e96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3847108013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3847108013
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1912597681
Short name T971
Test name
Test status
Simulation time 143083688 ps
CPU time 1.17 seconds
Started Aug 10 06:20:50 PM PDT 24
Finished Aug 10 06:20:52 PM PDT 24
Peak memory 208280 kb
Host smart-e4a610db-a8e8-43e8-9b23-c77c21d1ecf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912597681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1912597681
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.207519408
Short name T955
Test name
Test status
Simulation time 6633291664 ps
CPU time 32.28 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:21:23 PM PDT 24
Peak memory 217020 kb
Host smart-3a80ecae-31c1-4e5c-b63e-ae914df95383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207519408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.207519408
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.874091442
Short name T1016
Test name
Test status
Simulation time 1259627340 ps
CPU time 7.12 seconds
Started Aug 10 06:20:40 PM PDT 24
Finished Aug 10 06:20:48 PM PDT 24
Peak memory 216984 kb
Host smart-91f93441-5d2a-45d0-99c6-ad4ef05ee236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874091442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.874091442
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3036599253
Short name T555
Test name
Test status
Simulation time 44186772 ps
CPU time 0.69 seconds
Started Aug 10 06:20:49 PM PDT 24
Finished Aug 10 06:20:49 PM PDT 24
Peak memory 206112 kb
Host smart-281431e6-cac0-4dd4-90c5-1d2918bd7e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036599253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3036599253
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.822246875
Short name T438
Test name
Test status
Simulation time 145043115 ps
CPU time 0.92 seconds
Started Aug 10 06:20:50 PM PDT 24
Finished Aug 10 06:20:51 PM PDT 24
Peak memory 207620 kb
Host smart-bf36ce68-99d1-4549-bb9b-21254f86b551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822246875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.822246875
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2630754949
Short name T719
Test name
Test status
Simulation time 13247983157 ps
CPU time 13.18 seconds
Started Aug 10 06:20:55 PM PDT 24
Finished Aug 10 06:21:09 PM PDT 24
Peak memory 225280 kb
Host smart-2ab6ac81-bdc7-4862-a0da-a5a5bd2b9610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630754949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2630754949
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3233458181
Short name T646
Test name
Test status
Simulation time 25218521 ps
CPU time 0.76 seconds
Started Aug 10 06:20:55 PM PDT 24
Finished Aug 10 06:20:56 PM PDT 24
Peak memory 206252 kb
Host smart-c441c6eb-b3cf-47b2-b6f3-1a1b6a7cdb8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233458181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3233458181
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1519067562
Short name T312
Test name
Test status
Simulation time 4863071286 ps
CPU time 19.12 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:21:11 PM PDT 24
Peak memory 233480 kb
Host smart-3bea2852-6617-40af-9529-a546ca4d63f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519067562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1519067562
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3466133735
Short name T415
Test name
Test status
Simulation time 97081808 ps
CPU time 0.78 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:20:52 PM PDT 24
Peak memory 207048 kb
Host smart-ce4ee97b-d45d-4479-96b6-fe73c5f9d167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466133735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3466133735
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2626483972
Short name T78
Test name
Test status
Simulation time 36335956574 ps
CPU time 100.4 seconds
Started Aug 10 06:20:57 PM PDT 24
Finished Aug 10 06:22:38 PM PDT 24
Peak memory 255296 kb
Host smart-3dabb5c0-244c-412e-97d2-ce7b6af4ba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626483972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2626483972
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1387118377
Short name T317
Test name
Test status
Simulation time 1829476570 ps
CPU time 47.45 seconds
Started Aug 10 06:20:49 PM PDT 24
Finished Aug 10 06:21:36 PM PDT 24
Peak memory 249936 kb
Host smart-7a544ae8-b3e6-4f88-809d-0efab26b07c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387118377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1387118377
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3336706025
Short name T268
Test name
Test status
Simulation time 146377488098 ps
CPU time 362.73 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:26:53 PM PDT 24
Peak memory 258016 kb
Host smart-b346a786-6c2d-41ab-9165-22648eeccaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336706025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3336706025
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3219136003
Short name T612
Test name
Test status
Simulation time 457229755 ps
CPU time 5.17 seconds
Started Aug 10 06:20:49 PM PDT 24
Finished Aug 10 06:20:54 PM PDT 24
Peak memory 233424 kb
Host smart-f49074ee-c2b5-45dd-b81c-7290a5192e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219136003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3219136003
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.590648346
Short name T313
Test name
Test status
Simulation time 56627309478 ps
CPU time 426.47 seconds
Started Aug 10 06:20:55 PM PDT 24
Finished Aug 10 06:28:02 PM PDT 24
Peak memory 253108 kb
Host smart-51687cbd-a045-43e1-bc9e-86aef2657984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590648346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.590648346
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2563476620
Short name T951
Test name
Test status
Simulation time 193832475 ps
CPU time 5.75 seconds
Started Aug 10 06:20:52 PM PDT 24
Finished Aug 10 06:20:58 PM PDT 24
Peak memory 233476 kb
Host smart-e636de03-da56-425e-afb7-4e1ebf725c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563476620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2563476620
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4194272232
Short name T774
Test name
Test status
Simulation time 11313421279 ps
CPU time 23.87 seconds
Started Aug 10 06:20:53 PM PDT 24
Finished Aug 10 06:21:17 PM PDT 24
Peak memory 233332 kb
Host smart-823fe223-7f9b-4c55-9c84-9013c1774710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194272232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4194272232
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2864539122
Short name T553
Test name
Test status
Simulation time 6566042116 ps
CPU time 18.2 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:21:09 PM PDT 24
Peak memory 249412 kb
Host smart-04f43b4e-e313-4b7c-aebb-e97103103020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864539122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2864539122
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3920079560
Short name T935
Test name
Test status
Simulation time 33016901 ps
CPU time 2.54 seconds
Started Aug 10 06:20:52 PM PDT 24
Finished Aug 10 06:20:54 PM PDT 24
Peak memory 233064 kb
Host smart-d884f28e-e4d9-4617-855c-411f98e8d3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920079560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3920079560
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1851952540
Short name T525
Test name
Test status
Simulation time 585484705 ps
CPU time 6.13 seconds
Started Aug 10 06:20:53 PM PDT 24
Finished Aug 10 06:20:59 PM PDT 24
Peak memory 219340 kb
Host smart-da100275-b4bf-437e-8da8-a2706fce953e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1851952540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1851952540
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3801717323
Short name T812
Test name
Test status
Simulation time 196746282 ps
CPU time 1.01 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:20:52 PM PDT 24
Peak memory 208312 kb
Host smart-145d4625-74e0-4731-abd9-6e7dfdfc60a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801717323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3801717323
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.146219592
Short name T367
Test name
Test status
Simulation time 481853220 ps
CPU time 2.49 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:20:54 PM PDT 24
Peak memory 217164 kb
Host smart-8851d01a-3630-4472-ae40-d21378d6b4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146219592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.146219592
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1096467230
Short name T663
Test name
Test status
Simulation time 2011915804 ps
CPU time 6.42 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:20:57 PM PDT 24
Peak memory 216992 kb
Host smart-946187d3-81a3-4ea8-9108-139054a761c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096467230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1096467230
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3107524005
Short name T365
Test name
Test status
Simulation time 40223745 ps
CPU time 1.1 seconds
Started Aug 10 06:20:50 PM PDT 24
Finished Aug 10 06:20:51 PM PDT 24
Peak memory 208576 kb
Host smart-dbb9663f-cbd5-4201-878a-c91b7765c4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107524005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3107524005
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2139110756
Short name T644
Test name
Test status
Simulation time 77950112 ps
CPU time 0.97 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:20:52 PM PDT 24
Peak memory 207620 kb
Host smart-42c69a7f-4e4a-4d14-beba-4d062e70dd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139110756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2139110756
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3529255859
Short name T349
Test name
Test status
Simulation time 297868937 ps
CPU time 2.71 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:20:54 PM PDT 24
Peak memory 233112 kb
Host smart-bbf5e98a-5099-404e-92c2-57cb1951513b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529255859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3529255859
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2810438803
Short name T506
Test name
Test status
Simulation time 78092712 ps
CPU time 0.71 seconds
Started Aug 10 06:20:48 PM PDT 24
Finished Aug 10 06:20:49 PM PDT 24
Peak memory 206188 kb
Host smart-e5974c5d-5988-4849-837b-85c6832d1f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810438803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2810438803
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4223120878
Short name T992
Test name
Test status
Simulation time 33679822 ps
CPU time 2.22 seconds
Started Aug 10 06:20:53 PM PDT 24
Finished Aug 10 06:20:56 PM PDT 24
Peak memory 233360 kb
Host smart-4afa4520-218a-4577-8063-6abb0f1076fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223120878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4223120878
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.364472964
Short name T797
Test name
Test status
Simulation time 24385567 ps
CPU time 0.74 seconds
Started Aug 10 06:20:52 PM PDT 24
Finished Aug 10 06:20:52 PM PDT 24
Peak memory 206044 kb
Host smart-73e30f39-eb22-4db7-870e-a785c801b6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364472964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.364472964
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.4263450305
Short name T750
Test name
Test status
Simulation time 3258948714 ps
CPU time 43.39 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:21:34 PM PDT 24
Peak memory 253784 kb
Host smart-38bb0195-2119-4faa-8bc1-9d44926b5fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263450305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4263450305
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.984929872
Short name T895
Test name
Test status
Simulation time 10872715778 ps
CPU time 47.21 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:21:42 PM PDT 24
Peak memory 241724 kb
Host smart-0c171fcc-c6d9-44da-b5f1-0bf6f145ed07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984929872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.984929872
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2071596310
Short name T246
Test name
Test status
Simulation time 27318083618 ps
CPU time 34.36 seconds
Started Aug 10 06:20:52 PM PDT 24
Finished Aug 10 06:21:27 PM PDT 24
Peak memory 225328 kb
Host smart-ee9abd49-ab1d-45e5-8345-9e221f7c4b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071596310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2071596310
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2364568570
Short name T894
Test name
Test status
Simulation time 941047537 ps
CPU time 20.62 seconds
Started Aug 10 06:20:50 PM PDT 24
Finished Aug 10 06:21:11 PM PDT 24
Peak memory 249856 kb
Host smart-458eb834-dc45-4c8b-921e-19ea40dced08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364568570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2364568570
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3662113878
Short name T909
Test name
Test status
Simulation time 66226204155 ps
CPU time 231.87 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:24:46 PM PDT 24
Peak memory 251340 kb
Host smart-1a5a5f95-ff9c-4d77-ba9f-8870ce833c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662113878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3662113878
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3535773818
Short name T412
Test name
Test status
Simulation time 417057635 ps
CPU time 2.54 seconds
Started Aug 10 06:20:53 PM PDT 24
Finished Aug 10 06:20:56 PM PDT 24
Peak memory 233048 kb
Host smart-6f7da82c-bbe1-46c8-8e90-e935a594f12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535773818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3535773818
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1091265475
Short name T74
Test name
Test status
Simulation time 352576121 ps
CPU time 5.81 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:20:57 PM PDT 24
Peak memory 233424 kb
Host smart-90585ed4-e08d-4ffd-9b49-0c471634a94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091265475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1091265475
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.872152960
Short name T1025
Test name
Test status
Simulation time 12951231851 ps
CPU time 33.43 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:21:24 PM PDT 24
Peak memory 233488 kb
Host smart-c63233a5-5c05-4b24-90d6-4384fe5ee801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872152960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.872152960
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1068925244
Short name T1023
Test name
Test status
Simulation time 15186092846 ps
CPU time 13.6 seconds
Started Aug 10 06:20:55 PM PDT 24
Finished Aug 10 06:21:08 PM PDT 24
Peak memory 233528 kb
Host smart-2a90b218-a728-42ea-8565-0fe7266ccff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068925244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1068925244
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.4193957807
Short name T799
Test name
Test status
Simulation time 4425899294 ps
CPU time 10.22 seconds
Started Aug 10 06:20:49 PM PDT 24
Finished Aug 10 06:20:59 PM PDT 24
Peak memory 222412 kb
Host smart-0ecdbf6a-ce07-48f9-8788-2a8099387cf6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4193957807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.4193957807
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1226438433
Short name T293
Test name
Test status
Simulation time 1751728529 ps
CPU time 32.83 seconds
Started Aug 10 06:20:55 PM PDT 24
Finished Aug 10 06:21:28 PM PDT 24
Peak memory 241684 kb
Host smart-03686cc3-d865-4c8d-8caf-e5a8b97d0229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226438433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1226438433
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2134230770
Short name T441
Test name
Test status
Simulation time 15684368622 ps
CPU time 24.43 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:21:19 PM PDT 24
Peak memory 220660 kb
Host smart-84f5b2c4-1e52-4f42-9355-4b5220a2b9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134230770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2134230770
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1612728231
Short name T381
Test name
Test status
Simulation time 2695384707 ps
CPU time 2.1 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:20:56 PM PDT 24
Peak memory 207856 kb
Host smart-12aa6211-76cb-489a-b503-f9092b56858e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612728231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1612728231
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1470788633
Short name T707
Test name
Test status
Simulation time 198302872 ps
CPU time 1.15 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:20:56 PM PDT 24
Peak memory 208292 kb
Host smart-a7efa73d-ba53-456a-81ba-3c3ebf7c789f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470788633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1470788633
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.4133965392
Short name T730
Test name
Test status
Simulation time 70387022 ps
CPU time 0.76 seconds
Started Aug 10 06:20:55 PM PDT 24
Finished Aug 10 06:20:56 PM PDT 24
Peak memory 206560 kb
Host smart-09436e89-5afa-4ae1-980c-e7eab3123fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133965392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4133965392
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.646304025
Short name T131
Test name
Test status
Simulation time 3317818738 ps
CPU time 15.86 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:21:07 PM PDT 24
Peak memory 241772 kb
Host smart-94464978-3f5b-4c3d-967c-cf5dff3e25c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646304025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.646304025
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3718615016
Short name T350
Test name
Test status
Simulation time 33824673 ps
CPU time 0.79 seconds
Started Aug 10 06:20:55 PM PDT 24
Finished Aug 10 06:20:55 PM PDT 24
Peak memory 205276 kb
Host smart-bcac67c8-4a2a-47ee-bd9f-8f75fb291671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718615016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3718615016
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2118130034
Short name T779
Test name
Test status
Simulation time 1527846963 ps
CPU time 12.95 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:21:04 PM PDT 24
Peak memory 233436 kb
Host smart-67ae1b5c-268f-4a41-b155-780db5662063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118130034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2118130034
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3946055872
Short name T590
Test name
Test status
Simulation time 52200113 ps
CPU time 0.77 seconds
Started Aug 10 06:20:53 PM PDT 24
Finished Aug 10 06:20:53 PM PDT 24
Peak memory 206024 kb
Host smart-726a3475-d365-41d5-b995-36ba8f3b799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946055872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3946055872
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2965071477
Short name T168
Test name
Test status
Simulation time 5428543771 ps
CPU time 50.02 seconds
Started Aug 10 06:20:52 PM PDT 24
Finished Aug 10 06:21:42 PM PDT 24
Peak memory 257572 kb
Host smart-2cfc507e-43fa-45d2-b106-f9e1f6a28f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965071477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2965071477
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2974324517
Short name T294
Test name
Test status
Simulation time 16479526547 ps
CPU time 182.85 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:23:57 PM PDT 24
Peak memory 255496 kb
Host smart-37cfa1ad-a4e1-4fc5-acc3-6f028e050d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974324517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2974324517
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3069920969
Short name T1002
Test name
Test status
Simulation time 119278857443 ps
CPU time 190.2 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:24:01 PM PDT 24
Peak memory 251632 kb
Host smart-e02846f9-f157-4a21-9238-56ecf7c707ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069920969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3069920969
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1685526177
Short name T1000
Test name
Test status
Simulation time 186778819 ps
CPU time 5.9 seconds
Started Aug 10 06:20:53 PM PDT 24
Finished Aug 10 06:20:59 PM PDT 24
Peak memory 237656 kb
Host smart-8c90cf4d-d40c-4519-a17e-617a19157d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685526177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1685526177
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1920053229
Short name T225
Test name
Test status
Simulation time 280341883232 ps
CPU time 172.29 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:23:43 PM PDT 24
Peak memory 253720 kb
Host smart-395ed1b0-7df4-44a2-a32e-5608f9cab851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920053229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1920053229
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3336292265
Short name T929
Test name
Test status
Simulation time 28166192 ps
CPU time 1.91 seconds
Started Aug 10 06:20:50 PM PDT 24
Finished Aug 10 06:20:53 PM PDT 24
Peak memory 223688 kb
Host smart-910513f1-09a3-42db-a328-a2a349f4bfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336292265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3336292265
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1215337000
Short name T824
Test name
Test status
Simulation time 4869068235 ps
CPU time 10.88 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:21:05 PM PDT 24
Peak memory 233540 kb
Host smart-c85a31eb-8b22-4deb-be24-8721566ee563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215337000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1215337000
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.102872666
Short name T578
Test name
Test status
Simulation time 16218456806 ps
CPU time 18.6 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:21:13 PM PDT 24
Peak memory 233536 kb
Host smart-5dfd2da6-5f93-4251-9aa3-9ee68595d9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102872666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.102872666
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.335086987
Short name T765
Test name
Test status
Simulation time 15160517317 ps
CPU time 18.1 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:21:09 PM PDT 24
Peak memory 249948 kb
Host smart-3e8d1c10-2986-4e07-b1b1-8608d1919c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335086987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.335086987
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3361354719
Short name T1029
Test name
Test status
Simulation time 321280118 ps
CPU time 3.66 seconds
Started Aug 10 06:20:51 PM PDT 24
Finished Aug 10 06:20:55 PM PDT 24
Peak memory 223564 kb
Host smart-b4f9f5d9-7d15-49f0-bdf4-8a9af2f163a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3361354719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3361354719
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1886311348
Short name T31
Test name
Test status
Simulation time 104811905 ps
CPU time 1.01 seconds
Started Aug 10 06:20:53 PM PDT 24
Finished Aug 10 06:20:54 PM PDT 24
Peak memory 207412 kb
Host smart-28df82a1-ba2f-46da-ab35-5bc3926007fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886311348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1886311348
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3512871072
Short name T936
Test name
Test status
Simulation time 1102994014 ps
CPU time 9.22 seconds
Started Aug 10 06:20:50 PM PDT 24
Finished Aug 10 06:20:59 PM PDT 24
Peak memory 219864 kb
Host smart-c37a28b9-193e-4972-94cc-99710597c1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512871072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3512871072
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1131513932
Short name T938
Test name
Test status
Simulation time 1382913327 ps
CPU time 3.96 seconds
Started Aug 10 06:20:55 PM PDT 24
Finished Aug 10 06:20:59 PM PDT 24
Peak memory 216996 kb
Host smart-7155612b-1e65-4cff-81da-219825e7d2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131513932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1131513932
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3093800123
Short name T998
Test name
Test status
Simulation time 25794664 ps
CPU time 1.05 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:20:55 PM PDT 24
Peak memory 208020 kb
Host smart-42cb3b86-0502-430c-976e-34e782fbac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093800123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3093800123
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2897646727
Short name T852
Test name
Test status
Simulation time 10983915 ps
CPU time 0.73 seconds
Started Aug 10 06:20:55 PM PDT 24
Finished Aug 10 06:20:56 PM PDT 24
Peak memory 206152 kb
Host smart-8646ed25-d96a-4e5c-be56-6d65d45e7c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897646727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2897646727
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3157911099
Short name T206
Test name
Test status
Simulation time 312788949 ps
CPU time 4.06 seconds
Started Aug 10 06:20:53 PM PDT 24
Finished Aug 10 06:20:57 PM PDT 24
Peak memory 225152 kb
Host smart-7ee436fc-5208-4c0e-adc9-0a78528cefd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157911099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3157911099
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2570254343
Short name T788
Test name
Test status
Simulation time 16283044 ps
CPU time 0.73 seconds
Started Aug 10 06:21:00 PM PDT 24
Finished Aug 10 06:21:01 PM PDT 24
Peak memory 205268 kb
Host smart-86983d10-3c29-4737-8b4b-f28bf34b1921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570254343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2570254343
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.534105953
Short name T77
Test name
Test status
Simulation time 60419391 ps
CPU time 2.62 seconds
Started Aug 10 06:21:03 PM PDT 24
Finished Aug 10 06:21:06 PM PDT 24
Peak memory 225244 kb
Host smart-d6b59359-a9dc-4364-a194-ddbedc398bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534105953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.534105953
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2308145052
Short name T492
Test name
Test status
Simulation time 38482766 ps
CPU time 0.75 seconds
Started Aug 10 06:20:58 PM PDT 24
Finished Aug 10 06:20:59 PM PDT 24
Peak memory 205972 kb
Host smart-80851112-6b9f-4311-9d6d-c778223b1bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308145052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2308145052
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1015653368
Short name T925
Test name
Test status
Simulation time 58502560779 ps
CPU time 197.43 seconds
Started Aug 10 06:21:02 PM PDT 24
Finished Aug 10 06:24:20 PM PDT 24
Peak memory 249856 kb
Host smart-597089ea-d706-4a41-8dbe-2f1c10f10733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015653368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1015653368
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3431027948
Short name T333
Test name
Test status
Simulation time 3984210866 ps
CPU time 81.38 seconds
Started Aug 10 06:21:01 PM PDT 24
Finished Aug 10 06:22:22 PM PDT 24
Peak memory 252456 kb
Host smart-427085c6-c1d5-4de5-b18d-efeaf787f24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431027948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3431027948
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.722121986
Short name T284
Test name
Test status
Simulation time 21111387760 ps
CPU time 39.82 seconds
Started Aug 10 06:21:01 PM PDT 24
Finished Aug 10 06:21:41 PM PDT 24
Peak memory 250092 kb
Host smart-1bbe6e65-1e5a-4839-93e6-5887be6a98cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722121986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.722121986
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2627958024
Short name T147
Test name
Test status
Simulation time 4235092171 ps
CPU time 13.57 seconds
Started Aug 10 06:21:02 PM PDT 24
Finished Aug 10 06:21:16 PM PDT 24
Peak memory 225324 kb
Host smart-80c5d71d-8dbb-4246-8aa6-831798119c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627958024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2627958024
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1574352699
Short name T874
Test name
Test status
Simulation time 1695434792 ps
CPU time 37.93 seconds
Started Aug 10 06:21:03 PM PDT 24
Finished Aug 10 06:21:41 PM PDT 24
Peak memory 250428 kb
Host smart-860e1ea4-bbf6-4fd6-addf-fe1fe74894e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574352699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1574352699
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.628621967
Short name T632
Test name
Test status
Simulation time 5193758108 ps
CPU time 12.99 seconds
Started Aug 10 06:20:58 PM PDT 24
Finished Aug 10 06:21:11 PM PDT 24
Peak memory 225280 kb
Host smart-4f4d50bf-e618-4593-b7c0-6a68f506a826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628621967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.628621967
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.868253929
Short name T135
Test name
Test status
Simulation time 20185133029 ps
CPU time 57.95 seconds
Started Aug 10 06:21:02 PM PDT 24
Finished Aug 10 06:22:00 PM PDT 24
Peak memory 241520 kb
Host smart-78837ba5-afea-4695-8974-7b26252cf227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868253929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.868253929
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.264529388
Short name T780
Test name
Test status
Simulation time 1328038562 ps
CPU time 3.12 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:20:58 PM PDT 24
Peak memory 225176 kb
Host smart-e02fcfb5-a8fa-48b5-bdc9-91f2a8cd1266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264529388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.264529388
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.252543477
Short name T304
Test name
Test status
Simulation time 914256356 ps
CPU time 10.01 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:21:04 PM PDT 24
Peak memory 236756 kb
Host smart-cefcb52f-c2f4-40ca-b98b-a4ed6684e717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252543477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.252543477
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3537464237
Short name T581
Test name
Test status
Simulation time 168521491 ps
CPU time 3.75 seconds
Started Aug 10 06:21:14 PM PDT 24
Finished Aug 10 06:21:17 PM PDT 24
Peak memory 219452 kb
Host smart-3cad8179-b26b-4e0b-8c5a-048a434da27d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3537464237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3537464237
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2778065647
Short name T339
Test name
Test status
Simulation time 8056987219 ps
CPU time 42.55 seconds
Started Aug 10 06:20:56 PM PDT 24
Finished Aug 10 06:21:39 PM PDT 24
Peak memory 216964 kb
Host smart-c548916c-1749-4646-b1e0-b48edd0a3212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778065647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2778065647
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3591149810
Short name T984
Test name
Test status
Simulation time 138213794015 ps
CPU time 19.57 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:21:14 PM PDT 24
Peak memory 216724 kb
Host smart-f635e701-96f6-472b-8e07-3b9190e945be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591149810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3591149810
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1747039197
Short name T736
Test name
Test status
Simulation time 118792686 ps
CPU time 1.98 seconds
Started Aug 10 06:20:54 PM PDT 24
Finished Aug 10 06:20:56 PM PDT 24
Peak memory 216956 kb
Host smart-de33ab6b-7ad6-411a-b94b-4029473b5cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747039197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1747039197
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2305318240
Short name T862
Test name
Test status
Simulation time 57369817 ps
CPU time 0.82 seconds
Started Aug 10 06:20:58 PM PDT 24
Finished Aug 10 06:20:58 PM PDT 24
Peak memory 206520 kb
Host smart-4ea43c87-19ae-4889-af41-61732d46053d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305318240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2305318240
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2297641803
Short name T978
Test name
Test status
Simulation time 605152353 ps
CPU time 3.99 seconds
Started Aug 10 06:21:09 PM PDT 24
Finished Aug 10 06:21:13 PM PDT 24
Peak memory 233436 kb
Host smart-6ea8e7d2-e13e-4e40-9106-f02d7d9c72f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297641803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2297641803
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1298138768
Short name T6
Test name
Test status
Simulation time 127903713 ps
CPU time 0.72 seconds
Started Aug 10 06:21:00 PM PDT 24
Finished Aug 10 06:21:01 PM PDT 24
Peak memory 205820 kb
Host smart-d28fdd00-61ff-4ff0-a275-b838cce2493a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298138768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1298138768
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3388875908
Short name T782
Test name
Test status
Simulation time 2306581466 ps
CPU time 4.08 seconds
Started Aug 10 06:21:00 PM PDT 24
Finished Aug 10 06:21:04 PM PDT 24
Peak memory 225292 kb
Host smart-f2242722-caf9-4ec8-9b24-80181eb2ee84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388875908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3388875908
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3489596896
Short name T1013
Test name
Test status
Simulation time 18867037 ps
CPU time 0.79 seconds
Started Aug 10 06:21:01 PM PDT 24
Finished Aug 10 06:21:01 PM PDT 24
Peak memory 207048 kb
Host smart-1051c9e3-7a91-402f-9391-8ffd5d1fad9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489596896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3489596896
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2588274192
Short name T546
Test name
Test status
Simulation time 19582732 ps
CPU time 0.75 seconds
Started Aug 10 06:21:01 PM PDT 24
Finished Aug 10 06:21:02 PM PDT 24
Peak memory 216528 kb
Host smart-639482c5-dc54-457f-9a56-2e6f1e3a7e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588274192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2588274192
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2052772770
Short name T964
Test name
Test status
Simulation time 328845633984 ps
CPU time 594.4 seconds
Started Aug 10 06:21:14 PM PDT 24
Finished Aug 10 06:31:08 PM PDT 24
Peak memory 261576 kb
Host smart-63bb787d-2ea4-407a-818e-ef2e5c4bc08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052772770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2052772770
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1832440593
Short name T185
Test name
Test status
Simulation time 9948800194 ps
CPU time 48.06 seconds
Started Aug 10 06:21:03 PM PDT 24
Finished Aug 10 06:21:51 PM PDT 24
Peak memory 258044 kb
Host smart-d23b9155-496e-42f9-b36a-fac8c512d742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832440593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1832440593
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.884066255
Short name T379
Test name
Test status
Simulation time 2152695808 ps
CPU time 21.42 seconds
Started Aug 10 06:21:01 PM PDT 24
Finished Aug 10 06:21:22 PM PDT 24
Peak memory 240044 kb
Host smart-f96b2af2-1917-4117-9839-1fe1763ce564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884066255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.884066255
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1612927348
Short name T425
Test name
Test status
Simulation time 1608616637 ps
CPU time 24.06 seconds
Started Aug 10 06:21:02 PM PDT 24
Finished Aug 10 06:21:27 PM PDT 24
Peak memory 250072 kb
Host smart-5c1c6d83-02af-459c-abed-3a443e3605eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612927348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1612927348
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.4040923099
Short name T968
Test name
Test status
Simulation time 3117830222 ps
CPU time 9.33 seconds
Started Aug 10 06:21:03 PM PDT 24
Finished Aug 10 06:21:13 PM PDT 24
Peak memory 225332 kb
Host smart-3c20e515-9967-4311-b633-673397639310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040923099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4040923099
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.998251920
Short name T939
Test name
Test status
Simulation time 19562308130 ps
CPU time 41.07 seconds
Started Aug 10 06:21:05 PM PDT 24
Finished Aug 10 06:21:46 PM PDT 24
Peak memory 233460 kb
Host smart-ba0648e9-751a-443a-9151-ba0e9aeb3188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998251920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.998251920
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3292252449
Short name T783
Test name
Test status
Simulation time 9386990055 ps
CPU time 12.45 seconds
Started Aug 10 06:21:02 PM PDT 24
Finished Aug 10 06:21:15 PM PDT 24
Peak memory 225340 kb
Host smart-df404d8c-398b-421d-9f49-1e68e0126a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292252449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3292252449
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.205999000
Short name T534
Test name
Test status
Simulation time 2920083481 ps
CPU time 10.53 seconds
Started Aug 10 06:21:00 PM PDT 24
Finished Aug 10 06:21:11 PM PDT 24
Peak memory 225360 kb
Host smart-be7a21ca-de38-4f67-85e5-ce9416620b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205999000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.205999000
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.348034563
Short name T976
Test name
Test status
Simulation time 525428739 ps
CPU time 6.16 seconds
Started Aug 10 06:21:01 PM PDT 24
Finished Aug 10 06:21:07 PM PDT 24
Peak memory 222956 kb
Host smart-5cb57e00-0005-4e9e-96f0-f2af6ff938b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=348034563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.348034563
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2357966089
Short name T808
Test name
Test status
Simulation time 279438603 ps
CPU time 1 seconds
Started Aug 10 06:21:01 PM PDT 24
Finished Aug 10 06:21:02 PM PDT 24
Peak memory 208068 kb
Host smart-9606cf90-87af-4ef7-afc8-b1ff72506d37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357966089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2357966089
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.406584401
Short name T330
Test name
Test status
Simulation time 5201322517 ps
CPU time 14.11 seconds
Started Aug 10 06:21:03 PM PDT 24
Finished Aug 10 06:21:17 PM PDT 24
Peak memory 217008 kb
Host smart-b45b0363-589e-40c2-a2eb-fa8cba0496b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406584401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.406584401
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2129982609
Short name T860
Test name
Test status
Simulation time 15893672976 ps
CPU time 8.88 seconds
Started Aug 10 06:21:13 PM PDT 24
Finished Aug 10 06:21:21 PM PDT 24
Peak memory 217088 kb
Host smart-638655f4-4acb-46fc-b147-38a81263c298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129982609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2129982609
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1539609082
Short name T471
Test name
Test status
Simulation time 24213944 ps
CPU time 0.81 seconds
Started Aug 10 06:21:03 PM PDT 24
Finished Aug 10 06:21:03 PM PDT 24
Peak memory 206440 kb
Host smart-9ff83a00-47a6-4891-85e6-bf7940d3ff41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539609082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1539609082
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2287959494
Short name T987
Test name
Test status
Simulation time 57459628 ps
CPU time 0.86 seconds
Started Aug 10 06:21:01 PM PDT 24
Finished Aug 10 06:21:02 PM PDT 24
Peak memory 206516 kb
Host smart-792e8253-8b66-4193-bb95-ac1fd29dbe9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287959494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2287959494
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.277406612
Short name T443
Test name
Test status
Simulation time 320575204 ps
CPU time 5.54 seconds
Started Aug 10 06:21:01 PM PDT 24
Finished Aug 10 06:21:07 PM PDT 24
Peak memory 225300 kb
Host smart-057bcfe5-e5fb-45ab-8ffa-3a71d094ee7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277406612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.277406612
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2283749860
Short name T655
Test name
Test status
Simulation time 14583171 ps
CPU time 0.72 seconds
Started Aug 10 06:18:23 PM PDT 24
Finished Aug 10 06:18:24 PM PDT 24
Peak memory 205284 kb
Host smart-897ea6c2-3703-4f24-b093-612f05e28158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283749860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
283749860
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1213393943
Short name T549
Test name
Test status
Simulation time 162499670 ps
CPU time 2.27 seconds
Started Aug 10 06:18:23 PM PDT 24
Finished Aug 10 06:18:26 PM PDT 24
Peak memory 225140 kb
Host smart-75757f74-4950-43f5-bec7-37625fe84d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213393943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1213393943
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2460838258
Short name T828
Test name
Test status
Simulation time 58322711 ps
CPU time 0.77 seconds
Started Aug 10 06:18:23 PM PDT 24
Finished Aug 10 06:18:24 PM PDT 24
Peak memory 207048 kb
Host smart-8ee78cd4-4a95-4d5b-a605-0668b17819fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460838258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2460838258
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3621663685
Short name T914
Test name
Test status
Simulation time 2895449155 ps
CPU time 13.16 seconds
Started Aug 10 06:18:24 PM PDT 24
Finished Aug 10 06:18:37 PM PDT 24
Peak memory 238772 kb
Host smart-a341171a-1cd4-4900-a02b-bf4b3e697df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621663685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3621663685
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.671704094
Short name T426
Test name
Test status
Simulation time 55367250930 ps
CPU time 67.99 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:19:40 PM PDT 24
Peak memory 249972 kb
Host smart-fd1346f1-e31b-4b99-b935-2cbf621f2dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671704094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
671704094
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2195424832
Short name T148
Test name
Test status
Simulation time 545843141 ps
CPU time 7.62 seconds
Started Aug 10 06:18:33 PM PDT 24
Finished Aug 10 06:18:40 PM PDT 24
Peak memory 233484 kb
Host smart-ca13fa03-5420-4f31-8c3d-ce3cf7efcc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195424832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2195424832
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1985990590
Short name T583
Test name
Test status
Simulation time 7306201073 ps
CPU time 73.91 seconds
Started Aug 10 06:18:24 PM PDT 24
Finished Aug 10 06:19:38 PM PDT 24
Peak memory 256000 kb
Host smart-d0a2ee37-19f2-4368-b699-ed995f04315c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985990590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1985990590
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2485540785
Short name T219
Test name
Test status
Simulation time 3248139026 ps
CPU time 6.98 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:18:39 PM PDT 24
Peak memory 233520 kb
Host smart-91a3f580-6765-415a-ad99-f1ea06dec983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485540785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2485540785
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.721374954
Short name T542
Test name
Test status
Simulation time 30843163 ps
CPU time 2.2 seconds
Started Aug 10 06:18:24 PM PDT 24
Finished Aug 10 06:18:26 PM PDT 24
Peak memory 225288 kb
Host smart-df91a775-0fd8-4486-8e6d-c174448b8120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721374954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.721374954
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3499130720
Short name T1031
Test name
Test status
Simulation time 53230459 ps
CPU time 1.05 seconds
Started Aug 10 06:18:22 PM PDT 24
Finished Aug 10 06:18:23 PM PDT 24
Peak memory 217376 kb
Host smart-bd19f9ba-c1ee-487a-b587-a9cc4a5383fb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499130720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3499130720
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2111923321
Short name T41
Test name
Test status
Simulation time 2160843618 ps
CPU time 8.58 seconds
Started Aug 10 06:18:31 PM PDT 24
Finished Aug 10 06:18:40 PM PDT 24
Peak memory 225324 kb
Host smart-f858ede6-c8a1-425c-b769-bf2d37e420e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111923321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2111923321
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3830805110
Short name T910
Test name
Test status
Simulation time 2982742904 ps
CPU time 10.62 seconds
Started Aug 10 06:18:21 PM PDT 24
Finished Aug 10 06:18:32 PM PDT 24
Peak memory 241600 kb
Host smart-198b6d10-d1d8-4431-b3ca-4cf127cfbab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830805110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3830805110
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2334409139
Short name T509
Test name
Test status
Simulation time 130034000 ps
CPU time 4.4 seconds
Started Aug 10 06:18:29 PM PDT 24
Finished Aug 10 06:18:33 PM PDT 24
Peak memory 221116 kb
Host smart-e945780d-f6b5-4629-b89f-3eb92b1d1302
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2334409139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2334409139
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3613033515
Short name T226
Test name
Test status
Simulation time 17049604576 ps
CPU time 195.8 seconds
Started Aug 10 06:18:21 PM PDT 24
Finished Aug 10 06:21:37 PM PDT 24
Peak memory 249480 kb
Host smart-ef61ab4f-deaa-4330-9fd3-be84b7bf1fcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613033515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3613033515
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3388925323
Short name T856
Test name
Test status
Simulation time 204157310 ps
CPU time 3.56 seconds
Started Aug 10 06:18:24 PM PDT 24
Finished Aug 10 06:18:28 PM PDT 24
Peak memory 217256 kb
Host smart-534f8353-6406-4e32-833f-9cf0ddd4a215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388925323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3388925323
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.353675666
Short name T834
Test name
Test status
Simulation time 10996682423 ps
CPU time 7.1 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:18:39 PM PDT 24
Peak memory 217024 kb
Host smart-337a0fab-dd67-43f6-b2a2-c82133794ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353675666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.353675666
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.713134036
Short name T905
Test name
Test status
Simulation time 152520574 ps
CPU time 2.9 seconds
Started Aug 10 06:18:24 PM PDT 24
Finished Aug 10 06:18:27 PM PDT 24
Peak memory 216964 kb
Host smart-3c1be319-7ac4-489b-b04a-9c80621c2c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713134036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.713134036
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.4009335432
Short name T562
Test name
Test status
Simulation time 45944822 ps
CPU time 0.76 seconds
Started Aug 10 06:18:23 PM PDT 24
Finished Aug 10 06:18:24 PM PDT 24
Peak memory 206600 kb
Host smart-5bb1c201-6fc0-45e3-9ff0-273f71d03346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009335432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4009335432
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.255075392
Short name T575
Test name
Test status
Simulation time 795084770 ps
CPU time 3.75 seconds
Started Aug 10 06:18:30 PM PDT 24
Finished Aug 10 06:18:34 PM PDT 24
Peak memory 233456 kb
Host smart-9ef58917-b713-4710-9929-abc4cd59855a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255075392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.255075392
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.4067967949
Short name T602
Test name
Test status
Simulation time 15597353 ps
CPU time 0.7 seconds
Started Aug 10 06:18:30 PM PDT 24
Finished Aug 10 06:18:31 PM PDT 24
Peak memory 205308 kb
Host smart-8e5f4658-c310-443a-8cf5-851f15cee91c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067967949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.4
067967949
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.739444839
Short name T364
Test name
Test status
Simulation time 112105157 ps
CPU time 2.53 seconds
Started Aug 10 06:18:31 PM PDT 24
Finished Aug 10 06:18:33 PM PDT 24
Peak memory 233032 kb
Host smart-6ae681a2-d93e-49c1-acfe-866aba30f05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739444839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.739444839
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1846081276
Short name T5
Test name
Test status
Simulation time 102151636 ps
CPU time 0.82 seconds
Started Aug 10 06:18:33 PM PDT 24
Finished Aug 10 06:18:34 PM PDT 24
Peak memory 207076 kb
Host smart-48c27280-6e59-4665-88a4-0ee313af7fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846081276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1846081276
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.173110009
Short name T355
Test name
Test status
Simulation time 18495562 ps
CPU time 0.79 seconds
Started Aug 10 06:18:23 PM PDT 24
Finished Aug 10 06:18:24 PM PDT 24
Peak memory 216480 kb
Host smart-4338c47c-d3a0-4728-896a-09e28760a4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173110009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.173110009
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2335914653
Short name T332
Test name
Test status
Simulation time 36681892695 ps
CPU time 132.18 seconds
Started Aug 10 06:18:25 PM PDT 24
Finished Aug 10 06:20:37 PM PDT 24
Peak memory 250028 kb
Host smart-16e37a0d-3ef7-44f8-abac-ce1602acab93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335914653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2335914653
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3331057922
Short name T230
Test name
Test status
Simulation time 106424239164 ps
CPU time 155.63 seconds
Started Aug 10 06:18:30 PM PDT 24
Finished Aug 10 06:21:06 PM PDT 24
Peak memory 249892 kb
Host smart-201d7ad7-2506-4cde-a863-c91889b98aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331057922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3331057922
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.238184424
Short name T169
Test name
Test status
Simulation time 9579840164 ps
CPU time 20.13 seconds
Started Aug 10 06:18:30 PM PDT 24
Finished Aug 10 06:18:50 PM PDT 24
Peak memory 241692 kb
Host smart-71f1f0ad-bfd6-4e34-bd34-80e4246ce45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238184424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
238184424
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.4270718641
Short name T346
Test name
Test status
Simulation time 288112411 ps
CPU time 2.8 seconds
Started Aug 10 06:18:24 PM PDT 24
Finished Aug 10 06:18:27 PM PDT 24
Peak memory 225236 kb
Host smart-8efd7aab-e829-4ea6-81b0-cd823e90fb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270718641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4270718641
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2640467630
Short name T191
Test name
Test status
Simulation time 18432242181 ps
CPU time 47.38 seconds
Started Aug 10 06:18:24 PM PDT 24
Finished Aug 10 06:19:12 PM PDT 24
Peak memory 233512 kb
Host smart-33376d60-b080-4bd2-a910-3f030303e446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640467630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2640467630
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3263038608
Short name T671
Test name
Test status
Simulation time 27042101 ps
CPU time 1.09 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:18:33 PM PDT 24
Peak memory 217188 kb
Host smart-a499fc40-5a6f-48f1-895a-a74921bf2ddc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263038608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3263038608
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3694341508
Short name T907
Test name
Test status
Simulation time 32012490 ps
CPU time 2.08 seconds
Started Aug 10 06:18:23 PM PDT 24
Finished Aug 10 06:18:26 PM PDT 24
Peak memory 224496 kb
Host smart-61ebe360-b873-48f7-91de-56aaa3fd2dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694341508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3694341508
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2301981948
Short name T311
Test name
Test status
Simulation time 1670413976 ps
CPU time 5.49 seconds
Started Aug 10 06:18:24 PM PDT 24
Finished Aug 10 06:18:30 PM PDT 24
Peak memory 233480 kb
Host smart-2cc53c58-d160-43e4-86ab-c615b4db364b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301981948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2301981948
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3346770575
Short name T368
Test name
Test status
Simulation time 2414744432 ps
CPU time 13.06 seconds
Started Aug 10 06:18:21 PM PDT 24
Finished Aug 10 06:18:35 PM PDT 24
Peak memory 220012 kb
Host smart-90517382-3ca5-45cb-a71e-4bb549b72dd5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3346770575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3346770575
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3270210228
Short name T945
Test name
Test status
Simulation time 59206983681 ps
CPU time 146.67 seconds
Started Aug 10 06:18:21 PM PDT 24
Finished Aug 10 06:20:48 PM PDT 24
Peak memory 257452 kb
Host smart-f23f8886-34eb-4a17-bb68-6180782d9acd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270210228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3270210228
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1150912771
Short name T557
Test name
Test status
Simulation time 5899499032 ps
CPU time 14.47 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:18:47 PM PDT 24
Peak memory 217248 kb
Host smart-a49425b7-5505-4d02-aba8-e8e5933aac06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150912771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1150912771
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1047717489
Short name T672
Test name
Test status
Simulation time 45516458 ps
CPU time 0.72 seconds
Started Aug 10 06:18:26 PM PDT 24
Finished Aug 10 06:18:27 PM PDT 24
Peak memory 206196 kb
Host smart-889da47e-0674-4eb4-9dcb-107eb462c5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047717489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1047717489
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2810626423
Short name T558
Test name
Test status
Simulation time 793804078 ps
CPU time 2.44 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:18:35 PM PDT 24
Peak memory 216964 kb
Host smart-1a8acb3f-b737-4e7c-8c0c-fd11f3135a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810626423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2810626423
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.601655770
Short name T840
Test name
Test status
Simulation time 219160662 ps
CPU time 0.87 seconds
Started Aug 10 06:18:23 PM PDT 24
Finished Aug 10 06:18:24 PM PDT 24
Peak memory 206728 kb
Host smart-a3055cc8-61e5-450a-8c40-38f7b7c85a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601655770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.601655770
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3827843826
Short name T864
Test name
Test status
Simulation time 619733229 ps
CPU time 6.65 seconds
Started Aug 10 06:18:30 PM PDT 24
Finished Aug 10 06:18:37 PM PDT 24
Peak memory 233424 kb
Host smart-144a0545-44f9-487c-9728-6bcee90c53cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827843826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3827843826
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3063426130
Short name T540
Test name
Test status
Simulation time 24571718 ps
CPU time 0.74 seconds
Started Aug 10 06:18:34 PM PDT 24
Finished Aug 10 06:18:35 PM PDT 24
Peak memory 205268 kb
Host smart-0ad50346-4279-4935-b6b0-02e350916dd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063426130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
063426130
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.602098612
Short name T371
Test name
Test status
Simulation time 3728795341 ps
CPU time 11.38 seconds
Started Aug 10 06:18:30 PM PDT 24
Finished Aug 10 06:18:41 PM PDT 24
Peak memory 225312 kb
Host smart-8cc6ebfa-6fc1-4849-84e6-f71d912424d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602098612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.602098612
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2741183700
Short name T756
Test name
Test status
Simulation time 14930889 ps
CPU time 0.76 seconds
Started Aug 10 06:18:34 PM PDT 24
Finished Aug 10 06:18:35 PM PDT 24
Peak memory 207408 kb
Host smart-9199f44a-0de2-47a9-8b21-b5be812c50c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741183700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2741183700
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.608138094
Short name T248
Test name
Test status
Simulation time 56339994556 ps
CPU time 371.62 seconds
Started Aug 10 06:18:33 PM PDT 24
Finished Aug 10 06:24:45 PM PDT 24
Peak memory 254932 kb
Host smart-ab1147b9-4559-4814-9f70-8b9da73075ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608138094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.608138094
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.507575880
Short name T229
Test name
Test status
Simulation time 5481982013 ps
CPU time 71.82 seconds
Started Aug 10 06:18:34 PM PDT 24
Finished Aug 10 06:19:46 PM PDT 24
Peak memory 255308 kb
Host smart-4d1e6bfb-896e-4f23-acbd-94105a157ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507575880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.507575880
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1998149872
Short name T236
Test name
Test status
Simulation time 156206536706 ps
CPU time 372.73 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:24:46 PM PDT 24
Peak memory 255712 kb
Host smart-460bfc87-3fdb-4340-9c1b-0f417d7ce7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998149872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1998149872
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2409814042
Short name T897
Test name
Test status
Simulation time 1608198161 ps
CPU time 14.9 seconds
Started Aug 10 06:18:33 PM PDT 24
Finished Aug 10 06:18:48 PM PDT 24
Peak memory 241664 kb
Host smart-bf384c3b-a02f-4bee-8324-e1ee9d8a4490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409814042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2409814042
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1602119075
Short name T960
Test name
Test status
Simulation time 6068136993 ps
CPU time 22.48 seconds
Started Aug 10 06:18:34 PM PDT 24
Finished Aug 10 06:18:57 PM PDT 24
Peak memory 250644 kb
Host smart-969db379-e4bf-473f-a856-3637278ae9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602119075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1602119075
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2748998206
Short name T287
Test name
Test status
Simulation time 307394503 ps
CPU time 5.19 seconds
Started Aug 10 06:18:21 PM PDT 24
Finished Aug 10 06:18:26 PM PDT 24
Peak memory 225288 kb
Host smart-9b656d48-2683-4982-bfb9-109a75a10608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748998206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2748998206
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1399081407
Short name T927
Test name
Test status
Simulation time 13409203492 ps
CPU time 105.44 seconds
Started Aug 10 06:18:33 PM PDT 24
Finished Aug 10 06:20:18 PM PDT 24
Peak memory 235948 kb
Host smart-71921a3a-b00b-491f-8cc5-a109410e5683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399081407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1399081407
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1420719434
Short name T418
Test name
Test status
Simulation time 70516471 ps
CPU time 1.02 seconds
Started Aug 10 06:18:29 PM PDT 24
Finished Aug 10 06:18:31 PM PDT 24
Peak memory 217212 kb
Host smart-82672144-4c6f-4753-bd52-6b5c12336550
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420719434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1420719434
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.883874763
Short name T515
Test name
Test status
Simulation time 35056876 ps
CPU time 2.48 seconds
Started Aug 10 06:18:34 PM PDT 24
Finished Aug 10 06:18:36 PM PDT 24
Peak memory 233108 kb
Host smart-b94e5f00-8456-44a9-a01f-c3a2fa62ede4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883874763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
883874763
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.4073780067
Short name T310
Test name
Test status
Simulation time 4701999099 ps
CPU time 14.48 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:18:47 PM PDT 24
Peak memory 233504 kb
Host smart-713fdbdd-d864-43a6-8a7e-113c1ac3c6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073780067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.4073780067
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.757980539
Short name T375
Test name
Test status
Simulation time 513601195 ps
CPU time 4.18 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:18:36 PM PDT 24
Peak memory 222688 kb
Host smart-6df92d14-792b-49f5-a806-c52764fa2b71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=757980539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.757980539
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2827379001
Short name T166
Test name
Test status
Simulation time 164301897 ps
CPU time 1.03 seconds
Started Aug 10 06:18:33 PM PDT 24
Finished Aug 10 06:18:34 PM PDT 24
Peak memory 207664 kb
Host smart-0e290a49-fac7-46ef-a6d5-7110b2bf40af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827379001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2827379001
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2564207267
Short name T606
Test name
Test status
Simulation time 9977273541 ps
CPU time 44.05 seconds
Started Aug 10 06:18:33 PM PDT 24
Finished Aug 10 06:19:17 PM PDT 24
Peak memory 217012 kb
Host smart-ca1cdd0a-7bd6-48db-8b68-8b4a96f995c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564207267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2564207267
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1631357716
Short name T922
Test name
Test status
Simulation time 1431789069 ps
CPU time 6.34 seconds
Started Aug 10 06:18:33 PM PDT 24
Finished Aug 10 06:18:40 PM PDT 24
Peak memory 217008 kb
Host smart-14c5a753-f17a-4018-a5a2-85af231c839c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631357716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1631357716
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3329166966
Short name T743
Test name
Test status
Simulation time 12861802 ps
CPU time 0.71 seconds
Started Aug 10 06:18:23 PM PDT 24
Finished Aug 10 06:18:24 PM PDT 24
Peak memory 206140 kb
Host smart-cce58f94-3e31-4dad-8d8b-4c40054b6a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329166966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3329166966
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.903754883
Short name T617
Test name
Test status
Simulation time 29759164 ps
CPU time 0.72 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:18:33 PM PDT 24
Peak memory 206088 kb
Host smart-a7abf4df-5eaf-4acb-986b-bd731816cb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903754883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.903754883
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2619000324
Short name T600
Test name
Test status
Simulation time 56561828804 ps
CPU time 19.36 seconds
Started Aug 10 06:18:23 PM PDT 24
Finished Aug 10 06:18:43 PM PDT 24
Peak memory 233512 kb
Host smart-be598255-fd85-45b7-9211-b765e283d4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619000324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2619000324
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3351949587
Short name T388
Test name
Test status
Simulation time 11854282 ps
CPU time 0.75 seconds
Started Aug 10 06:18:36 PM PDT 24
Finished Aug 10 06:18:37 PM PDT 24
Peak memory 205820 kb
Host smart-b0f2d8aa-f1d2-4460-a090-a8c777b67fdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351949587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
351949587
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3511943086
Short name T308
Test name
Test status
Simulation time 224099123 ps
CPU time 3.73 seconds
Started Aug 10 06:18:35 PM PDT 24
Finished Aug 10 06:18:39 PM PDT 24
Peak memory 225264 kb
Host smart-8883eddd-e01d-40f5-89a0-428de62c8eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511943086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3511943086
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.78147796
Short name T566
Test name
Test status
Simulation time 59461656 ps
CPU time 0.76 seconds
Started Aug 10 06:18:34 PM PDT 24
Finished Aug 10 06:18:35 PM PDT 24
Peak memory 207072 kb
Host smart-dbff9d24-e733-4d9f-8b04-2f0638f41b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78147796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.78147796
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2785717946
Short name T179
Test name
Test status
Simulation time 31180827863 ps
CPU time 253.15 seconds
Started Aug 10 06:18:33 PM PDT 24
Finished Aug 10 06:22:46 PM PDT 24
Peak memory 252004 kb
Host smart-a77298bb-514b-4d9a-812e-8267505276da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785717946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2785717946
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.743208838
Short name T715
Test name
Test status
Simulation time 25384798909 ps
CPU time 114.45 seconds
Started Aug 10 06:18:37 PM PDT 24
Finished Aug 10 06:20:32 PM PDT 24
Peak memory 249976 kb
Host smart-405fc3f2-ffda-4b3a-83ad-aefcc12ba1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743208838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.743208838
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2833290692
Short name T830
Test name
Test status
Simulation time 165477313918 ps
CPU time 409.36 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:25:22 PM PDT 24
Peak memory 264896 kb
Host smart-33d41d9b-10ed-4a36-817e-41e80d1a1d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833290692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2833290692
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.492527864
Short name T325
Test name
Test status
Simulation time 1745273906 ps
CPU time 28.48 seconds
Started Aug 10 06:18:33 PM PDT 24
Finished Aug 10 06:19:02 PM PDT 24
Peak memory 233932 kb
Host smart-8718aad7-ea29-4624-9ac1-dc2c6f261711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492527864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.492527864
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2891605075
Short name T965
Test name
Test status
Simulation time 13000301990 ps
CPU time 87.4 seconds
Started Aug 10 06:18:37 PM PDT 24
Finished Aug 10 06:20:04 PM PDT 24
Peak memory 239612 kb
Host smart-17a69175-d674-4e7e-825e-73e7c7f0e979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891605075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2891605075
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1222880328
Short name T545
Test name
Test status
Simulation time 204689191 ps
CPU time 4.41 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:18:37 PM PDT 24
Peak memory 233476 kb
Host smart-52cd0e4d-02cd-4cd7-9194-67dd2d7ad27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222880328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1222880328
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2058501450
Short name T633
Test name
Test status
Simulation time 2935363181 ps
CPU time 34.4 seconds
Started Aug 10 06:18:36 PM PDT 24
Finished Aug 10 06:19:11 PM PDT 24
Peak memory 233480 kb
Host smart-fe7598d3-f7d4-48dc-af78-9fdc84766e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058501450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2058501450
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1476132445
Short name T902
Test name
Test status
Simulation time 17021944 ps
CPU time 0.97 seconds
Started Aug 10 06:18:31 PM PDT 24
Finished Aug 10 06:18:32 PM PDT 24
Peak memory 218508 kb
Host smart-472cad08-cd95-4836-80ca-51ffaede1402
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476132445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1476132445
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1811518160
Short name T133
Test name
Test status
Simulation time 615224602 ps
CPU time 4.39 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:18:37 PM PDT 24
Peak memory 233460 kb
Host smart-ebf9d77d-a870-49c6-9921-393fd7bd778d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811518160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1811518160
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.914086217
Short name T455
Test name
Test status
Simulation time 799268182 ps
CPU time 5.25 seconds
Started Aug 10 06:18:34 PM PDT 24
Finished Aug 10 06:18:39 PM PDT 24
Peak memory 233452 kb
Host smart-fa40911f-649e-4780-8a5c-1bf5cb9c42e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914086217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.914086217
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2261577034
Short name T442
Test name
Test status
Simulation time 447362641 ps
CPU time 4.45 seconds
Started Aug 10 06:18:35 PM PDT 24
Finished Aug 10 06:18:39 PM PDT 24
Peak memory 221176 kb
Host smart-2172c973-bcc4-4d9a-958d-c1800caa10da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2261577034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2261577034
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3216148814
Short name T27
Test name
Test status
Simulation time 2514690967 ps
CPU time 21.88 seconds
Started Aug 10 06:18:34 PM PDT 24
Finished Aug 10 06:18:56 PM PDT 24
Peak memory 217084 kb
Host smart-a4c8dcbc-9beb-43c4-b1c4-a44273c3fba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216148814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3216148814
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2467775239
Short name T673
Test name
Test status
Simulation time 6842248611 ps
CPU time 20.78 seconds
Started Aug 10 06:18:36 PM PDT 24
Finished Aug 10 06:18:57 PM PDT 24
Peak memory 217084 kb
Host smart-2a6df517-df1b-4d9a-98ee-4b52d9c80fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467775239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2467775239
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1576860622
Short name T434
Test name
Test status
Simulation time 265228496 ps
CPU time 1.45 seconds
Started Aug 10 06:18:36 PM PDT 24
Finished Aug 10 06:18:38 PM PDT 24
Peak memory 216972 kb
Host smart-95c6a091-ed4b-48d6-9f18-158337e10853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576860622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1576860622
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2994352903
Short name T411
Test name
Test status
Simulation time 39100733 ps
CPU time 0.76 seconds
Started Aug 10 06:18:33 PM PDT 24
Finished Aug 10 06:18:34 PM PDT 24
Peak memory 206596 kb
Host smart-08fc795e-4d02-49a9-a569-a2174ce78e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994352903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2994352903
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3980149380
Short name T637
Test name
Test status
Simulation time 2821676865 ps
CPU time 7.09 seconds
Started Aug 10 06:18:37 PM PDT 24
Finished Aug 10 06:18:45 PM PDT 24
Peak memory 233552 kb
Host smart-bea1e78a-db75-40d9-908a-4696ce45fd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980149380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3980149380
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3194138558
Short name T42
Test name
Test status
Simulation time 14067610 ps
CPU time 0.73 seconds
Started Aug 10 06:18:39 PM PDT 24
Finished Aug 10 06:18:40 PM PDT 24
Peak memory 205212 kb
Host smart-323f0a3a-d80f-4416-90ec-846882603149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194138558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
194138558
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2139098742
Short name T1026
Test name
Test status
Simulation time 99071846 ps
CPU time 2.09 seconds
Started Aug 10 06:18:35 PM PDT 24
Finished Aug 10 06:18:38 PM PDT 24
Peak memory 224756 kb
Host smart-0c6a532a-3909-42ca-8825-26c7b691eba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139098742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2139098742
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1696046103
Short name T536
Test name
Test status
Simulation time 138293417 ps
CPU time 0.73 seconds
Started Aug 10 06:18:34 PM PDT 24
Finished Aug 10 06:18:35 PM PDT 24
Peak memory 205480 kb
Host smart-ec59e451-baa6-43e0-87df-9d6947190093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696046103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1696046103
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1767879312
Short name T724
Test name
Test status
Simulation time 11290543887 ps
CPU time 69.09 seconds
Started Aug 10 06:18:35 PM PDT 24
Finished Aug 10 06:19:45 PM PDT 24
Peak memory 258108 kb
Host smart-df98e60e-fdaa-4744-a418-1459efcb139d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767879312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1767879312
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3901220921
Short name T342
Test name
Test status
Simulation time 4234161459 ps
CPU time 65.91 seconds
Started Aug 10 06:18:38 PM PDT 24
Finished Aug 10 06:19:44 PM PDT 24
Peak memory 252088 kb
Host smart-c3f70f80-5fdd-4031-a4d9-f7aad15b7fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901220921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3901220921
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1607131021
Short name T503
Test name
Test status
Simulation time 59486458 ps
CPU time 2.98 seconds
Started Aug 10 06:18:36 PM PDT 24
Finished Aug 10 06:18:39 PM PDT 24
Peak memory 233460 kb
Host smart-cd37e687-6a06-417b-96a7-787b59b5524f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607131021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1607131021
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1535656308
Short name T193
Test name
Test status
Simulation time 822181131 ps
CPU time 8.14 seconds
Started Aug 10 06:18:34 PM PDT 24
Finished Aug 10 06:18:42 PM PDT 24
Peak memory 225232 kb
Host smart-ac8eb1c2-2711-4820-b894-2e144aa25e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535656308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1535656308
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.40539326
Short name T419
Test name
Test status
Simulation time 3883500692 ps
CPU time 33.92 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:19:06 PM PDT 24
Peak memory 238868 kb
Host smart-59a67f88-5f0a-45fd-846f-e7923687e4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40539326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.40539326
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3383121311
Short name T576
Test name
Test status
Simulation time 44853528 ps
CPU time 1.08 seconds
Started Aug 10 06:18:33 PM PDT 24
Finished Aug 10 06:18:35 PM PDT 24
Peak memory 217208 kb
Host smart-eb28bcbd-a42b-41ad-bbe4-2f96227b2635
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383121311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3383121311
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1261649159
Short name T407
Test name
Test status
Simulation time 842509921 ps
CPU time 5.16 seconds
Started Aug 10 06:18:31 PM PDT 24
Finished Aug 10 06:18:37 PM PDT 24
Peak memory 233460 kb
Host smart-156527cf-b2b5-42cc-a290-94234b8a3fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261649159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1261649159
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3386452391
Short name T303
Test name
Test status
Simulation time 975167921 ps
CPU time 8.49 seconds
Started Aug 10 06:18:32 PM PDT 24
Finished Aug 10 06:18:40 PM PDT 24
Peak memory 241244 kb
Host smart-e28b7cf7-ff45-4a50-b25b-162ca115b001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386452391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3386452391
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.196600732
Short name T532
Test name
Test status
Simulation time 949347086 ps
CPU time 5.07 seconds
Started Aug 10 06:18:39 PM PDT 24
Finished Aug 10 06:18:44 PM PDT 24
Peak memory 223780 kb
Host smart-900d5318-5ea3-4cef-ad7e-d753fed81cde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=196600732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.196600732
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3875987036
Short name T258
Test name
Test status
Simulation time 97678709223 ps
CPU time 392.48 seconds
Started Aug 10 06:18:39 PM PDT 24
Finished Aug 10 06:25:12 PM PDT 24
Peak memory 274348 kb
Host smart-80eb2320-c7e3-43b8-983e-c527170565af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875987036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3875987036
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4265878836
Short name T630
Test name
Test status
Simulation time 25134993 ps
CPU time 0.78 seconds
Started Aug 10 06:18:30 PM PDT 24
Finished Aug 10 06:18:31 PM PDT 24
Peak memory 206484 kb
Host smart-ede0ff60-8bf0-428a-b047-a18b865f9fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265878836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4265878836
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1043720288
Short name T400
Test name
Test status
Simulation time 12609774 ps
CPU time 0.69 seconds
Started Aug 10 06:18:34 PM PDT 24
Finished Aug 10 06:18:34 PM PDT 24
Peak memory 206188 kb
Host smart-b516a240-0ac8-4273-93cc-f43728802a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043720288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1043720288
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.598478981
Short name T900
Test name
Test status
Simulation time 47602964 ps
CPU time 1.5 seconds
Started Aug 10 06:18:33 PM PDT 24
Finished Aug 10 06:18:34 PM PDT 24
Peak memory 216972 kb
Host smart-8471f0b0-5000-449b-bffe-69155f55819b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598478981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.598478981
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1608046179
Short name T354
Test name
Test status
Simulation time 25979457 ps
CPU time 0.79 seconds
Started Aug 10 06:18:29 PM PDT 24
Finished Aug 10 06:18:30 PM PDT 24
Peak memory 206528 kb
Host smart-b794a0cc-7261-4406-9565-14bbd6aaddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608046179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1608046179
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2171377453
Short name T194
Test name
Test status
Simulation time 550294082 ps
CPU time 7.71 seconds
Started Aug 10 06:18:33 PM PDT 24
Finished Aug 10 06:18:41 PM PDT 24
Peak memory 241276 kb
Host smart-37dfd6a8-96b7-497e-b441-aa0ad889d033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171377453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2171377453
Directory /workspace/9.spi_device_upload/latest
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