Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2734480	1			T2	212		T3	2152		T4	19554
all_values[1]	2734480	1			T2	212		T3	2152		T4	19554
all_values[2]	2734480	1			T2	212		T3	2152		T4	19554
all_values[3]	2734480	1			T2	212		T3	2152		T4	19554
all_values[4]	2734480	1			T2	212		T3	2152		T4	19554
all_values[5]	2734480	1			T2	212		T3	2152		T4	19554
all_values[6]	2734480	1			T2	212		T3	2152		T4	19554
all_values[7]	2734480	1			T2	212		T3	2152		T4	19554

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21091570

1

T2

1696

T3

17216

T4

156432

auto[1]

784270

1

T13

26

T14

44

T15

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21846530

1

T2

1696

T3

17216

T4

156284

auto[1]

29310

1

T4

148

T8

226

T12

474

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2648074	1			T2	212		T3	2152		T4	19472
all_values[0]	auto[0]	auto[1]	14116	1			T4	82		T8	108		T12	220
all_values[0]	auto[1]	auto[0]	71730	1			T14	4		T15	5		T16	2
all_values[0]	auto[1]	auto[1]	560	1			T13	3		T14	3		T16	2
all_values[1]	auto[0]	auto[0]	2682365	1			T2	212		T3	2152		T4	19488
all_values[1]	auto[0]	auto[1]	9177	1			T4	66		T8	89		T12	190
all_values[1]	auto[1]	auto[0]	42678	1			T13	1		T14	2		T15	1
all_values[1]	auto[1]	auto[1]	260	1			T13	1		T14	2		T15	1
all_values[2]	auto[0]	auto[0]	2654029	1			T2	212		T3	2152		T4	19554
all_values[2]	auto[0]	auto[1]	3076	1			T8	29		T12	64		T26	7
all_values[2]	auto[1]	auto[0]	77106	1			T13	5		T14	4		T15	4
all_values[2]	auto[1]	auto[1]	269	1			T13	1		T14	1		T15	1
all_values[3]	auto[0]	auto[0]	2654251	1			T2	212		T3	2152		T4	19554
all_values[3]	auto[0]	auto[1]	182	1			T106	1		T14	1		T17	4
all_values[3]	auto[1]	auto[0]	79866	1			T13	2		T14	6		T15	4
all_values[3]	auto[1]	auto[1]	181	1			T13	1		T14	1		T15	2
all_values[4]	auto[0]	auto[0]	2636642	1			T2	212		T3	2152		T4	19554
all_values[4]	auto[0]	auto[1]	206	1			T13	5		T14	3		T15	2
all_values[4]	auto[1]	auto[0]	97449	1			T13	1		T14	3		T15	1
all_values[4]	auto[1]	auto[1]	183	1			T13	1		T14	1		T16	1
all_values[5]	auto[0]	auto[0]	2591858	1			T2	212		T3	2152		T4	19554
all_values[5]	auto[0]	auto[1]	167	1			T13	1		T14	2		T16	2
all_values[5]	auto[1]	auto[0]	142281	1			T13	3		T14	6		T16	2861
all_values[5]	auto[1]	auto[1]	174	1			T13	1		T15	2		T16	1
all_values[6]	auto[0]	auto[0]	2605226	1			T2	212		T3	2152		T4	19554
all_values[6]	auto[0]	auto[1]	186	1			T13	3		T14	1		T16	3
all_values[6]	auto[1]	auto[0]	128896	1			T14	4		T15	1		T16	1
all_values[6]	auto[1]	auto[1]	172	1			T14	1		T16	2		T17	1
all_values[7]	auto[0]	auto[0]	2591827	1			T2	212		T3	2152		T4	19554
all_values[7]	auto[0]	auto[1]	188	1			T13	1		T14	1		T15	1
all_values[7]	auto[1]	auto[0]	142252	1			T13	2		T14	4		T15	5
all_values[7]	auto[1]	auto[1]	213	1			T13	4		T14	2		T16	3