Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	31007	1			T3	296		T4	68		T6	6
auto[SpiFlashAddrCfg]	7422	1			T3	34		T4	19		T6	4
auto[SpiFlashAddr3b]	9037	1			T3	61		T4	32		T6	2
auto[SpiFlashAddr4b]	7184	1			T3	35		T4	16		T6	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31040

1

T3

209

T4

94

T6

16

auto[1]

23610

1

T3

217

T4

41

T8

56

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29807

1

T3

227

T4

81

T6

2

auto[1]

24843

1

T3

199

T4

54

T6

14

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	35565	1			T3	318		T4	83		T6	10
values[1]	1083	1			T3	9		T4	2		T8	4
values[2]	1376	1			T3	8		T4	3		T6	2
values[3]	1425	1			T3	8		T4	6		T8	5
values[4]	1374	1			T3	6		T4	6		T8	2
values[5]	1493	1			T3	7		T4	10		T8	7
values[6]	1424	1			T3	6		T4	5		T8	1
values[7]	1418	1			T3	8		T4	2		T6	2
values[8]	9492	1			T3	56		T4	18		T6	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24559

1

T6

16

T7

10

T8

68

auto[1]

30091

1

T3

426

T4

135

T8

201

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

51542

1

T3

406

T4

127

T6

16

write

3108

1

T3

20

T4

8

T8

10

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18665

1

T3

101

T4

57

T6

4

valids[0x1]

35985

1

T3

325

T4

78

T6

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1578	1			T3	9		T4	6		T6	4
internal_process_ops[0x5a]	1599	1			T3	8		T4	5		T8	5
internal_process_ops[0x05]	17395	1			T3	213		T4	19		T6	2
internal_process_ops[0x35]	1550	1			T3	4		T4	5		T8	7
internal_process_ops[0x15]	1551	1			T3	10		T4	8		T8	6
internal_process_ops[0x03]	977	1			T3	4		T4	3		T6	4
internal_process_ops[0x0b]	990	1			T3	1		T4	2		T6	2
internal_process_ops[0x3b]	923	1			T3	2		T4	1		T8	4
internal_process_ops[0x6b]	1028	1			T3	4		T4	1		T6	2
internal_process_ops[0xbb]	967	1			T3	3		T4	3		T8	4
internal_process_ops[0xeb]	948	1			T3	3		T4	2		T6	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53074

1

T3

414

T4

132

T6

16

auto[1]

1576

1

T3

12

T4

3

T8

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52286

1

T3

414

T4

130

T6

16

auto[1]

2364

1

T3

12

T4

5

T8

15

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8124

1

T6

6

T7

4

T8

24

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4347

1

T8

10

T40

14

T97

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1780

1

T6

4

T7

6

T8

3

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1519

1

T8

12

T40

6

T97

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2234

1

T6

2

T8

3

T23

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1869

1

T8

3

T45

8

T40

9

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1787

1

T6

4

T8

9

T40

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1547

1

T8

2

T39

2

T45

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

112

1

T37

2

T175

2

T41

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

79

1

T46

2

T50

1

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

85

1

T39

2

T46

1

T176

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

93

1

T45

6

T46

2

T48

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

80

1

T23

2

T39

3

T14

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

65

1

T39

2

T37

1

T46

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

68

1

T37

1

T41

3

T50

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

99

1

T45

2

T46

3

T41

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

89

1

T44

2

T37

1

T31

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

63

1

T37

2

T48

1

T41

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

84

1

T40

1

T46

1

T41

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

106

1

T45

2

T41

1

T50

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

94

1

T37

2

T177

6

T48

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

73

1

T46

1

T48

1

T50

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

73

1

T8

2

T40

1

T37

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

89

1

T46

1

T48

4

T50

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10196

1

T3

144

T4

57

T8

129

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7511

1

T3

144

T4

8

T8

10

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1710

1

T3

19

T4

12

T8

11

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1645

1

T3

14

T4

6

T8

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2115

1

T3

28

T4

14

T8

12

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2052

1

T3

28

T4

16

T8

7

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1595

1

T3

12

T4

8

T8

14

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1511

1

T3

17

T4

6

T8

8

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

108

1

T4

1

T8

2

T12

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

104

1

T3

2

T26

1

T57

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

119

1

T3

2

T4

1

T12

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

129

1

T3

4

T4

1

T12

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

111

1

T8

1

T12

1

T26

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

111

1

T12

1

T38

3

T178

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

108

1

T3

1

T12

1

T26

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

126

1

T4

1

T12

1

T53

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

85

1

T3

1

T4

2

T12

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

124

1

T3

2

T12

2

T26

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

92

1

T12

5

T26

1

T38

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

124

1

T3

2

T12

4

T26

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

106

1

T8

2

T26

1

T38

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

95

1

T3

1

T8

3

T57

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

118

1

T3

4

T4

1

T12

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

96

1

T3

1

T4

1

T12

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3261	1			T7	4		T8	8		T11	16
auto[0]	values[0]	valids[0x1]	11743	1			T6	10		T8	28		T23	4
auto[0]	values[1]	valids[0x1]	466	1			T8	2		T39	2		T37	3
auto[0]	values[2]	valids[0x0]	459	1			T6	2		T39	1		T45	2
auto[0]	values[2]	valids[0x1]	255	1			T40	1		T37	4		T46	3
auto[0]	values[3]	valids[0x0]	520	1			T8	1		T43	4		T39	1
auto[0]	values[3]	valids[0x1]	247	1			T45	2		T37	6		T46	2
auto[0]	values[4]	valids[0x0]	430	1			T40	3		T37	3		T46	2
auto[0]	values[4]	valids[0x1]	258	1			T43	2		T40	3		T97	2
auto[0]	values[5]	valids[0x0]	442	1			T8	2		T23	2		T39	1
auto[0]	values[5]	valids[0x1]	260	1			T8	1		T40	1		T97	4
auto[0]	values[6]	valids[0x0]	487	1			T40	7		T37	8		T46	9
auto[0]	values[6]	valids[0x1]	255	1			T40	2		T37	1		T46	2
auto[0]	values[7]	valids[0x0]	479	1			T40	2		T37	6		T46	9
auto[0]	values[7]	valids[0x1]	264	1			T6	2		T8	2		T45	2
auto[0]	values[8]	valids[0x0]	2955	1			T6	2		T7	6		T8	20
auto[0]	values[8]	valids[0x1]	1778	1			T8	4		T40	9		T49	2
auto[1]	values[0]	valids[0x0]	4288	1			T3	47		T4	32		T8	25
auto[1]	values[0]	valids[0x1]	16273	1			T3	271		T4	51		T8	132
auto[1]	values[1]	valids[0x1]	617	1			T3	9		T4	2		T8	2
auto[1]	values[2]	valids[0x0]	420	1			T3	7		T4	1		T12	2
auto[1]	values[2]	valids[0x1]	242	1			T3	1		T4	2		T8	1
auto[1]	values[3]	valids[0x0]	387	1			T3	3		T4	2		T8	4
auto[1]	values[3]	valids[0x1]	271	1			T3	5		T4	4		T12	3
auto[1]	values[4]	valids[0x0]	394	1			T3	5		T4	6		T8	2
auto[1]	values[4]	valids[0x1]	292	1			T3	1		T12	11		T26	1
auto[1]	values[5]	valids[0x0]	454	1			T3	3		T4	3		T8	2
auto[1]	values[5]	valids[0x1]	337	1			T3	4		T4	7		T8	2
auto[1]	values[6]	valids[0x0]	417	1			T3	4		T9	3		T12	6
auto[1]	values[6]	valids[0x1]	265	1			T3	2		T4	5		T8	1
auto[1]	values[7]	valids[0x0]	423	1			T3	5		T4	2		T8	2
auto[1]	values[7]	valids[0x1]	252	1			T3	3		T12	2		T26	1
auto[1]	values[8]	valids[0x0]	2849	1			T3	27		T4	11		T8	20
auto[1]	values[8]	valids[0x1]	1910	1			T3	29		T4	7		T8	8