Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3545258

1

T3

4735

T4

1842

T6

1161

auto[1]

26038

1

T3

206

T4

15

T8

109

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1162079

1

T3

64

T4

27

T6

1161

auto[1]

2409217

1

T3

4877

T4

1830

T8

12745

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	682721	1			T3	613		T6	12		T7	232
auto[524288:1048575]	435692	1			T3	296		T4	305		T6	42
auto[1048576:1572863]	402811	1			T3	146		T4	537		T6	368
auto[1572864:2097151]	440550	1			T3	1451		T4	6		T6	8
auto[2097152:2621439]	353431	1			T3	8		T4	412		T7	52
auto[2621440:3145727]	391362	1			T3	778		T4	41		T6	319
auto[3145728:3670015]	463399	1			T3	400		T4	1		T6	6
auto[3670016:4194303]	401330	1			T3	1249		T4	555		T6	406

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2443247

1

T3

4924

T4

1857

T6

23

auto[1]

1128049

1

T3

17

T6

1138

T7

906

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3104325

1

T3

4471

T4

1584

T6

1161

auto[1]

466971

1

T3

470

T4

273

T7

465

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	248378	1			T3	6		T6	12		T7	118
auto[0]	auto[0]	auto[0:524287]	auto[1]	355090	1			T3	514		T8	4		T12	1535
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	140999	1			T3	2		T4	2		T6	42
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	220749	1			T3	6		T4	300		T8	1963
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	132075	1			T3	9		T4	2		T6	368
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	209285	1			T3	105		T4	534		T8	3054
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	165792	1			T3	8		T6	8		T9	786
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	226728	1			T3	1399		T8	512		T12	2524
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	89674	1			T3	3		T4	1		T8	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	215457	1			T4	154		T8	1953		T12	4399
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	126487	1			T3	2		T4	10		T6	319
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	207679	1			T3	771		T4	16		T8	165
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	108737	1			T3	1		T4	1		T6	6
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	276395	1			T3	385		T8	5		T12	2485
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	138432	1			T3	1		T6	406		T7	57
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	221022	1			T3	1129		T4	553		T8	130
auto[0]	auto[1]	auto[0:524287]	auto[0]	1527	1			T3	3		T7	114		T8	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	73508	1			T3	4		T8	728		T12	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1100	1			T3	6		T7	3		T8	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	69245	1			T3	257		T8	1		T37	512
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1210	1			T3	1		T4	1		T8	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	56791	1			T8	1		T12	5		T38	3289
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	563	1			T3	2		T4	1		T7	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	45340	1			T3	1		T4	5		T196	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	995	1			T4	1		T7	52		T26	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	44916	1			T3	5		T4	256		T8	2339
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	762	1			T3	5		T4	2		T11	51
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	53025	1			T4	1		T12	556		T26	2198
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	733	1			T7	66		T26	6		T40	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	73861	1			T26	3		T46	2503		T48	4960
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	809	1			T3	3		T4	1		T7	227
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	37894	1			T3	107		T4	1		T8	1796
auto[1]	auto[0]	auto[0:524287]	auto[0]	470	1			T3	2		T12	2		T26	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	3340	1			T3	47		T12	52		T26	14
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	350	1			T3	1		T4	1		T8	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2634	1			T3	17		T4	2		T8	10
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	335	1			T3	2		T12	4		T26	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2437	1			T3	29		T12	30		T26	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	348	1			T3	2		T12	3		T26	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1295	1			T3	16		T12	40		T26	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	373	1			T12	3		T53	1		T38	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1556	1			T12	4		T53	4		T38	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	431	1			T4	3		T8	2		T12	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2200	1			T4	5		T8	3		T12	12
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	391	1			T3	1		T8	2		T12	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2487	1			T3	13		T8	10		T12	8
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	372	1			T8	2		T39	1		T37	44
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2327	1			T8	6		T39	21		T37	3
auto[1]	auto[1]	auto[0:524287]	auto[0]	78	1			T3	1		T8	1		T12	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	330	1			T3	36		T8	2		T12	14
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	94	1			T3	1		T8	1		T50	11
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	521	1			T3	6		T8	2		T31	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	115	1			T8	1		T38	1		T48	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	563	1			T8	21		T38	1		T48	52
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	84	1			T3	1		T63	6		T48	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	400	1			T3	22		T196	1		T14	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	74	1			T38	1		T41	1		T14	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	386	1			T41	6		T14	4		T178	7
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	97	1			T4	1		T12	2		T88	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	681	1			T4	3		T12	9		T88	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	96	1			T26	2		T48	3		T50	11
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	699	1			T26	24		T48	15		T50	87
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	98	1			T3	1		T8	3		T39	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	376	1			T3	8		T8	40		T39	24

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1958421	1			T3	4336		T4	1573		T6	23
auto[0]	auto[0]	auto[1]	1124558	1			T3	5		T6	1138		T7	457
auto[0]	auto[1]	auto[0]	459463	1			T3	391		T4	269		T7	16
auto[0]	auto[1]	auto[1]	2816	1			T3	3		T7	449		T11	47
auto[1]	auto[0]	auto[0]	20807	1			T3	123		T4	11		T8	38
auto[1]	auto[0]	auto[1]	539	1			T3	7		T12	1		T26	2
auto[1]	auto[1]	auto[0]	4556	1			T3	74		T4	4		T8	70
auto[1]	auto[1]	auto[1]	136	1			T3	2		T8	1		T26	1