Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2734480	1			T2	212		T3	2152		T4	19554
all_pins[1]	2734480	1			T2	212		T3	2152		T4	19554
all_pins[2]	2734480	1			T2	212		T3	2152		T4	19554
all_pins[3]	2734480	1			T2	212		T3	2152		T4	19554
all_pins[4]	2734480	1			T2	212		T3	2152		T4	19554
all_pins[5]	2734480	1			T2	212		T3	2152		T4	19554
all_pins[6]	2734480	1			T2	212		T3	2152		T4	19554
all_pins[7]	2734480	1			T2	212		T3	2152		T4	19554

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21742066	1			T2	1696		T3	17216		T4	156432
values[0x1]	133774	1			T13	12		T14	11		T15	6
transitions[0x0=>0x1]	130928	1			T13	10		T14	8		T15	5
transitions[0x1=>0x0]	130942	1			T13	11		T14	8		T15	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2733884	1			T2	212		T3	2152		T4	19554
all_pins[0]	values[0x1]	596	1			T13	3		T14	3		T16	2
all_pins[0]	transitions[0x0=>0x1]	451	1			T13	3		T14	1		T17	3
all_pins[0]	transitions[0x1=>0x0]	131	1			T13	1		T15	1		T16	9
all_pins[1]	values[0x0]	2734204	1			T2	212		T3	2152		T4	19554
all_pins[1]	values[0x1]	276	1			T13	1		T14	2		T15	1
all_pins[1]	transitions[0x0=>0x1]	186	1			T13	1		T14	2		T16	9
all_pins[1]	transitions[0x1=>0x0]	185	1			T13	1		T14	1		T16	1
all_pins[2]	values[0x0]	2734205	1			T2	212		T3	2152		T4	19554
all_pins[2]	values[0x1]	275	1			T13	1		T14	1		T15	1
all_pins[2]	transitions[0x0=>0x1]	226	1			T13	1		T14	1		T15	1
all_pins[2]	transitions[0x1=>0x0]	132	1			T13	1		T14	1		T15	2
all_pins[3]	values[0x0]	2734299	1			T2	212		T3	2152		T4	19554
all_pins[3]	values[0x1]	181	1			T13	1		T14	1		T15	2
all_pins[3]	transitions[0x0=>0x1]	139	1			T14	1		T15	2		T16	4
all_pins[3]	transitions[0x1=>0x0]	141	1			T14	1		T16	1		T17	2
all_pins[4]	values[0x0]	2734297	1			T2	212		T3	2152		T4	19554
all_pins[4]	values[0x1]	183	1			T13	1		T14	1		T16	1
all_pins[4]	transitions[0x0=>0x1]	145	1			T13	1		T14	1		T16	1
all_pins[4]	transitions[0x1=>0x0]	3334	1			T13	1		T15	2		T16	329
all_pins[5]	values[0x0]	2731108	1			T2	212		T3	2152		T4	19554
all_pins[5]	values[0x1]	3372	1			T13	1		T15	2		T16	329
all_pins[5]	transitions[0x0=>0x1]	1011	1			T13	1		T15	2		T16	329
all_pins[5]	transitions[0x1=>0x0]	126317	1			T14	1		T16	2		T17	1
all_pins[6]	values[0x0]	2605802	1			T2	212		T3	2152		T4	19554
all_pins[6]	values[0x1]	128678	1			T14	1		T16	2		T17	1
all_pins[6]	transitions[0x0=>0x1]	128622	1			T16	1		T17	1		T19	5
all_pins[6]	transitions[0x1=>0x0]	157	1			T13	4		T14	1		T16	2
all_pins[7]	values[0x0]	2734267	1			T2	212		T3	2152		T4	19554
all_pins[7]	values[0x1]	213	1			T13	4		T14	2		T16	3
all_pins[7]	transitions[0x0=>0x1]	148	1			T13	3		T14	2		T16	2
all_pins[7]	transitions[0x1=>0x0]	545	1			T13	3		T14	3		T16	1