Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14580

1

T6

16

T7

10

T8

39

auto[1]

9979

1

T8

29

T39

4

T45

20

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3430	1			T7	10		T44	2		T40	20
values[1]	3346	1			T6	16		T45	20		T97	12
values[2]	2953	1			T8	20		T46	24		T41	44
values[3]	3267	1			T8	28		T11	16		T92	12
values[4]	3277	1			T39	105		T239	22		T37	20
values[5]	2671	1			T25	22		T37	20		T46	45
values[6]	2646	1			T43	18		T37	20		T46	22
values[7]	2969	1			T8	20		T23	6		T37	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3366	1			T44	2		T37	20		T46	40
values[1]	3009	1			T7	10		T11	16		T40	20
values[2]	2766	1			T43	18		T39	105		T37	20
values[3]	3010	1			T37	60		T46	24		T47	21
values[4]	3511	1			T40	21		T37	20		T46	47
values[5]	3154	1			T25	22		T92	12		T45	20
values[6]	3076	1			T8	20		T23	6		T49	22
values[7]	2667	1			T6	16		T8	48		T37	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	411	1			T44	2		T179	12		T221	16
auto[0]	values[0]	values[1]	169	1			T7	10		T40	7		T31	12
auto[0]	values[0]	values[2]	269	1			T46	10		T175	14		T20	8
auto[0]	values[0]	values[3]	331	1			T37	14		T41	18		T208	18
auto[0]	values[0]	values[4]	205	1			T205	16		T14	15		T186	8
auto[0]	values[0]	values[5]	372	1			T41	33		T222	35		T176	13
auto[0]	values[0]	values[6]	277	1			T37	13		T41	12		T50	10
auto[0]	values[0]	values[7]	167	1			T58	22		T20	16		T240	34
auto[0]	values[1]	values[0]	301	1			T37	5		T46	22		T211	13
auto[0]	values[1]	values[1]	204	1			T31	13		T190	13		T241	13
auto[0]	values[1]	values[2]	259	1			T176	10		T31	28		T242	4
auto[0]	values[1]	values[3]	343	1			T46	13		T235	13		T18	9
auto[0]	values[1]	values[4]	364	1			T41	17		T50	29		T31	14
auto[0]	values[1]	values[5]	265	1			T211	12		T219	9		T19	9
auto[0]	values[1]	values[6]	157	1			T48	13		T243	10		T234	11
auto[0]	values[1]	values[7]	177	1			T6	16		T48	14		T244	14
auto[0]	values[2]	values[0]	417	1			T41	10		T245	142		T186	9
auto[0]	values[2]	values[1]	199	1			T230	12		T219	9		T180	6
auto[0]	values[2]	values[2]	139	1			T46	6		T31	9		T246	14
auto[0]	values[2]	values[3]	133	1			T31	13		T14	24		T247	2
auto[0]	values[2]	values[4]	197	1			T179	4		T248	6		T18	13
auto[0]	values[2]	values[5]	249	1			T249	12		T250	14		T216	45
auto[0]	values[2]	values[6]	285	1			T8	11		T20	14		T251	14
auto[0]	values[2]	values[7]	161	1			T246	8		T18	13		T19	15
auto[0]	values[3]	values[0]	179	1			T47	9		T41	9		T200	16
auto[0]	values[3]	values[1]	250	1			T11	16		T50	16		T220	2
auto[0]	values[3]	values[2]	147	1			T50	12		T209	10		T171	13
auto[0]	values[3]	values[3]	316	1			T37	15		T47	13		T50	13
auto[0]	values[3]	values[4]	194	1			T40	14		T15	13		T252	2
auto[0]	values[3]	values[5]	148	1			T92	12		T40	11		T47	7
auto[0]	values[3]	values[6]	329	1			T49	22		T31	21		T14	7
auto[0]	values[3]	values[7]	455	1			T8	16		T177	111		T235	7
auto[0]	values[4]	values[0]	259	1			T50	10		T31	14		T14	78
auto[0]	values[4]	values[1]	185	1			T253	10		T19	22		T254	29
auto[0]	values[4]	values[2]	320	1			T39	101		T48	12		T235	77
auto[0]	values[4]	values[3]	171	1			T217	11		T200	8		T255	2
auto[0]	values[4]	values[4]	190	1			T31	16		T95	12		T186	14
auto[0]	values[4]	values[5]	170	1			T62	10		T256	8		T58	23
auto[0]	values[4]	values[6]	286	1			T239	22		T46	7		T58	22
auto[0]	values[4]	values[7]	264	1			T37	10		T48	15		T31	16
auto[0]	values[5]	values[0]	137	1			T185	18		T176	8		T200	15
auto[0]	values[5]	values[1]	184	1			T20	13		T192	8		T200	23
auto[0]	values[5]	values[2]	193	1			T46	13		T67	2		T186	12
auto[0]	values[5]	values[3]	203	1			T198	11		T257	24		T258	6
auto[0]	values[5]	values[4]	197	1			T46	11		T66	12		T219	11
auto[0]	values[5]	values[5]	311	1			T25	22		T37	14		T50	14
auto[0]	values[5]	values[6]	178	1			T41	14		T58	8		T192	43
auto[0]	values[5]	values[7]	165	1			T19	11		T20	17		T210	19
auto[0]	values[6]	values[0]	206	1			T14	72		T259	18		T193	14
auto[0]	values[6]	values[1]	170	1			T198	11		T169	20		T199	10
auto[0]	values[6]	values[2]	166	1			T43	18		T46	11		T48	25
auto[0]	values[6]	values[3]	204	1			T31	18		T19	12		T210	18
auto[0]	values[6]	values[4]	307	1			T37	17		T14	14		T202	24
auto[0]	values[6]	values[5]	184	1			T48	23		T223	12		T142	11
auto[0]	values[6]	values[6]	151	1			T41	9		T50	11		T20	29
auto[0]	values[6]	values[7]	97	1			T58	17		T193	13		T260	16
auto[0]	values[7]	values[0]	330	1			T31	22		T186	6		T82	18
auto[0]	values[7]	values[1]	181	1			T46	10		T93	12		T261	8
auto[0]	values[7]	values[2]	177	1			T37	13		T179	11		T246	15
auto[0]	values[7]	values[3]	206	1			T37	9		T179	11		T58	17
auto[0]	values[7]	values[4]	253	1			T46	13		T96	18		T228	20
auto[0]	values[7]	values[5]	181	1			T262	4		T48	13		T41	20
auto[0]	values[7]	values[6]	156	1			T23	6		T190	13		T82	34
auto[0]	values[7]	values[7]	129	1			T8	12		T47	37		T179	10
auto[1]	values[0]	values[0]	214	1			T179	8		T20	16		T203	5
auto[1]	values[0]	values[1]	138	1			T40	13		T31	22		T20	10
auto[1]	values[0]	values[2]	174	1			T46	15		T20	13		T198	8
auto[1]	values[0]	values[3]	200	1			T37	6		T41	2		T52	16
auto[1]	values[0]	values[4]	82	1			T14	5		T186	12		T19	7
auto[1]	values[0]	values[5]	162	1			T41	4		T176	10		T263	8
auto[1]	values[0]	values[6]	185	1			T37	7		T41	8		T50	10
auto[1]	values[0]	values[7]	74	1			T218	22		T58	11		T20	4
auto[1]	values[1]	values[0]	123	1			T37	15		T46	18		T211	7
auto[1]	values[1]	values[1]	163	1			T31	9		T190	19		T264	12
auto[1]	values[1]	values[2]	102	1			T176	10		T31	19		T186	7
auto[1]	values[1]	values[3]	166	1			T46	11		T235	7		T18	34
auto[1]	values[1]	values[4]	241	1			T41	3		T50	11		T31	10
auto[1]	values[1]	values[5]	220	1			T45	20		T97	12		T211	8
auto[1]	values[1]	values[6]	133	1			T48	7		T234	9		T219	29
auto[1]	values[1]	values[7]	128	1			T48	6		T58	8		T82	13
auto[1]	values[2]	values[0]	160	1			T41	34		T186	21		T142	8
auto[1]	values[2]	values[1]	110	1			T219	11		T142	7		T194	11
auto[1]	values[2]	values[2]	157	1			T46	18		T31	14		T265	4
auto[1]	values[2]	values[3]	89	1			T31	13		T14	10		T18	4
auto[1]	values[2]	values[4]	242	1			T179	16		T18	7		T198	122
auto[1]	values[2]	values[5]	47	1			T212	18		T216	9		T266	8
auto[1]	values[2]	values[6]	165	1			T8	9		T20	6		T190	9
auto[1]	values[2]	values[7]	203	1			T246	12		T18	7		T19	9
auto[1]	values[3]	values[0]	151	1			T47	48		T41	11		T200	10
auto[1]	values[3]	values[1]	197	1			T50	4		T200	14		T267	10
auto[1]	values[3]	values[2]	66	1			T50	8		T171	16		T215	5
auto[1]	values[3]	values[3]	98	1			T37	5		T47	8		T50	7
auto[1]	values[3]	values[4]	151	1			T40	7		T15	8		T187	24
auto[1]	values[3]	values[5]	252	1			T40	13		T47	13		T48	9
auto[1]	values[3]	values[6]	186	1			T31	5		T14	23		T235	4
auto[1]	values[3]	values[7]	148	1			T8	12		T235	13		T20	9
auto[1]	values[4]	values[0]	143	1			T50	10		T31	7		T14	8
auto[1]	values[4]	values[1]	258	1			T19	98		T254	7		T194	36
auto[1]	values[4]	values[2]	122	1			T39	4		T48	8		T235	9
auto[1]	values[4]	values[3]	142	1			T217	9		T200	12		T268	16
auto[1]	values[4]	values[4]	194	1			T31	8		T186	6		T19	8
auto[1]	values[4]	values[5]	148	1			T58	10		T234	13		T217	9
auto[1]	values[4]	values[6]	234	1			T46	14		T58	8		T246	11
auto[1]	values[4]	values[7]	191	1			T37	10		T48	5		T31	5
auto[1]	values[5]	values[0]	64	1			T176	12		T200	8		T266	5
auto[1]	values[5]	values[1]	128	1			T20	7		T192	12		T269	2
auto[1]	values[5]	values[2]	190	1			T46	9		T186	8		T18	76
auto[1]	values[5]	values[3]	67	1			T198	9		T270	6		T271	6
auto[1]	values[5]	values[4]	258	1			T46	12		T219	11		T82	10
auto[1]	values[5]	values[5]	119	1			T37	6		T50	6		T215	11
auto[1]	values[5]	values[6]	140	1			T41	8		T58	64		T192	14
auto[1]	values[5]	values[7]	137	1			T19	11		T20	10		T210	12
auto[1]	values[6]	values[0]	73	1			T14	4		T193	6		T271	9
auto[1]	values[6]	values[1]	327	1			T51	16		T198	167		T169	23
auto[1]	values[6]	values[2]	127	1			T46	11		T48	15		T50	8
auto[1]	values[6]	values[3]	137	1			T31	2		T19	8		T210	5
auto[1]	values[6]	values[4]	207	1			T37	3		T14	30		T219	7
auto[1]	values[6]	values[5]	137	1			T48	17		T142	9		T270	12
auto[1]	values[6]	values[6]	102	1			T41	11		T50	9		T272	18
auto[1]	values[6]	values[7]	51	1			T58	11		T193	10		T260	8
auto[1]	values[7]	values[0]	198	1			T31	6		T186	42		T82	9
auto[1]	values[7]	values[1]	146	1			T46	10		T142	10		T233	6
auto[1]	values[7]	values[2]	158	1			T37	7		T179	9		T246	18
auto[1]	values[7]	values[3]	204	1			T37	11		T179	9		T58	14
auto[1]	values[7]	values[4]	229	1			T46	11		T18	8		T192	36
auto[1]	values[7]	values[5]	189	1			T48	7		T41	5		T198	10
auto[1]	values[7]	values[6]	112	1			T190	26		T82	16		T215	5
auto[1]	values[7]	values[7]	120	1			T8	8		T47	9		T179	10