Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	359	1			T6	8		T8	1		T49	2
auto[ReadAddrCrossIntoMailbox]	248	1			T37	1		T46	4		T47	1
auto[ReadAddrCrossOutOfMailbox]	275	1			T8	3		T37	3		T46	7
auto[ReadAddrCrossAllMailbox]	205	1			T8	1		T49	10		T37	1
auto[ReadAddrOutsideMailbox]	3001	1			T6	2		T8	12		T23	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2046

1

T6

5

T8

9

T23

1

auto[1]

2042

1

T6

5

T8

8

T23

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	682	1			T6	4		T8	1		T40	3
read_ops[0x0b]	709	1			T6	2		T43	2		T39	1
read_ops[0x3b]	640	1			T8	3		T39	1		T40	3
read_ops[0x6b]	708	1			T6	2		T8	6		T43	2
read_ops[0xbb]	677	1			T8	4		T23	2		T43	4
read_ops[0xeb]	672	1			T6	2		T8	3		T97	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T6	2		T50	1		T211	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T6	2		T50	1		T31	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T219	1		T235	1		T190	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T46	1		T41	1		T176	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T14	1		T234	1		T219	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T46	1		T179	2		T58	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T49	1		T179	1		T19	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T49	1		T41	1		T179	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	250	1			T37	1		T46	2		T47	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	255	1			T8	1		T40	3		T37	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T6	1		T62	2		T46	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T6	1		T62	2		T176	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T41	1		T58	1		T246	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T41	2		T31	1		T186	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T46	1		T14	1		T186	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T37	1		T31	2		T58	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T48	1		T179	1		T221	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T47	1		T50	2		T221	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	262	1			T43	1		T39	1		T45	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	244	1			T43	1		T45	1		T37	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T46	1		T41	1		T50	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T8	1		T41	1		T31	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T46	1		T41	1		T186	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T50	1		T14	1		T15	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T46	1		T48	1		T230	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T50	1		T230	1		T179	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T46	1		T48	1		T221	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T31	1		T179	1		T221	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	212	1			T40	2		T37	2		T46	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	259	1			T8	2		T39	1		T40	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T49	1		T46	2		T205	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T49	1		T48	1		T205	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T46	1		T41	1		T211	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T48	1		T230	1		T31	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T8	1		T37	1		T46	3
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T41	1		T176	1		T246	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T50	1		T211	1		T179	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T176	1		T179	2		T58	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	273	1			T6	1		T8	5		T43	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	263	1			T6	1		T43	1		T40	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T62	1		T19	1		T198	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T62	1		T211	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T46	1		T47	1		T50	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T37	1		T48	1		T41	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T176	1		T31	1		T246	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T8	1		T37	1		T41	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T49	4		T46	1		T246	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T49	4		T37	1		T20	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	241	1			T23	1		T43	2		T45	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	249	1			T8	3		T23	1		T43	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T6	1		T37	1		T205	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T6	1		T48	2		T205	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T41	1		T211	1		T230	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T48	1		T230	1		T221	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T8	1		T46	1		T47	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T48	1		T50	1		T230	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T8	1		T179	1		T234	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T46	1		T41	1		T50	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	246	1			T8	1		T97	1		T37	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	247	1			T97	1		T37	4		T46	1