Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2912	1			T92	12		T49	22		T62	10
values[1]	3049	1			T6	16		T25	22		T44	2
values[2]	2720	1			T45	20		T40	20		T37	40
values[3]	2485	1			T8	20		T40	21		T47	21
values[4]	3447	1			T43	18		T39	105		T40	24
values[5]	3246	1			T11	16		T37	40		T46	44
values[6]	3529	1			T8	48		T37	40		T46	24
values[7]	3171	1			T7	10		T23	6		T239	22

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2736	1			T47	41		T93	12		T41	20
values[1]	3310	1			T7	10		T37	40		T46	24
values[2]	3286	1			T6	16		T8	48		T43	18
values[3]	3355	1			T8	20		T40	20		T239	22
values[4]	2464	1			T40	24		T37	40		T67	2
values[5]	2865	1			T92	12		T44	2		T40	21
values[6]	2993	1			T11	16		T37	20		T46	22
values[7]	3550	1			T23	6		T25	22		T39	105

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23892

1

T6

16

T7

10

T8

68

auto[1]

667

1

T39

2

T45

10

T37

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	385	1			T31	26		T58	31		T219	22
auto[0]	values[0]	values[1]	470	1			T46	21		T48	18		T19	50
auto[0]	values[0]	values[2]	545	1			T49	22		T41	41		T50	18
auto[0]	values[0]	values[3]	344	1			T198	19		T217	18		T194	20
auto[0]	values[0]	values[4]	234	1			T211	20		T51	12		T218	22
auto[0]	values[0]	values[5]	246	1			T92	12		T179	17		T240	34
auto[0]	values[0]	values[6]	210	1			T20	23		T200	23		T171	24
auto[0]	values[0]	values[7]	364	1			T62	10		T96	18		T50	36
auto[0]	values[1]	values[0]	363	1			T176	22		T14	19		T58	72
auto[0]	values[1]	values[1]	211	1			T230	12		T58	29		T242	4
auto[0]	values[1]	values[2]	500	1			T6	16		T97	12		T37	20
auto[0]	values[1]	values[3]	411	1			T37	20		T41	20		T222	35
auto[0]	values[1]	values[4]	261	1			T269	2		T210	24		T193	23
auto[0]	values[1]	values[5]	435	1			T44	2		T46	20		T14	76
auto[0]	values[1]	values[6]	358	1			T58	25		T19	20		T190	41
auto[0]	values[1]	values[7]	439	1			T25	22		T208	18		T14	30
auto[0]	values[2]	values[0]	340	1			T273	14		T87	12		T194	20
auto[0]	values[2]	values[1]	415	1			T48	18		T256	8		T31	45
auto[0]	values[2]	values[2]	348	1			T198	69		T274	16		T275	36
auto[0]	values[2]	values[3]	258	1			T40	20		T37	19		T20	24
auto[0]	values[2]	values[4]	359	1			T37	20		T211	20		T244	14
auto[0]	values[2]	values[5]	274	1			T262	4		T179	17		T217	19
auto[0]	values[2]	values[6]	270	1			T46	21		T276	2		T277	12
auto[0]	values[2]	values[7]	366	1			T45	10		T48	19		T31	20
auto[0]	values[3]	values[0]	318	1			T47	21		T202	24		T261	8
auto[0]	values[3]	values[1]	273	1			T48	38		T58	23		T190	38
auto[0]	values[3]	values[2]	185	1			T41	25		T209	10		T20	23
auto[0]	values[3]	values[3]	547	1			T8	20		T219	44		T235	32
auto[0]	values[3]	values[4]	188	1			T48	20		T50	38		T217	20
auto[0]	values[3]	values[5]	241	1			T40	21		T198	20		T216	22
auto[0]	values[3]	values[6]	252	1			T189	21		T278	4		T201	21
auto[0]	values[3]	values[7]	410	1			T177	111		T31	21		T198	20
auto[0]	values[4]	values[0]	365	1			T47	20		T50	20		T14	20
auto[0]	values[4]	values[1]	305	1			T234	16		T246	20		T190	20
auto[0]	values[4]	values[2]	521	1			T43	18		T176	19		T235	20
auto[0]	values[4]	values[3]	370	1			T66	12		T205	16		T14	34
auto[0]	values[4]	values[4]	312	1			T40	24		T219	42		T235	86
auto[0]	values[4]	values[5]	464	1			T46	19		T50	20		T179	20
auto[0]	values[4]	values[6]	563	1			T37	20		T186	40		T189	20
auto[0]	values[4]	values[7]	468	1			T39	103		T46	22		T41	22
auto[0]	values[5]	values[0]	216	1			T199	19		T171	28		T279	16
auto[0]	values[5]	values[1]	772	1			T37	19		T185	18		T58	28
auto[0]	values[5]	values[2]	314	1			T31	20		T19	22		T190	15
auto[0]	values[5]	values[3]	304	1			T31	32		T19	23		T199	20
auto[0]	values[5]	values[4]	278	1			T37	20		T247	2		T19	20
auto[0]	values[5]	values[5]	575	1			T48	20		T179	35		T234	20
auto[0]	values[5]	values[6]	314	1			T11	16		T48	20		T176	20
auto[0]	values[5]	values[7]	400	1			T46	41		T47	57		T31	24
auto[0]	values[6]	values[0]	443	1			T41	20		T245	142		T188	10
auto[0]	values[6]	values[1]	429	1			T37	19		T15	20		T20	20
auto[0]	values[6]	values[2]	310	1			T8	48		T48	19		T186	29
auto[0]	values[6]	values[3]	656	1			T46	24		T176	23		T186	20
auto[0]	values[6]	values[4]	422	1			T47	46		T48	18		T41	20
auto[0]	values[6]	values[5]	240	1			T37	20		T175	14		T31	21
auto[0]	values[6]	values[6]	494	1			T31	20		T237	2		T14	43
auto[0]	values[6]	values[7]	440	1			T31	25		T186	38		T19	63
auto[0]	values[7]	values[0]	233	1			T93	12		T18	20		T198	20
auto[0]	values[7]	values[1]	320	1			T7	10		T41	18		T20	27
auto[0]	values[7]	values[2]	462	1			T50	19		T246	19		T189	21
auto[0]	values[7]	values[3]	412	1			T239	22		T50	20		T179	20
auto[0]	values[7]	values[4]	344	1			T67	2		T253	10		T31	24
auto[0]	values[7]	values[5]	316	1			T46	21		T41	20		T52	12
auto[0]	values[7]	values[6]	453	1			T243	10		T186	20		T20	40
auto[0]	values[7]	values[7]	557	1			T23	6		T46	20		T31	22
auto[1]	values[0]	values[0]	19	1			T58	2		T280	4		T281	4
auto[1]	values[0]	values[1]	27	1			T46	3		T48	2		T19	3
auto[1]	values[0]	values[2]	25	1			T41	3		T50	2		T31	2
auto[1]	values[0]	values[3]	4	1			T198	1		T217	2		T282	1
auto[1]	values[0]	values[4]	10	1			T51	4		T283	2		T284	1
auto[1]	values[0]	values[5]	9	1			T179	3		T271	2		T285	2
auto[1]	values[0]	values[6]	4	1			T171	1		T286	1		T284	1
auto[1]	values[0]	values[7]	16	1			T50	4		T265	2		T215	2
auto[1]	values[1]	values[0]	5	1			T14	1		T20	1		T285	1
auto[1]	values[1]	values[1]	9	1			T58	2		T142	2		T60	3
auto[1]	values[1]	values[2]	15	1			T46	1		T18	3		T20	2
auto[1]	values[1]	values[3]	5	1			T20	1		T82	2		T194	1
auto[1]	values[1]	values[4]	10	1			T193	2		T187	1		T270	1
auto[1]	values[1]	values[5]	8	1			T46	1		T20	3		T193	1
auto[1]	values[1]	values[6]	10	1			T58	5		T190	2		T287	1
auto[1]	values[1]	values[7]	9	1			T190	2		T82	3		T171	1
auto[1]	values[2]	values[0]	13	1			T273	4		T270	2		T288	1
auto[1]	values[2]	values[1]	10	1			T48	2		T31	2		T200	1
auto[1]	values[2]	values[2]	12	1			T198	1		T274	4		T275	1
auto[1]	values[2]	values[3]	4	1			T37	1		T20	1		T289	1
auto[1]	values[2]	values[4]	13	1			T215	5		T287	2		T285	1
auto[1]	values[2]	values[5]	8	1			T179	3		T217	1		T275	1
auto[1]	values[2]	values[6]	6	1			T46	1		T270	3		T290	2
auto[1]	values[2]	values[7]	24	1			T45	10		T48	1		T31	4
auto[1]	values[3]	values[0]	6	1			T187	2		T150	1		T291	2
auto[1]	values[3]	values[1]	19	1			T48	2		T190	1		T292	14
auto[1]	values[3]	values[2]	7	1			T20	2		T287	3		T289	2
auto[1]	values[3]	values[3]	12	1			T219	1		T82	1		T260	2
auto[1]	values[3]	values[4]	5	1			T50	2		T216	2		T293	1
auto[1]	values[3]	values[5]	8	1			T216	1		T294	2		T287	3
auto[1]	values[3]	values[6]	9	1			T189	3		T142	2		T215	2
auto[1]	values[3]	values[7]	5	1			T31	2		T184	2		T287	1
auto[1]	values[4]	values[0]	8	1			T59	1		T260	1		T288	2
auto[1]	values[4]	values[1]	14	1			T234	4		T86	2		T295	1
auto[1]	values[4]	values[2]	9	1			T176	1		T194	2		T283	1
auto[1]	values[4]	values[3]	11	1			T58	1		T296	3		T297	2
auto[1]	values[4]	values[4]	1	1			T282	1		-	-		-	-
auto[1]	values[4]	values[5]	10	1			T46	1		T86	4		T254	2
auto[1]	values[4]	values[6]	9	1			T189	1		T190	2		T86	3
auto[1]	values[4]	values[7]	17	1			T39	2		T50	1		T298	2
auto[1]	values[5]	values[0]	3	1			T199	1		T171	1		T266	1
auto[1]	values[5]	values[1]	9	1			T37	1		T198	2		T194	2
auto[1]	values[5]	values[2]	14	1			T19	2		T190	5		T200	1
auto[1]	values[5]	values[3]	3	1			T31	2		T271	1		-	-
auto[1]	values[5]	values[4]	9	1			T19	1		T190	2		T201	2
auto[1]	values[5]	values[5]	14	1			T179	5		T217	1		T299	1
auto[1]	values[5]	values[6]	16	1			T86	2		T267	1		T275	2
auto[1]	values[5]	values[7]	5	1			T46	3		T210	1		T227	1
auto[1]	values[6]	values[0]	18	1			T188	2		T142	1		T254	3
auto[1]	values[6]	values[1]	17	1			T37	1		T15	1		T300	8
auto[1]	values[6]	values[2]	7	1			T48	1		T186	1		T297	1
auto[1]	values[6]	values[3]	11	1			T187	1		T295	3		T283	1
auto[1]	values[6]	values[4]	5	1			T48	2		T210	1		T266	1
auto[1]	values[6]	values[5]	5	1			T20	3		T212	2		-	-
auto[1]	values[6]	values[6]	16	1			T31	1		T14	1		T200	1
auto[1]	values[6]	values[7]	16	1			T31	1		T186	2		T19	4
auto[1]	values[7]	values[0]	1	1			T295	1		-	-		-	-
auto[1]	values[7]	values[1]	10	1			T41	2		T20	3		T142	1
auto[1]	values[7]	values[2]	12	1			T50	1		T246	1		T206	1
auto[1]	values[7]	values[3]	3	1			T203	1		T191	1		T291	1
auto[1]	values[7]	values[4]	13	1			T246	1		T149	2		T254	1
auto[1]	values[7]	values[5]	12	1			T46	2		T52	4		T18	1
auto[1]	values[7]	values[6]	9	1			T192	1		T195	3		T266	3
auto[1]	values[7]	values[7]	14	1			T19	3		T82	1		T206	1