SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_flip_position | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_opcode | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 76 | 1 | T9 | 6 | T106 | 2 | T64 | 3 | ||||
auto[1] | 27 | 1 | T9 | 2 | T106 | 1 | T64 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
read_ops[0x03] | 19 | 1 | T9 | 2 | T106 | 2 | T159 | 4 | ||||
read_ops[0x0b] | 24 | 1 | T106 | 1 | T161 | 6 | T164 | 6 | ||||
read_ops[0x3b] | 8 | 1 | T9 | 6 | T301 | 2 | - | - | ||||
read_ops[0x6b] | 12 | 1 | T161 | 4 | T302 | 2 | T303 | 2 | ||||
read_ops[0xbb] | 17 | 1 | T64 | 2 | T161 | 2 | T164 | 4 | ||||
read_ops[0xeb] | 23 | 1 | T64 | 2 | T163 | 8 | T304 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |