Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	794	1			T13	7		T14	7		T15	4
all_values[1]	794	1			T13	7		T14	7		T15	4
all_values[2]	794	1			T13	7		T14	7		T15	4
all_values[3]	794	1			T13	7		T14	7		T15	4
all_values[4]	794	1			T13	7		T14	7		T15	4
all_values[5]	794	1			T13	7		T14	7		T15	4
all_values[6]	794	1			T13	7		T14	7		T15	4
all_values[7]	794	1			T13	7		T14	7		T15	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3376

1

T13

30

T14

24

T15

12

auto[1]

2976

1

T13

26

T14

32

T15

20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2564

1

T13

23

T14

21

T15

14

auto[1]

3788

1

T13

33

T14

35

T15

18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3587

1

T13

33

T14

29

T15

19

auto[1]

2765

1

T13

23

T14

27

T15

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	165	1			T13	1		T16	3		T17	3
all_values[0]	auto[0]	auto[0]	auto[1]	80	1			T17	3		T19	7		T21	5
all_values[0]	auto[0]	auto[1]	auto[0]	138	1			T14	1		T15	4		T16	2
all_values[0]	auto[0]	auto[1]	auto[1]	73	1			T13	1		T14	2		T17	1
all_values[0]	auto[1]	auto[0]	auto[1]	185	1			T13	2		T14	2		T17	3
all_values[0]	auto[1]	auto[1]	auto[1]	153	1			T13	3		T14	2		T16	2
all_values[1]	auto[0]	auto[0]	auto[0]	186	1			T13	1		T14	2		T17	5
all_values[1]	auto[0]	auto[0]	auto[1]	58	1			T13	1		T15	1		T21	3
all_values[1]	auto[0]	auto[1]	auto[0]	126	1			T14	1		T17	2		T19	5
all_values[1]	auto[0]	auto[1]	auto[1]	73	1			T13	1		T14	1		T16	2
all_values[1]	auto[1]	auto[0]	auto[1]	181	1			T13	4		T15	1		T17	1
all_values[1]	auto[1]	auto[1]	auto[1]	170	1			T14	3		T15	2		T16	5
all_values[2]	auto[0]	auto[0]	auto[0]	173	1			T14	1		T17	5		T19	11
all_values[2]	auto[0]	auto[0]	auto[1]	68	1			T14	1		T16	3		T17	1
all_values[2]	auto[0]	auto[1]	auto[0]	134	1			T13	5		T14	1		T15	1
all_values[2]	auto[0]	auto[1]	auto[1]	67	1			T13	1		T15	1		T19	3
all_values[2]	auto[1]	auto[0]	auto[1]	179	1			T14	2		T16	2		T17	4
all_values[2]	auto[1]	auto[1]	auto[1]	173	1			T13	1		T14	2		T15	2
all_values[3]	auto[0]	auto[0]	auto[0]	169	1			T13	3		T14	1		T16	2
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T19	1		T168	2		T169	3
all_values[3]	auto[0]	auto[1]	auto[0]	147	1			T13	2		T14	3		T15	2
all_values[3]	auto[0]	auto[1]	auto[1]	74	1			T15	1		T16	2		T17	2
all_values[3]	auto[1]	auto[0]	auto[1]	184	1			T13	1		T14	1		T16	1
all_values[3]	auto[1]	auto[1]	auto[1]	147	1			T13	1		T14	2		T15	1
all_values[4]	auto[0]	auto[0]	auto[0]	152	1			T15	1		T16	1		T17	1
all_values[4]	auto[0]	auto[0]	auto[1]	78	1			T13	1		T14	2		T15	1
all_values[4]	auto[0]	auto[1]	auto[0]	140	1			T13	1		T14	1		T16	3
all_values[4]	auto[0]	auto[1]	auto[1]	74	1			T13	1		T17	3		T19	2
all_values[4]	auto[1]	auto[0]	auto[1]	194	1			T13	3		T14	3		T15	2
all_values[4]	auto[1]	auto[1]	auto[1]	156	1			T13	1		T14	1		T16	1
all_values[5]	auto[0]	auto[0]	auto[0]	237	1			T13	2		T14	2		T15	2
all_values[5]	auto[0]	auto[1]	auto[0]	216	1			T13	3		T14	3		T16	3
all_values[5]	auto[1]	auto[0]	auto[1]	171	1			T13	2		T14	1		T16	1
all_values[5]	auto[1]	auto[1]	auto[1]	170	1			T14	1		T15	2		T16	2
all_values[6]	auto[0]	auto[0]	auto[0]	186	1			T13	4		T14	1		T15	2
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T13	2		T16	1		T19	3
all_values[6]	auto[0]	auto[1]	auto[0]	131	1			T14	2		T16	1		T19	2
all_values[6]	auto[0]	auto[1]	auto[1]	70	1			T16	1		T19	3		T21	2
all_values[6]	auto[1]	auto[0]	auto[1]	183	1			T13	1		T14	2		T15	2
all_values[6]	auto[1]	auto[1]	auto[1]	151	1			T14	2		T16	1		T17	1
all_values[7]	auto[0]	auto[0]	auto[0]	146	1			T13	1		T14	1		T17	2
all_values[7]	auto[0]	auto[0]	auto[1]	76	1			T14	1		T19	3		T21	5
all_values[7]	auto[0]	auto[1]	auto[0]	118	1			T14	1		T15	2		T16	1
all_values[7]	auto[0]	auto[1]	auto[1]	86	1			T13	2		T14	1		T15	1
all_values[7]	auto[1]	auto[0]	auto[1]	179	1			T13	1		T14	1		T16	2
all_values[7]	auto[1]	auto[1]	auto[1]	189	1			T13	3		T14	2		T15	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal