Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1871

1

T4

9

T8

7

T10

3

auto[1]

1735

1

T4

8

T8

11

T10

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1957

1

T4

9

T8

18

T12

10

auto[1]

1649

1

T4

8

T10

7

T22

16

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2875

1

T4

13

T8

16

T10

7

auto[1]

731

1

T4

4

T8

2

T12

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	713	1			T4	4		T8	2		T10	1
valid[1]	647	1			T4	2		T8	5		T10	1
valid[2]	738	1			T4	3		T8	2		T10	1
valid[3]	749	1			T4	3		T8	4		T10	3
valid[4]	759	1			T4	5		T8	5		T10	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	97	1			T12	1		T27	1		T56	1
auto[0]	auto[0]	valid[0]	auto[1]	164	1			T4	1		T12	1		T28	2
auto[0]	auto[0]	valid[1]	auto[0]	124	1			T8	3		T12	1		T27	2
auto[0]	auto[0]	valid[1]	auto[1]	155	1			T4	1		T10	1		T22	1
auto[0]	auto[0]	valid[2]	auto[0]	140	1			T4	2		T8	1		T40	3
auto[0]	auto[0]	valid[2]	auto[1]	174	1			T10	1		T22	2		T55	1
auto[0]	auto[0]	valid[3]	auto[0]	133	1			T4	1		T8	1		T27	1
auto[0]	auto[0]	valid[3]	auto[1]	178	1			T22	4		T12	2		T28	1
auto[0]	auto[0]	valid[4]	auto[0]	137	1			T4	1		T8	1		T12	2
auto[0]	auto[0]	valid[4]	auto[1]	183	1			T4	1		T10	1		T22	2
auto[0]	auto[1]	valid[0]	auto[0]	120	1			T8	2		T27	2		T69	1
auto[0]	auto[1]	valid[0]	auto[1]	170	1			T4	2		T10	1		T22	3
auto[0]	auto[1]	valid[1]	auto[0]	94	1			T8	1		T40	2		T56	1
auto[0]	auto[1]	valid[1]	auto[1]	141	1			T22	1		T12	1		T28	2
auto[0]	auto[1]	valid[2]	auto[0]	119	1			T26	1		T27	1		T40	1
auto[0]	auto[1]	valid[2]	auto[1]	159	1			T22	1		T12	1		T55	2
auto[0]	auto[1]	valid[3]	auto[0]	137	1			T8	3		T46	1		T47	1
auto[0]	auto[1]	valid[3]	auto[1]	161	1			T4	1		T10	3		T22	1
auto[0]	auto[1]	valid[4]	auto[0]	125	1			T4	1		T8	4		T27	1
auto[0]	auto[1]	valid[4]	auto[1]	164	1			T4	2		T22	1		T28	1
auto[1]	auto[0]	valid[0]	auto[0]	83	1			T12	1		T56	3		T46	1
auto[1]	auto[0]	valid[1]	auto[0]	70	1			T4	1		T8	1		T40	1
auto[1]	auto[0]	valid[2]	auto[0]	81	1			T4	1		T27	1		T38	3
auto[1]	auto[0]	valid[3]	auto[0]	68	1			T12	2		T69	1		T196	1
auto[1]	auto[0]	valid[4]	auto[0]	84	1			T12	2		T56	1		T46	1
auto[1]	auto[1]	valid[0]	auto[0]	79	1			T4	1		T27	1		T40	1
auto[1]	auto[1]	valid[1]	auto[0]	63	1			T12	1		T38	3		T305	1
auto[1]	auto[1]	valid[2]	auto[0]	65	1			T8	1		T40	1		T38	1
auto[1]	auto[1]	valid[3]	auto[0]	72	1			T4	1		T176	1		T88	3
auto[1]	auto[1]	valid[4]	auto[0]	66	1			T27	1		T56	1		T196	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal