Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50836

1

T2

11

T4

474

T8

561

auto[1]

17420

1

T4

93

T10

96

T22

286

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49886

1

T2

4

T4

361

T8

386

auto[1]

18370

1

T2

7

T4

206

T8

175

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35245	1			T2	5		T4	308		T8	274
others[1]	5769	1			T2	1		T4	38		T8	47
others[2]	5768	1			T2	1		T4	53		T8	45
others[3]	6425	1			T4	48		T8	57		T10	13
interest[1]	3661	1			T2	3		T4	23		T8	34
interest[4]	23112	1			T2	2		T4	208		T8	176
interest[64]	11388	1			T2	1		T4	97		T8	104

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16630	1			T2	1		T4	141		T8	184
auto[0]	auto[0]	others[1]	2775	1			T4	13		T8	34		T12	18
auto[0]	auto[0]	others[2]	2728	1			T2	1		T4	26		T8	32
auto[0]	auto[0]	others[3]	3134	1			T4	19		T8	43		T12	14
auto[0]	auto[0]	interest[1]	1760	1			T2	1		T4	14		T8	25
auto[0]	auto[0]	interest[4]	10914	1			T2	1		T4	97		T8	120
auto[0]	auto[0]	interest[64]	5439	1			T2	1		T4	55		T8	68
auto[0]	auto[1]	others[0]	9102	1			T4	45		T10	48		T22	139
auto[0]	auto[1]	others[1]	1382	1			T4	9		T10	1		T22	30
auto[0]	auto[1]	others[2]	1437	1			T4	10		T10	9		T22	31
auto[0]	auto[1]	others[3]	1607	1			T4	12		T10	13		T22	32
auto[0]	auto[1]	interest[1]	941	1			T4	3		T10	7		T22	15
auto[0]	auto[1]	interest[4]	5994	1			T4	34		T10	34		T22	85
auto[0]	auto[1]	interest[64]	2951	1			T4	14		T10	18		T22	39
auto[1]	auto[0]	others[0]	9513	1			T2	4		T4	122		T8	90
auto[1]	auto[0]	others[1]	1612	1			T2	1		T4	16		T8	13
auto[1]	auto[0]	others[2]	1603	1			T4	17		T8	13		T12	7
auto[1]	auto[0]	others[3]	1684	1			T4	17		T8	14		T12	20
auto[1]	auto[0]	interest[1]	960	1			T2	2		T4	6		T8	9
auto[1]	auto[0]	interest[4]	6204	1			T2	1		T4	77		T8	56
auto[1]	auto[0]	interest[64]	2998	1			T4	28		T8	36		T12	23

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal