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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.08 98.62 89.36 97.28 95.43 99.21


Total test records in report: 1151
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T156 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.348380262 Aug 11 06:17:29 PM PDT 24 Aug 11 06:17:31 PM PDT 24 77272248 ps
T1040 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1783525388 Aug 11 06:17:34 PM PDT 24 Aug 11 06:17:35 PM PDT 24 44415506 ps
T157 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1612807934 Aug 11 06:17:25 PM PDT 24 Aug 11 06:17:27 PM PDT 24 523922616 ps
T102 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.901671902 Aug 11 06:17:17 PM PDT 24 Aug 11 06:17:19 PM PDT 24 693409607 ps
T126 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4117789979 Aug 11 06:17:25 PM PDT 24 Aug 11 06:17:47 PM PDT 24 13112174301 ps
T1041 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1023325484 Aug 11 06:17:29 PM PDT 24 Aug 11 06:17:33 PM PDT 24 236637942 ps
T1042 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3421681940 Aug 11 06:17:16 PM PDT 24 Aug 11 06:17:17 PM PDT 24 17245287 ps
T1043 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1652460798 Aug 11 06:17:25 PM PDT 24 Aug 11 06:17:26 PM PDT 24 151326927 ps
T120 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1669056498 Aug 11 06:17:00 PM PDT 24 Aug 11 06:17:02 PM PDT 24 77356632 ps
T1044 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1669726164 Aug 11 06:17:00 PM PDT 24 Aug 11 06:17:01 PM PDT 24 13409619 ps
T131 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4003584140 Aug 11 06:17:26 PM PDT 24 Aug 11 06:17:28 PM PDT 24 94259477 ps
T1045 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.401005086 Aug 11 06:17:22 PM PDT 24 Aug 11 06:17:22 PM PDT 24 11098488 ps
T127 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1199570784 Aug 11 06:17:01 PM PDT 24 Aug 11 06:17:14 PM PDT 24 579768935 ps
T121 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3384194517 Aug 11 06:17:17 PM PDT 24 Aug 11 06:17:35 PM PDT 24 1423852565 ps
T122 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1790423087 Aug 11 06:17:18 PM PDT 24 Aug 11 06:17:22 PM PDT 24 56907484 ps
T132 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3418920289 Aug 11 06:17:02 PM PDT 24 Aug 11 06:17:05 PM PDT 24 434995522 ps
T1046 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3205198634 Aug 11 06:17:25 PM PDT 24 Aug 11 06:17:26 PM PDT 24 34803998 ps
T1047 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.347308933 Aug 11 06:17:25 PM PDT 24 Aug 11 06:17:26 PM PDT 24 42123062 ps
T116 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1902334131 Aug 11 06:17:13 PM PDT 24 Aug 11 06:17:16 PM PDT 24 620742255 ps
T123 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2985637829 Aug 11 06:17:08 PM PDT 24 Aug 11 06:17:12 PM PDT 24 136943727 ps
T104 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.711362040 Aug 11 06:17:29 PM PDT 24 Aug 11 06:17:32 PM PDT 24 138425176 ps
T1048 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1922196050 Aug 11 06:17:22 PM PDT 24 Aug 11 06:17:22 PM PDT 24 28492764 ps
T165 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3648034284 Aug 11 06:17:16 PM PDT 24 Aug 11 06:17:19 PM PDT 24 741128762 ps
T118 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1794679210 Aug 11 06:17:00 PM PDT 24 Aug 11 06:17:03 PM PDT 24 426888662 ps
T105 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.704079189 Aug 11 06:17:16 PM PDT 24 Aug 11 06:17:20 PM PDT 24 197349994 ps
T1049 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.115776181 Aug 11 06:17:17 PM PDT 24 Aug 11 06:17:18 PM PDT 24 21109226 ps
T133 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3509797559 Aug 11 06:17:08 PM PDT 24 Aug 11 06:17:10 PM PDT 24 21637834 ps
T1050 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3666471974 Aug 11 06:17:22 PM PDT 24 Aug 11 06:17:24 PM PDT 24 27401999 ps
T1051 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.392931433 Aug 11 06:17:23 PM PDT 24 Aug 11 06:17:26 PM PDT 24 412444010 ps
T1052 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.673568347 Aug 11 06:17:00 PM PDT 24 Aug 11 06:17:15 PM PDT 24 217150064 ps
T108 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2234454217 Aug 11 06:17:16 PM PDT 24 Aug 11 06:17:21 PM PDT 24 71494354 ps
T112 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3210207625 Aug 11 06:17:17 PM PDT 24 Aug 11 06:17:20 PM PDT 24 92178398 ps
T107 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2619081754 Aug 11 06:17:02 PM PDT 24 Aug 11 06:17:07 PM PDT 24 332920691 ps
T1053 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.119864575 Aug 11 06:17:31 PM PDT 24 Aug 11 06:17:32 PM PDT 24 113419730 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2524843573 Aug 11 06:17:04 PM PDT 24 Aug 11 06:17:36 PM PDT 24 3479406465 ps
T1055 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2824209217 Aug 11 06:17:29 PM PDT 24 Aug 11 06:17:29 PM PDT 24 26067495 ps
T166 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3904530175 Aug 11 06:17:15 PM PDT 24 Aug 11 06:17:23 PM PDT 24 629862541 ps
T1056 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.680872946 Aug 11 06:17:38 PM PDT 24 Aug 11 06:17:39 PM PDT 24 16968342 ps
T1057 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3732864553 Aug 11 06:17:16 PM PDT 24 Aug 11 06:17:17 PM PDT 24 13617848 ps
T119 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.682856534 Aug 11 06:17:17 PM PDT 24 Aug 11 06:17:24 PM PDT 24 251226464 ps
T1058 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1337848939 Aug 11 06:17:08 PM PDT 24 Aug 11 06:17:14 PM PDT 24 455880342 ps
T174 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3920305465 Aug 11 06:17:15 PM PDT 24 Aug 11 06:17:37 PM PDT 24 1619294422 ps
T1059 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4200392874 Aug 11 06:17:08 PM PDT 24 Aug 11 06:17:10 PM PDT 24 129671684 ps
T1060 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4025839047 Aug 11 06:17:07 PM PDT 24 Aug 11 06:17:09 PM PDT 24 58869426 ps
T1061 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.991120507 Aug 11 06:17:32 PM PDT 24 Aug 11 06:17:33 PM PDT 24 16085707 ps
T1062 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.71599109 Aug 11 06:17:16 PM PDT 24 Aug 11 06:17:20 PM PDT 24 405058024 ps
T1063 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.481606579 Aug 11 06:17:33 PM PDT 24 Aug 11 06:17:34 PM PDT 24 23264615 ps
T1064 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1795242282 Aug 11 06:17:27 PM PDT 24 Aug 11 06:17:45 PM PDT 24 1171985749 ps
T134 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4247307770 Aug 11 06:17:18 PM PDT 24 Aug 11 06:17:20 PM PDT 24 41361808 ps
T1065 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2080229566 Aug 11 06:17:15 PM PDT 24 Aug 11 06:17:19 PM PDT 24 155526932 ps
T1066 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3002833327 Aug 11 06:17:02 PM PDT 24 Aug 11 06:17:27 PM PDT 24 5011039060 ps
T135 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2681313435 Aug 11 06:17:05 PM PDT 24 Aug 11 06:17:21 PM PDT 24 613895841 ps
T1067 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2335035640 Aug 11 06:17:34 PM PDT 24 Aug 11 06:17:34 PM PDT 24 15140815 ps
T1068 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1544817938 Aug 11 06:17:08 PM PDT 24 Aug 11 06:17:12 PM PDT 24 62302356 ps
T136 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2228163484 Aug 11 06:17:17 PM PDT 24 Aug 11 06:17:19 PM PDT 24 123645366 ps
T1069 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2349302914 Aug 11 06:17:06 PM PDT 24 Aug 11 06:17:10 PM PDT 24 1706408449 ps
T1070 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.407935141 Aug 11 06:17:38 PM PDT 24 Aug 11 06:17:39 PM PDT 24 14842050 ps
T109 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3484657822 Aug 11 06:17:00 PM PDT 24 Aug 11 06:17:04 PM PDT 24 305912688 ps
T137 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3409790576 Aug 11 06:17:06 PM PDT 24 Aug 11 06:17:07 PM PDT 24 32839099 ps
T1071 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.528533919 Aug 11 06:17:06 PM PDT 24 Aug 11 06:17:07 PM PDT 24 137638418 ps
T138 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1062585711 Aug 11 06:17:16 PM PDT 24 Aug 11 06:17:20 PM PDT 24 110524227 ps
T139 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.193240749 Aug 11 06:17:05 PM PDT 24 Aug 11 06:17:07 PM PDT 24 23034089 ps
T1072 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1627604233 Aug 11 06:17:08 PM PDT 24 Aug 11 06:17:11 PM PDT 24 91554304 ps
T1073 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1853873145 Aug 11 06:17:08 PM PDT 24 Aug 11 06:17:10 PM PDT 24 134009033 ps
T167 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3763353571 Aug 11 06:17:15 PM PDT 24 Aug 11 06:17:30 PM PDT 24 8384816935 ps
T110 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3376890306 Aug 11 06:17:25 PM PDT 24 Aug 11 06:17:29 PM PDT 24 707523152 ps
T1074 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1893968920 Aug 11 06:17:14 PM PDT 24 Aug 11 06:17:16 PM PDT 24 641814406 ps
T90 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4189528470 Aug 11 06:17:06 PM PDT 24 Aug 11 06:17:07 PM PDT 24 20816919 ps
T1075 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3654996491 Aug 11 06:17:34 PM PDT 24 Aug 11 06:17:34 PM PDT 24 54716921 ps
T1076 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1882609985 Aug 11 06:17:16 PM PDT 24 Aug 11 06:17:21 PM PDT 24 320459638 ps
T1077 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1418914608 Aug 11 06:17:22 PM PDT 24 Aug 11 06:17:24 PM PDT 24 27842442 ps
T1078 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2717827547 Aug 11 06:17:25 PM PDT 24 Aug 11 06:17:26 PM PDT 24 15997073 ps
T1079 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1826108650 Aug 11 06:17:31 PM PDT 24 Aug 11 06:17:32 PM PDT 24 50230282 ps
T1080 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.449139179 Aug 11 06:17:01 PM PDT 24 Aug 11 06:17:02 PM PDT 24 73580803 ps
T1081 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.723903354 Aug 11 06:17:36 PM PDT 24 Aug 11 06:17:37 PM PDT 24 12501323 ps
T1082 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4147442998 Aug 11 06:17:00 PM PDT 24 Aug 11 06:17:01 PM PDT 24 22180229 ps
T1083 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1742334004 Aug 11 06:17:38 PM PDT 24 Aug 11 06:17:39 PM PDT 24 14501924 ps
T1084 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1211267772 Aug 11 06:17:00 PM PDT 24 Aug 11 06:17:12 PM PDT 24 775111802 ps
T1085 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4079093548 Aug 11 06:17:31 PM PDT 24 Aug 11 06:17:52 PM PDT 24 1680570125 ps
T1086 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3723261617 Aug 11 06:17:20 PM PDT 24 Aug 11 06:17:22 PM PDT 24 120540704 ps
T1087 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.373573815 Aug 11 06:17:33 PM PDT 24 Aug 11 06:17:34 PM PDT 24 30376586 ps
T91 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2407012061 Aug 11 06:17:12 PM PDT 24 Aug 11 06:17:14 PM PDT 24 34732892 ps
T1088 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.18450294 Aug 11 06:17:13 PM PDT 24 Aug 11 06:17:16 PM PDT 24 38734468 ps
T1089 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.830862883 Aug 11 06:17:34 PM PDT 24 Aug 11 06:17:35 PM PDT 24 35699094 ps
T1090 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3369078823 Aug 11 06:17:23 PM PDT 24 Aug 11 06:17:24 PM PDT 24 49399121 ps
T1091 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3073900654 Aug 11 06:16:59 PM PDT 24 Aug 11 06:17:00 PM PDT 24 42017771 ps
T1092 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1796265843 Aug 11 06:17:17 PM PDT 24 Aug 11 06:17:18 PM PDT 24 109459292 ps
T1093 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.393884486 Aug 11 06:17:29 PM PDT 24 Aug 11 06:17:30 PM PDT 24 15094308 ps
T1094 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3336488044 Aug 11 06:17:15 PM PDT 24 Aug 11 06:17:18 PM PDT 24 43814954 ps
T1095 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1399653051 Aug 11 06:17:01 PM PDT 24 Aug 11 06:17:02 PM PDT 24 14219993 ps
T113 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3316293452 Aug 11 06:17:14 PM PDT 24 Aug 11 06:17:17 PM PDT 24 163810305 ps
T1096 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4217598986 Aug 11 06:17:08 PM PDT 24 Aug 11 06:17:12 PM PDT 24 62312566 ps
T1097 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.183869528 Aug 11 06:17:16 PM PDT 24 Aug 11 06:17:35 PM PDT 24 1120556366 ps
T111 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1388165682 Aug 11 06:17:06 PM PDT 24 Aug 11 06:17:11 PM PDT 24 229930405 ps
T1098 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1783986262 Aug 11 06:17:13 PM PDT 24 Aug 11 06:17:14 PM PDT 24 49867923 ps
T117 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4226851441 Aug 11 06:17:23 PM PDT 24 Aug 11 06:17:25 PM PDT 24 28784835 ps
T1099 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1478413049 Aug 11 06:17:15 PM PDT 24 Aug 11 06:17:18 PM PDT 24 74756437 ps
T1100 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.465589072 Aug 11 06:17:16 PM PDT 24 Aug 11 06:17:18 PM PDT 24 297003478 ps
T1101 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1865867859 Aug 11 06:17:07 PM PDT 24 Aug 11 06:17:25 PM PDT 24 570198775 ps
T1102 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2191527005 Aug 11 06:17:06 PM PDT 24 Aug 11 06:17:09 PM PDT 24 72719672 ps
T114 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1646542713 Aug 11 06:17:19 PM PDT 24 Aug 11 06:17:24 PM PDT 24 1901498256 ps
T1103 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3977747059 Aug 11 06:17:12 PM PDT 24 Aug 11 06:17:14 PM PDT 24 176995184 ps
T1104 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4216669550 Aug 11 06:17:33 PM PDT 24 Aug 11 06:17:34 PM PDT 24 32968706 ps
T1105 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1358205299 Aug 11 06:17:02 PM PDT 24 Aug 11 06:17:10 PM PDT 24 112297740 ps
T1106 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4094991494 Aug 11 06:17:08 PM PDT 24 Aug 11 06:17:22 PM PDT 24 936597645 ps
T1107 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4097993276 Aug 11 06:17:32 PM PDT 24 Aug 11 06:17:33 PM PDT 24 49292850 ps
T1108 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4136542597 Aug 11 06:16:58 PM PDT 24 Aug 11 06:17:01 PM PDT 24 206698926 ps
T1109 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1292480876 Aug 11 06:17:25 PM PDT 24 Aug 11 06:17:28 PM PDT 24 254659500 ps
T1110 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2301937977 Aug 11 06:17:05 PM PDT 24 Aug 11 06:17:06 PM PDT 24 13466665 ps
T1111 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3433189856 Aug 11 06:17:25 PM PDT 24 Aug 11 06:17:26 PM PDT 24 56244050 ps
T1112 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3510193027 Aug 11 06:17:25 PM PDT 24 Aug 11 06:17:26 PM PDT 24 198540880 ps
T1113 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4089922356 Aug 11 06:17:17 PM PDT 24 Aug 11 06:17:18 PM PDT 24 40567301 ps
T1114 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1214022073 Aug 11 06:17:10 PM PDT 24 Aug 11 06:17:27 PM PDT 24 296183880 ps
T1115 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1314350373 Aug 11 06:17:08 PM PDT 24 Aug 11 06:17:12 PM PDT 24 163022464 ps
T1116 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.676470548 Aug 11 06:17:32 PM PDT 24 Aug 11 06:17:33 PM PDT 24 30211599 ps
T1117 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.14448177 Aug 11 06:17:15 PM PDT 24 Aug 11 06:17:17 PM PDT 24 160309603 ps
T1118 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4144200575 Aug 11 06:17:26 PM PDT 24 Aug 11 06:17:28 PM PDT 24 73728722 ps
T1119 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.385704961 Aug 11 06:17:25 PM PDT 24 Aug 11 06:17:27 PM PDT 24 134342372 ps
T1120 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2053606709 Aug 11 06:17:07 PM PDT 24 Aug 11 06:17:08 PM PDT 24 34303440 ps
T1121 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1789446060 Aug 11 06:17:02 PM PDT 24 Aug 11 06:17:05 PM PDT 24 1362545382 ps
T1122 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.108365624 Aug 11 06:17:09 PM PDT 24 Aug 11 06:17:11 PM PDT 24 137000120 ps
T115 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4167012620 Aug 11 06:17:06 PM PDT 24 Aug 11 06:17:12 PM PDT 24 834124133 ps
T1123 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1923294287 Aug 11 06:17:08 PM PDT 24 Aug 11 06:17:32 PM PDT 24 2216820756 ps
T1124 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1974410191 Aug 11 06:17:08 PM PDT 24 Aug 11 06:17:16 PM PDT 24 119935898 ps
T1125 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.517034227 Aug 11 06:17:29 PM PDT 24 Aug 11 06:17:30 PM PDT 24 13257436 ps
T1126 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2124228616 Aug 11 06:17:08 PM PDT 24 Aug 11 06:17:10 PM PDT 24 178300465 ps
T1127 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3433307759 Aug 11 06:17:26 PM PDT 24 Aug 11 06:17:28 PM PDT 24 218010869 ps
T1128 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2677257059 Aug 11 06:17:16 PM PDT 24 Aug 11 06:17:19 PM PDT 24 225802896 ps
T1129 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3336149387 Aug 11 06:17:08 PM PDT 24 Aug 11 06:17:09 PM PDT 24 17595436 ps
T1130 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3579431386 Aug 11 06:17:17 PM PDT 24 Aug 11 06:17:19 PM PDT 24 32969771 ps
T1131 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1324254839 Aug 11 06:17:02 PM PDT 24 Aug 11 06:17:05 PM PDT 24 2329834083 ps
T1132 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.893867107 Aug 11 06:17:31 PM PDT 24 Aug 11 06:17:32 PM PDT 24 146796659 ps
T1133 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1898417375 Aug 11 06:17:24 PM PDT 24 Aug 11 06:17:25 PM PDT 24 11867907 ps
T1134 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2397095555 Aug 11 06:17:28 PM PDT 24 Aug 11 06:17:42 PM PDT 24 1064064518 ps
T1135 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1025399071 Aug 11 06:17:53 PM PDT 24 Aug 11 06:17:57 PM PDT 24 68516174 ps
T1136 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3973060297 Aug 11 06:17:02 PM PDT 24 Aug 11 06:17:03 PM PDT 24 26181967 ps
T1137 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1749180967 Aug 11 06:17:17 PM PDT 24 Aug 11 06:17:20 PM PDT 24 109294949 ps
T1138 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1378379282 Aug 11 06:17:31 PM PDT 24 Aug 11 06:17:31 PM PDT 24 25125383 ps
T1139 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.651554123 Aug 11 06:17:24 PM PDT 24 Aug 11 06:17:27 PM PDT 24 42340602 ps
T1140 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.881909895 Aug 11 06:17:17 PM PDT 24 Aug 11 06:17:19 PM PDT 24 31883667 ps
T1141 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3119419760 Aug 11 06:17:17 PM PDT 24 Aug 11 06:17:21 PM PDT 24 318798406 ps
T1142 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1064951698 Aug 11 06:17:29 PM PDT 24 Aug 11 06:17:31 PM PDT 24 56783361 ps
T1143 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3408208351 Aug 11 06:17:15 PM PDT 24 Aug 11 06:17:17 PM PDT 24 104461111 ps
T1144 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3789747805 Aug 11 06:17:23 PM PDT 24 Aug 11 06:17:25 PM PDT 24 40768948 ps
T1145 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1984934821 Aug 11 06:17:16 PM PDT 24 Aug 11 06:17:18 PM PDT 24 95135881 ps
T1146 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4070527907 Aug 11 06:17:22 PM PDT 24 Aug 11 06:17:24 PM PDT 24 22344300 ps
T1147 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3278219612 Aug 11 06:17:08 PM PDT 24 Aug 11 06:17:09 PM PDT 24 37336817 ps
T1148 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2555326968 Aug 11 06:17:33 PM PDT 24 Aug 11 06:17:34 PM PDT 24 15819153 ps
T1149 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3276941139 Aug 11 06:17:26 PM PDT 24 Aug 11 06:17:32 PM PDT 24 1083353302 ps
T1150 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3940374442 Aug 11 06:17:07 PM PDT 24 Aug 11 06:17:08 PM PDT 24 15430804 ps
T1151 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1761218360 Aug 11 06:17:00 PM PDT 24 Aug 11 06:17:02 PM PDT 24 59916576 ps

Test location /workspace/coverage/default/21.spi_device_stress_all.3965191453
Short name T8
Test name
Test status
Simulation time 6873305127 ps
CPU time 101.93 seconds
Started Aug 11 06:19:31 PM PDT 24
Finished Aug 11 06:21:13 PM PDT 24
Peak memory 255264 kb
Host smart-89941dbf-9d2e-45c0-b58a-59b829b537f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965191453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3965191453
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.273380910
Short name T14
Test name
Test status
Simulation time 14329504696 ps
CPU time 162.61 seconds
Started Aug 11 06:18:41 PM PDT 24
Finished Aug 11 06:21:23 PM PDT 24
Peak memory 266336 kb
Host smart-41a4fb8f-6b3e-4254-85dd-f1f6a488e9ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273380910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.273380910
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.713135756
Short name T4
Test name
Test status
Simulation time 17957888621 ps
CPU time 157.95 seconds
Started Aug 11 06:19:18 PM PDT 24
Finished Aug 11 06:21:56 PM PDT 24
Peak memory 249868 kb
Host smart-d1561660-c294-4a95-ade1-ab820264777d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713135756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.713135756
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.891203214
Short name T46
Test name
Test status
Simulation time 66085123928 ps
CPU time 469.57 seconds
Started Aug 11 06:19:25 PM PDT 24
Finished Aug 11 06:27:15 PM PDT 24
Peak memory 257620 kb
Host smart-8567b65a-8904-4ecb-a48b-9f8cf7e85cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891203214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.891203214
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1840331429
Short name T103
Test name
Test status
Simulation time 366605865 ps
CPU time 8.32 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:25 PM PDT 24
Peak memory 216308 kb
Host smart-9fb8a770-09b8-4588-bec3-1828b929d69f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840331429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1840331429
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1338488669
Short name T31
Test name
Test status
Simulation time 785710515546 ps
CPU time 662.57 seconds
Started Aug 11 06:20:00 PM PDT 24
Finished Aug 11 06:31:03 PM PDT 24
Peak memory 265772 kb
Host smart-23a2781b-66ad-4840-91ee-089a029d657a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338488669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1338488669
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.963609589
Short name T74
Test name
Test status
Simulation time 16991063 ps
CPU time 0.74 seconds
Started Aug 11 06:18:03 PM PDT 24
Finished Aug 11 06:18:04 PM PDT 24
Peak memory 216688 kb
Host smart-232c77a1-d306-4fee-88ef-dc696be7ebac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963609589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.963609589
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.678031628
Short name T19
Test name
Test status
Simulation time 108541478592 ps
CPU time 842.64 seconds
Started Aug 11 06:19:08 PM PDT 24
Finished Aug 11 06:33:11 PM PDT 24
Peak memory 274172 kb
Host smart-0f5ea6e5-77ce-4a9c-b81b-33102f7ae84f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678031628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.678031628
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3176012876
Short name T100
Test name
Test status
Simulation time 38737400 ps
CPU time 2.46 seconds
Started Aug 11 06:17:14 PM PDT 24
Finished Aug 11 06:17:17 PM PDT 24
Peak memory 215764 kb
Host smart-0617a928-76de-4f2a-81e0-fe87ef705796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176012876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
176012876
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1116886479
Short name T50
Test name
Test status
Simulation time 185214941441 ps
CPU time 337.28 seconds
Started Aug 11 06:20:26 PM PDT 24
Finished Aug 11 06:26:03 PM PDT 24
Peak memory 257736 kb
Host smart-2c493d9f-972f-4a6f-93db-74de28d2bd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116886479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1116886479
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3445073124
Short name T20
Test name
Test status
Simulation time 76363584913 ps
CPU time 399.28 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:26:26 PM PDT 24
Peak memory 280808 kb
Host smart-9514a291-d6e6-4d95-ace2-5e9a11ae57c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445073124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3445073124
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.630050166
Short name T9
Test name
Test status
Simulation time 1666488670 ps
CPU time 20.19 seconds
Started Aug 11 06:18:16 PM PDT 24
Finished Aug 11 06:18:36 PM PDT 24
Peak memory 240904 kb
Host smart-9ab99c30-1af8-455e-904f-4d3c9c7dcfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630050166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.630050166
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.754448743
Short name T270
Test name
Test status
Simulation time 67407737297 ps
CPU time 719.18 seconds
Started Aug 11 06:19:26 PM PDT 24
Finished Aug 11 06:31:26 PM PDT 24
Peak memory 259972 kb
Host smart-9048b0bb-8ddc-4bed-ba5a-980d46770436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754448743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.754448743
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2892901330
Short name T347
Test name
Test status
Simulation time 25203046 ps
CPU time 0.73 seconds
Started Aug 11 06:18:10 PM PDT 24
Finished Aug 11 06:18:11 PM PDT 24
Peak memory 206252 kb
Host smart-f4a326ec-6f01-4784-a001-4c27f95937ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892901330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
892901330
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.4293803600
Short name T186
Test name
Test status
Simulation time 6644643607 ps
CPU time 113.83 seconds
Started Aug 11 06:18:05 PM PDT 24
Finished Aug 11 06:19:59 PM PDT 24
Peak memory 265444 kb
Host smart-ded8418b-73a0-4a54-9e2f-f4287d1fe01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293803600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.4293803600
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3901800529
Short name T129
Test name
Test status
Simulation time 26747867 ps
CPU time 1.77 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:18 PM PDT 24
Peak memory 207308 kb
Host smart-c76cfe8b-225c-4d4f-a6e3-f3e98d51159d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901800529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3901800529
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3076342433
Short name T58
Test name
Test status
Simulation time 9759912174 ps
CPU time 65.83 seconds
Started Aug 11 06:18:36 PM PDT 24
Finished Aug 11 06:19:42 PM PDT 24
Peak memory 255172 kb
Host smart-64a4de9b-d22f-4d3d-aed3-e0c9657a92dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076342433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3076342433
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1557602305
Short name T200
Test name
Test status
Simulation time 150368811856 ps
CPU time 426.33 seconds
Started Aug 11 06:18:10 PM PDT 24
Finished Aug 11 06:25:16 PM PDT 24
Peak memory 270516 kb
Host smart-e641553e-9cd6-4afe-b265-b218cbc69f3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557602305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1557602305
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2173555189
Short name T217
Test name
Test status
Simulation time 88979252267 ps
CPU time 153.38 seconds
Started Aug 11 06:19:13 PM PDT 24
Finished Aug 11 06:21:47 PM PDT 24
Peak memory 250652 kb
Host smart-978bc28f-ef5e-4794-a6c2-3c1e3b17fd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173555189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2173555189
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2591435287
Short name T12
Test name
Test status
Simulation time 8181896218 ps
CPU time 82.11 seconds
Started Aug 11 06:20:45 PM PDT 24
Finished Aug 11 06:22:07 PM PDT 24
Peak memory 257348 kb
Host smart-a1577084-c5b6-41dc-b3b7-ea7eb4368e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591435287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2591435287
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1430881496
Short name T679
Test name
Test status
Simulation time 168187386 ps
CPU time 1.08 seconds
Started Aug 11 06:18:03 PM PDT 24
Finished Aug 11 06:18:04 PM PDT 24
Peak memory 217224 kb
Host smart-07cd1323-6342-4d13-9cf6-0df3a4536567
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430881496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1430881496
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3184535550
Short name T285
Test name
Test status
Simulation time 49756722797 ps
CPU time 198.23 seconds
Started Aug 11 06:19:28 PM PDT 24
Finished Aug 11 06:22:47 PM PDT 24
Peak memory 265488 kb
Host smart-dd8ed117-9fcb-42d7-a56c-4537ea3050be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184535550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3184535550
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.507907828
Short name T37
Test name
Test status
Simulation time 92988156362 ps
CPU time 313.15 seconds
Started Aug 11 06:20:56 PM PDT 24
Finished Aug 11 06:26:09 PM PDT 24
Peak memory 252368 kb
Host smart-a26e304d-63aa-441b-b233-88292b93c406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507907828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.507907828
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1466710471
Short name T78
Test name
Test status
Simulation time 366712274 ps
CPU time 1.23 seconds
Started Aug 11 06:18:02 PM PDT 24
Finished Aug 11 06:18:03 PM PDT 24
Peak memory 235604 kb
Host smart-06b77402-9544-4deb-96e0-5c68f5161621
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466710471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1466710471
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.750022153
Short name T216
Test name
Test status
Simulation time 45698325116 ps
CPU time 447.31 seconds
Started Aug 11 06:20:47 PM PDT 24
Finished Aug 11 06:28:15 PM PDT 24
Peak memory 282100 kb
Host smart-d9e96f9d-944c-4ef5-83a3-de2729e87b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750022153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.750022153
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.711362040
Short name T104
Test name
Test status
Simulation time 138425176 ps
CPU time 2.53 seconds
Started Aug 11 06:17:29 PM PDT 24
Finished Aug 11 06:17:32 PM PDT 24
Peak memory 215832 kb
Host smart-383e2993-6053-45f4-bc2e-e45e8ad6b238
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711362040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.711362040
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1102782755
Short name T98
Test name
Test status
Simulation time 1350673410 ps
CPU time 19.47 seconds
Started Aug 11 06:17:17 PM PDT 24
Finished Aug 11 06:17:37 PM PDT 24
Peak memory 215648 kb
Host smart-64a565fd-649f-4935-bb16-84625c1c6ba4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102782755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1102782755
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.491136652
Short name T295
Test name
Test status
Simulation time 306639110354 ps
CPU time 522.64 seconds
Started Aug 11 06:18:46 PM PDT 24
Finished Aug 11 06:27:29 PM PDT 24
Peak memory 253544 kb
Host smart-f39037d5-1242-4a79-832a-e5edfb274b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491136652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.491136652
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.210917092
Short name T189
Test name
Test status
Simulation time 16960255819 ps
CPU time 166.02 seconds
Started Aug 11 06:18:01 PM PDT 24
Finished Aug 11 06:20:47 PM PDT 24
Peak memory 233564 kb
Host smart-e0d9397b-2fac-4f03-96ea-0e00f42b1a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210917092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
210917092
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2952763194
Short name T284
Test name
Test status
Simulation time 38419004057 ps
CPU time 312.47 seconds
Started Aug 11 06:18:47 PM PDT 24
Finished Aug 11 06:23:59 PM PDT 24
Peak memory 265388 kb
Host smart-75f4aaa5-1a26-43a9-9f51-d06416ddd297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952763194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2952763194
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1641419787
Short name T196
Test name
Test status
Simulation time 86339234735 ps
CPU time 199.69 seconds
Started Aug 11 06:19:03 PM PDT 24
Finished Aug 11 06:22:23 PM PDT 24
Peak memory 249920 kb
Host smart-440ab101-f388-475c-9030-b1771fe5dcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641419787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1641419787
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.166568430
Short name T266
Test name
Test status
Simulation time 12431295245 ps
CPU time 181.19 seconds
Started Aug 11 06:20:14 PM PDT 24
Finished Aug 11 06:23:15 PM PDT 24
Peak memory 251492 kb
Host smart-95684ba1-284c-434c-930f-3d01361a8bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166568430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.166568430
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4079093548
Short name T1085
Test name
Test status
Simulation time 1680570125 ps
CPU time 21.65 seconds
Started Aug 11 06:17:31 PM PDT 24
Finished Aug 11 06:17:52 PM PDT 24
Peak memory 215548 kb
Host smart-536dee64-05bb-40de-8876-eac244be286a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079093548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.4079093548
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.13538244
Short name T161
Test name
Test status
Simulation time 253846805 ps
CPU time 13.7 seconds
Started Aug 11 06:19:14 PM PDT 24
Finished Aug 11 06:19:28 PM PDT 24
Peak memory 234512 kb
Host smart-d2854c2d-f414-42fd-b11c-b4f45cd1aef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13538244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.13538244
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2753292851
Short name T282
Test name
Test status
Simulation time 92376536365 ps
CPU time 253 seconds
Started Aug 11 06:20:04 PM PDT 24
Finished Aug 11 06:24:17 PM PDT 24
Peak memory 250996 kb
Host smart-c87b49af-a127-4193-a303-daa618228311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753292851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2753292851
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2989864941
Short name T6
Test name
Test status
Simulation time 536998651 ps
CPU time 6.15 seconds
Started Aug 11 06:18:58 PM PDT 24
Finished Aug 11 06:19:04 PM PDT 24
Peak memory 225272 kb
Host smart-08640191-40df-4477-be37-e1dc91e94dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989864941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2989864941
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3575321929
Short name T191
Test name
Test status
Simulation time 63114187788 ps
CPU time 193.34 seconds
Started Aug 11 06:18:54 PM PDT 24
Finished Aug 11 06:22:07 PM PDT 24
Peak memory 249944 kb
Host smart-49bc99c0-6500-4c07-98e3-8c91701d7fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575321929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3575321929
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1114136309
Short name T184
Test name
Test status
Simulation time 3581083288 ps
CPU time 75.58 seconds
Started Aug 11 06:19:16 PM PDT 24
Finished Aug 11 06:20:32 PM PDT 24
Peak memory 254644 kb
Host smart-e42144f3-efa0-4191-acf7-0a2a5b34d257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114136309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1114136309
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4226851441
Short name T117
Test name
Test status
Simulation time 28784835 ps
CPU time 1.56 seconds
Started Aug 11 06:17:23 PM PDT 24
Finished Aug 11 06:17:25 PM PDT 24
Peak memory 215708 kb
Host smart-5fa62e1f-bc51-48e0-a15c-1eb7532762fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226851441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4226851441
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.218399603
Short name T759
Test name
Test status
Simulation time 9207434791 ps
CPU time 40.91 seconds
Started Aug 11 06:18:04 PM PDT 24
Finished Aug 11 06:18:45 PM PDT 24
Peak memory 240544 kb
Host smart-1cf358ea-c28c-4c52-b236-a5eb3126a00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218399603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.218399603
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.539331468
Short name T168
Test name
Test status
Simulation time 11369857509 ps
CPU time 56.67 seconds
Started Aug 11 06:18:11 PM PDT 24
Finished Aug 11 06:19:08 PM PDT 24
Peak memory 251680 kb
Host smart-e0ccbbdb-4919-4529-9c93-10f602c5f5fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539331468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.539331468
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3251671007
Short name T305
Test name
Test status
Simulation time 9094079737 ps
CPU time 29.5 seconds
Started Aug 11 06:18:38 PM PDT 24
Finished Aug 11 06:19:07 PM PDT 24
Peak memory 217308 kb
Host smart-e25fa196-d06b-463d-bb6d-1dad4bdf70a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251671007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3251671007
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1019905092
Short name T869
Test name
Test status
Simulation time 3552702178 ps
CPU time 8.78 seconds
Started Aug 11 06:19:01 PM PDT 24
Finished Aug 11 06:19:10 PM PDT 24
Peak memory 241536 kb
Host smart-ec8d5323-c1ec-428e-ba7c-2ffe87b4e551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019905092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1019905092
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3522285396
Short name T784
Test name
Test status
Simulation time 18880126079 ps
CPU time 158.42 seconds
Started Aug 11 06:19:04 PM PDT 24
Finished Aug 11 06:21:43 PM PDT 24
Peak memory 255012 kb
Host smart-fbec7592-7ca9-4b48-9326-568663f2846c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522285396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3522285396
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2462659718
Short name T187
Test name
Test status
Simulation time 185274808105 ps
CPU time 510.13 seconds
Started Aug 11 06:19:15 PM PDT 24
Finished Aug 11 06:27:45 PM PDT 24
Peak memory 252780 kb
Host smart-b4befbae-3be4-4d67-8134-e65e2f7e6730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462659718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2462659718
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3345496929
Short name T451
Test name
Test status
Simulation time 186849127 ps
CPU time 2.9 seconds
Started Aug 11 06:18:13 PM PDT 24
Finished Aug 11 06:18:16 PM PDT 24
Peak memory 233404 kb
Host smart-4ca4363c-ab57-4d32-9234-76897ac15d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345496929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3345496929
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3618834010
Short name T316
Test name
Test status
Simulation time 11462996600 ps
CPU time 24.26 seconds
Started Aug 11 06:20:02 PM PDT 24
Finished Aug 11 06:20:27 PM PDT 24
Peak memory 224528 kb
Host smart-6db2139c-971b-42c5-b46a-d326cd273cda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618834010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3618834010
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.621655182
Short name T481
Test name
Test status
Simulation time 3019971542 ps
CPU time 16.1 seconds
Started Aug 11 06:18:11 PM PDT 24
Finished Aug 11 06:18:28 PM PDT 24
Peak memory 225444 kb
Host smart-d78bcfe1-7e19-4f4d-a1a2-87d19ba3cb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621655182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
621655182
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3484657822
Short name T109
Test name
Test status
Simulation time 305912688 ps
CPU time 4.03 seconds
Started Aug 11 06:17:00 PM PDT 24
Finished Aug 11 06:17:04 PM PDT 24
Peak memory 215716 kb
Host smart-5be801cc-7c1a-4a6b-8533-0e75f781b175
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484657822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
484657822
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3556732591
Short name T89
Test name
Test status
Simulation time 47713827 ps
CPU time 1.42 seconds
Started Aug 11 06:16:59 PM PDT 24
Finished Aug 11 06:17:00 PM PDT 24
Peak memory 207332 kb
Host smart-21fc3de7-a7aa-477d-8de4-5847d6e771c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556732591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3556732591
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.673568347
Short name T1052
Test name
Test status
Simulation time 217150064 ps
CPU time 14.8 seconds
Started Aug 11 06:17:00 PM PDT 24
Finished Aug 11 06:17:15 PM PDT 24
Peak memory 215592 kb
Host smart-2b50a71b-c1b3-43c9-8f49-1d852fce13f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673568347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.673568347
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3002833327
Short name T1066
Test name
Test status
Simulation time 5011039060 ps
CPU time 25.52 seconds
Started Aug 11 06:17:02 PM PDT 24
Finished Aug 11 06:17:27 PM PDT 24
Peak memory 207476 kb
Host smart-e2675f92-fc48-4928-9107-29d77c4e5fab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002833327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3002833327
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1669056498
Short name T120
Test name
Test status
Simulation time 77356632 ps
CPU time 2.72 seconds
Started Aug 11 06:17:00 PM PDT 24
Finished Aug 11 06:17:02 PM PDT 24
Peak memory 217848 kb
Host smart-454cf9b8-8e19-4ac1-b711-e2534c429796
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669056498 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1669056498
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1789446060
Short name T1121
Test name
Test status
Simulation time 1362545382 ps
CPU time 2.8 seconds
Started Aug 11 06:17:02 PM PDT 24
Finished Aug 11 06:17:05 PM PDT 24
Peak memory 215524 kb
Host smart-2ff287d3-8952-43f3-a78d-497022cff344
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789446060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
789446060
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.449139179
Short name T1080
Test name
Test status
Simulation time 73580803 ps
CPU time 0.75 seconds
Started Aug 11 06:17:01 PM PDT 24
Finished Aug 11 06:17:02 PM PDT 24
Peak memory 204268 kb
Host smart-c4d5392a-33a8-485f-8ee0-62b586a55aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449139179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.449139179
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3409790576
Short name T137
Test name
Test status
Simulation time 32839099 ps
CPU time 1.32 seconds
Started Aug 11 06:17:06 PM PDT 24
Finished Aug 11 06:17:07 PM PDT 24
Peak memory 215576 kb
Host smart-370e8d5a-a723-425f-b4f2-5c053dcb88e8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409790576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3409790576
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3073900654
Short name T1091
Test name
Test status
Simulation time 42017771 ps
CPU time 0.65 seconds
Started Aug 11 06:16:59 PM PDT 24
Finished Aug 11 06:17:00 PM PDT 24
Peak memory 203904 kb
Host smart-959b16ce-42f6-445f-b950-514a6f721fd6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073900654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3073900654
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4136542597
Short name T1108
Test name
Test status
Simulation time 206698926 ps
CPU time 2.77 seconds
Started Aug 11 06:16:58 PM PDT 24
Finished Aug 11 06:17:01 PM PDT 24
Peak memory 215456 kb
Host smart-38a03b50-ca27-47cd-a88b-d67d67f87c4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136542597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.4136542597
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2619081754
Short name T107
Test name
Test status
Simulation time 332920691 ps
CPU time 4.76 seconds
Started Aug 11 06:17:02 PM PDT 24
Finished Aug 11 06:17:07 PM PDT 24
Peak memory 215816 kb
Host smart-2cde0dd3-c648-489f-9f20-515cf3e600e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619081754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
619081754
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2960286851
Short name T101
Test name
Test status
Simulation time 3251338882 ps
CPU time 19.25 seconds
Started Aug 11 06:17:00 PM PDT 24
Finished Aug 11 06:17:19 PM PDT 24
Peak memory 215624 kb
Host smart-4ecb7b08-ac6c-43be-ba06-df689cf03c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960286851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2960286851
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1358205299
Short name T1105
Test name
Test status
Simulation time 112297740 ps
CPU time 7.87 seconds
Started Aug 11 06:17:02 PM PDT 24
Finished Aug 11 06:17:10 PM PDT 24
Peak memory 207360 kb
Host smart-50c88fba-d8c9-4226-8d09-40f467680244
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358205299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1358205299
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1211267772
Short name T1084
Test name
Test status
Simulation time 775111802 ps
CPU time 12.13 seconds
Started Aug 11 06:17:00 PM PDT 24
Finished Aug 11 06:17:12 PM PDT 24
Peak memory 207312 kb
Host smart-7858d119-c180-4847-ba82-522e1273b777
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211267772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1211267772
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4147442998
Short name T1082
Test name
Test status
Simulation time 22180229 ps
CPU time 0.94 seconds
Started Aug 11 06:17:00 PM PDT 24
Finished Aug 11 06:17:01 PM PDT 24
Peak memory 207132 kb
Host smart-4dc1fe51-870f-4f49-bc6d-b15cbb4e1198
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147442998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.4147442998
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1794679210
Short name T118
Test name
Test status
Simulation time 426888662 ps
CPU time 2.81 seconds
Started Aug 11 06:17:00 PM PDT 24
Finished Aug 11 06:17:03 PM PDT 24
Peak memory 216920 kb
Host smart-45ef80d7-3b88-4be3-9264-4adcda6ecfb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794679210 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1794679210
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3418920289
Short name T132
Test name
Test status
Simulation time 434995522 ps
CPU time 2.62 seconds
Started Aug 11 06:17:02 PM PDT 24
Finished Aug 11 06:17:05 PM PDT 24
Peak memory 215520 kb
Host smart-024300e5-7021-42cf-99ed-b39514a039dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418920289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
418920289
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3712311873
Short name T1035
Test name
Test status
Simulation time 13158795 ps
CPU time 0.73 seconds
Started Aug 11 06:16:58 PM PDT 24
Finished Aug 11 06:16:58 PM PDT 24
Peak memory 204032 kb
Host smart-e96b4b3c-a4fc-4cdc-bf64-1599c1fa96e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712311873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
712311873
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.378056027
Short name T130
Test name
Test status
Simulation time 197444523 ps
CPU time 2.29 seconds
Started Aug 11 06:17:00 PM PDT 24
Finished Aug 11 06:17:02 PM PDT 24
Peak memory 215588 kb
Host smart-5ded320e-5f4d-45e2-a80e-eb3fca70db08
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378056027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.378056027
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1669726164
Short name T1044
Test name
Test status
Simulation time 13409619 ps
CPU time 0.67 seconds
Started Aug 11 06:17:00 PM PDT 24
Finished Aug 11 06:17:01 PM PDT 24
Peak memory 203888 kb
Host smart-cf358c89-48b4-48fa-a983-5cd248a2ae34
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669726164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1669726164
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1761218360
Short name T1151
Test name
Test status
Simulation time 59916576 ps
CPU time 1.91 seconds
Started Aug 11 06:17:00 PM PDT 24
Finished Aug 11 06:17:02 PM PDT 24
Peak memory 207300 kb
Host smart-c948131d-f83d-46bc-92a5-9223a7ac6d7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761218360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1761218360
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1518958607
Short name T128
Test name
Test status
Simulation time 2509466769 ps
CPU time 15.59 seconds
Started Aug 11 06:16:59 PM PDT 24
Finished Aug 11 06:17:15 PM PDT 24
Peak memory 216192 kb
Host smart-b99ad715-e3ef-4b03-97e0-dbd51e141399
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518958607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1518958607
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3336488044
Short name T1094
Test name
Test status
Simulation time 43814954 ps
CPU time 2.83 seconds
Started Aug 11 06:17:15 PM PDT 24
Finished Aug 11 06:17:18 PM PDT 24
Peak memory 217236 kb
Host smart-43e0705f-adbf-4be8-9bd3-17da193af239
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336488044 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3336488044
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.343724102
Short name T1037
Test name
Test status
Simulation time 13546390 ps
CPU time 0.71 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:18 PM PDT 24
Peak memory 203872 kb
Host smart-03c8a837-90a5-49bb-b7d6-2d8f493ba8a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343724102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.343724102
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.71599109
Short name T1062
Test name
Test status
Simulation time 405058024 ps
CPU time 2.92 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:20 PM PDT 24
Peak memory 215996 kb
Host smart-de6d3130-a35a-4261-91ee-4325067efe66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71599109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sp
i_device_same_csr_outstanding.71599109
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1882609985
Short name T1076
Test name
Test status
Simulation time 320459638 ps
CPU time 3.84 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:21 PM PDT 24
Peak memory 215780 kb
Host smart-2262b3d5-7cac-40f4-977a-7ffdf7c741c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882609985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1882609985
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3763353571
Short name T167
Test name
Test status
Simulation time 8384816935 ps
CPU time 14.9 seconds
Started Aug 11 06:17:15 PM PDT 24
Finished Aug 11 06:17:30 PM PDT 24
Peak memory 215764 kb
Host smart-1af8f80d-09f8-46b4-9215-8a0bdcb81b59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763353571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3763353571
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.901671902
Short name T102
Test name
Test status
Simulation time 693409607 ps
CPU time 1.67 seconds
Started Aug 11 06:17:17 PM PDT 24
Finished Aug 11 06:17:19 PM PDT 24
Peak memory 215664 kb
Host smart-e7b56b3c-0f24-4c9e-ab59-5842a144e05f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901671902 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.901671902
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3723261617
Short name T1086
Test name
Test status
Simulation time 120540704 ps
CPU time 1.95 seconds
Started Aug 11 06:17:20 PM PDT 24
Finished Aug 11 06:17:22 PM PDT 24
Peak memory 215532 kb
Host smart-3492d786-6d00-4874-9d8e-4e3537ef4d81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723261617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3723261617
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3421681940
Short name T1042
Test name
Test status
Simulation time 17245287 ps
CPU time 0.76 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:17 PM PDT 24
Peak memory 204040 kb
Host smart-4563d6e1-89d7-4060-b36e-f4e309914372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421681940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3421681940
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3119419760
Short name T1141
Test name
Test status
Simulation time 318798406 ps
CPU time 4 seconds
Started Aug 11 06:17:17 PM PDT 24
Finished Aug 11 06:17:21 PM PDT 24
Peak memory 215576 kb
Host smart-2723ed82-2092-472c-8ba7-38cea35d49c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119419760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3119419760
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2234454217
Short name T108
Test name
Test status
Simulation time 71494354 ps
CPU time 4.52 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:21 PM PDT 24
Peak memory 215764 kb
Host smart-2f1e922c-d231-421e-8cd7-8a0b850f961c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234454217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2234454217
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3920305465
Short name T174
Test name
Test status
Simulation time 1619294422 ps
CPU time 20.94 seconds
Started Aug 11 06:17:15 PM PDT 24
Finished Aug 11 06:17:37 PM PDT 24
Peak memory 215612 kb
Host smart-3d6edbda-90e9-4329-ba94-05f144580fd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920305465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3920305465
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.18450294
Short name T1088
Test name
Test status
Simulation time 38734468 ps
CPU time 2.82 seconds
Started Aug 11 06:17:13 PM PDT 24
Finished Aug 11 06:17:16 PM PDT 24
Peak memory 217332 kb
Host smart-270f7b44-640a-4c58-adac-e25e413dc731
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18450294 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.18450294
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4247307770
Short name T134
Test name
Test status
Simulation time 41361808 ps
CPU time 2.54 seconds
Started Aug 11 06:17:18 PM PDT 24
Finished Aug 11 06:17:20 PM PDT 24
Peak memory 215516 kb
Host smart-e5cf5620-5bd7-47f1-abec-0a5e801ea4a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247307770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4247307770
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4089922356
Short name T1113
Test name
Test status
Simulation time 40567301 ps
CPU time 0.71 seconds
Started Aug 11 06:17:17 PM PDT 24
Finished Aug 11 06:17:18 PM PDT 24
Peak memory 203976 kb
Host smart-3b9db55b-6b91-4952-bb49-65eb0ee51f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089922356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
4089922356
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2713227179
Short name T153
Test name
Test status
Simulation time 245661078 ps
CPU time 1.79 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:18 PM PDT 24
Peak memory 215552 kb
Host smart-db35996b-95b0-4ca0-8a5a-0266a7d1f258
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713227179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2713227179
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.14448177
Short name T1117
Test name
Test status
Simulation time 160309603 ps
CPU time 1.5 seconds
Started Aug 11 06:17:15 PM PDT 24
Finished Aug 11 06:17:17 PM PDT 24
Peak memory 216728 kb
Host smart-22b9f535-026a-42b9-afb6-c0d929f0adfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14448177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.14448177
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3904530175
Short name T166
Test name
Test status
Simulation time 629862541 ps
CPU time 7.33 seconds
Started Aug 11 06:17:15 PM PDT 24
Finished Aug 11 06:17:23 PM PDT 24
Peak memory 216788 kb
Host smart-2f9d109a-75dc-4544-a578-c2050736a884
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904530175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3904530175
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.704079189
Short name T105
Test name
Test status
Simulation time 197349994 ps
CPU time 3.41 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:20 PM PDT 24
Peak memory 217316 kb
Host smart-8ce7147c-9c1f-4e58-bdfa-33b1dc2c9170
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704079189 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.704079189
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2228163484
Short name T136
Test name
Test status
Simulation time 123645366 ps
CPU time 1.37 seconds
Started Aug 11 06:17:17 PM PDT 24
Finished Aug 11 06:17:19 PM PDT 24
Peak memory 207584 kb
Host smart-89745602-c3d4-4a54-a761-4a50db21e071
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228163484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2228163484
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1783986262
Short name T1098
Test name
Test status
Simulation time 49867923 ps
CPU time 0.75 seconds
Started Aug 11 06:17:13 PM PDT 24
Finished Aug 11 06:17:14 PM PDT 24
Peak memory 204396 kb
Host smart-7f89a450-f557-4979-973d-84536871367c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783986262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1783986262
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3648034284
Short name T165
Test name
Test status
Simulation time 741128762 ps
CPU time 3.11 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:19 PM PDT 24
Peak memory 215572 kb
Host smart-eb59d053-0a4c-409c-b03f-bfd67ee8c5b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648034284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3648034284
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3210207625
Short name T112
Test name
Test status
Simulation time 92178398 ps
CPU time 2.43 seconds
Started Aug 11 06:17:17 PM PDT 24
Finished Aug 11 06:17:20 PM PDT 24
Peak memory 215760 kb
Host smart-683701e9-4617-4ebc-ae31-654c3e584b21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210207625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3210207625
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3384194517
Short name T121
Test name
Test status
Simulation time 1423852565 ps
CPU time 17.61 seconds
Started Aug 11 06:17:17 PM PDT 24
Finished Aug 11 06:17:35 PM PDT 24
Peak memory 215780 kb
Host smart-d7864b5d-5677-4059-9171-fe658c600b66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384194517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3384194517
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.651554123
Short name T1139
Test name
Test status
Simulation time 42340602 ps
CPU time 3.08 seconds
Started Aug 11 06:17:24 PM PDT 24
Finished Aug 11 06:17:27 PM PDT 24
Peak memory 217608 kb
Host smart-bc9cb6ac-623f-41b4-a28a-2b538d9edf10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651554123 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.651554123
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4003584140
Short name T131
Test name
Test status
Simulation time 94259477 ps
CPU time 2.56 seconds
Started Aug 11 06:17:26 PM PDT 24
Finished Aug 11 06:17:28 PM PDT 24
Peak memory 215584 kb
Host smart-96cbc1bc-46f2-46ee-ba1a-68e6b35eca93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003584140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4003584140
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3732864553
Short name T1057
Test name
Test status
Simulation time 13617848 ps
CPU time 0.68 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:17 PM PDT 24
Peak memory 203996 kb
Host smart-5d036065-9ac8-4ed1-8730-c4855e457acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732864553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3732864553
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.385704961
Short name T1119
Test name
Test status
Simulation time 134342372 ps
CPU time 1.88 seconds
Started Aug 11 06:17:25 PM PDT 24
Finished Aug 11 06:17:27 PM PDT 24
Peak memory 215528 kb
Host smart-6194c49a-ef0e-4791-b15e-3d8d4c31254e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385704961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.385704961
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1646542713
Short name T114
Test name
Test status
Simulation time 1901498256 ps
CPU time 4.59 seconds
Started Aug 11 06:17:19 PM PDT 24
Finished Aug 11 06:17:24 PM PDT 24
Peak memory 215740 kb
Host smart-2d5ea62f-fa83-49e9-9262-b712f87eeb3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646542713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1646542713
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.183869528
Short name T1097
Test name
Test status
Simulation time 1120556366 ps
CPU time 17.77 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:35 PM PDT 24
Peak memory 215532 kb
Host smart-e8f66a7b-8999-42af-905f-3bd0d245fd63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183869528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.183869528
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3433307759
Short name T1127
Test name
Test status
Simulation time 218010869 ps
CPU time 1.72 seconds
Started Aug 11 06:17:26 PM PDT 24
Finished Aug 11 06:17:28 PM PDT 24
Peak memory 215600 kb
Host smart-153a8fc5-8c26-441a-be62-30b3f6732f83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433307759 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3433307759
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3789747805
Short name T1144
Test name
Test status
Simulation time 40768948 ps
CPU time 2.37 seconds
Started Aug 11 06:17:23 PM PDT 24
Finished Aug 11 06:17:25 PM PDT 24
Peak memory 207400 kb
Host smart-cce15c84-ae77-4c98-84bc-11c912eae01b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789747805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3789747805
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3433189856
Short name T1111
Test name
Test status
Simulation time 56244050 ps
CPU time 0.74 seconds
Started Aug 11 06:17:25 PM PDT 24
Finished Aug 11 06:17:26 PM PDT 24
Peak memory 204192 kb
Host smart-49b663eb-00a2-4c7c-91be-ba8446ce0b11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433189856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3433189856
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1612807934
Short name T157
Test name
Test status
Simulation time 523922616 ps
CPU time 2.85 seconds
Started Aug 11 06:17:25 PM PDT 24
Finished Aug 11 06:17:27 PM PDT 24
Peak memory 215588 kb
Host smart-31f94896-ed92-45ae-be56-c4515a4ba515
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612807934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1612807934
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2397095555
Short name T1134
Test name
Test status
Simulation time 1064064518 ps
CPU time 14.08 seconds
Started Aug 11 06:17:28 PM PDT 24
Finished Aug 11 06:17:42 PM PDT 24
Peak memory 217752 kb
Host smart-af90609b-1a74-4155-b284-f0e2e91f71d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397095555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2397095555
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1292480876
Short name T1109
Test name
Test status
Simulation time 254659500 ps
CPU time 2.53 seconds
Started Aug 11 06:17:25 PM PDT 24
Finished Aug 11 06:17:28 PM PDT 24
Peak memory 216996 kb
Host smart-35a7943d-95e0-4e25-ba1c-0e3073803130
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292480876 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1292480876
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4070527907
Short name T1146
Test name
Test status
Simulation time 22344300 ps
CPU time 1.3 seconds
Started Aug 11 06:17:22 PM PDT 24
Finished Aug 11 06:17:24 PM PDT 24
Peak memory 207260 kb
Host smart-d8abb695-5272-4e04-8716-1673f28361d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070527907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4070527907
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.347308933
Short name T1047
Test name
Test status
Simulation time 42123062 ps
CPU time 0.71 seconds
Started Aug 11 06:17:25 PM PDT 24
Finished Aug 11 06:17:26 PM PDT 24
Peak memory 204000 kb
Host smart-a6e4cf25-5229-42fe-afd3-63b4bab29eb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347308933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.347308933
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.392931433
Short name T1051
Test name
Test status
Simulation time 412444010 ps
CPU time 2.93 seconds
Started Aug 11 06:17:23 PM PDT 24
Finished Aug 11 06:17:26 PM PDT 24
Peak memory 215512 kb
Host smart-f28c6ef9-5f7f-4548-be8c-75401c4f2747
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392931433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.392931433
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3376890306
Short name T110
Test name
Test status
Simulation time 707523152 ps
CPU time 4.14 seconds
Started Aug 11 06:17:25 PM PDT 24
Finished Aug 11 06:17:29 PM PDT 24
Peak memory 216784 kb
Host smart-b53b0b7b-5a58-4380-bcb2-b5116daf33ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376890306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3376890306
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1153622061
Short name T124
Test name
Test status
Simulation time 102540234 ps
CPU time 6.82 seconds
Started Aug 11 06:17:26 PM PDT 24
Finished Aug 11 06:17:33 PM PDT 24
Peak memory 215616 kb
Host smart-0e81acce-3ac7-42c5-b366-7c8f5d5c7c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153622061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1153622061
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1064951698
Short name T1142
Test name
Test status
Simulation time 56783361 ps
CPU time 1.87 seconds
Started Aug 11 06:17:29 PM PDT 24
Finished Aug 11 06:17:31 PM PDT 24
Peak memory 215664 kb
Host smart-8aa806dd-bae3-49d0-8e73-d77317c40521
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064951698 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1064951698
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.348380262
Short name T156
Test name
Test status
Simulation time 77272248 ps
CPU time 2.3 seconds
Started Aug 11 06:17:29 PM PDT 24
Finished Aug 11 06:17:31 PM PDT 24
Peak memory 215552 kb
Host smart-ec7318f2-4776-476a-9189-03d64a259274
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348380262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.348380262
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3510193027
Short name T1112
Test name
Test status
Simulation time 198540880 ps
CPU time 0.71 seconds
Started Aug 11 06:17:25 PM PDT 24
Finished Aug 11 06:17:26 PM PDT 24
Peak memory 204032 kb
Host smart-ae750751-844e-42e3-9cc8-6b6d34c16e96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510193027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3510193027
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4144200575
Short name T1118
Test name
Test status
Simulation time 73728722 ps
CPU time 1.81 seconds
Started Aug 11 06:17:26 PM PDT 24
Finished Aug 11 06:17:28 PM PDT 24
Peak memory 215532 kb
Host smart-b968a49d-04f4-4d85-b479-821d6b18c19d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144200575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.4144200575
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4117789979
Short name T126
Test name
Test status
Simulation time 13112174301 ps
CPU time 21.6 seconds
Started Aug 11 06:17:25 PM PDT 24
Finished Aug 11 06:17:47 PM PDT 24
Peak memory 215708 kb
Host smart-3db23723-ea26-4660-b3a4-5003d72648f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117789979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.4117789979
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1418914608
Short name T1077
Test name
Test status
Simulation time 27842442 ps
CPU time 1.86 seconds
Started Aug 11 06:17:22 PM PDT 24
Finished Aug 11 06:17:24 PM PDT 24
Peak memory 216612 kb
Host smart-2c90794b-711e-49e5-b734-cc9df6f03e61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418914608 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1418914608
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.893867107
Short name T1132
Test name
Test status
Simulation time 146796659 ps
CPU time 1.38 seconds
Started Aug 11 06:17:31 PM PDT 24
Finished Aug 11 06:17:32 PM PDT 24
Peak memory 215520 kb
Host smart-e6e71d1c-9ab5-43ae-9357-5eb35ff46649
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893867107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.893867107
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.287502061
Short name T1032
Test name
Test status
Simulation time 33992470 ps
CPU time 0.69 seconds
Started Aug 11 06:17:26 PM PDT 24
Finished Aug 11 06:17:27 PM PDT 24
Peak memory 204048 kb
Host smart-7e7343da-d6f9-45fa-b4d8-a1d88546369d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287502061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.287502061
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1072467053
Short name T154
Test name
Test status
Simulation time 202947962 ps
CPU time 4.35 seconds
Started Aug 11 06:17:28 PM PDT 24
Finished Aug 11 06:17:33 PM PDT 24
Peak memory 215488 kb
Host smart-9d226681-8b62-409e-9e03-9c34844d95ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072467053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1072467053
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3276941139
Short name T1149
Test name
Test status
Simulation time 1083353302 ps
CPU time 6.06 seconds
Started Aug 11 06:17:26 PM PDT 24
Finished Aug 11 06:17:32 PM PDT 24
Peak memory 215872 kb
Host smart-1cdd7d17-0555-4400-8912-318a1539ae31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276941139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3276941139
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1795242282
Short name T1064
Test name
Test status
Simulation time 1171985749 ps
CPU time 17.54 seconds
Started Aug 11 06:17:27 PM PDT 24
Finished Aug 11 06:17:45 PM PDT 24
Peak memory 215604 kb
Host smart-27e65647-ca74-4030-acd3-588993a73a21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795242282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1795242282
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3666471974
Short name T1050
Test name
Test status
Simulation time 27401999 ps
CPU time 1.75 seconds
Started Aug 11 06:17:22 PM PDT 24
Finished Aug 11 06:17:24 PM PDT 24
Peak memory 216672 kb
Host smart-7907cf81-42a6-453a-9c4f-1d49b0d026db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666471974 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3666471974
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1652460798
Short name T1043
Test name
Test status
Simulation time 151326927 ps
CPU time 1.38 seconds
Started Aug 11 06:17:25 PM PDT 24
Finished Aug 11 06:17:26 PM PDT 24
Peak memory 207232 kb
Host smart-1156ec4b-d202-408b-a842-9284f155dc6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652460798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1652460798
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4210722220
Short name T1033
Test name
Test status
Simulation time 15178927 ps
CPU time 0.72 seconds
Started Aug 11 06:17:25 PM PDT 24
Finished Aug 11 06:17:26 PM PDT 24
Peak memory 204008 kb
Host smart-8749007f-6281-4346-a980-80c49754dc12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210722220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
4210722220
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1023325484
Short name T1041
Test name
Test status
Simulation time 236637942 ps
CPU time 3.72 seconds
Started Aug 11 06:17:29 PM PDT 24
Finished Aug 11 06:17:33 PM PDT 24
Peak memory 215524 kb
Host smart-568e2ef3-82a9-46b5-a37b-8ad0830c7c76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023325484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1023325484
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1025399071
Short name T1135
Test name
Test status
Simulation time 68516174 ps
CPU time 4.51 seconds
Started Aug 11 06:17:53 PM PDT 24
Finished Aug 11 06:17:57 PM PDT 24
Peak memory 215792 kb
Host smart-fa414fa6-35b3-4b17-ac2b-32947ffefcf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025399071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1025399071
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1974410191
Short name T1124
Test name
Test status
Simulation time 119935898 ps
CPU time 8.01 seconds
Started Aug 11 06:17:08 PM PDT 24
Finished Aug 11 06:17:16 PM PDT 24
Peak memory 215528 kb
Host smart-73825e50-dedd-4cc8-8869-bcd6254a3d25
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974410191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1974410191
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4094991494
Short name T1106
Test name
Test status
Simulation time 936597645 ps
CPU time 14.14 seconds
Started Aug 11 06:17:08 PM PDT 24
Finished Aug 11 06:17:22 PM PDT 24
Peak memory 207392 kb
Host smart-56670324-cc0c-4147-baf3-13c393fb7a96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094991494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.4094991494
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2124228616
Short name T1126
Test name
Test status
Simulation time 178300465 ps
CPU time 1.17 seconds
Started Aug 11 06:17:08 PM PDT 24
Finished Aug 11 06:17:10 PM PDT 24
Peak memory 207292 kb
Host smart-d9745591-152e-4a35-9f77-ae7752ce3e0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124228616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2124228616
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1314350373
Short name T1115
Test name
Test status
Simulation time 163022464 ps
CPU time 3.94 seconds
Started Aug 11 06:17:08 PM PDT 24
Finished Aug 11 06:17:12 PM PDT 24
Peak memory 218508 kb
Host smart-f2bb775c-0ee0-4edb-ba03-65672f4689ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314350373 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1314350373
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2053606709
Short name T1120
Test name
Test status
Simulation time 34303440 ps
CPU time 1.26 seconds
Started Aug 11 06:17:07 PM PDT 24
Finished Aug 11 06:17:08 PM PDT 24
Peak memory 207308 kb
Host smart-023695fc-f8c2-4639-b5b2-71d4db9ed900
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053606709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
053606709
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1399653051
Short name T1095
Test name
Test status
Simulation time 14219993 ps
CPU time 0.74 seconds
Started Aug 11 06:17:01 PM PDT 24
Finished Aug 11 06:17:02 PM PDT 24
Peak memory 204052 kb
Host smart-80457639-a7e0-4e51-8e11-24dee9db58b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399653051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
399653051
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.193240749
Short name T139
Test name
Test status
Simulation time 23034089 ps
CPU time 1.75 seconds
Started Aug 11 06:17:05 PM PDT 24
Finished Aug 11 06:17:07 PM PDT 24
Peak memory 215524 kb
Host smart-ef1d5c71-18e4-49c4-83dc-b54947275c57
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193240749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.193240749
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3973060297
Short name T1136
Test name
Test status
Simulation time 26181967 ps
CPU time 0.67 seconds
Started Aug 11 06:17:02 PM PDT 24
Finished Aug 11 06:17:03 PM PDT 24
Peak memory 203936 kb
Host smart-1b748ba5-6377-41b9-a0a4-6013f12c1662
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973060297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3973060297
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1627604233
Short name T1072
Test name
Test status
Simulation time 91554304 ps
CPU time 2.86 seconds
Started Aug 11 06:17:08 PM PDT 24
Finished Aug 11 06:17:11 PM PDT 24
Peak memory 215572 kb
Host smart-ed7a120e-f68a-4f00-85a1-3c530001469a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627604233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1627604233
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1324254839
Short name T1131
Test name
Test status
Simulation time 2329834083 ps
CPU time 3.41 seconds
Started Aug 11 06:17:02 PM PDT 24
Finished Aug 11 06:17:05 PM PDT 24
Peak memory 215900 kb
Host smart-872c0ca5-8056-4f5b-adec-70838d5e11db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324254839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
324254839
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1199570784
Short name T127
Test name
Test status
Simulation time 579768935 ps
CPU time 13.25 seconds
Started Aug 11 06:17:01 PM PDT 24
Finished Aug 11 06:17:14 PM PDT 24
Peak memory 216760 kb
Host smart-ad9a0348-27f8-42d5-841e-3c605d129dec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199570784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1199570784
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3369078823
Short name T1090
Test name
Test status
Simulation time 49399121 ps
CPU time 0.74 seconds
Started Aug 11 06:17:23 PM PDT 24
Finished Aug 11 06:17:24 PM PDT 24
Peak memory 203960 kb
Host smart-ea353975-bafb-49cc-a730-06d1761120cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369078823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3369078823
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3205198634
Short name T1046
Test name
Test status
Simulation time 34803998 ps
CPU time 0.75 seconds
Started Aug 11 06:17:25 PM PDT 24
Finished Aug 11 06:17:26 PM PDT 24
Peak memory 204076 kb
Host smart-8712f724-5f73-4ec6-a84d-9750c0d5df1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205198634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3205198634
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1378379282
Short name T1138
Test name
Test status
Simulation time 25125383 ps
CPU time 0.76 seconds
Started Aug 11 06:17:31 PM PDT 24
Finished Aug 11 06:17:31 PM PDT 24
Peak memory 204016 kb
Host smart-0d34d04c-11b0-44cb-bbe8-0d224255175c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378379282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1378379282
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.393884486
Short name T1093
Test name
Test status
Simulation time 15094308 ps
CPU time 0.75 seconds
Started Aug 11 06:17:29 PM PDT 24
Finished Aug 11 06:17:30 PM PDT 24
Peak memory 204000 kb
Host smart-2c095af2-d41d-4e77-a1f2-6fa36f92035c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393884486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.393884486
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1922196050
Short name T1048
Test name
Test status
Simulation time 28492764 ps
CPU time 0.68 seconds
Started Aug 11 06:17:22 PM PDT 24
Finished Aug 11 06:17:22 PM PDT 24
Peak memory 203996 kb
Host smart-175a52e5-2ea2-44ec-af40-6db692500a0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922196050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1922196050
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.401005086
Short name T1045
Test name
Test status
Simulation time 11098488 ps
CPU time 0.68 seconds
Started Aug 11 06:17:22 PM PDT 24
Finished Aug 11 06:17:22 PM PDT 24
Peak memory 203972 kb
Host smart-a5debd68-2f57-4705-8244-05e2f0712663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401005086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.401005086
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2824209217
Short name T1055
Test name
Test status
Simulation time 26067495 ps
CPU time 0.69 seconds
Started Aug 11 06:17:29 PM PDT 24
Finished Aug 11 06:17:29 PM PDT 24
Peak memory 203968 kb
Host smart-9f6d9402-db3c-42bc-8819-f17efebac38c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824209217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2824209217
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2717827547
Short name T1078
Test name
Test status
Simulation time 15997073 ps
CPU time 0.75 seconds
Started Aug 11 06:17:25 PM PDT 24
Finished Aug 11 06:17:26 PM PDT 24
Peak memory 203960 kb
Host smart-62949939-b41c-4da5-91bb-4a640c885370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717827547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2717827547
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1898417375
Short name T1133
Test name
Test status
Simulation time 11867907 ps
CPU time 0.69 seconds
Started Aug 11 06:17:24 PM PDT 24
Finished Aug 11 06:17:25 PM PDT 24
Peak memory 203992 kb
Host smart-f54cd9b6-a34f-43e2-bb13-0809b86e22e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898417375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1898417375
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.761967643
Short name T1031
Test name
Test status
Simulation time 20855503 ps
CPU time 0.77 seconds
Started Aug 11 06:17:34 PM PDT 24
Finished Aug 11 06:17:35 PM PDT 24
Peak memory 203892 kb
Host smart-dfe3498e-e512-4b6e-9217-a37f610c8297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761967643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.761967643
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2681313435
Short name T135
Test name
Test status
Simulation time 613895841 ps
CPU time 15.31 seconds
Started Aug 11 06:17:05 PM PDT 24
Finished Aug 11 06:17:21 PM PDT 24
Peak memory 215580 kb
Host smart-b969f81c-5fce-4298-8956-cf49fbf73871
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681313435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2681313435
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2338637853
Short name T1038
Test name
Test status
Simulation time 3054469722 ps
CPU time 12.52 seconds
Started Aug 11 06:17:05 PM PDT 24
Finished Aug 11 06:17:18 PM PDT 24
Peak memory 207432 kb
Host smart-dad75a1c-2fe9-4907-9180-7415f59889fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338637853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2338637853
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4189528470
Short name T90
Test name
Test status
Simulation time 20816919 ps
CPU time 1.1 seconds
Started Aug 11 06:17:06 PM PDT 24
Finished Aug 11 06:17:07 PM PDT 24
Peak memory 207304 kb
Host smart-5647750e-e1b2-4d46-99c6-d2a0ff593f36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189528470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4189528470
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4200392874
Short name T1059
Test name
Test status
Simulation time 129671684 ps
CPU time 1.6 seconds
Started Aug 11 06:17:08 PM PDT 24
Finished Aug 11 06:17:10 PM PDT 24
Peak memory 215644 kb
Host smart-997287d0-cc6c-4d6c-8620-a97cff4ea737
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200392874 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.4200392874
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.108365624
Short name T1122
Test name
Test status
Simulation time 137000120 ps
CPU time 2.04 seconds
Started Aug 11 06:17:09 PM PDT 24
Finished Aug 11 06:17:11 PM PDT 24
Peak memory 207292 kb
Host smart-c28659b1-71bf-4382-a886-25c33ecc7ea7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108365624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.108365624
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3336149387
Short name T1129
Test name
Test status
Simulation time 17595436 ps
CPU time 0.7 seconds
Started Aug 11 06:17:08 PM PDT 24
Finished Aug 11 06:17:09 PM PDT 24
Peak memory 204008 kb
Host smart-01dc3617-b059-4f3a-a93a-77d52c92f12a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336149387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
336149387
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3977747059
Short name T1103
Test name
Test status
Simulation time 176995184 ps
CPU time 1.78 seconds
Started Aug 11 06:17:12 PM PDT 24
Finished Aug 11 06:17:14 PM PDT 24
Peak memory 215516 kb
Host smart-834c2619-5b7a-498d-8b93-5268b4513cd4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977747059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3977747059
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.528533919
Short name T1071
Test name
Test status
Simulation time 137638418 ps
CPU time 0.65 seconds
Started Aug 11 06:17:06 PM PDT 24
Finished Aug 11 06:17:07 PM PDT 24
Peak memory 204280 kb
Host smart-90e325ce-de10-40a0-87a9-d11352bd6aa1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528533919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.528533919
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2349302914
Short name T1069
Test name
Test status
Simulation time 1706408449 ps
CPU time 2.93 seconds
Started Aug 11 06:17:06 PM PDT 24
Finished Aug 11 06:17:10 PM PDT 24
Peak memory 215424 kb
Host smart-892039e2-7bb4-4f7f-92bd-7b7080f2e6fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349302914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2349302914
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1388165682
Short name T111
Test name
Test status
Simulation time 229930405 ps
CPU time 5.13 seconds
Started Aug 11 06:17:06 PM PDT 24
Finished Aug 11 06:17:11 PM PDT 24
Peak memory 215760 kb
Host smart-08377a43-7faa-4ecf-9fa0-c147c90e98c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388165682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
388165682
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1214022073
Short name T1114
Test name
Test status
Simulation time 296183880 ps
CPU time 17.05 seconds
Started Aug 11 06:17:10 PM PDT 24
Finished Aug 11 06:17:27 PM PDT 24
Peak memory 215788 kb
Host smart-40b33312-d3bd-42e8-a0af-d2d2560ed361
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214022073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1214022073
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.830862883
Short name T1089
Test name
Test status
Simulation time 35699094 ps
CPU time 0.68 seconds
Started Aug 11 06:17:34 PM PDT 24
Finished Aug 11 06:17:35 PM PDT 24
Peak memory 204304 kb
Host smart-ee950e87-6374-41a6-8595-1e6dfdd81056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830862883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.830862883
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.991120507
Short name T1061
Test name
Test status
Simulation time 16085707 ps
CPU time 0.75 seconds
Started Aug 11 06:17:32 PM PDT 24
Finished Aug 11 06:17:33 PM PDT 24
Peak memory 204016 kb
Host smart-0bed7eda-c792-4a59-98fb-6e02bc9b5805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991120507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.991120507
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.373573815
Short name T1087
Test name
Test status
Simulation time 30376586 ps
CPU time 0.82 seconds
Started Aug 11 06:17:33 PM PDT 24
Finished Aug 11 06:17:34 PM PDT 24
Peak memory 203976 kb
Host smart-acfaa3d2-df74-4a55-9ba6-ce1310f01724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373573815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.373573815
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4097993276
Short name T1107
Test name
Test status
Simulation time 49292850 ps
CPU time 0.75 seconds
Started Aug 11 06:17:32 PM PDT 24
Finished Aug 11 06:17:33 PM PDT 24
Peak memory 204052 kb
Host smart-e14aa178-797f-4117-85f1-bb83024fc92f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097993276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4097993276
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4176652836
Short name T1030
Test name
Test status
Simulation time 13562828 ps
CPU time 0.69 seconds
Started Aug 11 06:17:37 PM PDT 24
Finished Aug 11 06:17:38 PM PDT 24
Peak memory 204360 kb
Host smart-06572d0a-08da-4319-a2a4-085ad5539e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176652836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4176652836
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.481606579
Short name T1063
Test name
Test status
Simulation time 23264615 ps
CPU time 0.71 seconds
Started Aug 11 06:17:33 PM PDT 24
Finished Aug 11 06:17:34 PM PDT 24
Peak memory 203952 kb
Host smart-0f1e708d-1d92-43d5-aa6a-eb0bc5238fb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481606579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.481606579
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4216669550
Short name T1104
Test name
Test status
Simulation time 32968706 ps
CPU time 0.71 seconds
Started Aug 11 06:17:33 PM PDT 24
Finished Aug 11 06:17:34 PM PDT 24
Peak memory 204364 kb
Host smart-45c0ebd4-2ee0-45c0-ae24-a30df8f7aa69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216669550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
4216669550
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.517034227
Short name T1125
Test name
Test status
Simulation time 13257436 ps
CPU time 0.72 seconds
Started Aug 11 06:17:29 PM PDT 24
Finished Aug 11 06:17:30 PM PDT 24
Peak memory 203996 kb
Host smart-1361fa66-0bd9-4791-bb77-b89a7fd636e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517034227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.517034227
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.676470548
Short name T1116
Test name
Test status
Simulation time 30211599 ps
CPU time 0.75 seconds
Started Aug 11 06:17:32 PM PDT 24
Finished Aug 11 06:17:33 PM PDT 24
Peak memory 204348 kb
Host smart-2daf7cf3-aa4d-45c8-9571-51dcc5499be6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676470548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.676470548
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3654996491
Short name T1075
Test name
Test status
Simulation time 54716921 ps
CPU time 0.76 seconds
Started Aug 11 06:17:34 PM PDT 24
Finished Aug 11 06:17:34 PM PDT 24
Peak memory 204048 kb
Host smart-2318b0ca-4a33-4e31-b1bc-fa30c569ce32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654996491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3654996491
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1923294287
Short name T1123
Test name
Test status
Simulation time 2216820756 ps
CPU time 23.71 seconds
Started Aug 11 06:17:08 PM PDT 24
Finished Aug 11 06:17:32 PM PDT 24
Peak memory 215732 kb
Host smart-dd944ed3-85c3-448c-96c9-a01ca9cd8034
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923294287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1923294287
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2524843573
Short name T1054
Test name
Test status
Simulation time 3479406465 ps
CPU time 32 seconds
Started Aug 11 06:17:04 PM PDT 24
Finished Aug 11 06:17:36 PM PDT 24
Peak memory 215680 kb
Host smart-c4f082b2-c285-43c8-a243-732341477a05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524843573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2524843573
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2407012061
Short name T91
Test name
Test status
Simulation time 34732892 ps
CPU time 1.17 seconds
Started Aug 11 06:17:12 PM PDT 24
Finished Aug 11 06:17:14 PM PDT 24
Peak memory 207348 kb
Host smart-df1d47fe-39f9-463a-b882-962a57ed709a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407012061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2407012061
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2985637829
Short name T123
Test name
Test status
Simulation time 136943727 ps
CPU time 3.77 seconds
Started Aug 11 06:17:08 PM PDT 24
Finished Aug 11 06:17:12 PM PDT 24
Peak memory 217712 kb
Host smart-239e7065-15ae-41f6-ad5c-14290162719a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985637829 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2985637829
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2191527005
Short name T1102
Test name
Test status
Simulation time 72719672 ps
CPU time 2.56 seconds
Started Aug 11 06:17:06 PM PDT 24
Finished Aug 11 06:17:09 PM PDT 24
Peak memory 207380 kb
Host smart-4e899d0d-ae4a-4a10-aaf2-90f5afbd78d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191527005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
191527005
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2301937977
Short name T1110
Test name
Test status
Simulation time 13466665 ps
CPU time 0.72 seconds
Started Aug 11 06:17:05 PM PDT 24
Finished Aug 11 06:17:06 PM PDT 24
Peak memory 204024 kb
Host smart-8cd7f5a0-6d5e-45f8-b234-f4ddc0239c4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301937977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
301937977
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4025839047
Short name T1060
Test name
Test status
Simulation time 58869426 ps
CPU time 2.18 seconds
Started Aug 11 06:17:07 PM PDT 24
Finished Aug 11 06:17:09 PM PDT 24
Peak memory 215540 kb
Host smart-4866ec00-66fc-471c-8abf-57dc91e445fa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025839047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4025839047
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3278219612
Short name T1147
Test name
Test status
Simulation time 37336817 ps
CPU time 0.66 seconds
Started Aug 11 06:17:08 PM PDT 24
Finished Aug 11 06:17:09 PM PDT 24
Peak memory 204268 kb
Host smart-26b4c0f7-4f5e-47fb-92f7-65042364f80d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278219612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3278219612
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4217598986
Short name T1096
Test name
Test status
Simulation time 62312566 ps
CPU time 3.72 seconds
Started Aug 11 06:17:08 PM PDT 24
Finished Aug 11 06:17:12 PM PDT 24
Peak memory 215628 kb
Host smart-72aec037-959d-453d-aac6-b8be861bf5e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217598986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.4217598986
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4167012620
Short name T115
Test name
Test status
Simulation time 834124133 ps
CPU time 5.22 seconds
Started Aug 11 06:17:06 PM PDT 24
Finished Aug 11 06:17:12 PM PDT 24
Peak memory 215948 kb
Host smart-e2f3bf7f-db50-4828-bf15-6999d768a17d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167012620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4
167012620
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1865867859
Short name T1101
Test name
Test status
Simulation time 570198775 ps
CPU time 18.25 seconds
Started Aug 11 06:17:07 PM PDT 24
Finished Aug 11 06:17:25 PM PDT 24
Peak memory 216072 kb
Host smart-0d350450-4d43-4e83-823f-640299224972
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865867859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1865867859
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1742334004
Short name T1083
Test name
Test status
Simulation time 14501924 ps
CPU time 0.71 seconds
Started Aug 11 06:17:38 PM PDT 24
Finished Aug 11 06:17:39 PM PDT 24
Peak memory 204036 kb
Host smart-f5e7ce09-ee44-4d67-a779-376dc6a04442
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742334004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1742334004
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.680872946
Short name T1056
Test name
Test status
Simulation time 16968342 ps
CPU time 0.77 seconds
Started Aug 11 06:17:38 PM PDT 24
Finished Aug 11 06:17:39 PM PDT 24
Peak memory 204376 kb
Host smart-3fce724b-6396-49cf-b007-1d408cf13eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680872946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.680872946
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2555326968
Short name T1148
Test name
Test status
Simulation time 15819153 ps
CPU time 0.77 seconds
Started Aug 11 06:17:33 PM PDT 24
Finished Aug 11 06:17:34 PM PDT 24
Peak memory 204012 kb
Host smart-c95e8eb4-5cc1-4b22-82ee-7742e4ea001e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555326968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2555326968
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.407935141
Short name T1070
Test name
Test status
Simulation time 14842050 ps
CPU time 0.73 seconds
Started Aug 11 06:17:38 PM PDT 24
Finished Aug 11 06:17:39 PM PDT 24
Peak memory 204376 kb
Host smart-ec21c299-2c0c-4c90-9f81-3c4b2ea11dd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407935141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.407935141
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.119864575
Short name T1053
Test name
Test status
Simulation time 113419730 ps
CPU time 0.68 seconds
Started Aug 11 06:17:31 PM PDT 24
Finished Aug 11 06:17:32 PM PDT 24
Peak memory 203980 kb
Host smart-f0aeb9e3-332b-4f82-a3eb-ad034715dd08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119864575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.119864575
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1826108650
Short name T1079
Test name
Test status
Simulation time 50230282 ps
CPU time 0.71 seconds
Started Aug 11 06:17:31 PM PDT 24
Finished Aug 11 06:17:32 PM PDT 24
Peak memory 204048 kb
Host smart-39b1c916-cbb9-444f-ab2c-83138e1e6f01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826108650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1826108650
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.723903354
Short name T1081
Test name
Test status
Simulation time 12501323 ps
CPU time 0.69 seconds
Started Aug 11 06:17:36 PM PDT 24
Finished Aug 11 06:17:37 PM PDT 24
Peak memory 204004 kb
Host smart-a236f5da-9be5-439b-a6ab-fd7883a3c1c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723903354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.723903354
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2335035640
Short name T1067
Test name
Test status
Simulation time 15140815 ps
CPU time 0.76 seconds
Started Aug 11 06:17:34 PM PDT 24
Finished Aug 11 06:17:34 PM PDT 24
Peak memory 204056 kb
Host smart-baf61134-d351-403b-b0aa-d6e19d040684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335035640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2335035640
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1009608002
Short name T1036
Test name
Test status
Simulation time 52215508 ps
CPU time 0.77 seconds
Started Aug 11 06:17:31 PM PDT 24
Finished Aug 11 06:17:32 PM PDT 24
Peak memory 204336 kb
Host smart-89831834-7d8e-44c1-8d66-14d4f359095d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009608002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1009608002
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1783525388
Short name T1040
Test name
Test status
Simulation time 44415506 ps
CPU time 0.73 seconds
Started Aug 11 06:17:34 PM PDT 24
Finished Aug 11 06:17:35 PM PDT 24
Peak memory 204008 kb
Host smart-e5dfaac4-ea03-4d18-89e1-f03c307b5ce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783525388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1783525388
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1853873145
Short name T1073
Test name
Test status
Simulation time 134009033 ps
CPU time 2.6 seconds
Started Aug 11 06:17:08 PM PDT 24
Finished Aug 11 06:17:10 PM PDT 24
Peak memory 217924 kb
Host smart-dd91676f-f440-4159-bad3-40d232a60dbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853873145 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1853873145
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3509797559
Short name T133
Test name
Test status
Simulation time 21637834 ps
CPU time 1.22 seconds
Started Aug 11 06:17:08 PM PDT 24
Finished Aug 11 06:17:10 PM PDT 24
Peak memory 207320 kb
Host smart-9f752d8b-ed13-47c5-806c-7abc8d026a6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509797559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
509797559
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3940374442
Short name T1150
Test name
Test status
Simulation time 15430804 ps
CPU time 0.71 seconds
Started Aug 11 06:17:07 PM PDT 24
Finished Aug 11 06:17:08 PM PDT 24
Peak memory 204040 kb
Host smart-c7c97acf-cb19-4838-85b5-c72729147b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940374442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
940374442
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1544817938
Short name T1068
Test name
Test status
Simulation time 62302356 ps
CPU time 3.8 seconds
Started Aug 11 06:17:08 PM PDT 24
Finished Aug 11 06:17:12 PM PDT 24
Peak memory 215480 kb
Host smart-722cd83c-40dc-4452-ae24-604e95442883
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544817938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1544817938
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2087097816
Short name T99
Test name
Test status
Simulation time 739860874 ps
CPU time 4.67 seconds
Started Aug 11 06:17:06 PM PDT 24
Finished Aug 11 06:17:11 PM PDT 24
Peak memory 216732 kb
Host smart-d8517a2b-6fbb-4938-84dd-5943769a22f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087097816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
087097816
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1337848939
Short name T1058
Test name
Test status
Simulation time 455880342 ps
CPU time 6.58 seconds
Started Aug 11 06:17:08 PM PDT 24
Finished Aug 11 06:17:14 PM PDT 24
Peak memory 215812 kb
Host smart-eac0c951-2ac5-479e-af77-e11d2693256f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337848939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1337848939
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1902334131
Short name T116
Test name
Test status
Simulation time 620742255 ps
CPU time 3.75 seconds
Started Aug 11 06:17:13 PM PDT 24
Finished Aug 11 06:17:16 PM PDT 24
Peak memory 218380 kb
Host smart-2c98bc3b-e8f6-4af8-b10e-926a59250799
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902334131 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1902334131
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1984934821
Short name T1145
Test name
Test status
Simulation time 95135881 ps
CPU time 1.42 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:18 PM PDT 24
Peak memory 207344 kb
Host smart-63bb7c82-6afd-4aca-ae71-867be2bd1ae4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984934821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
984934821
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.115776181
Short name T1049
Test name
Test status
Simulation time 21109226 ps
CPU time 0.68 seconds
Started Aug 11 06:17:17 PM PDT 24
Finished Aug 11 06:17:18 PM PDT 24
Peak memory 204020 kb
Host smart-e68fb432-e2dd-4ca8-ba34-136ddc0927e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115776181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.115776181
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2080229566
Short name T1065
Test name
Test status
Simulation time 155526932 ps
CPU time 3.88 seconds
Started Aug 11 06:17:15 PM PDT 24
Finished Aug 11 06:17:19 PM PDT 24
Peak memory 215532 kb
Host smart-c50b9d7c-ce17-4b59-a2a3-8a9c21613fb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080229566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2080229566
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3579431386
Short name T1130
Test name
Test status
Simulation time 32969771 ps
CPU time 1.93 seconds
Started Aug 11 06:17:17 PM PDT 24
Finished Aug 11 06:17:19 PM PDT 24
Peak memory 215784 kb
Host smart-9a436709-2341-4371-aaba-a8463110fa33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579431386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
579431386
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1893968920
Short name T1074
Test name
Test status
Simulation time 641814406 ps
CPU time 1.58 seconds
Started Aug 11 06:17:14 PM PDT 24
Finished Aug 11 06:17:16 PM PDT 24
Peak memory 215616 kb
Host smart-a596a17e-51ca-4e9f-b3bb-fa4f63629448
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893968920 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1893968920
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1062585711
Short name T138
Test name
Test status
Simulation time 110524227 ps
CPU time 2.69 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:20 PM PDT 24
Peak memory 215548 kb
Host smart-0271540b-e270-45a7-9ee3-9aaa8d837bd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062585711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
062585711
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2571131129
Short name T1039
Test name
Test status
Simulation time 31675655 ps
CPU time 0.73 seconds
Started Aug 11 06:17:15 PM PDT 24
Finished Aug 11 06:17:16 PM PDT 24
Peak memory 203980 kb
Host smart-e4a70cb2-02fa-4272-9882-996f64fa77a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571131129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
571131129
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1240007463
Short name T155
Test name
Test status
Simulation time 74008781 ps
CPU time 1.9 seconds
Started Aug 11 06:17:17 PM PDT 24
Finished Aug 11 06:17:19 PM PDT 24
Peak memory 207396 kb
Host smart-f35f9612-7735-49d4-8dee-56429c4b4412
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240007463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1240007463
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3408208351
Short name T1143
Test name
Test status
Simulation time 104461111 ps
CPU time 1.91 seconds
Started Aug 11 06:17:15 PM PDT 24
Finished Aug 11 06:17:17 PM PDT 24
Peak memory 216688 kb
Host smart-0d1b6ffe-f1d3-487e-a2ea-41f229f3b5d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408208351 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3408208351
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1478413049
Short name T1099
Test name
Test status
Simulation time 74756437 ps
CPU time 1.95 seconds
Started Aug 11 06:17:15 PM PDT 24
Finished Aug 11 06:17:18 PM PDT 24
Peak memory 207456 kb
Host smart-20523d6b-2b0e-4a00-872e-02e9e06e980b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478413049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
478413049
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2258056199
Short name T1034
Test name
Test status
Simulation time 14329372 ps
CPU time 0.72 seconds
Started Aug 11 06:17:17 PM PDT 24
Finished Aug 11 06:17:18 PM PDT 24
Peak memory 204012 kb
Host smart-9c729d1a-bc14-4183-9714-bfc23342bdb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258056199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
258056199
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1749180967
Short name T1137
Test name
Test status
Simulation time 109294949 ps
CPU time 2.86 seconds
Started Aug 11 06:17:17 PM PDT 24
Finished Aug 11 06:17:20 PM PDT 24
Peak memory 215536 kb
Host smart-35c7c839-53f5-46f0-9289-711e492151eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749180967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1749180967
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3316293452
Short name T113
Test name
Test status
Simulation time 163810305 ps
CPU time 2.68 seconds
Started Aug 11 06:17:14 PM PDT 24
Finished Aug 11 06:17:17 PM PDT 24
Peak memory 215760 kb
Host smart-37da93c1-7360-4c9d-9a90-accb4357024e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316293452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
316293452
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3998303166
Short name T125
Test name
Test status
Simulation time 108842412 ps
CPU time 6.78 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:23 PM PDT 24
Peak memory 215676 kb
Host smart-619092de-7cec-4445-b4b9-218dd368ebb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998303166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3998303166
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1790423087
Short name T122
Test name
Test status
Simulation time 56907484 ps
CPU time 3.59 seconds
Started Aug 11 06:17:18 PM PDT 24
Finished Aug 11 06:17:22 PM PDT 24
Peak memory 217108 kb
Host smart-a9c7a1dd-4882-4c54-a59f-750f6bf68e2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790423087 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1790423087
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.465589072
Short name T1100
Test name
Test status
Simulation time 297003478 ps
CPU time 1.36 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:18 PM PDT 24
Peak memory 215460 kb
Host smart-558444ba-8c93-48bd-aea7-70cd638763ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465589072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.465589072
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1796265843
Short name T1092
Test name
Test status
Simulation time 109459292 ps
CPU time 0.73 seconds
Started Aug 11 06:17:17 PM PDT 24
Finished Aug 11 06:17:18 PM PDT 24
Peak memory 204360 kb
Host smart-6c6bb249-51ea-4bd4-8833-d587805d3f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796265843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
796265843
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2677257059
Short name T1128
Test name
Test status
Simulation time 225802896 ps
CPU time 1.85 seconds
Started Aug 11 06:17:16 PM PDT 24
Finished Aug 11 06:17:19 PM PDT 24
Peak memory 207212 kb
Host smart-65545924-e0f3-4a62-8dbf-f1009a5aa4a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677257059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2677257059
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.881909895
Short name T1140
Test name
Test status
Simulation time 31883667 ps
CPU time 1.81 seconds
Started Aug 11 06:17:17 PM PDT 24
Finished Aug 11 06:17:19 PM PDT 24
Peak memory 215704 kb
Host smart-7421e942-dd1b-469d-b58e-4c16a1a4f25e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881909895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.881909895
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.682856534
Short name T119
Test name
Test status
Simulation time 251226464 ps
CPU time 6.32 seconds
Started Aug 11 06:17:17 PM PDT 24
Finished Aug 11 06:17:24 PM PDT 24
Peak memory 215668 kb
Host smart-df9796dd-79c2-4127-9c2b-49a1a1188d16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682856534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.682856534
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.261107578
Short name T540
Test name
Test status
Simulation time 22930447 ps
CPU time 0.72 seconds
Started Aug 11 06:18:04 PM PDT 24
Finished Aug 11 06:18:04 PM PDT 24
Peak memory 205892 kb
Host smart-65958de7-8675-4cde-98a0-dea93b6eeae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261107578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.261107578
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.597058800
Short name T92
Test name
Test status
Simulation time 966442932 ps
CPU time 12.28 seconds
Started Aug 11 06:18:04 PM PDT 24
Finished Aug 11 06:18:17 PM PDT 24
Peak memory 225156 kb
Host smart-f38996d6-1a18-4fd7-916b-588b0f5b2ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597058800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.597058800
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.701378137
Short name T800
Test name
Test status
Simulation time 18394254 ps
CPU time 0.81 seconds
Started Aug 11 06:18:09 PM PDT 24
Finished Aug 11 06:18:10 PM PDT 24
Peak memory 207060 kb
Host smart-9423dd8d-b6d8-4751-bc15-eba0c673d540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701378137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.701378137
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3008446752
Short name T241
Test name
Test status
Simulation time 5475870451 ps
CPU time 17.69 seconds
Started Aug 11 06:18:05 PM PDT 24
Finished Aug 11 06:18:22 PM PDT 24
Peak memory 234984 kb
Host smart-3139a37b-a437-4799-9173-240fdfa85f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008446752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3008446752
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.663499427
Short name T289
Test name
Test status
Simulation time 25116083266 ps
CPU time 169.04 seconds
Started Aug 11 06:18:11 PM PDT 24
Finished Aug 11 06:21:01 PM PDT 24
Peak memory 263836 kb
Host smart-158d5819-48e4-488a-a90a-652a69604f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663499427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
663499427
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3553382505
Short name T62
Test name
Test status
Simulation time 186279198 ps
CPU time 4.34 seconds
Started Aug 11 06:18:11 PM PDT 24
Finished Aug 11 06:18:16 PM PDT 24
Peak memory 233596 kb
Host smart-a3f8277b-18ed-4287-acb9-a8e232bcb50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553382505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3553382505
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.78710192
Short name T345
Test name
Test status
Simulation time 51687853 ps
CPU time 2.01 seconds
Started Aug 11 06:18:05 PM PDT 24
Finished Aug 11 06:18:07 PM PDT 24
Peak memory 224812 kb
Host smart-8efca5d5-acf0-40d9-bff5-3e12182912e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78710192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.78710192
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4007511000
Short name T1026
Test name
Test status
Simulation time 1428066101 ps
CPU time 3.55 seconds
Started Aug 11 06:18:03 PM PDT 24
Finished Aug 11 06:18:07 PM PDT 24
Peak memory 233460 kb
Host smart-7ae4ecd5-1a50-4161-916d-6c4c514c2d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007511000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4007511000
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2100543584
Short name T828
Test name
Test status
Simulation time 170940479 ps
CPU time 4.67 seconds
Started Aug 11 06:18:03 PM PDT 24
Finished Aug 11 06:18:08 PM PDT 24
Peak memory 241420 kb
Host smart-a0df4995-396c-498d-b51e-a74142c0b609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100543584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2100543584
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3795404003
Short name T536
Test name
Test status
Simulation time 362794577 ps
CPU time 3.88 seconds
Started Aug 11 06:18:03 PM PDT 24
Finished Aug 11 06:18:07 PM PDT 24
Peak memory 223580 kb
Host smart-2e9db7b7-95cf-419b-b4e6-9fa5322ee4d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3795404003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3795404003
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2490461613
Short name T13
Test name
Test status
Simulation time 48234029 ps
CPU time 1 seconds
Started Aug 11 06:18:03 PM PDT 24
Finished Aug 11 06:18:04 PM PDT 24
Peak memory 208060 kb
Host smart-7620d551-b8ca-4264-b56c-0698ae401de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490461613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2490461613
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1088031516
Short name T624
Test name
Test status
Simulation time 9274295835 ps
CPU time 11.03 seconds
Started Aug 11 06:18:09 PM PDT 24
Finished Aug 11 06:18:20 PM PDT 24
Peak memory 217048 kb
Host smart-ea67e491-28ef-4c86-aeaf-f9c75ff7b77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088031516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1088031516
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.645434557
Short name T572
Test name
Test status
Simulation time 8084447204 ps
CPU time 4.66 seconds
Started Aug 11 06:18:02 PM PDT 24
Finished Aug 11 06:18:07 PM PDT 24
Peak memory 217128 kb
Host smart-8f14c920-02dc-42ff-b657-9e02151cee59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645434557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.645434557
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1324384076
Short name T2
Test name
Test status
Simulation time 105051336 ps
CPU time 1.26 seconds
Started Aug 11 06:18:00 PM PDT 24
Finished Aug 11 06:18:02 PM PDT 24
Peak memory 216960 kb
Host smart-3365be79-f4f8-4c8a-a3fd-05ccce500443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324384076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1324384076
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3317928566
Short name T805
Test name
Test status
Simulation time 75692878 ps
CPU time 0.92 seconds
Started Aug 11 06:18:01 PM PDT 24
Finished Aug 11 06:18:02 PM PDT 24
Peak memory 206600 kb
Host smart-04cd1535-f07d-4db4-877f-aeb17d097015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317928566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3317928566
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1851905947
Short name T244
Test name
Test status
Simulation time 15409686151 ps
CPU time 11.63 seconds
Started Aug 11 06:18:04 PM PDT 24
Finished Aug 11 06:18:16 PM PDT 24
Peak memory 241680 kb
Host smart-bde5a884-937a-4967-8491-ac47744e1d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851905947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1851905947
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3449950804
Short name T334
Test name
Test status
Simulation time 84886901 ps
CPU time 2.53 seconds
Started Aug 11 06:18:05 PM PDT 24
Finished Aug 11 06:18:08 PM PDT 24
Peak memory 225248 kb
Host smart-721334fa-e47d-4e09-8b75-092b651e500d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449950804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3449950804
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1039268258
Short name T725
Test name
Test status
Simulation time 27930942 ps
CPU time 0.85 seconds
Started Aug 11 06:18:02 PM PDT 24
Finished Aug 11 06:18:03 PM PDT 24
Peak memory 207020 kb
Host smart-e5ec6ab1-9e40-4176-b3eb-2394753ac1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039268258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1039268258
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1684886548
Short name T380
Test name
Test status
Simulation time 158936503 ps
CPU time 4.53 seconds
Started Aug 11 06:18:00 PM PDT 24
Finished Aug 11 06:18:05 PM PDT 24
Peak memory 241640 kb
Host smart-b7f1deee-7c6d-4396-b628-d6c2db589eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684886548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1684886548
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2123477960
Short name T246
Test name
Test status
Simulation time 139173455849 ps
CPU time 210.06 seconds
Started Aug 11 06:18:05 PM PDT 24
Finished Aug 11 06:21:35 PM PDT 24
Peak memory 233472 kb
Host smart-416c3c91-01fd-4173-aedd-f54c4e113c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123477960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2123477960
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2662846147
Short name T215
Test name
Test status
Simulation time 433044481851 ps
CPU time 369.43 seconds
Started Aug 11 06:18:13 PM PDT 24
Finished Aug 11 06:24:22 PM PDT 24
Peak memory 274580 kb
Host smart-2e369f4f-ed1b-40b5-aefa-d3f7aef2c62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662846147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2662846147
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.386819710
Short name T348
Test name
Test status
Simulation time 1241295709 ps
CPU time 5.71 seconds
Started Aug 11 06:18:11 PM PDT 24
Finished Aug 11 06:18:17 PM PDT 24
Peak memory 233604 kb
Host smart-a98e0029-8864-4d23-86df-f47c43764042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386819710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.386819710
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2440186067
Short name T644
Test name
Test status
Simulation time 51880097 ps
CPU time 3.26 seconds
Started Aug 11 06:18:05 PM PDT 24
Finished Aug 11 06:18:08 PM PDT 24
Peak memory 233480 kb
Host smart-2c2a14f4-1a7f-46c8-b356-9aae4d5966c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440186067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2440186067
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3546662053
Short name T745
Test name
Test status
Simulation time 6789858904 ps
CPU time 37.65 seconds
Started Aug 11 06:18:11 PM PDT 24
Finished Aug 11 06:18:49 PM PDT 24
Peak memory 225420 kb
Host smart-91c21e1d-ae71-4ac8-9839-26b271a4147b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546662053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3546662053
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.4286555392
Short name T383
Test name
Test status
Simulation time 26287591 ps
CPU time 1.03 seconds
Started Aug 11 06:18:05 PM PDT 24
Finished Aug 11 06:18:06 PM PDT 24
Peak memory 218480 kb
Host smart-e4b2fa31-d382-4bbe-901d-615efe82bf1e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286555392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.4286555392
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3901599893
Short name T979
Test name
Test status
Simulation time 21284273558 ps
CPU time 6.5 seconds
Started Aug 11 06:18:09 PM PDT 24
Finished Aug 11 06:18:16 PM PDT 24
Peak memory 233500 kb
Host smart-b9a884bb-3c2a-4163-a2ee-8d8d69b7afe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901599893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3901599893
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2456857660
Short name T258
Test name
Test status
Simulation time 536259638 ps
CPU time 4.31 seconds
Started Aug 11 06:18:03 PM PDT 24
Finished Aug 11 06:18:08 PM PDT 24
Peak memory 233424 kb
Host smart-b8851b6a-fbff-4cdf-b339-c25f5554b9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456857660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2456857660
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3818231263
Short name T721
Test name
Test status
Simulation time 224824257 ps
CPU time 3.6 seconds
Started Aug 11 06:18:09 PM PDT 24
Finished Aug 11 06:18:13 PM PDT 24
Peak memory 223724 kb
Host smart-b221cb92-f517-45cb-b540-209af632e01d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3818231263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3818231263
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1860724140
Short name T77
Test name
Test status
Simulation time 207305604 ps
CPU time 1.45 seconds
Started Aug 11 06:18:16 PM PDT 24
Finished Aug 11 06:18:18 PM PDT 24
Peak memory 236624 kb
Host smart-b0868dde-43cb-4d85-b07e-d71851ef14f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860724140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1860724140
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2386384757
Short name T829
Test name
Test status
Simulation time 19693931673 ps
CPU time 47.46 seconds
Started Aug 11 06:18:02 PM PDT 24
Finished Aug 11 06:18:50 PM PDT 24
Peak memory 218436 kb
Host smart-0a998d79-a651-495d-93e8-9f38a6861d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386384757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2386384757
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2841419158
Short name T807
Test name
Test status
Simulation time 18965432073 ps
CPU time 14.41 seconds
Started Aug 11 06:18:03 PM PDT 24
Finished Aug 11 06:18:18 PM PDT 24
Peak memory 216996 kb
Host smart-94c3542f-0919-48fb-8569-50b8e7e6fcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841419158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2841419158
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1652260374
Short name T606
Test name
Test status
Simulation time 13358857 ps
CPU time 0.7 seconds
Started Aug 11 06:18:09 PM PDT 24
Finished Aug 11 06:18:10 PM PDT 24
Peak memory 206104 kb
Host smart-0296eceb-3bfe-4546-bcbc-b8f4c0a94691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652260374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1652260374
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.4086946735
Short name T803
Test name
Test status
Simulation time 235784162 ps
CPU time 0.83 seconds
Started Aug 11 06:18:04 PM PDT 24
Finished Aug 11 06:18:05 PM PDT 24
Peak memory 206540 kb
Host smart-7496df67-a608-446b-b85c-171536306f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086946735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.4086946735
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3839180158
Short name T781
Test name
Test status
Simulation time 1985989103 ps
CPU time 6.32 seconds
Started Aug 11 06:18:00 PM PDT 24
Finished Aug 11 06:18:06 PM PDT 24
Peak memory 240912 kb
Host smart-c7825e16-7edd-4cb4-8b8c-6ca03564f044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839180158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3839180158
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3360227801
Short name T934
Test name
Test status
Simulation time 17615838 ps
CPU time 0.79 seconds
Started Aug 11 06:18:47 PM PDT 24
Finished Aug 11 06:18:48 PM PDT 24
Peak memory 205236 kb
Host smart-f5053b50-abf8-411a-8032-21678802780f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360227801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3360227801
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2228510575
Short name T423
Test name
Test status
Simulation time 3261602947 ps
CPU time 8.16 seconds
Started Aug 11 06:18:50 PM PDT 24
Finished Aug 11 06:18:58 PM PDT 24
Peak memory 233572 kb
Host smart-bdc7e3c5-4bbc-4734-a131-6a2b8b4bcc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228510575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2228510575
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1007620416
Short name T941
Test name
Test status
Simulation time 23556580 ps
CPU time 0.84 seconds
Started Aug 11 06:18:36 PM PDT 24
Finished Aug 11 06:18:37 PM PDT 24
Peak memory 207028 kb
Host smart-49841f7c-e2f6-433a-9cce-b5c10a30c4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007620416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1007620416
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1843066962
Short name T145
Test name
Test status
Simulation time 245061905 ps
CPU time 0.87 seconds
Started Aug 11 06:18:47 PM PDT 24
Finished Aug 11 06:18:48 PM PDT 24
Peak memory 216676 kb
Host smart-f96ca190-29d0-4000-82bb-b72d599e4d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843066962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1843066962
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.109299475
Short name T294
Test name
Test status
Simulation time 34730775905 ps
CPU time 71.8 seconds
Started Aug 11 06:18:50 PM PDT 24
Finished Aug 11 06:20:02 PM PDT 24
Peak memory 233572 kb
Host smart-b96e6ccb-bd54-45ae-9292-3925d80d93e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109299475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.109299475
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2734246435
Short name T943
Test name
Test status
Simulation time 3538786763 ps
CPU time 53.88 seconds
Started Aug 11 06:18:45 PM PDT 24
Finished Aug 11 06:19:39 PM PDT 24
Peak memory 233532 kb
Host smart-94cb41db-4d25-4d45-a675-3f7101d1607a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734246435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2734246435
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.722266811
Short name T106
Test name
Test status
Simulation time 179794994 ps
CPU time 6.57 seconds
Started Aug 11 06:18:44 PM PDT 24
Finished Aug 11 06:18:51 PM PDT 24
Peak memory 234488 kb
Host smart-31303563-2ca3-4ab0-9bcd-3f5fc59c6127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722266811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.722266811
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.928033883
Short name T286
Test name
Test status
Simulation time 36288127543 ps
CPU time 129.56 seconds
Started Aug 11 06:18:47 PM PDT 24
Finished Aug 11 06:20:57 PM PDT 24
Peak memory 254064 kb
Host smart-c9416088-b988-4347-8d38-72621e26ed87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928033883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.928033883
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3477646706
Short name T43
Test name
Test status
Simulation time 11947665525 ps
CPU time 33.59 seconds
Started Aug 11 06:18:44 PM PDT 24
Finished Aug 11 06:19:18 PM PDT 24
Peak memory 225336 kb
Host smart-87dfa782-8e87-4d7e-9538-e6313383e663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477646706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3477646706
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.312293246
Short name T878
Test name
Test status
Simulation time 22151779129 ps
CPU time 91.45 seconds
Started Aug 11 06:18:49 PM PDT 24
Finished Aug 11 06:20:21 PM PDT 24
Peak memory 238648 kb
Host smart-a2bd32df-0f95-43df-acad-14065a957042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312293246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.312293246
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3485366880
Short name T34
Test name
Test status
Simulation time 40495802 ps
CPU time 1.11 seconds
Started Aug 11 06:18:39 PM PDT 24
Finished Aug 11 06:18:40 PM PDT 24
Peak memory 217216 kb
Host smart-b01268b6-92ef-408f-bdc4-482bf1673af9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485366880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3485366880
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2495498937
Short name T272
Test name
Test status
Simulation time 475804931 ps
CPU time 5.62 seconds
Started Aug 11 06:18:48 PM PDT 24
Finished Aug 11 06:18:54 PM PDT 24
Peak memory 241528 kb
Host smart-aa4a2d77-96f5-4dc2-9254-60833694b705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495498937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2495498937
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3561105679
Short name T925
Test name
Test status
Simulation time 2336656316 ps
CPU time 8.59 seconds
Started Aug 11 06:18:38 PM PDT 24
Finished Aug 11 06:18:47 PM PDT 24
Peak memory 233436 kb
Host smart-f2832897-709b-4af5-962f-8e3920b2ea5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561105679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3561105679
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2901995186
Short name T410
Test name
Test status
Simulation time 563382116 ps
CPU time 7.8 seconds
Started Aug 11 06:18:50 PM PDT 24
Finished Aug 11 06:18:58 PM PDT 24
Peak memory 222664 kb
Host smart-643d01b2-bde4-4092-9c63-dcd1387703b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2901995186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2901995186
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3261524627
Short name T864
Test name
Test status
Simulation time 39790781 ps
CPU time 0.94 seconds
Started Aug 11 06:18:46 PM PDT 24
Finished Aug 11 06:18:47 PM PDT 24
Peak memory 207396 kb
Host smart-2017966b-f120-429d-9f8a-9bfefaa2055a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261524627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3261524627
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3825459824
Short name T958
Test name
Test status
Simulation time 7337019010 ps
CPU time 6.85 seconds
Started Aug 11 06:18:38 PM PDT 24
Finished Aug 11 06:18:45 PM PDT 24
Peak memory 217024 kb
Host smart-9710f5e5-47ae-47b9-9182-1f07e8b91473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825459824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3825459824
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.858481079
Short name T370
Test name
Test status
Simulation time 96159151 ps
CPU time 1.63 seconds
Started Aug 11 06:18:39 PM PDT 24
Finished Aug 11 06:18:41 PM PDT 24
Peak memory 217164 kb
Host smart-73081b57-371a-4f9b-ab55-95b781f41d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858481079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.858481079
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.4100340787
Short name T404
Test name
Test status
Simulation time 31284522 ps
CPU time 0.74 seconds
Started Aug 11 06:18:40 PM PDT 24
Finished Aug 11 06:18:41 PM PDT 24
Peak memory 206552 kb
Host smart-e4a73af4-530b-4000-8247-1f40501470e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100340787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4100340787
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2594863526
Short name T766
Test name
Test status
Simulation time 3992880734 ps
CPU time 8.64 seconds
Started Aug 11 06:18:48 PM PDT 24
Finished Aug 11 06:18:57 PM PDT 24
Peak memory 233464 kb
Host smart-07dd7c1d-03de-47cc-9c4e-adf111ee68b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594863526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2594863526
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2479569110
Short name T756
Test name
Test status
Simulation time 46785894 ps
CPU time 0.74 seconds
Started Aug 11 06:18:48 PM PDT 24
Finished Aug 11 06:18:49 PM PDT 24
Peak memory 205856 kb
Host smart-651c4564-2d17-452d-9e8c-e188f45eeaff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479569110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2479569110
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1508589562
Short name T388
Test name
Test status
Simulation time 4076110683 ps
CPU time 21.61 seconds
Started Aug 11 06:18:46 PM PDT 24
Finished Aug 11 06:19:08 PM PDT 24
Peak memory 233472 kb
Host smart-7061d357-ddc9-417e-aafc-3575f8986bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508589562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1508589562
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2718965497
Short name T978
Test name
Test status
Simulation time 39882810 ps
CPU time 0.76 seconds
Started Aug 11 06:18:47 PM PDT 24
Finished Aug 11 06:18:48 PM PDT 24
Peak memory 207064 kb
Host smart-fa1e2b6e-b7c6-4a14-a93a-1df1aa98f2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718965497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2718965497
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1708224571
Short name T627
Test name
Test status
Simulation time 14384554821 ps
CPU time 133.68 seconds
Started Aug 11 06:18:47 PM PDT 24
Finished Aug 11 06:21:01 PM PDT 24
Peak memory 250064 kb
Host smart-a2dbfe17-f35d-4875-9336-2b8a6e649342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708224571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1708224571
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2378418030
Short name T32
Test name
Test status
Simulation time 5101555382 ps
CPU time 63.24 seconds
Started Aug 11 06:18:46 PM PDT 24
Finished Aug 11 06:19:49 PM PDT 24
Peak memory 249912 kb
Host smart-d7caa9a0-b432-434b-96cb-8ba90d50e59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378418030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2378418030
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.284201299
Short name T542
Test name
Test status
Simulation time 935568730 ps
CPU time 14.97 seconds
Started Aug 11 06:18:50 PM PDT 24
Finished Aug 11 06:19:05 PM PDT 24
Peak memory 225240 kb
Host smart-8f4be630-8bd4-41f1-8c51-d81bfac593e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284201299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.284201299
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.937365963
Short name T977
Test name
Test status
Simulation time 18812790383 ps
CPU time 161.88 seconds
Started Aug 11 06:18:48 PM PDT 24
Finished Aug 11 06:21:30 PM PDT 24
Peak memory 253452 kb
Host smart-b6a955f4-c95c-4a49-9685-0d8532bc1c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937365963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.937365963
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3949368267
Short name T839
Test name
Test status
Simulation time 1977467419 ps
CPU time 11.95 seconds
Started Aug 11 06:18:46 PM PDT 24
Finished Aug 11 06:18:58 PM PDT 24
Peak memory 225204 kb
Host smart-af5e6a08-70db-4f7a-ba1e-ee6ef928d806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949368267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3949368267
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.4195926195
Short name T446
Test name
Test status
Simulation time 5177823109 ps
CPU time 17.12 seconds
Started Aug 11 06:18:48 PM PDT 24
Finished Aug 11 06:19:06 PM PDT 24
Peak memory 241256 kb
Host smart-06bc9dba-7b27-4072-b60b-b49c17f4cda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195926195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4195926195
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.782269594
Short name T36
Test name
Test status
Simulation time 29920212 ps
CPU time 1.03 seconds
Started Aug 11 06:18:49 PM PDT 24
Finished Aug 11 06:18:50 PM PDT 24
Peak memory 218464 kb
Host smart-5be1406f-19a8-45b3-b5d5-08beaec26ed6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782269594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.782269594
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.824709984
Short name T146
Test name
Test status
Simulation time 11738909339 ps
CPU time 33.79 seconds
Started Aug 11 06:18:49 PM PDT 24
Finished Aug 11 06:19:23 PM PDT 24
Peak memory 225308 kb
Host smart-84abbd86-63f0-469c-9968-8d21ab7ec1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824709984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.824709984
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3903689781
Short name T566
Test name
Test status
Simulation time 3115681557 ps
CPU time 10.5 seconds
Started Aug 11 06:18:50 PM PDT 24
Finished Aug 11 06:19:01 PM PDT 24
Peak memory 241676 kb
Host smart-197f249f-3adb-43a8-a5de-ac33e11cf0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903689781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3903689781
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.286426513
Short name T707
Test name
Test status
Simulation time 1223886838 ps
CPU time 4.11 seconds
Started Aug 11 06:18:47 PM PDT 24
Finished Aug 11 06:18:51 PM PDT 24
Peak memory 223636 kb
Host smart-8022a608-d28e-4d30-b600-883dc3cf4301
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=286426513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.286426513
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.268191133
Short name T531
Test name
Test status
Simulation time 46223116 ps
CPU time 0.97 seconds
Started Aug 11 06:18:50 PM PDT 24
Finished Aug 11 06:18:51 PM PDT 24
Peak memory 208056 kb
Host smart-19bb72ec-8b82-436a-a08f-f33547fd5984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268191133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.268191133
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2061940526
Short name T467
Test name
Test status
Simulation time 9227310420 ps
CPU time 12.86 seconds
Started Aug 11 06:18:46 PM PDT 24
Finished Aug 11 06:18:59 PM PDT 24
Peak memory 217068 kb
Host smart-e4f36811-ba91-478e-9c6e-5c169cd7af20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061940526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2061940526
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2805786720
Short name T344
Test name
Test status
Simulation time 736652640 ps
CPU time 2.22 seconds
Started Aug 11 06:18:46 PM PDT 24
Finished Aug 11 06:18:48 PM PDT 24
Peak memory 217000 kb
Host smart-e8dedef8-6abb-4d2c-b2e5-a2d9ba87486a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805786720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2805786720
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3585418597
Short name T30
Test name
Test status
Simulation time 165029772 ps
CPU time 2.97 seconds
Started Aug 11 06:18:48 PM PDT 24
Finished Aug 11 06:18:51 PM PDT 24
Peak memory 216956 kb
Host smart-7cee7fc4-5a3c-4dc0-821b-92b783f529fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585418597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3585418597
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.180890417
Short name T880
Test name
Test status
Simulation time 20163535 ps
CPU time 0.71 seconds
Started Aug 11 06:18:48 PM PDT 24
Finished Aug 11 06:18:49 PM PDT 24
Peak memory 206052 kb
Host smart-0331bf35-0a6e-4ec2-8ebb-9786a104e717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180890417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.180890417
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1608568342
Short name T515
Test name
Test status
Simulation time 1076487904 ps
CPU time 4.08 seconds
Started Aug 11 06:18:47 PM PDT 24
Finished Aug 11 06:18:52 PM PDT 24
Peak memory 233456 kb
Host smart-b645ecfc-8e0c-4f55-8b78-4e65bae081e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608568342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1608568342
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2102000910
Short name T992
Test name
Test status
Simulation time 41449862 ps
CPU time 0.74 seconds
Started Aug 11 06:18:47 PM PDT 24
Finished Aug 11 06:18:48 PM PDT 24
Peak memory 205300 kb
Host smart-dad6ac0d-9277-44ba-9ca8-4bf72fd8c23a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102000910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2102000910
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.352818741
Short name T252
Test name
Test status
Simulation time 820928667 ps
CPU time 3.03 seconds
Started Aug 11 06:18:48 PM PDT 24
Finished Aug 11 06:18:51 PM PDT 24
Peak memory 225236 kb
Host smart-3389b1ef-ecc5-4a1a-9cbf-5910014d59ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352818741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.352818741
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3313342353
Short name T924
Test name
Test status
Simulation time 15543957 ps
CPU time 0.78 seconds
Started Aug 11 06:18:49 PM PDT 24
Finished Aug 11 06:18:50 PM PDT 24
Peak memory 207100 kb
Host smart-5d91148f-fda6-4309-9cc5-1ad7f1787185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313342353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3313342353
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1720709991
Short name T386
Test name
Test status
Simulation time 22797880657 ps
CPU time 71.11 seconds
Started Aug 11 06:18:48 PM PDT 24
Finished Aug 11 06:19:59 PM PDT 24
Peak memory 249956 kb
Host smart-be0e2e4c-d995-450a-bbe4-36f9f5a22d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720709991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1720709991
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2981126400
Short name T1024
Test name
Test status
Simulation time 3801280212 ps
CPU time 25.12 seconds
Started Aug 11 06:18:47 PM PDT 24
Finished Aug 11 06:19:13 PM PDT 24
Peak memory 249996 kb
Host smart-3224c3cc-d38e-4a3e-94a9-a74bc57d1639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981126400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2981126400
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1131911371
Short name T163
Test name
Test status
Simulation time 1045047558 ps
CPU time 21.94 seconds
Started Aug 11 06:18:46 PM PDT 24
Finished Aug 11 06:19:08 PM PDT 24
Peak memory 234452 kb
Host smart-65a94db2-76ae-43fb-a2c1-8f2bf71e1b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131911371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1131911371
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.698713205
Short name T910
Test name
Test status
Simulation time 9000253774 ps
CPU time 74.58 seconds
Started Aug 11 06:18:48 PM PDT 24
Finished Aug 11 06:20:03 PM PDT 24
Peak memory 252804 kb
Host smart-290c6eb8-f49e-4934-9f7a-5ca847966b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698713205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.698713205
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3677624405
Short name T702
Test name
Test status
Simulation time 908985256 ps
CPU time 4.23 seconds
Started Aug 11 06:18:44 PM PDT 24
Finished Aug 11 06:18:48 PM PDT 24
Peak memory 225176 kb
Host smart-01b8e6a6-93f0-4ebe-9abd-de752d48775b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677624405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3677624405
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.778056669
Short name T898
Test name
Test status
Simulation time 494546501 ps
CPU time 13.79 seconds
Started Aug 11 06:18:50 PM PDT 24
Finished Aug 11 06:19:04 PM PDT 24
Peak memory 241560 kb
Host smart-2e4fe83d-ba48-4200-bfd7-eb6576c92f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778056669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.778056669
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3374391710
Short name T384
Test name
Test status
Simulation time 24279380 ps
CPU time 1.11 seconds
Started Aug 11 06:18:47 PM PDT 24
Finished Aug 11 06:18:48 PM PDT 24
Peak memory 217212 kb
Host smart-a09612b0-4270-4fcc-88f9-dd598b44dbb3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374391710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3374391710
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2205849722
Short name T538
Test name
Test status
Simulation time 6624508839 ps
CPU time 21.55 seconds
Started Aug 11 06:18:48 PM PDT 24
Finished Aug 11 06:19:10 PM PDT 24
Peak memory 233524 kb
Host smart-b9c26636-4768-4271-87ed-1ea1d090951d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205849722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2205849722
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3441259762
Short name T845
Test name
Test status
Simulation time 2358653425 ps
CPU time 5.56 seconds
Started Aug 11 06:18:50 PM PDT 24
Finished Aug 11 06:18:55 PM PDT 24
Peak memory 225336 kb
Host smart-5e3397c3-dfe8-4a75-8237-7fdaf29b91cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441259762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3441259762
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.442476452
Short name T479
Test name
Test status
Simulation time 335774264 ps
CPU time 3.81 seconds
Started Aug 11 06:18:50 PM PDT 24
Finished Aug 11 06:18:54 PM PDT 24
Peak memory 220908 kb
Host smart-bc70cc47-758b-47d9-af60-f7e25072f3d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=442476452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.442476452
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2226305682
Short name T18
Test name
Test status
Simulation time 53057854603 ps
CPU time 271.32 seconds
Started Aug 11 06:18:49 PM PDT 24
Finished Aug 11 06:23:20 PM PDT 24
Peak memory 266320 kb
Host smart-0e43e022-7838-45ba-a558-2642fde17878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226305682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2226305682
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.821987397
Short name T714
Test name
Test status
Simulation time 886431378 ps
CPU time 2.21 seconds
Started Aug 11 06:18:45 PM PDT 24
Finished Aug 11 06:18:48 PM PDT 24
Peak memory 217232 kb
Host smart-047b134c-c0db-4a91-923b-a831ad6e017f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821987397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.821987397
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.574566608
Short name T691
Test name
Test status
Simulation time 1866892043 ps
CPU time 6.57 seconds
Started Aug 11 06:18:50 PM PDT 24
Finished Aug 11 06:18:57 PM PDT 24
Peak memory 216980 kb
Host smart-e983a561-cee2-428c-a2c4-ae6504d98e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574566608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.574566608
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1051112587
Short name T989
Test name
Test status
Simulation time 406887069 ps
CPU time 4.47 seconds
Started Aug 11 06:18:48 PM PDT 24
Finished Aug 11 06:18:53 PM PDT 24
Peak memory 217028 kb
Host smart-4bccb7c5-a0bf-4406-a6a5-aae058ed85ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051112587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1051112587
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1424115854
Short name T484
Test name
Test status
Simulation time 64141424 ps
CPU time 0.74 seconds
Started Aug 11 06:18:49 PM PDT 24
Finished Aug 11 06:18:50 PM PDT 24
Peak memory 206592 kb
Host smart-c14f86f5-bc0b-48a4-8092-3a523a49758d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424115854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1424115854
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.644298278
Short name T561
Test name
Test status
Simulation time 6647976441 ps
CPU time 13.22 seconds
Started Aug 11 06:18:51 PM PDT 24
Finished Aug 11 06:19:04 PM PDT 24
Peak memory 225336 kb
Host smart-123073a6-f94f-4f92-9b94-9723a3b2a33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644298278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.644298278
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.583740286
Short name T693
Test name
Test status
Simulation time 96621988 ps
CPU time 0.75 seconds
Started Aug 11 06:19:06 PM PDT 24
Finished Aug 11 06:19:07 PM PDT 24
Peak memory 205896 kb
Host smart-e5b05435-9cb4-4ea1-93cc-9bc9459dfa41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583740286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.583740286
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1787129736
Short name T239
Test name
Test status
Simulation time 1030482988 ps
CPU time 2.58 seconds
Started Aug 11 06:18:54 PM PDT 24
Finished Aug 11 06:18:56 PM PDT 24
Peak memory 233408 kb
Host smart-4fc3ac29-78f6-4eb4-9f49-bbb5000592d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787129736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1787129736
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3152619160
Short name T694
Test name
Test status
Simulation time 55687866 ps
CPU time 0.74 seconds
Started Aug 11 06:18:47 PM PDT 24
Finished Aug 11 06:18:47 PM PDT 24
Peak memory 206344 kb
Host smart-65b8404a-5f8e-418f-bdeb-912fe5063127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152619160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3152619160
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.43605357
Short name T81
Test name
Test status
Simulation time 325155256249 ps
CPU time 171.55 seconds
Started Aug 11 06:18:57 PM PDT 24
Finished Aug 11 06:21:49 PM PDT 24
Peak memory 249924 kb
Host smart-e1bd436f-5371-4e0f-9481-5918daa250dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43605357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.43605357
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.823543826
Short name T657
Test name
Test status
Simulation time 32368200306 ps
CPU time 141.28 seconds
Started Aug 11 06:18:56 PM PDT 24
Finished Aug 11 06:21:17 PM PDT 24
Peak memory 253476 kb
Host smart-18a7a8b7-8608-4bfe-8e9e-316006c03bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823543826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.823543826
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3884869260
Short name T508
Test name
Test status
Simulation time 384445450 ps
CPU time 4.57 seconds
Started Aug 11 06:19:02 PM PDT 24
Finished Aug 11 06:19:07 PM PDT 24
Peak memory 233444 kb
Host smart-7ee4c02e-0b01-439c-8d44-fae0879e9ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884869260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3884869260
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.4126600188
Short name T359
Test name
Test status
Simulation time 27959878226 ps
CPU time 210.62 seconds
Started Aug 11 06:19:01 PM PDT 24
Finished Aug 11 06:22:32 PM PDT 24
Peak memory 249932 kb
Host smart-4b9ce1dc-be4b-4e50-b653-edcc241ece7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126600188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.4126600188
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4111896092
Short name T863
Test name
Test status
Simulation time 396923789 ps
CPU time 6.48 seconds
Started Aug 11 06:18:57 PM PDT 24
Finished Aug 11 06:19:03 PM PDT 24
Peak memory 225224 kb
Host smart-e2fb8424-92e1-49a9-82ec-4cecfbd85720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111896092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4111896092
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3921194311
Short name T765
Test name
Test status
Simulation time 9938381780 ps
CPU time 59.14 seconds
Started Aug 11 06:19:00 PM PDT 24
Finished Aug 11 06:20:00 PM PDT 24
Peak memory 233368 kb
Host smart-d696734e-2bd4-4b0f-8b5a-ea7db016c5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921194311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3921194311
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1648958229
Short name T35
Test name
Test status
Simulation time 28888763 ps
CPU time 1.16 seconds
Started Aug 11 06:18:50 PM PDT 24
Finished Aug 11 06:18:52 PM PDT 24
Peak memory 217160 kb
Host smart-93c1147a-a4db-4f6e-8f4b-ab276899f054
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648958229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1648958229
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3059646385
Short name T944
Test name
Test status
Simulation time 5475942436 ps
CPU time 11.39 seconds
Started Aug 11 06:18:55 PM PDT 24
Finished Aug 11 06:19:06 PM PDT 24
Peak memory 236748 kb
Host smart-5dea9256-89f1-4b85-9e42-e65af7d6e9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059646385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3059646385
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2048915638
Short name T441
Test name
Test status
Simulation time 11438720172 ps
CPU time 13.57 seconds
Started Aug 11 06:18:57 PM PDT 24
Finished Aug 11 06:19:10 PM PDT 24
Peak memory 221108 kb
Host smart-fb1ce3e9-0e09-4a22-a5f8-ab8c0f763dfa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2048915638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2048915638
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1651891840
Short name T214
Test name
Test status
Simulation time 7439280481 ps
CPU time 94.23 seconds
Started Aug 11 06:18:57 PM PDT 24
Finished Aug 11 06:20:31 PM PDT 24
Peak memory 253512 kb
Host smart-c1379607-23fe-40af-9152-4e1fbeff3622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651891840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1651891840
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1802229683
Short name T422
Test name
Test status
Simulation time 14656553 ps
CPU time 0.74 seconds
Started Aug 11 06:18:50 PM PDT 24
Finished Aug 11 06:18:51 PM PDT 24
Peak memory 206192 kb
Host smart-a9981a49-bf75-4ed5-954b-1a2772cdfff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802229683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1802229683
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1350089548
Short name T424
Test name
Test status
Simulation time 3524218880 ps
CPU time 7.62 seconds
Started Aug 11 06:18:50 PM PDT 24
Finished Aug 11 06:18:57 PM PDT 24
Peak memory 217012 kb
Host smart-a762b5ed-4a85-4390-85f2-6c02e9af8563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350089548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1350089548
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2797113724
Short name T433
Test name
Test status
Simulation time 1664810822 ps
CPU time 4.4 seconds
Started Aug 11 06:18:50 PM PDT 24
Finished Aug 11 06:18:55 PM PDT 24
Peak memory 217000 kb
Host smart-f5653ff5-a729-42f1-a190-2525f56a40a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797113724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2797113724
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2617683400
Short name T907
Test name
Test status
Simulation time 21043837 ps
CPU time 0.78 seconds
Started Aug 11 06:18:51 PM PDT 24
Finished Aug 11 06:18:52 PM PDT 24
Peak memory 206552 kb
Host smart-ac20fdc6-d70c-4433-8969-0714d8935345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617683400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2617683400
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2009549741
Short name T250
Test name
Test status
Simulation time 7716697835 ps
CPU time 21.58 seconds
Started Aug 11 06:19:00 PM PDT 24
Finished Aug 11 06:19:22 PM PDT 24
Peak memory 234528 kb
Host smart-be837179-b44d-41d0-9610-82b8107143da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009549741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2009549741
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3503656670
Short name T409
Test name
Test status
Simulation time 84728760 ps
CPU time 0.77 seconds
Started Aug 11 06:19:02 PM PDT 24
Finished Aug 11 06:19:04 PM PDT 24
Peak memory 205832 kb
Host smart-8ee4f259-df27-4285-9f75-05a671c5898c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503656670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3503656670
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.4280108212
Short name T749
Test name
Test status
Simulation time 294058815 ps
CPU time 4.25 seconds
Started Aug 11 06:19:00 PM PDT 24
Finished Aug 11 06:19:04 PM PDT 24
Peak memory 233364 kb
Host smart-49bc2a60-4fd1-4b8b-9687-f8a0c28bd95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280108212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4280108212
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3725107778
Short name T1016
Test name
Test status
Simulation time 65275900 ps
CPU time 0.85 seconds
Started Aug 11 06:18:55 PM PDT 24
Finished Aug 11 06:18:56 PM PDT 24
Peak memory 207032 kb
Host smart-3de4415b-9ab8-47e3-b5ac-889325ed89e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725107778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3725107778
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1646754762
Short name T1019
Test name
Test status
Simulation time 26473334279 ps
CPU time 111.99 seconds
Started Aug 11 06:19:01 PM PDT 24
Finished Aug 11 06:20:53 PM PDT 24
Peak memory 249924 kb
Host smart-16d4c503-164f-4897-bf1c-729674ab0bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646754762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1646754762
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.733361336
Short name T511
Test name
Test status
Simulation time 4640702406 ps
CPU time 24.85 seconds
Started Aug 11 06:19:06 PM PDT 24
Finished Aug 11 06:19:31 PM PDT 24
Peak memory 233248 kb
Host smart-5339afd2-b8a2-40ff-8690-d8d60f01a43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733361336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.733361336
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2259456741
Short name T301
Test name
Test status
Simulation time 3969590185 ps
CPU time 37.98 seconds
Started Aug 11 06:18:57 PM PDT 24
Finished Aug 11 06:19:35 PM PDT 24
Peak memory 225280 kb
Host smart-de327ae9-3511-425c-8d2a-dc5975ebeb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259456741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2259456741
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2495544928
Short name T812
Test name
Test status
Simulation time 17786315415 ps
CPU time 62.24 seconds
Started Aug 11 06:19:02 PM PDT 24
Finished Aug 11 06:20:04 PM PDT 24
Peak memory 258116 kb
Host smart-b2a1e5d8-68b2-465b-ae62-4c41d581070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495544928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2495544928
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3575963551
Short name T49
Test name
Test status
Simulation time 1425123861 ps
CPU time 26.5 seconds
Started Aug 11 06:18:58 PM PDT 24
Finished Aug 11 06:19:25 PM PDT 24
Peak memory 225276 kb
Host smart-199e23b3-3755-44a9-8e95-5c2d4886b5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575963551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3575963551
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1010215017
Short name T963
Test name
Test status
Simulation time 25131134 ps
CPU time 1.03 seconds
Started Aug 11 06:18:57 PM PDT 24
Finished Aug 11 06:18:58 PM PDT 24
Peak memory 217208 kb
Host smart-508a5714-cf6a-4482-a44b-f9cd8c0f9ebc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010215017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1010215017
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.548621557
Short name T298
Test name
Test status
Simulation time 13463952128 ps
CPU time 37.45 seconds
Started Aug 11 06:19:01 PM PDT 24
Finished Aug 11 06:19:39 PM PDT 24
Peak memory 233520 kb
Host smart-2bd0126e-9e95-4e5e-b92b-0e48928354a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548621557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.548621557
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2679020885
Short name T640
Test name
Test status
Simulation time 1604626912 ps
CPU time 7.24 seconds
Started Aug 11 06:19:03 PM PDT 24
Finished Aug 11 06:19:10 PM PDT 24
Peak memory 241636 kb
Host smart-5f395770-fec3-4d27-8c95-15a815625400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679020885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2679020885
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.702110506
Short name T710
Test name
Test status
Simulation time 834787112 ps
CPU time 4.61 seconds
Started Aug 11 06:18:54 PM PDT 24
Finished Aug 11 06:18:58 PM PDT 24
Peak memory 223876 kb
Host smart-a0891ad0-7c51-4133-942a-af21aa57e33b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=702110506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.702110506
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3979451472
Short name T874
Test name
Test status
Simulation time 195548471222 ps
CPU time 438.43 seconds
Started Aug 11 06:19:02 PM PDT 24
Finished Aug 11 06:26:21 PM PDT 24
Peak memory 274220 kb
Host smart-197f3124-8543-4be7-a1d7-91e1c7853dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979451472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3979451472
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.293761553
Short name T343
Test name
Test status
Simulation time 32192724 ps
CPU time 0.73 seconds
Started Aug 11 06:19:06 PM PDT 24
Finished Aug 11 06:19:07 PM PDT 24
Peak memory 206176 kb
Host smart-2e8d95a2-dfbe-48f7-9fb7-bbef404e96d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293761553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.293761553
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2943104706
Short name T772
Test name
Test status
Simulation time 55034534343 ps
CPU time 27.68 seconds
Started Aug 11 06:18:57 PM PDT 24
Finished Aug 11 06:19:25 PM PDT 24
Peak memory 218020 kb
Host smart-f7095285-015f-4a49-b399-d87abcae0c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943104706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2943104706
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3665249070
Short name T703
Test name
Test status
Simulation time 111115440 ps
CPU time 1 seconds
Started Aug 11 06:18:54 PM PDT 24
Finished Aug 11 06:18:55 PM PDT 24
Peak memory 208724 kb
Host smart-f1227248-ca2c-4ab4-b1da-91b90f304513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665249070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3665249070
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3386762013
Short name T859
Test name
Test status
Simulation time 19599437 ps
CPU time 0.78 seconds
Started Aug 11 06:18:55 PM PDT 24
Finished Aug 11 06:18:55 PM PDT 24
Peak memory 206580 kb
Host smart-574cfbca-dced-417f-9ffe-9a1718f8b36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386762013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3386762013
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1181038023
Short name T569
Test name
Test status
Simulation time 6227201138 ps
CPU time 13.76 seconds
Started Aug 11 06:18:58 PM PDT 24
Finished Aug 11 06:19:12 PM PDT 24
Peak memory 241696 kb
Host smart-50f92d78-a34d-46d4-97fc-e4fb1e21fff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181038023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1181038023
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.979596168
Short name T589
Test name
Test status
Simulation time 42537192 ps
CPU time 0.7 seconds
Started Aug 11 06:19:07 PM PDT 24
Finished Aug 11 06:19:08 PM PDT 24
Peak memory 205272 kb
Host smart-b94dad8f-206b-4695-b8b7-4f19962ad156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979596168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.979596168
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2255005541
Short name T180
Test name
Test status
Simulation time 79712019 ps
CPU time 2.59 seconds
Started Aug 11 06:19:06 PM PDT 24
Finished Aug 11 06:19:08 PM PDT 24
Peak memory 233436 kb
Host smart-9332046a-fb3d-490a-97a0-1f5fd7a25a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255005541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2255005541
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1448710247
Short name T450
Test name
Test status
Simulation time 58719654 ps
CPU time 0.78 seconds
Started Aug 11 06:18:56 PM PDT 24
Finished Aug 11 06:18:57 PM PDT 24
Peak memory 207052 kb
Host smart-2e441750-969a-4500-9632-a9b88f2d8ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448710247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1448710247
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.4206499010
Short name T3
Test name
Test status
Simulation time 95916486701 ps
CPU time 128.3 seconds
Started Aug 11 06:19:02 PM PDT 24
Finished Aug 11 06:21:10 PM PDT 24
Peak memory 251392 kb
Host smart-27d613f6-1453-4ba4-9823-54a9f99dc4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206499010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.4206499010
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1399529445
Short name T390
Test name
Test status
Simulation time 6587663319 ps
CPU time 10.86 seconds
Started Aug 11 06:19:07 PM PDT 24
Finished Aug 11 06:19:19 PM PDT 24
Peak memory 220312 kb
Host smart-cc3400a3-29c4-490c-a4a8-d2b1f8082590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399529445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1399529445
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1844825035
Short name T151
Test name
Test status
Simulation time 26602606878 ps
CPU time 85.38 seconds
Started Aug 11 06:19:07 PM PDT 24
Finished Aug 11 06:20:32 PM PDT 24
Peak memory 255436 kb
Host smart-f4d4da67-cbc3-45a5-b19d-d99ef6ce3c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844825035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1844825035
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2507439110
Short name T700
Test name
Test status
Simulation time 75543672 ps
CPU time 2.73 seconds
Started Aug 11 06:19:03 PM PDT 24
Finished Aug 11 06:19:06 PM PDT 24
Peak memory 225164 kb
Host smart-a0fe808b-609d-4aae-8854-5d73a0320453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507439110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2507439110
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3728792347
Short name T646
Test name
Test status
Simulation time 52284345271 ps
CPU time 36.45 seconds
Started Aug 11 06:19:04 PM PDT 24
Finished Aug 11 06:19:40 PM PDT 24
Peak memory 241708 kb
Host smart-8ef6aad7-b9ee-4108-bf6a-9d89350fd4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728792347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3728792347
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.788495200
Short name T1011
Test name
Test status
Simulation time 2602955642 ps
CPU time 26.62 seconds
Started Aug 11 06:19:02 PM PDT 24
Finished Aug 11 06:19:30 PM PDT 24
Peak memory 225296 kb
Host smart-81559d6a-00ff-46f9-b61a-31ea421e59dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788495200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.788495200
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3293696413
Short name T323
Test name
Test status
Simulation time 39580052604 ps
CPU time 74.19 seconds
Started Aug 11 06:18:56 PM PDT 24
Finished Aug 11 06:20:11 PM PDT 24
Peak memory 249444 kb
Host smart-b9099692-433d-4364-8536-d16612fb5e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293696413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3293696413
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2771796900
Short name T754
Test name
Test status
Simulation time 14517372 ps
CPU time 1.1 seconds
Started Aug 11 06:18:53 PM PDT 24
Finished Aug 11 06:18:54 PM PDT 24
Peak memory 217112 kb
Host smart-7a3ee45d-c861-4749-b804-a14417fdea08
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771796900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2771796900
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2157222841
Short name T684
Test name
Test status
Simulation time 417110561 ps
CPU time 2.42 seconds
Started Aug 11 06:19:00 PM PDT 24
Finished Aug 11 06:19:03 PM PDT 24
Peak memory 224496 kb
Host smart-1fe6ac51-a22d-4774-8820-73135c10c04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157222841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2157222841
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3091365353
Short name T637
Test name
Test status
Simulation time 2297437637 ps
CPU time 8.01 seconds
Started Aug 11 06:19:03 PM PDT 24
Finished Aug 11 06:19:11 PM PDT 24
Peak memory 225224 kb
Host smart-2528861b-3a23-426c-9675-b8a73a4298da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091365353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3091365353
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2911843011
Short name T953
Test name
Test status
Simulation time 215847813 ps
CPU time 3.99 seconds
Started Aug 11 06:19:03 PM PDT 24
Finished Aug 11 06:19:07 PM PDT 24
Peak memory 223504 kb
Host smart-17e76f64-fd48-4d46-8dbc-2ff254998a4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2911843011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2911843011
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.446652902
Short name T172
Test name
Test status
Simulation time 199715225125 ps
CPU time 297.14 seconds
Started Aug 11 06:19:08 PM PDT 24
Finished Aug 11 06:24:06 PM PDT 24
Peak memory 268644 kb
Host smart-0ea4bd03-631d-437b-ad0f-6b04abaae6d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446652902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.446652902
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1370819436
Short name T980
Test name
Test status
Simulation time 19672693151 ps
CPU time 14.34 seconds
Started Aug 11 06:19:03 PM PDT 24
Finished Aug 11 06:19:17 PM PDT 24
Peak memory 216872 kb
Host smart-b361de27-6f76-4540-81c6-1ae81771187e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370819436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1370819436
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.687117562
Short name T574
Test name
Test status
Simulation time 3589950162 ps
CPU time 6.26 seconds
Started Aug 11 06:18:56 PM PDT 24
Finished Aug 11 06:19:03 PM PDT 24
Peak memory 217096 kb
Host smart-79399fd7-840d-42eb-8c53-e9395e61f3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687117562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.687117562
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3151582363
Short name T554
Test name
Test status
Simulation time 69685632 ps
CPU time 1.96 seconds
Started Aug 11 06:19:06 PM PDT 24
Finished Aug 11 06:19:08 PM PDT 24
Peak memory 217000 kb
Host smart-6cf06518-0e4b-4547-8606-e808b0234f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151582363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3151582363
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.4086054073
Short name T403
Test name
Test status
Simulation time 90936859 ps
CPU time 0.91 seconds
Started Aug 11 06:19:03 PM PDT 24
Finished Aug 11 06:19:04 PM PDT 24
Peak memory 207588 kb
Host smart-d189784d-0aff-487f-8a0d-f4d88dcd4a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086054073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.4086054073
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2551408236
Short name T785
Test name
Test status
Simulation time 3856730541 ps
CPU time 8.45 seconds
Started Aug 11 06:19:02 PM PDT 24
Finished Aug 11 06:19:11 PM PDT 24
Peak memory 233572 kb
Host smart-0e47db62-aff6-4ae5-bbdd-d69dd351e9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551408236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2551408236
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3927404599
Short name T972
Test name
Test status
Simulation time 26264752 ps
CPU time 0.72 seconds
Started Aug 11 06:19:01 PM PDT 24
Finished Aug 11 06:19:02 PM PDT 24
Peak memory 205836 kb
Host smart-8078e100-8876-4f78-b101-a1c4e92ec7f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927404599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3927404599
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.235679750
Short name T752
Test name
Test status
Simulation time 193917812 ps
CPU time 4.23 seconds
Started Aug 11 06:19:06 PM PDT 24
Finished Aug 11 06:19:11 PM PDT 24
Peak memory 233404 kb
Host smart-b9c9f672-fc16-4b76-830c-4270e67f6ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235679750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.235679750
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1449339798
Short name T338
Test name
Test status
Simulation time 26115910 ps
CPU time 0.77 seconds
Started Aug 11 06:19:02 PM PDT 24
Finished Aug 11 06:19:03 PM PDT 24
Peak memory 207404 kb
Host smart-855f1163-09d6-49f7-ac54-59704c3b21de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449339798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1449339798
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.279266573
Short name T559
Test name
Test status
Simulation time 13738814019 ps
CPU time 75.17 seconds
Started Aug 11 06:19:08 PM PDT 24
Finished Aug 11 06:20:24 PM PDT 24
Peak memory 255492 kb
Host smart-31930852-157c-44e0-bc17-b3ac34d4080f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279266573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.279266573
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3516542991
Short name T41
Test name
Test status
Simulation time 44476039265 ps
CPU time 398.97 seconds
Started Aug 11 06:19:05 PM PDT 24
Finished Aug 11 06:25:44 PM PDT 24
Peak memory 258104 kb
Host smart-2cb61e41-4786-4493-aab6-aa65d0cbf227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516542991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3516542991
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3855129100
Short name T658
Test name
Test status
Simulation time 4148275203 ps
CPU time 21.01 seconds
Started Aug 11 06:19:04 PM PDT 24
Finished Aug 11 06:19:25 PM PDT 24
Peak memory 252828 kb
Host smart-258c7fc6-9b82-4d82-8438-942784ce1933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855129100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3855129100
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1908473146
Short name T790
Test name
Test status
Simulation time 98242453 ps
CPU time 0.72 seconds
Started Aug 11 06:19:04 PM PDT 24
Finished Aug 11 06:19:05 PM PDT 24
Peak memory 216416 kb
Host smart-867bdb2d-f3ba-43e9-a4e1-3901830d2161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908473146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1908473146
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2847923231
Short name T740
Test name
Test status
Simulation time 2917195983 ps
CPU time 9.32 seconds
Started Aug 11 06:19:07 PM PDT 24
Finished Aug 11 06:19:16 PM PDT 24
Peak memory 225264 kb
Host smart-04ea37d5-3247-4d58-a0f2-3cc9328feef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847923231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2847923231
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.477988511
Short name T663
Test name
Test status
Simulation time 45660674869 ps
CPU time 129.41 seconds
Started Aug 11 06:19:00 PM PDT 24
Finished Aug 11 06:21:09 PM PDT 24
Peak memory 225340 kb
Host smart-8126206a-f713-405e-a965-8cec2eb7d51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477988511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.477988511
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2907678030
Short name T712
Test name
Test status
Simulation time 16762425 ps
CPU time 1.06 seconds
Started Aug 11 06:19:05 PM PDT 24
Finished Aug 11 06:19:07 PM PDT 24
Peak memory 217172 kb
Host smart-467da170-1133-408e-9c7e-156a518b4c0f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907678030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2907678030
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.552412679
Short name T274
Test name
Test status
Simulation time 37462519763 ps
CPU time 28.83 seconds
Started Aug 11 06:19:08 PM PDT 24
Finished Aug 11 06:19:37 PM PDT 24
Peak memory 249832 kb
Host smart-ce5a1079-cea6-48bd-b67a-cdbb137ca4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552412679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.552412679
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1059827743
Short name T257
Test name
Test status
Simulation time 53161290687 ps
CPU time 33.12 seconds
Started Aug 11 06:19:06 PM PDT 24
Finished Aug 11 06:19:39 PM PDT 24
Peak memory 233868 kb
Host smart-8f19a205-b75a-41d5-ae91-957ad9ac9b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059827743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1059827743
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1278866780
Short name T854
Test name
Test status
Simulation time 181344813 ps
CPU time 3.68 seconds
Started Aug 11 06:19:04 PM PDT 24
Finished Aug 11 06:19:07 PM PDT 24
Peak memory 223684 kb
Host smart-5cda850b-f287-4219-b613-e1697a920644
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1278866780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1278866780
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3856685186
Short name T469
Test name
Test status
Simulation time 2225149973 ps
CPU time 27.44 seconds
Started Aug 11 06:19:05 PM PDT 24
Finished Aug 11 06:19:32 PM PDT 24
Peak memory 217136 kb
Host smart-9c8aa5e1-3839-45f1-ac05-23f31488d8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856685186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3856685186
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1678510216
Short name T736
Test name
Test status
Simulation time 29853872638 ps
CPU time 18.42 seconds
Started Aug 11 06:19:08 PM PDT 24
Finished Aug 11 06:19:27 PM PDT 24
Peak memory 217096 kb
Host smart-3a935010-7ed1-4d22-b59a-c16c9664e2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678510216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1678510216
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2597861464
Short name T372
Test name
Test status
Simulation time 216919351 ps
CPU time 2.63 seconds
Started Aug 11 06:19:03 PM PDT 24
Finished Aug 11 06:19:06 PM PDT 24
Peak memory 216972 kb
Host smart-64722969-94e2-4c92-ae01-b01ad9483933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597861464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2597861464
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2401486709
Short name T687
Test name
Test status
Simulation time 144875658 ps
CPU time 0.86 seconds
Started Aug 11 06:19:08 PM PDT 24
Finished Aug 11 06:19:09 PM PDT 24
Peak memory 206496 kb
Host smart-7829e7ef-3711-4991-8dba-58355c8538c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401486709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2401486709
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2451890799
Short name T837
Test name
Test status
Simulation time 35657783091 ps
CPU time 24.74 seconds
Started Aug 11 06:19:06 PM PDT 24
Finished Aug 11 06:19:31 PM PDT 24
Peak memory 233540 kb
Host smart-883f45cf-86fc-49d6-8375-11057a2d6b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451890799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2451890799
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.459915627
Short name T680
Test name
Test status
Simulation time 24501386 ps
CPU time 0.75 seconds
Started Aug 11 06:19:07 PM PDT 24
Finished Aug 11 06:19:08 PM PDT 24
Peak memory 206024 kb
Host smart-2b8df06c-9a02-4d9d-8b59-97668c8680ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459915627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.459915627
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.4256591955
Short name T903
Test name
Test status
Simulation time 942635495 ps
CPU time 5.57 seconds
Started Aug 11 06:19:13 PM PDT 24
Finished Aug 11 06:19:18 PM PDT 24
Peak memory 233392 kb
Host smart-c4adb077-1a6c-4065-b4c5-11edebc3b538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256591955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.4256591955
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1252391791
Short name T900
Test name
Test status
Simulation time 14628002 ps
CPU time 0.8 seconds
Started Aug 11 06:19:08 PM PDT 24
Finished Aug 11 06:19:09 PM PDT 24
Peak memory 206972 kb
Host smart-4189a10d-013d-4e96-9f2c-4403e0490275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252391791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1252391791
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3972535382
Short name T592
Test name
Test status
Simulation time 10977390234 ps
CPU time 84.85 seconds
Started Aug 11 06:19:08 PM PDT 24
Finished Aug 11 06:20:33 PM PDT 24
Peak memory 254824 kb
Host smart-e52cecd6-4324-4af6-899c-3222f550f607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972535382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3972535382
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2074083652
Short name T456
Test name
Test status
Simulation time 24078784268 ps
CPU time 224.15 seconds
Started Aug 11 06:19:04 PM PDT 24
Finished Aug 11 06:22:49 PM PDT 24
Peak memory 251336 kb
Host smart-204bcb4d-c423-4204-84bb-0a2d0baadc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074083652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2074083652
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1109319683
Short name T40
Test name
Test status
Simulation time 11105299511 ps
CPU time 46.2 seconds
Started Aug 11 06:19:07 PM PDT 24
Finished Aug 11 06:19:53 PM PDT 24
Peak memory 236664 kb
Host smart-10c2c376-b483-4158-a0bb-ce7abfb36b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109319683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1109319683
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2188472760
Short name T160
Test name
Test status
Simulation time 156963930 ps
CPU time 2.67 seconds
Started Aug 11 06:19:08 PM PDT 24
Finished Aug 11 06:19:11 PM PDT 24
Peak memory 233468 kb
Host smart-74ac8d27-d452-4623-b529-65b39f243d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188472760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2188472760
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2584266175
Short name T830
Test name
Test status
Simulation time 12671886612 ps
CPU time 61.53 seconds
Started Aug 11 06:19:08 PM PDT 24
Finished Aug 11 06:20:09 PM PDT 24
Peak memory 255964 kb
Host smart-ec103148-9c1d-41fa-a6ee-66ba981331d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584266175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2584266175
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2436631600
Short name T735
Test name
Test status
Simulation time 73083360 ps
CPU time 2.14 seconds
Started Aug 11 06:19:08 PM PDT 24
Finished Aug 11 06:19:11 PM PDT 24
Peak memory 218996 kb
Host smart-4b4c25f2-df94-47c6-81ca-d0eca686ff8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436631600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2436631600
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1664222477
Short name T682
Test name
Test status
Simulation time 10396661901 ps
CPU time 56.14 seconds
Started Aug 11 06:19:07 PM PDT 24
Finished Aug 11 06:20:03 PM PDT 24
Peak memory 233500 kb
Host smart-56c1a7b5-4639-4d81-a33c-99630c680b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664222477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1664222477
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2909073259
Short name T857
Test name
Test status
Simulation time 28080156 ps
CPU time 1.11 seconds
Started Aug 11 06:19:03 PM PDT 24
Finished Aug 11 06:19:04 PM PDT 24
Peak memory 218540 kb
Host smart-b0f1f259-8578-49b6-be66-7b9a67b4f871
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909073259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2909073259
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1146929185
Short name T873
Test name
Test status
Simulation time 28975755 ps
CPU time 2.49 seconds
Started Aug 11 06:19:09 PM PDT 24
Finished Aug 11 06:19:12 PM PDT 24
Peak memory 233024 kb
Host smart-bd9445bf-0cb4-4102-a76e-239ae7c42de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146929185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1146929185
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3997609725
Short name T636
Test name
Test status
Simulation time 1142997316 ps
CPU time 7.83 seconds
Started Aug 11 06:19:07 PM PDT 24
Finished Aug 11 06:19:15 PM PDT 24
Peak memory 233452 kb
Host smart-e0e7a15a-2466-4555-941d-28f1d6967510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997609725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3997609725
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2710487814
Short name T394
Test name
Test status
Simulation time 3109079969 ps
CPU time 8.31 seconds
Started Aug 11 06:19:08 PM PDT 24
Finished Aug 11 06:19:17 PM PDT 24
Peak memory 221188 kb
Host smart-d31faf6f-4ec7-4954-b40a-91f5cefefbcf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2710487814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2710487814
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1859909196
Short name T713
Test name
Test status
Simulation time 13066213068 ps
CPU time 131.82 seconds
Started Aug 11 06:19:10 PM PDT 24
Finished Aug 11 06:21:22 PM PDT 24
Peak memory 269184 kb
Host smart-b5f28343-3c1f-4cd9-a959-d8c651ddf232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859909196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1859909196
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3263728666
Short name T788
Test name
Test status
Simulation time 7955033670 ps
CPU time 33.29 seconds
Started Aug 11 06:19:03 PM PDT 24
Finished Aug 11 06:19:36 PM PDT 24
Peak memory 220872 kb
Host smart-733214c8-57fe-4d6b-8c8b-c75d74ef2b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263728666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3263728666
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3165948020
Short name T917
Test name
Test status
Simulation time 13446612314 ps
CPU time 9.01 seconds
Started Aug 11 06:19:05 PM PDT 24
Finished Aug 11 06:19:14 PM PDT 24
Peak memory 217048 kb
Host smart-2e9fdb27-5713-45d4-8f90-36ac863396dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165948020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3165948020
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.743590274
Short name T333
Test name
Test status
Simulation time 21013813 ps
CPU time 0.68 seconds
Started Aug 11 06:19:00 PM PDT 24
Finished Aug 11 06:19:01 PM PDT 24
Peak memory 206096 kb
Host smart-32676b06-53b3-48db-b3b6-300ad757b5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743590274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.743590274
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1563172646
Short name T28
Test name
Test status
Simulation time 306024466 ps
CPU time 0.91 seconds
Started Aug 11 06:19:02 PM PDT 24
Finished Aug 11 06:19:04 PM PDT 24
Peak memory 206544 kb
Host smart-d3176ebf-4da4-4f13-b175-cbf4408c9638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563172646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1563172646
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1350804495
Short name T643
Test name
Test status
Simulation time 10191559614 ps
CPU time 29.3 seconds
Started Aug 11 06:19:08 PM PDT 24
Finished Aug 11 06:19:37 PM PDT 24
Peak memory 235604 kb
Host smart-7b2de67d-a416-46d0-940b-0f32c1d68935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350804495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1350804495
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3778827925
Short name T72
Test name
Test status
Simulation time 12545281 ps
CPU time 0.71 seconds
Started Aug 11 06:19:13 PM PDT 24
Finished Aug 11 06:19:13 PM PDT 24
Peak memory 205836 kb
Host smart-335239ad-0f07-4783-9747-a21f2d762aff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778827925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3778827925
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4199501262
Short name T598
Test name
Test status
Simulation time 349574877 ps
CPU time 3.44 seconds
Started Aug 11 06:19:14 PM PDT 24
Finished Aug 11 06:19:18 PM PDT 24
Peak memory 233432 kb
Host smart-3773e610-c3e7-4890-940b-bc193f03d68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199501262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4199501262
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2880416204
Short name T921
Test name
Test status
Simulation time 48819901 ps
CPU time 0.73 seconds
Started Aug 11 06:19:07 PM PDT 24
Finished Aug 11 06:19:08 PM PDT 24
Peak memory 206376 kb
Host smart-cf2414cf-47c6-4450-98e2-1501dc22077b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880416204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2880416204
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3994893111
Short name T464
Test name
Test status
Simulation time 11567779256 ps
CPU time 70.47 seconds
Started Aug 11 06:19:15 PM PDT 24
Finished Aug 11 06:20:26 PM PDT 24
Peak memory 257100 kb
Host smart-25293f78-4bff-4721-8135-3dcdfea805fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994893111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3994893111
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.197572682
Short name T1014
Test name
Test status
Simulation time 24629395256 ps
CPU time 49.29 seconds
Started Aug 11 06:19:16 PM PDT 24
Finished Aug 11 06:20:06 PM PDT 24
Peak memory 234516 kb
Host smart-cfe536eb-9c25-4a32-854a-fcf409d2d8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197572682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.197572682
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3171833795
Short name T744
Test name
Test status
Simulation time 20252149778 ps
CPU time 134.65 seconds
Started Aug 11 06:19:14 PM PDT 24
Finished Aug 11 06:21:29 PM PDT 24
Peak memory 251040 kb
Host smart-8ac879ea-60b9-43a3-a977-b7466e045d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171833795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3171833795
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2937575286
Short name T697
Test name
Test status
Simulation time 914924613 ps
CPU time 9.21 seconds
Started Aug 11 06:19:12 PM PDT 24
Finished Aug 11 06:19:22 PM PDT 24
Peak memory 233396 kb
Host smart-48ba87de-99dc-474e-af84-33b50420bf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937575286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2937575286
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2360057684
Short name T248
Test name
Test status
Simulation time 4462910181 ps
CPU time 9.87 seconds
Started Aug 11 06:19:07 PM PDT 24
Finished Aug 11 06:19:17 PM PDT 24
Peak memory 233512 kb
Host smart-64111597-ef40-435a-b3f7-2a79fcbd73be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360057684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2360057684
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1947671131
Short name T741
Test name
Test status
Simulation time 101679344 ps
CPU time 1.13 seconds
Started Aug 11 06:19:08 PM PDT 24
Finished Aug 11 06:19:10 PM PDT 24
Peak memory 217200 kb
Host smart-d51772d9-bd0a-4398-91ef-f3a32370f603
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947671131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1947671131
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2695354515
Short name T719
Test name
Test status
Simulation time 409542972 ps
CPU time 6.72 seconds
Started Aug 11 06:19:07 PM PDT 24
Finished Aug 11 06:19:14 PM PDT 24
Peak memory 233392 kb
Host smart-c87d2cbb-16bb-4d57-a022-d10663f95d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695354515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2695354515
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3162660810
Short name T571
Test name
Test status
Simulation time 110324127 ps
CPU time 2.58 seconds
Started Aug 11 06:19:12 PM PDT 24
Finished Aug 11 06:19:15 PM PDT 24
Peak memory 233008 kb
Host smart-e72eaf04-2bc9-498d-abd1-916928755b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162660810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3162660810
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1831623687
Short name T850
Test name
Test status
Simulation time 663467474 ps
CPU time 6.2 seconds
Started Aug 11 06:19:17 PM PDT 24
Finished Aug 11 06:19:23 PM PDT 24
Peak memory 221112 kb
Host smart-a71c46b5-8a87-40aa-a3e4-0b6655dd912f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1831623687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1831623687
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.904427339
Short name T21
Test name
Test status
Simulation time 887969197 ps
CPU time 1.22 seconds
Started Aug 11 06:19:18 PM PDT 24
Finished Aug 11 06:19:19 PM PDT 24
Peak memory 207540 kb
Host smart-b8d5c864-23a0-45b5-b522-912bbc5e5218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904427339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.904427339
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1005960354
Short name T306
Test name
Test status
Simulation time 8289539365 ps
CPU time 42.27 seconds
Started Aug 11 06:19:04 PM PDT 24
Finished Aug 11 06:19:46 PM PDT 24
Peak memory 217040 kb
Host smart-1c85c659-0a79-4f3f-b4b2-102f7cfa7454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005960354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1005960354
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1784623085
Short name T871
Test name
Test status
Simulation time 71639135819 ps
CPU time 11.45 seconds
Started Aug 11 06:19:06 PM PDT 24
Finished Aug 11 06:19:18 PM PDT 24
Peak memory 217044 kb
Host smart-7c2099b1-9ea3-42a6-87f7-fae5bf9fe19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784623085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1784623085
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2277213187
Short name T330
Test name
Test status
Simulation time 199869969 ps
CPU time 1.39 seconds
Started Aug 11 06:19:07 PM PDT 24
Finished Aug 11 06:19:09 PM PDT 24
Peak memory 216984 kb
Host smart-bfbc0f26-7357-4c91-b438-240f855eda41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277213187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2277213187
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.873059011
Short name T364
Test name
Test status
Simulation time 21568768 ps
CPU time 0.76 seconds
Started Aug 11 06:19:09 PM PDT 24
Finished Aug 11 06:19:09 PM PDT 24
Peak memory 206588 kb
Host smart-ece65370-59a9-4833-a06e-1eb6b45b5e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873059011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.873059011
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3532066066
Short name T226
Test name
Test status
Simulation time 13511724934 ps
CPU time 17.93 seconds
Started Aug 11 06:19:15 PM PDT 24
Finished Aug 11 06:19:33 PM PDT 24
Peak memory 249748 kb
Host smart-3025990e-7fb6-4035-bb3a-d7a8cf609d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532066066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3532066066
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4173330441
Short name T550
Test name
Test status
Simulation time 41702972 ps
CPU time 0.72 seconds
Started Aug 11 06:19:17 PM PDT 24
Finished Aug 11 06:19:18 PM PDT 24
Peak memory 205888 kb
Host smart-7592ddf3-180f-45be-b97b-6f521adc3063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173330441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4173330441
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2126527188
Short name T814
Test name
Test status
Simulation time 307781760 ps
CPU time 3.16 seconds
Started Aug 11 06:19:15 PM PDT 24
Finished Aug 11 06:19:18 PM PDT 24
Peak memory 233476 kb
Host smart-fd65d8d7-c395-4694-b94d-a772604389ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126527188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2126527188
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3798073607
Short name T70
Test name
Test status
Simulation time 54531830 ps
CPU time 0.79 seconds
Started Aug 11 06:19:15 PM PDT 24
Finished Aug 11 06:19:16 PM PDT 24
Peak memory 207052 kb
Host smart-fed0f388-901b-4ae3-91bf-24e7dc668581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798073607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3798073607
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1179923817
Short name T578
Test name
Test status
Simulation time 4520522388 ps
CPU time 30.32 seconds
Started Aug 11 06:19:16 PM PDT 24
Finished Aug 11 06:19:47 PM PDT 24
Peak memory 240216 kb
Host smart-626ed22c-5a10-4fb7-9caf-5a509396d492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179923817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1179923817
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.893118963
Short name T922
Test name
Test status
Simulation time 15850030182 ps
CPU time 18.45 seconds
Started Aug 11 06:19:14 PM PDT 24
Finished Aug 11 06:19:33 PM PDT 24
Peak memory 220492 kb
Host smart-70105b20-8d2d-4361-8275-1a31f9b7db00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893118963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.893118963
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_intercept.573699701
Short name T849
Test name
Test status
Simulation time 1017713644 ps
CPU time 10.3 seconds
Started Aug 11 06:19:15 PM PDT 24
Finished Aug 11 06:19:26 PM PDT 24
Peak memory 233484 kb
Host smart-30ae8ee6-437f-4cf5-86f1-5bfe718e9887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573699701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.573699701
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1738974891
Short name T591
Test name
Test status
Simulation time 4413663835 ps
CPU time 30.4 seconds
Started Aug 11 06:19:15 PM PDT 24
Finished Aug 11 06:19:46 PM PDT 24
Peak memory 233500 kb
Host smart-8b6b34e6-d0f5-4936-bd9d-274f0dd727b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738974891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1738974891
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.46508174
Short name T912
Test name
Test status
Simulation time 49961963 ps
CPU time 1.03 seconds
Started Aug 11 06:19:15 PM PDT 24
Finished Aug 11 06:19:16 PM PDT 24
Peak memory 217188 kb
Host smart-a95b2fb4-b7b0-4964-a145-17f8b0dde5cc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46508174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.46508174
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.520593345
Short name T212
Test name
Test status
Simulation time 5090710436 ps
CPU time 10.48 seconds
Started Aug 11 06:19:16 PM PDT 24
Finished Aug 11 06:19:27 PM PDT 24
Peak memory 241352 kb
Host smart-c6272ab3-0fbb-4dbd-ac5c-57bbf6f6a981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520593345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.520593345
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3420232937
Short name T939
Test name
Test status
Simulation time 2757868629 ps
CPU time 9.98 seconds
Started Aug 11 06:19:14 PM PDT 24
Finished Aug 11 06:19:24 PM PDT 24
Peak memory 241272 kb
Host smart-bf899efc-20ba-4af0-8925-0f8536e8df4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420232937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3420232937
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2436647879
Short name T522
Test name
Test status
Simulation time 434471248 ps
CPU time 7.17 seconds
Started Aug 11 06:19:16 PM PDT 24
Finished Aug 11 06:19:24 PM PDT 24
Peak memory 222752 kb
Host smart-1fb00c87-2cc0-4ad9-9e96-0942f86f25fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2436647879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2436647879
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.236032161
Short name T546
Test name
Test status
Simulation time 48568044 ps
CPU time 1.12 seconds
Started Aug 11 06:19:13 PM PDT 24
Finished Aug 11 06:19:15 PM PDT 24
Peak memory 207640 kb
Host smart-7c8cd0bf-78e9-44ba-98ac-22c0fb5cd7aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236032161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.236032161
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.668601588
Short name T309
Test name
Test status
Simulation time 3352562147 ps
CPU time 28.06 seconds
Started Aug 11 06:19:17 PM PDT 24
Finished Aug 11 06:19:45 PM PDT 24
Peak memory 217372 kb
Host smart-a1131688-5c7b-47b4-b95e-fadcdac6be73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668601588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.668601588
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.975204852
Short name T462
Test name
Test status
Simulation time 943223151 ps
CPU time 1.86 seconds
Started Aug 11 06:19:18 PM PDT 24
Finished Aug 11 06:19:20 PM PDT 24
Peak memory 208480 kb
Host smart-1b1d1f9e-1c0f-4798-8dcf-0a6a0fb5aabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975204852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.975204852
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1259347888
Short name T497
Test name
Test status
Simulation time 110848650 ps
CPU time 1.54 seconds
Started Aug 11 06:19:15 PM PDT 24
Finished Aug 11 06:19:17 PM PDT 24
Peak memory 208844 kb
Host smart-1c8aadac-77c8-4271-8028-3f0598a99f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259347888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1259347888
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3156502822
Short name T474
Test name
Test status
Simulation time 17263600 ps
CPU time 0.69 seconds
Started Aug 11 06:19:17 PM PDT 24
Finished Aug 11 06:19:18 PM PDT 24
Peak memory 206024 kb
Host smart-9f064834-38a1-42b6-89ec-4dfc1e200851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156502822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3156502822
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1257228646
Short name T664
Test name
Test status
Simulation time 1064461529 ps
CPU time 2.47 seconds
Started Aug 11 06:19:17 PM PDT 24
Finished Aug 11 06:19:20 PM PDT 24
Peak memory 225236 kb
Host smart-5d6c7237-2a09-4182-b65d-57673310186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257228646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1257228646
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4189979475
Short name T960
Test name
Test status
Simulation time 35223194 ps
CPU time 0.69 seconds
Started Aug 11 06:18:10 PM PDT 24
Finished Aug 11 06:18:11 PM PDT 24
Peak memory 205284 kb
Host smart-b945c223-2588-4250-9b0c-e7cf28254328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189979475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
189979475
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1162559213
Short name T425
Test name
Test status
Simulation time 143457679 ps
CPU time 2.27 seconds
Started Aug 11 06:18:09 PM PDT 24
Finished Aug 11 06:18:12 PM PDT 24
Peak memory 224284 kb
Host smart-1b259485-5e06-441a-ac90-b25c2c82f8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162559213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1162559213
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3867331553
Short name T906
Test name
Test status
Simulation time 23052955 ps
CPU time 0.78 seconds
Started Aug 11 06:18:13 PM PDT 24
Finished Aug 11 06:18:13 PM PDT 24
Peak memory 207412 kb
Host smart-5555fb32-45c2-4406-8179-a9e150d233af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867331553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3867331553
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1283726652
Short name T500
Test name
Test status
Simulation time 2509867008 ps
CPU time 13.08 seconds
Started Aug 11 06:18:12 PM PDT 24
Finished Aug 11 06:18:26 PM PDT 24
Peak memory 225332 kb
Host smart-f85f100f-f6ee-4d48-91fa-9089ee1395cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283726652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1283726652
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2702327861
Short name T415
Test name
Test status
Simulation time 44294011575 ps
CPU time 71.87 seconds
Started Aug 11 06:18:12 PM PDT 24
Finished Aug 11 06:19:24 PM PDT 24
Peak memory 240292 kb
Host smart-ab5367f5-9a7a-4465-83e9-e1c8079f2be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702327861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2702327861
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3978505179
Short name T889
Test name
Test status
Simulation time 94555302508 ps
CPU time 479.07 seconds
Started Aug 11 06:18:16 PM PDT 24
Finished Aug 11 06:26:15 PM PDT 24
Peak memory 273052 kb
Host smart-e51a954d-6308-4cd0-9557-e75b8fd6c0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978505179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3978505179
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.403657855
Short name T472
Test name
Test status
Simulation time 316377391 ps
CPU time 7.15 seconds
Started Aug 11 06:18:10 PM PDT 24
Finished Aug 11 06:18:17 PM PDT 24
Peak memory 225248 kb
Host smart-506770d8-84f6-4ef1-b33f-5596a5addf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403657855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.403657855
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1856432531
Short name T804
Test name
Test status
Simulation time 615819509 ps
CPU time 4.31 seconds
Started Aug 11 06:18:12 PM PDT 24
Finished Aug 11 06:18:16 PM PDT 24
Peak memory 221220 kb
Host smart-b06370ef-8977-4cdf-8105-cc1271cee5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856432531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1856432531
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.817630415
Short name T964
Test name
Test status
Simulation time 599269782 ps
CPU time 9.66 seconds
Started Aug 11 06:18:13 PM PDT 24
Finished Aug 11 06:18:23 PM PDT 24
Peak memory 236928 kb
Host smart-e99d5c4e-ee6f-4ee0-ad6a-cb8ea564b612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817630415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.817630415
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1051676746
Short name T526
Test name
Test status
Simulation time 74542899 ps
CPU time 0.97 seconds
Started Aug 11 06:18:11 PM PDT 24
Finished Aug 11 06:18:12 PM PDT 24
Peak memory 218308 kb
Host smart-e63185b8-a9ce-4ee9-be9d-78a8d4527acb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051676746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1051676746
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2148235003
Short name T660
Test name
Test status
Simulation time 371756813 ps
CPU time 2.78 seconds
Started Aug 11 06:18:13 PM PDT 24
Finished Aug 11 06:18:16 PM PDT 24
Peak memory 225132 kb
Host smart-857cc215-c43a-4f86-bdc2-dcdd7b8411cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148235003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2148235003
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2062566324
Short name T335
Test name
Test status
Simulation time 119658755 ps
CPU time 2.18 seconds
Started Aug 11 06:18:10 PM PDT 24
Finished Aug 11 06:18:12 PM PDT 24
Peak memory 223720 kb
Host smart-e1b7262f-13f0-4859-8d11-ca562854b9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062566324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2062566324
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1062326805
Short name T395
Test name
Test status
Simulation time 11160666163 ps
CPU time 20.03 seconds
Started Aug 11 06:18:08 PM PDT 24
Finished Aug 11 06:18:28 PM PDT 24
Peak memory 222324 kb
Host smart-8b6a4d68-15ed-47d9-80f5-90e4a672cf3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1062326805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1062326805
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.209748726
Short name T75
Test name
Test status
Simulation time 427150098 ps
CPU time 1.07 seconds
Started Aug 11 06:18:13 PM PDT 24
Finished Aug 11 06:18:14 PM PDT 24
Peak memory 235628 kb
Host smart-04a10d04-84f0-4950-8c4c-9a031f80d9dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209748726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.209748726
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.599905972
Short name T750
Test name
Test status
Simulation time 55975839 ps
CPU time 0.91 seconds
Started Aug 11 06:18:13 PM PDT 24
Finished Aug 11 06:18:14 PM PDT 24
Peak memory 206976 kb
Host smart-1837607e-4c2a-4663-9020-89963a6adb14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599905972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.599905972
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1231951244
Short name T312
Test name
Test status
Simulation time 1012782175 ps
CPU time 3.29 seconds
Started Aug 11 06:18:11 PM PDT 24
Finished Aug 11 06:18:15 PM PDT 24
Peak memory 216964 kb
Host smart-881c3191-e894-4d37-bcce-05273f3e2115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231951244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1231951244
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.165086528
Short name T22
Test name
Test status
Simulation time 959305784 ps
CPU time 5.92 seconds
Started Aug 11 06:18:09 PM PDT 24
Finished Aug 11 06:18:15 PM PDT 24
Peak memory 216916 kb
Host smart-d5fe92d1-189c-402a-93f9-3e213ed40197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165086528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.165086528
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2405672066
Short name T470
Test name
Test status
Simulation time 119079598 ps
CPU time 2.02 seconds
Started Aug 11 06:18:11 PM PDT 24
Finished Aug 11 06:18:13 PM PDT 24
Peak memory 216960 kb
Host smart-1fff8e80-017c-4de4-a54d-d234c098ab50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405672066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2405672066
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.726577715
Short name T612
Test name
Test status
Simulation time 60832993 ps
CPU time 0.82 seconds
Started Aug 11 06:18:09 PM PDT 24
Finished Aug 11 06:18:10 PM PDT 24
Peak memory 206608 kb
Host smart-0661a792-fa9c-4982-a817-8cabf43d8251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726577715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.726577715
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.187761048
Short name T923
Test name
Test status
Simulation time 3519099521 ps
CPU time 3.24 seconds
Started Aug 11 06:18:11 PM PDT 24
Finished Aug 11 06:18:14 PM PDT 24
Peak memory 225232 kb
Host smart-ba0222c1-d2db-48c8-82bd-62d9dd82695c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187761048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.187761048
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1782574022
Short name T867
Test name
Test status
Simulation time 12656679 ps
CPU time 0.74 seconds
Started Aug 11 06:19:27 PM PDT 24
Finished Aug 11 06:19:27 PM PDT 24
Peak memory 205288 kb
Host smart-fbf9bd4f-08cf-490b-be14-a8a8b1111758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782574022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1782574022
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3181968411
Short name T183
Test name
Test status
Simulation time 137734069 ps
CPU time 2.76 seconds
Started Aug 11 06:19:20 PM PDT 24
Finished Aug 11 06:19:23 PM PDT 24
Peak memory 233412 kb
Host smart-0a9c3285-e755-477e-8ad5-cf4aea78fdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181968411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3181968411
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1711079584
Short name T505
Test name
Test status
Simulation time 67370366 ps
CPU time 0.83 seconds
Started Aug 11 06:19:16 PM PDT 24
Finished Aug 11 06:19:17 PM PDT 24
Peak memory 207360 kb
Host smart-76ff5f92-9611-493f-b9af-c6074f17e439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711079584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1711079584
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3220275802
Short name T267
Test name
Test status
Simulation time 6324389094 ps
CPU time 30.25 seconds
Started Aug 11 06:19:21 PM PDT 24
Finished Aug 11 06:19:51 PM PDT 24
Peak memory 236620 kb
Host smart-e1d59a98-64fe-45bc-b101-1dc4e95db584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220275802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3220275802
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2165441871
Short name T254
Test name
Test status
Simulation time 36986752066 ps
CPU time 225.68 seconds
Started Aug 11 06:19:20 PM PDT 24
Finished Aug 11 06:23:06 PM PDT 24
Peak memory 250144 kb
Host smart-771812f8-8267-474e-bbe3-66ea92b45df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165441871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2165441871
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2124040486
Short name T930
Test name
Test status
Simulation time 1435043429 ps
CPU time 10.56 seconds
Started Aug 11 06:19:23 PM PDT 24
Finished Aug 11 06:19:34 PM PDT 24
Peak memory 238944 kb
Host smart-bffebc73-7e09-452a-87b4-3ad11865ab34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124040486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2124040486
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1339565079
Short name T861
Test name
Test status
Simulation time 25778377360 ps
CPU time 52.93 seconds
Started Aug 11 06:19:22 PM PDT 24
Finished Aug 11 06:20:15 PM PDT 24
Peak memory 241716 kb
Host smart-a4291815-2851-4e3a-be22-686185199ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339565079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1339565079
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4291379868
Short name T826
Test name
Test status
Simulation time 629674194 ps
CPU time 4.11 seconds
Started Aug 11 06:19:20 PM PDT 24
Finished Aug 11 06:19:24 PM PDT 24
Peak memory 233376 kb
Host smart-241110a1-a55d-4004-b46a-7fc806516bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291379868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4291379868
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3613435433
Short name T237
Test name
Test status
Simulation time 917980931 ps
CPU time 6.07 seconds
Started Aug 11 06:19:30 PM PDT 24
Finished Aug 11 06:19:36 PM PDT 24
Peak memory 225216 kb
Host smart-c05100e7-2bcd-46cd-9b35-84d6bc97af4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613435433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3613435433
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2473275097
Short name T218
Test name
Test status
Simulation time 3745889372 ps
CPU time 7 seconds
Started Aug 11 06:19:17 PM PDT 24
Finished Aug 11 06:19:25 PM PDT 24
Peak memory 225164 kb
Host smart-284e224b-7358-4e1f-b6d4-6374ebda00c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473275097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2473275097
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.382762356
Short name T431
Test name
Test status
Simulation time 484526742 ps
CPU time 3.36 seconds
Started Aug 11 06:19:14 PM PDT 24
Finished Aug 11 06:19:18 PM PDT 24
Peak memory 225256 kb
Host smart-ae323e1b-9ffe-4a34-b332-07310e416f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382762356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.382762356
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3484595023
Short name T565
Test name
Test status
Simulation time 387994054 ps
CPU time 4.83 seconds
Started Aug 11 06:19:26 PM PDT 24
Finished Aug 11 06:19:31 PM PDT 24
Peak memory 220788 kb
Host smart-fe5e7aaa-b860-4e70-b971-2bb8798d44a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3484595023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3484595023
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3037991381
Short name T541
Test name
Test status
Simulation time 2346410292 ps
CPU time 29.82 seconds
Started Aug 11 06:19:15 PM PDT 24
Finished Aug 11 06:19:45 PM PDT 24
Peak memory 217184 kb
Host smart-0357c28a-40fa-492b-a51a-729e2ab7c91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037991381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3037991381
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1852045499
Short name T865
Test name
Test status
Simulation time 4607319605 ps
CPU time 5.44 seconds
Started Aug 11 06:19:15 PM PDT 24
Finished Aug 11 06:19:20 PM PDT 24
Peak memory 217012 kb
Host smart-c36757b6-aee8-40d3-82b8-e8ab808837a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852045499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1852045499
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.295159128
Short name T787
Test name
Test status
Simulation time 51172720 ps
CPU time 1.61 seconds
Started Aug 11 06:19:18 PM PDT 24
Finished Aug 11 06:19:20 PM PDT 24
Peak memory 216904 kb
Host smart-cc5f2742-d69d-47ad-9142-c33fdf5d2d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295159128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.295159128
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2753355969
Short name T811
Test name
Test status
Simulation time 88880843 ps
CPU time 0.88 seconds
Started Aug 11 06:19:18 PM PDT 24
Finished Aug 11 06:19:19 PM PDT 24
Peak memory 207776 kb
Host smart-2e38a1af-a6ed-498e-88eb-a3295e5b253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753355969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2753355969
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1061060787
Short name T240
Test name
Test status
Simulation time 2642855343 ps
CPU time 15.01 seconds
Started Aug 11 06:19:22 PM PDT 24
Finished Aug 11 06:19:37 PM PDT 24
Peak memory 238348 kb
Host smart-41911aca-d751-4dac-9632-60593979e0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061060787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1061060787
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2485018914
Short name T454
Test name
Test status
Simulation time 12560339 ps
CPU time 0.74 seconds
Started Aug 11 06:19:29 PM PDT 24
Finished Aug 11 06:19:30 PM PDT 24
Peak memory 206168 kb
Host smart-934545ef-b9f0-4045-a286-7f57372bac45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485018914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2485018914
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1078193566
Short name T886
Test name
Test status
Simulation time 125629592 ps
CPU time 4.02 seconds
Started Aug 11 06:19:23 PM PDT 24
Finished Aug 11 06:19:27 PM PDT 24
Peak memory 233652 kb
Host smart-bfbc4a7d-998c-4221-89a8-7368687eb301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078193566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1078193566
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.240971215
Short name T318
Test name
Test status
Simulation time 53489331 ps
CPU time 0.79 seconds
Started Aug 11 06:19:30 PM PDT 24
Finished Aug 11 06:19:31 PM PDT 24
Peak memory 207012 kb
Host smart-89e7b237-5bac-4f89-9578-748d8bb3b248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240971215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.240971215
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3835399740
Short name T238
Test name
Test status
Simulation time 7783594235 ps
CPU time 48.62 seconds
Started Aug 11 06:19:33 PM PDT 24
Finished Aug 11 06:20:21 PM PDT 24
Peak memory 249924 kb
Host smart-22952808-a8a6-4cfc-9bd5-53006568aff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835399740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3835399740
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2671769888
Short name T529
Test name
Test status
Simulation time 12090141320 ps
CPU time 36.06 seconds
Started Aug 11 06:19:40 PM PDT 24
Finished Aug 11 06:20:16 PM PDT 24
Peak memory 249480 kb
Host smart-7fb034a3-cfb9-4cb6-9ec3-c399975be624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671769888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2671769888
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1554329067
Short name T635
Test name
Test status
Simulation time 40059811903 ps
CPU time 213.12 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:23:05 PM PDT 24
Peak memory 250008 kb
Host smart-1187f7ee-a6ea-4ac6-9d22-d4a11a378d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554329067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1554329067
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1701567574
Short name T428
Test name
Test status
Simulation time 97540131 ps
CPU time 2.56 seconds
Started Aug 11 06:19:31 PM PDT 24
Finished Aug 11 06:19:34 PM PDT 24
Peak memory 225200 kb
Host smart-5ff1d087-b29d-40af-b574-7414d7392c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701567574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1701567574
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.708354721
Short name T881
Test name
Test status
Simulation time 8433258258 ps
CPU time 36.09 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:20:09 PM PDT 24
Peak memory 237560 kb
Host smart-a32e8de8-30c3-48f5-9d9e-4e3585364571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708354721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.708354721
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1671358060
Short name T205
Test name
Test status
Simulation time 21918022275 ps
CPU time 23.47 seconds
Started Aug 11 06:19:26 PM PDT 24
Finished Aug 11 06:19:49 PM PDT 24
Peak memory 233532 kb
Host smart-0bf5d11b-0743-4bc0-b54a-963c6d6307d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671358060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1671358060
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3364604237
Short name T375
Test name
Test status
Simulation time 1209735655 ps
CPU time 7.58 seconds
Started Aug 11 06:19:22 PM PDT 24
Finished Aug 11 06:19:29 PM PDT 24
Peak memory 233456 kb
Host smart-aa58c434-a75c-4b1c-a012-b33535f837b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364604237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3364604237
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2138715221
Short name T280
Test name
Test status
Simulation time 247662060 ps
CPU time 4.98 seconds
Started Aug 11 06:19:22 PM PDT 24
Finished Aug 11 06:19:27 PM PDT 24
Peak memory 233308 kb
Host smart-190758a8-0cf2-425b-af12-f3ec684de922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138715221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2138715221
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1150257867
Short name T337
Test name
Test status
Simulation time 106285844 ps
CPU time 2.42 seconds
Started Aug 11 06:19:22 PM PDT 24
Finished Aug 11 06:19:24 PM PDT 24
Peak memory 233040 kb
Host smart-9909accc-c5d3-44df-abb0-c539b8acc815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150257867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1150257867
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3120702193
Short name T876
Test name
Test status
Simulation time 4753992856 ps
CPU time 5.94 seconds
Started Aug 11 06:19:30 PM PDT 24
Finished Aug 11 06:19:36 PM PDT 24
Peak memory 221396 kb
Host smart-62575934-bf84-4e09-8629-0a66e8950761
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3120702193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3120702193
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2718151237
Short name T408
Test name
Test status
Simulation time 4752614793 ps
CPU time 6.74 seconds
Started Aug 11 06:19:22 PM PDT 24
Finished Aug 11 06:19:29 PM PDT 24
Peak memory 220760 kb
Host smart-4c7068cc-63b2-4b89-96a1-4a82b6ba7610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718151237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2718151237
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.791627426
Short name T770
Test name
Test status
Simulation time 1879698003 ps
CPU time 2.63 seconds
Started Aug 11 06:19:23 PM PDT 24
Finished Aug 11 06:19:26 PM PDT 24
Peak memory 217008 kb
Host smart-1e937c98-684a-43d3-b538-a6049ca1e90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791627426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.791627426
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.658321944
Short name T995
Test name
Test status
Simulation time 121961710 ps
CPU time 2.25 seconds
Started Aug 11 06:19:30 PM PDT 24
Finished Aug 11 06:19:32 PM PDT 24
Peak memory 216916 kb
Host smart-9b7573e4-e2d0-4764-9224-538dae375c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658321944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.658321944
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3064456349
Short name T506
Test name
Test status
Simulation time 164309415 ps
CPU time 0.81 seconds
Started Aug 11 06:19:22 PM PDT 24
Finished Aug 11 06:19:23 PM PDT 24
Peak memory 206504 kb
Host smart-b488d942-58d1-4be8-8f7a-674dc0eb0d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064456349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3064456349
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3778179634
Short name T738
Test name
Test status
Simulation time 6810163834 ps
CPU time 7.3 seconds
Started Aug 11 06:19:29 PM PDT 24
Finished Aug 11 06:19:36 PM PDT 24
Peak memory 233472 kb
Host smart-1fd61b96-a436-464f-a8f7-a9c9d2e1855b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778179634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3778179634
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2329350647
Short name T813
Test name
Test status
Simulation time 18689742 ps
CPU time 0.77 seconds
Started Aug 11 06:19:30 PM PDT 24
Finished Aug 11 06:19:31 PM PDT 24
Peak memory 205860 kb
Host smart-957f4e90-2a6b-4d22-ad97-39818c4106eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329350647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2329350647
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2857630205
Short name T840
Test name
Test status
Simulation time 475821171 ps
CPU time 3.4 seconds
Started Aug 11 06:19:30 PM PDT 24
Finished Aug 11 06:19:33 PM PDT 24
Peak memory 233416 kb
Host smart-ee853a21-1108-4d57-8bb8-ee7aa6dddfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857630205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2857630205
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.4218786520
Short name T143
Test name
Test status
Simulation time 155738038 ps
CPU time 0.79 seconds
Started Aug 11 06:19:29 PM PDT 24
Finished Aug 11 06:19:30 PM PDT 24
Peak memory 207052 kb
Host smart-102117b2-544d-4668-8a1e-535351c3dd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218786520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4218786520
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1126852902
Short name T875
Test name
Test status
Simulation time 32984454744 ps
CPU time 111.6 seconds
Started Aug 11 06:19:31 PM PDT 24
Finished Aug 11 06:21:23 PM PDT 24
Peak memory 249912 kb
Host smart-782ba4b9-2b73-4ab3-8ca6-e856789f3c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126852902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1126852902
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.729304728
Short name T468
Test name
Test status
Simulation time 382629044648 ps
CPU time 217.73 seconds
Started Aug 11 06:19:33 PM PDT 24
Finished Aug 11 06:23:11 PM PDT 24
Peak memory 250004 kb
Host smart-0f83b2e8-e135-42ce-8602-8ce9f9aee051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729304728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.729304728
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3795975313
Short name T206
Test name
Test status
Simulation time 332003227805 ps
CPU time 171.76 seconds
Started Aug 11 06:19:29 PM PDT 24
Finished Aug 11 06:22:21 PM PDT 24
Peak memory 250124 kb
Host smart-e90cf628-5620-4cea-b274-7a833ca915f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795975313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3795975313
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1370969072
Short name T570
Test name
Test status
Simulation time 264159379 ps
CPU time 3.61 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:19:36 PM PDT 24
Peak memory 233764 kb
Host smart-67e130cd-a874-4ee6-ac4b-e7b188c3c17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370969072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1370969072
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.134727091
Short name T968
Test name
Test status
Simulation time 2967704713 ps
CPU time 58.45 seconds
Started Aug 11 06:19:33 PM PDT 24
Finished Aug 11 06:20:31 PM PDT 24
Peak memory 252352 kb
Host smart-29a0aaaf-54ca-4863-ae2c-40170faf6979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134727091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.134727091
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.977359375
Short name T593
Test name
Test status
Simulation time 701745623 ps
CPU time 5.59 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:19:38 PM PDT 24
Peak memory 233492 kb
Host smart-8c245dd7-1762-41f6-8c77-38c905566b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977359375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.977359375
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4055985006
Short name T1007
Test name
Test status
Simulation time 22200619716 ps
CPU time 141.95 seconds
Started Aug 11 06:19:30 PM PDT 24
Finished Aug 11 06:21:52 PM PDT 24
Peak memory 225316 kb
Host smart-d2381550-5185-4aeb-8596-4fd6e3bf81cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055985006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4055985006
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1846147676
Short name T909
Test name
Test status
Simulation time 3183903276 ps
CPU time 10.5 seconds
Started Aug 11 06:19:33 PM PDT 24
Finished Aug 11 06:19:43 PM PDT 24
Peak memory 225472 kb
Host smart-9439983d-398a-401f-bdcf-dc5f08ccf4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846147676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1846147676
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1784626434
Short name T482
Test name
Test status
Simulation time 2703830429 ps
CPU time 6.36 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:19:38 PM PDT 24
Peak memory 225296 kb
Host smart-17efc656-6c36-485b-8e1b-65ba3f0e9bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784626434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1784626434
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3911540337
Short name T613
Test name
Test status
Simulation time 262184536 ps
CPU time 5.37 seconds
Started Aug 11 06:19:31 PM PDT 24
Finished Aug 11 06:19:36 PM PDT 24
Peak memory 223156 kb
Host smart-c581d0a5-08de-4490-8de0-02228d21f823
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3911540337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3911540337
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.356170041
Short name T533
Test name
Test status
Simulation time 10109759272 ps
CPU time 8.48 seconds
Started Aug 11 06:19:29 PM PDT 24
Finished Aug 11 06:19:37 PM PDT 24
Peak memory 225348 kb
Host smart-8ccd7b82-4c04-4630-9f71-caf702c6a649
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356170041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.356170041
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.476432945
Short name T458
Test name
Test status
Simulation time 1338793464 ps
CPU time 13.59 seconds
Started Aug 11 06:19:30 PM PDT 24
Finished Aug 11 06:19:44 PM PDT 24
Peak memory 216948 kb
Host smart-6522f806-4a88-473b-ade8-f8a6f8510b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476432945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.476432945
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2257610922
Short name T879
Test name
Test status
Simulation time 6027840522 ps
CPU time 7.9 seconds
Started Aug 11 06:19:35 PM PDT 24
Finished Aug 11 06:19:43 PM PDT 24
Peak memory 217188 kb
Host smart-856f4327-acf8-4b45-a254-febfbe69effc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257610922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2257610922
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2393368726
Short name T349
Test name
Test status
Simulation time 26859458 ps
CPU time 1.53 seconds
Started Aug 11 06:19:36 PM PDT 24
Finished Aug 11 06:19:37 PM PDT 24
Peak memory 217176 kb
Host smart-5cbca3e1-1155-4c85-94a0-21b8890101fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393368726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2393368726
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.191698905
Short name T562
Test name
Test status
Simulation time 229921061 ps
CPU time 0.95 seconds
Started Aug 11 06:19:33 PM PDT 24
Finished Aug 11 06:19:34 PM PDT 24
Peak memory 206540 kb
Host smart-fe05b9cd-c103-4351-9c02-6c73d1922c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191698905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.191698905
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.4075374829
Short name T261
Test name
Test status
Simulation time 617934342 ps
CPU time 6.15 seconds
Started Aug 11 06:19:34 PM PDT 24
Finished Aug 11 06:19:40 PM PDT 24
Peak memory 233480 kb
Host smart-bafbfa11-59c2-4fb7-9314-5572e4e42307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075374829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.4075374829
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2923542288
Short name T504
Test name
Test status
Simulation time 22372629 ps
CPU time 0.74 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:19:33 PM PDT 24
Peak memory 205480 kb
Host smart-cd8c40ab-45ca-44b8-84a5-c23010f4957f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923542288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2923542288
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3403769645
Short name T599
Test name
Test status
Simulation time 535022411 ps
CPU time 2.79 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:19:35 PM PDT 24
Peak memory 225184 kb
Host smart-d15f673b-0179-41a4-a7a0-bfbf24084ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403769645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3403769645
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2617067448
Short name T771
Test name
Test status
Simulation time 15283463 ps
CPU time 0.84 seconds
Started Aug 11 06:19:31 PM PDT 24
Finished Aug 11 06:19:32 PM PDT 24
Peak memory 207076 kb
Host smart-0d66eb1e-ebe9-4e7b-a13e-5c74ab4c095d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617067448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2617067448
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.4224617754
Short name T969
Test name
Test status
Simulation time 49806089466 ps
CPU time 98.56 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:21:11 PM PDT 24
Peak memory 249904 kb
Host smart-e26f3568-2404-4dc0-9e4d-d5d6d267eb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224617754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.4224617754
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1971959428
Short name T838
Test name
Test status
Simulation time 10051593505 ps
CPU time 116.39 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:21:28 PM PDT 24
Peak memory 249908 kb
Host smart-f64f5c87-21b9-46d5-8c10-dc06e86f0d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971959428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1971959428
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.871408781
Short name T827
Test name
Test status
Simulation time 272230541 ps
CPU time 4 seconds
Started Aug 11 06:19:30 PM PDT 24
Finished Aug 11 06:19:34 PM PDT 24
Peak memory 233432 kb
Host smart-054fe3a8-6bc4-4cdb-882c-aae9e65c7068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871408781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.871408781
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2644340994
Short name T516
Test name
Test status
Simulation time 22697130813 ps
CPU time 42.44 seconds
Started Aug 11 06:19:28 PM PDT 24
Finished Aug 11 06:20:11 PM PDT 24
Peak memory 240768 kb
Host smart-243ae627-59ec-4ee4-90b6-944de1ab5b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644340994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2644340994
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.206134742
Short name T659
Test name
Test status
Simulation time 18382202657 ps
CPU time 18.71 seconds
Started Aug 11 06:19:30 PM PDT 24
Finished Aug 11 06:19:49 PM PDT 24
Peak memory 225248 kb
Host smart-2bc50de5-22b2-412f-bb43-a87aa3b0e85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206134742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.206134742
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4107596929
Short name T243
Test name
Test status
Simulation time 47274606067 ps
CPU time 97.17 seconds
Started Aug 11 06:19:39 PM PDT 24
Finished Aug 11 06:21:17 PM PDT 24
Peak memory 238256 kb
Host smart-a5c1a8e9-82a6-40dc-9d3b-98d2559d0a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107596929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4107596929
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.545592162
Short name T530
Test name
Test status
Simulation time 2773770510 ps
CPU time 11.13 seconds
Started Aug 11 06:19:30 PM PDT 24
Finished Aug 11 06:19:41 PM PDT 24
Peak memory 233504 kb
Host smart-1b41cb62-7cad-4330-9775-e3e289cdfb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545592162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.545592162
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2397496854
Short name T610
Test name
Test status
Simulation time 104514227 ps
CPU time 2.27 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:19:34 PM PDT 24
Peak memory 223744 kb
Host smart-ea4b19d2-f898-463e-9512-796adab1c9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397496854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2397496854
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3074499395
Short name T993
Test name
Test status
Simulation time 1410395667 ps
CPU time 12.55 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:19:45 PM PDT 24
Peak memory 222884 kb
Host smart-d87fb7dc-80e2-488c-af52-e5e76af043c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3074499395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3074499395
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2413326613
Short name T15
Test name
Test status
Simulation time 2434106959 ps
CPU time 23.64 seconds
Started Aug 11 06:19:34 PM PDT 24
Finished Aug 11 06:19:57 PM PDT 24
Peak memory 225376 kb
Host smart-354a3de7-4fef-4adb-9b50-7e778f02cda9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413326613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2413326613
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2507877245
Short name T489
Test name
Test status
Simulation time 13258792559 ps
CPU time 22.4 seconds
Started Aug 11 06:19:33 PM PDT 24
Finished Aug 11 06:19:55 PM PDT 24
Peak memory 217272 kb
Host smart-4b382c33-3af1-426d-a15b-6bb9a1094b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507877245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2507877245
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3388258179
Short name T676
Test name
Test status
Simulation time 445863617 ps
CPU time 3.38 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:19:35 PM PDT 24
Peak memory 216944 kb
Host smart-5645fb28-f3fc-4e38-ab76-abf49cc92c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388258179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3388258179
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2712395409
Short name T313
Test name
Test status
Simulation time 89013872 ps
CPU time 0.98 seconds
Started Aug 11 06:19:40 PM PDT 24
Finished Aug 11 06:19:41 PM PDT 24
Peak memory 207908 kb
Host smart-95bd740a-5ad5-4d8c-81f0-1a8b4cf4ad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712395409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2712395409
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1855345567
Short name T617
Test name
Test status
Simulation time 158306983 ps
CPU time 0.84 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:19:33 PM PDT 24
Peak memory 206564 kb
Host smart-08e7f596-65d7-4cab-b71e-4dbd1fc4685d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855345567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1855345567
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.801585188
Short name T762
Test name
Test status
Simulation time 638236184 ps
CPU time 7.51 seconds
Started Aug 11 06:19:30 PM PDT 24
Finished Aug 11 06:19:38 PM PDT 24
Peak memory 239680 kb
Host smart-aeb573ed-0019-4235-9a1f-f7881c754c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801585188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.801585188
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4127594315
Short name T607
Test name
Test status
Simulation time 13228335 ps
CPU time 0.82 seconds
Started Aug 11 06:19:37 PM PDT 24
Finished Aug 11 06:19:38 PM PDT 24
Peak memory 205808 kb
Host smart-70671680-62a0-418a-81f5-9a4a111b6709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127594315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4127594315
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.720517816
Short name T696
Test name
Test status
Simulation time 2450003987 ps
CPU time 14.47 seconds
Started Aug 11 06:19:39 PM PDT 24
Finished Aug 11 06:19:53 PM PDT 24
Peak memory 233488 kb
Host smart-05f83005-ff9f-466a-ace0-2eb1cb31aa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720517816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.720517816
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3469240886
Short name T501
Test name
Test status
Simulation time 14691354 ps
CPU time 0.76 seconds
Started Aug 11 06:19:29 PM PDT 24
Finished Aug 11 06:19:30 PM PDT 24
Peak memory 207392 kb
Host smart-853d8993-6da1-4e64-8d86-c58c23adc2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469240886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3469240886
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3871245948
Short name T942
Test name
Test status
Simulation time 199035213225 ps
CPU time 359.72 seconds
Started Aug 11 06:19:39 PM PDT 24
Finished Aug 11 06:25:39 PM PDT 24
Peak memory 257608 kb
Host smart-81288143-528a-4324-9103-781516431248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871245948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3871245948
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3859043028
Short name T88
Test name
Test status
Simulation time 40106282185 ps
CPU time 383.2 seconds
Started Aug 11 06:19:39 PM PDT 24
Finished Aug 11 06:26:03 PM PDT 24
Peak memory 249976 kb
Host smart-e8426bb1-82c1-48ea-88a3-e734eef543be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859043028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3859043028
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.132835923
Short name T733
Test name
Test status
Simulation time 7543515528 ps
CPU time 34.48 seconds
Started Aug 11 06:19:37 PM PDT 24
Finished Aug 11 06:20:12 PM PDT 24
Peak memory 225304 kb
Host smart-c67d4c09-4e43-4cf5-98db-3468a00f3b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132835923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.132835923
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.791969631
Short name T164
Test name
Test status
Simulation time 5871036221 ps
CPU time 41.91 seconds
Started Aug 11 06:19:38 PM PDT 24
Finished Aug 11 06:20:20 PM PDT 24
Peak memory 225376 kb
Host smart-2feb9963-4ba0-4d9e-bd52-cb5b7a360d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791969631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.791969631
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3534529098
Short name T836
Test name
Test status
Simulation time 59992042701 ps
CPU time 136.79 seconds
Started Aug 11 06:19:49 PM PDT 24
Finished Aug 11 06:22:06 PM PDT 24
Peak memory 254996 kb
Host smart-1bca7bc0-f481-40ef-a8a8-319d9310905e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534529098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3534529098
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.877040821
Short name T321
Test name
Test status
Simulation time 109849518 ps
CPU time 2.51 seconds
Started Aug 11 06:19:38 PM PDT 24
Finished Aug 11 06:19:41 PM PDT 24
Peak memory 233128 kb
Host smart-b4ae1199-ed09-4d7e-b6f2-30511cb004dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877040821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.877040821
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3065099048
Short name T256
Test name
Test status
Simulation time 1988110695 ps
CPU time 29.49 seconds
Started Aug 11 06:19:38 PM PDT 24
Finished Aug 11 06:20:07 PM PDT 24
Peak memory 251208 kb
Host smart-37d578dd-d88c-4505-88ce-4d31b2d2b0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065099048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3065099048
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3613356282
Short name T715
Test name
Test status
Simulation time 5602938013 ps
CPU time 6.4 seconds
Started Aug 11 06:19:40 PM PDT 24
Finished Aug 11 06:19:47 PM PDT 24
Peak memory 225280 kb
Host smart-207b0b54-a8b3-4217-819f-16ed2c873767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613356282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3613356282
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2169972281
Short name T477
Test name
Test status
Simulation time 102442511 ps
CPU time 2.29 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:19:34 PM PDT 24
Peak memory 225256 kb
Host smart-fc10b226-8fe3-4ca7-b7d3-5da48f8e0c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169972281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2169972281
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2919645740
Short name T490
Test name
Test status
Simulation time 4740500522 ps
CPU time 13.1 seconds
Started Aug 11 06:19:40 PM PDT 24
Finished Aug 11 06:19:53 PM PDT 24
Peak memory 219412 kb
Host smart-7cef7ea4-cc61-4069-9206-cba698f71250
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2919645740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2919645740
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2945472977
Short name T169
Test name
Test status
Simulation time 23088691816 ps
CPU time 252.05 seconds
Started Aug 11 06:19:39 PM PDT 24
Finished Aug 11 06:23:52 PM PDT 24
Peak memory 258128 kb
Host smart-c23d7b17-750e-472f-8cff-4229d6a23e63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945472977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2945472977
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3197815040
Short name T757
Test name
Test status
Simulation time 17630878 ps
CPU time 0.74 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:19:33 PM PDT 24
Peak memory 206144 kb
Host smart-fb23dd3c-bf5e-4a66-aef4-dc2377f321a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197815040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3197815040
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4102136891
Short name T549
Test name
Test status
Simulation time 2159963621 ps
CPU time 6.69 seconds
Started Aug 11 06:19:32 PM PDT 24
Finished Aug 11 06:19:39 PM PDT 24
Peak memory 217060 kb
Host smart-72a3faa9-f87f-4403-b621-787eafda83cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102136891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4102136891
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1783720621
Short name T487
Test name
Test status
Simulation time 112598370 ps
CPU time 1.12 seconds
Started Aug 11 06:19:34 PM PDT 24
Finished Aug 11 06:19:35 PM PDT 24
Peak memory 216784 kb
Host smart-413ff56d-e5f2-4395-bef3-2dc95470337a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783720621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1783720621
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.605506244
Short name T373
Test name
Test status
Simulation time 204486502 ps
CPU time 0.79 seconds
Started Aug 11 06:19:34 PM PDT 24
Finished Aug 11 06:19:35 PM PDT 24
Peak memory 206592 kb
Host smart-44fe35aa-5441-4c46-b8e6-dbf1f3fbd396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605506244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.605506244
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3979707649
Short name T485
Test name
Test status
Simulation time 4318951704 ps
CPU time 6.1 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:19:53 PM PDT 24
Peak memory 233492 kb
Host smart-56724382-e665-4896-b322-b48c14422ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979707649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3979707649
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2407160833
Short name T822
Test name
Test status
Simulation time 26910945 ps
CPU time 0.73 seconds
Started Aug 11 06:19:40 PM PDT 24
Finished Aug 11 06:19:41 PM PDT 24
Peak memory 205476 kb
Host smart-4d230330-742c-4c24-8823-acde012b63e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407160833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2407160833
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3143639778
Short name T93
Test name
Test status
Simulation time 719912178 ps
CPU time 4.98 seconds
Started Aug 11 06:19:44 PM PDT 24
Finished Aug 11 06:19:49 PM PDT 24
Peak memory 233428 kb
Host smart-544d8aad-959e-4603-bcbb-f348116575e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143639778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3143639778
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1283770061
Short name T638
Test name
Test status
Simulation time 66884757 ps
CPU time 0.75 seconds
Started Aug 11 06:19:40 PM PDT 24
Finished Aug 11 06:19:41 PM PDT 24
Peak memory 207040 kb
Host smart-ea7dfa15-eff0-4bd7-84fc-ffca8dd2b1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283770061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1283770061
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1104762337
Short name T57
Test name
Test status
Simulation time 57166685397 ps
CPU time 92.14 seconds
Started Aug 11 06:19:39 PM PDT 24
Finished Aug 11 06:21:11 PM PDT 24
Peak memory 239544 kb
Host smart-b72ff376-3282-4789-bf60-ddbf0a2d65d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104762337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1104762337
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.4293911372
Short name T311
Test name
Test status
Simulation time 55510387457 ps
CPU time 86.48 seconds
Started Aug 11 06:19:42 PM PDT 24
Finished Aug 11 06:21:08 PM PDT 24
Peak memory 241828 kb
Host smart-c19bc7c3-247c-4198-9a69-63ff47709cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293911372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.4293911372
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3382450341
Short name T178
Test name
Test status
Simulation time 12345867812 ps
CPU time 149.16 seconds
Started Aug 11 06:19:39 PM PDT 24
Finished Aug 11 06:22:09 PM PDT 24
Peak memory 250104 kb
Host smart-48f23858-b54b-4969-848a-8302d2fb1c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382450341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3382450341
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.229247375
Short name T361
Test name
Test status
Simulation time 1026637644 ps
CPU time 6.33 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:19:53 PM PDT 24
Peak memory 234484 kb
Host smart-c281e706-8860-4ff7-a941-37e2a72f7d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229247375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.229247375
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1016757520
Short name T211
Test name
Test status
Simulation time 8156107935 ps
CPU time 20.71 seconds
Started Aug 11 06:19:38 PM PDT 24
Finished Aug 11 06:19:59 PM PDT 24
Peak memory 234548 kb
Host smart-ad1903ce-4a7a-4ca8-8006-7e9699598ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016757520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1016757520
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.603292929
Short name T674
Test name
Test status
Simulation time 236835384 ps
CPU time 5.31 seconds
Started Aug 11 06:19:40 PM PDT 24
Finished Aug 11 06:19:46 PM PDT 24
Peak memory 219520 kb
Host smart-61427c63-48e6-4a80-96d5-da4ce983b544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603292929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.603292929
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1431931216
Short name T518
Test name
Test status
Simulation time 40303073984 ps
CPU time 46.13 seconds
Started Aug 11 06:19:40 PM PDT 24
Finished Aug 11 06:20:27 PM PDT 24
Peak memory 249640 kb
Host smart-4edc3e5e-c0a4-45dd-8648-d3d1455e8770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431931216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1431931216
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2655130760
Short name T949
Test name
Test status
Simulation time 1016462402 ps
CPU time 3.29 seconds
Started Aug 11 06:19:41 PM PDT 24
Finished Aug 11 06:19:45 PM PDT 24
Peak memory 233472 kb
Host smart-f1b005de-af6a-4b4d-a007-20057b8ce096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655130760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2655130760
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3753051988
Short name T276
Test name
Test status
Simulation time 2807566017 ps
CPU time 9.22 seconds
Started Aug 11 06:19:40 PM PDT 24
Finished Aug 11 06:19:49 PM PDT 24
Peak memory 233536 kb
Host smart-7dedf0bf-8432-4a1b-a1db-661c650ed248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753051988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3753051988
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2312723147
Short name T1
Test name
Test status
Simulation time 356825455 ps
CPU time 6.37 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:19:53 PM PDT 24
Peak memory 223652 kb
Host smart-8bbecd51-b5d3-43c4-a212-306c9fa946f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2312723147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2312723147
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.4248828104
Short name T678
Test name
Test status
Simulation time 355870173230 ps
CPU time 542.86 seconds
Started Aug 11 06:19:42 PM PDT 24
Finished Aug 11 06:28:45 PM PDT 24
Peak memory 270732 kb
Host smart-85ef2f4e-ebf5-42e2-876f-c5e5daa5064b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248828104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.4248828104
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3191821340
Short name T705
Test name
Test status
Simulation time 5387585222 ps
CPU time 29.14 seconds
Started Aug 11 06:19:44 PM PDT 24
Finished Aug 11 06:20:13 PM PDT 24
Peak memory 216992 kb
Host smart-d34bd170-7d55-4649-ac78-2241aaab20eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191821340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3191821340
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1431453770
Short name T768
Test name
Test status
Simulation time 101096784 ps
CPU time 0.99 seconds
Started Aug 11 06:19:39 PM PDT 24
Finished Aug 11 06:19:41 PM PDT 24
Peak memory 207752 kb
Host smart-6b02c8ff-6a66-4111-b259-c9f17f730e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431453770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1431453770
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.4171487307
Short name T29
Test name
Test status
Simulation time 115794310 ps
CPU time 0.78 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:19:47 PM PDT 24
Peak memory 206832 kb
Host smart-6ce119ff-debc-4740-a0d9-818478f33535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171487307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.4171487307
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3095047236
Short name T856
Test name
Test status
Simulation time 83094180 ps
CPU time 0.8 seconds
Started Aug 11 06:19:37 PM PDT 24
Finished Aug 11 06:19:38 PM PDT 24
Peak memory 206476 kb
Host smart-a4852294-cf25-4fea-af9b-75f651600fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095047236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3095047236
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4170165895
Short name T896
Test name
Test status
Simulation time 40296986748 ps
CPU time 23.58 seconds
Started Aug 11 06:19:37 PM PDT 24
Finished Aug 11 06:20:00 PM PDT 24
Peak memory 233496 kb
Host smart-d81c12cf-8195-44d2-9710-2bd6670aa4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170165895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4170165895
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2252006708
Short name T1020
Test name
Test status
Simulation time 14220687 ps
CPU time 0.76 seconds
Started Aug 11 06:19:44 PM PDT 24
Finished Aug 11 06:19:44 PM PDT 24
Peak memory 205788 kb
Host smart-42f73ae9-7e23-4a26-9655-529198e64195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252006708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2252006708
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4155103426
Short name T434
Test name
Test status
Simulation time 5737614351 ps
CPU time 7.54 seconds
Started Aug 11 06:19:41 PM PDT 24
Finished Aug 11 06:19:49 PM PDT 24
Peak memory 225256 kb
Host smart-85ac07de-7ca5-4131-b9d1-e13f0d65a15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155103426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4155103426
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.4242612607
Short name T328
Test name
Test status
Simulation time 39745821 ps
CPU time 0.78 seconds
Started Aug 11 06:19:37 PM PDT 24
Finished Aug 11 06:19:38 PM PDT 24
Peak memory 207028 kb
Host smart-491b973c-412c-405f-ad6a-1f95bf438b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242612607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.4242612607
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1153148947
Short name T753
Test name
Test status
Simulation time 4052536422 ps
CPU time 24.15 seconds
Started Aug 11 06:19:45 PM PDT 24
Finished Aug 11 06:20:09 PM PDT 24
Peak memory 249904 kb
Host smart-7c0d1e96-a2f9-4805-bb56-8575801094e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153148947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1153148947
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.15908739
Short name T376
Test name
Test status
Simulation time 71713949776 ps
CPU time 153.57 seconds
Started Aug 11 06:19:45 PM PDT 24
Finished Aug 11 06:22:19 PM PDT 24
Peak memory 258048 kb
Host smart-4c70794a-8aef-4ecc-85b9-ba3d562bdb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15908739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.15908739
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3194067020
Short name T47
Test name
Test status
Simulation time 2930922499 ps
CPU time 47.89 seconds
Started Aug 11 06:19:49 PM PDT 24
Finished Aug 11 06:20:37 PM PDT 24
Peak memory 239380 kb
Host smart-1865af12-9873-46ae-9a41-7c93e42f27b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194067020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3194067020
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3652134853
Short name T519
Test name
Test status
Simulation time 647961597 ps
CPU time 8.36 seconds
Started Aug 11 06:19:40 PM PDT 24
Finished Aug 11 06:19:49 PM PDT 24
Peak memory 234448 kb
Host smart-e75ced74-9eaa-499c-91c0-38f024cb1535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652134853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3652134853
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3954330050
Short name T774
Test name
Test status
Simulation time 1132981290 ps
CPU time 26.11 seconds
Started Aug 11 06:19:45 PM PDT 24
Finished Aug 11 06:20:12 PM PDT 24
Peak memory 254704 kb
Host smart-c1d7e6d3-2d5f-46dc-8b25-9aff5c358def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954330050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3954330050
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3298389335
Short name T220
Test name
Test status
Simulation time 127181220 ps
CPU time 3.38 seconds
Started Aug 11 06:19:40 PM PDT 24
Finished Aug 11 06:19:44 PM PDT 24
Peak memory 220980 kb
Host smart-5f508652-b887-4f44-b4b9-d903aef7741a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298389335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3298389335
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3101087488
Short name T225
Test name
Test status
Simulation time 444273598 ps
CPU time 10.09 seconds
Started Aug 11 06:19:39 PM PDT 24
Finished Aug 11 06:19:49 PM PDT 24
Peak memory 233452 kb
Host smart-595c4c81-f3e8-4782-8e57-d7cbb0beadd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101087488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3101087488
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3319718997
Short name T835
Test name
Test status
Simulation time 25725231392 ps
CPU time 27.68 seconds
Started Aug 11 06:19:39 PM PDT 24
Finished Aug 11 06:20:07 PM PDT 24
Peak memory 225312 kb
Host smart-684a627c-ade2-45a8-916d-9643b9aed65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319718997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3319718997
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.4098039833
Short name T543
Test name
Test status
Simulation time 145269680 ps
CPU time 2.62 seconds
Started Aug 11 06:19:38 PM PDT 24
Finished Aug 11 06:19:41 PM PDT 24
Peak memory 225236 kb
Host smart-47ad8176-131e-48b1-9e44-437d4f9bbd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098039833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4098039833
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2305647978
Short name T820
Test name
Test status
Simulation time 727515359 ps
CPU time 9.21 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:19:55 PM PDT 24
Peak memory 223708 kb
Host smart-ff9bc2a6-b617-469e-a248-e493d7f21a53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2305647978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2305647978
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.796219800
Short name T683
Test name
Test status
Simulation time 5733875561 ps
CPU time 79.4 seconds
Started Aug 11 06:19:52 PM PDT 24
Finished Aug 11 06:21:11 PM PDT 24
Peak memory 249832 kb
Host smart-b0726745-3e6e-4e0b-8f05-02945d2e1d5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796219800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.796219800
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1242294166
Short name T56
Test name
Test status
Simulation time 4530529933 ps
CPU time 15.56 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:20:02 PM PDT 24
Peak memory 217016 kb
Host smart-7f37359b-1aa5-4cce-a34a-5e5f712532fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242294166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1242294166
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1538498686
Short name T331
Test name
Test status
Simulation time 2801123562 ps
CPU time 8.8 seconds
Started Aug 11 06:19:42 PM PDT 24
Finished Aug 11 06:19:51 PM PDT 24
Peak memory 217004 kb
Host smart-cf3e02c3-787b-4bf8-a3fe-f1778ea6c340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538498686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1538498686
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2019550990
Short name T1022
Test name
Test status
Simulation time 558065324 ps
CPU time 1.98 seconds
Started Aug 11 06:19:41 PM PDT 24
Finished Aug 11 06:19:43 PM PDT 24
Peak memory 216988 kb
Host smart-458e6138-d230-4705-9a49-741d78fccc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019550990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2019550990
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1789121405
Short name T340
Test name
Test status
Simulation time 31363860 ps
CPU time 0.82 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:19:47 PM PDT 24
Peak memory 206236 kb
Host smart-07825bb1-801f-42e3-9dfd-50c567965f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789121405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1789121405
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3258430617
Short name T385
Test name
Test status
Simulation time 421410590 ps
CPU time 2.2 seconds
Started Aug 11 06:19:42 PM PDT 24
Finished Aug 11 06:19:44 PM PDT 24
Peak memory 224764 kb
Host smart-294fbd5c-e3e7-4304-8494-b54611acd858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258430617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3258430617
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.624837979
Short name T389
Test name
Test status
Simulation time 46320572 ps
CPU time 0.73 seconds
Started Aug 11 06:19:52 PM PDT 24
Finished Aug 11 06:19:52 PM PDT 24
Peak memory 205320 kb
Host smart-113e0c77-3953-425b-8463-1e077640a74c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624837979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.624837979
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.4253390677
Short name T507
Test name
Test status
Simulation time 348509521 ps
CPU time 5.54 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:19:52 PM PDT 24
Peak memory 225280 kb
Host smart-24807220-3123-40d3-a83f-c37cb234a27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253390677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.4253390677
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3597474635
Short name T350
Test name
Test status
Simulation time 37572452 ps
CPU time 0.78 seconds
Started Aug 11 06:19:48 PM PDT 24
Finished Aug 11 06:19:49 PM PDT 24
Peak memory 207052 kb
Host smart-0d089cd7-22ff-4bef-b02b-4d238a7d3a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597474635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3597474635
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.540318547
Short name T1005
Test name
Test status
Simulation time 109561868387 ps
CPU time 192.78 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:22:59 PM PDT 24
Peak memory 257124 kb
Host smart-e5fdcb04-717b-4414-9478-60eacd59d6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540318547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.540318547
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2823601726
Short name T287
Test name
Test status
Simulation time 12593721183 ps
CPU time 197.36 seconds
Started Aug 11 06:19:47 PM PDT 24
Finished Aug 11 06:23:04 PM PDT 24
Peak memory 264896 kb
Host smart-fdb3ad93-e4ff-4601-9af9-0842d4e68596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823601726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2823601726
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1007946042
Short name T201
Test name
Test status
Simulation time 114082198422 ps
CPU time 550.8 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:28:57 PM PDT 24
Peak memory 262032 kb
Host smart-95b80ec4-a1b9-4782-9a62-c50b37cfa0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007946042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1007946042
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.4114729121
Short name T776
Test name
Test status
Simulation time 72634974 ps
CPU time 2.97 seconds
Started Aug 11 06:19:51 PM PDT 24
Finished Aug 11 06:19:54 PM PDT 24
Peak memory 233588 kb
Host smart-fbcd803c-989d-472d-9005-dec46ada1626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114729121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.4114729121
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.772491
Short name T379
Test name
Test status
Simulation time 2228080378 ps
CPU time 42.92 seconds
Started Aug 11 06:19:47 PM PDT 24
Finished Aug 11 06:20:30 PM PDT 24
Peak memory 249896 kb
Host smart-58831934-346b-4c38-b2d9-4f92d08a6868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.772491
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3522539549
Short name T209
Test name
Test status
Simulation time 2552781205 ps
CPU time 15.89 seconds
Started Aug 11 06:19:52 PM PDT 24
Finished Aug 11 06:20:08 PM PDT 24
Peak memory 225220 kb
Host smart-cfa4f142-fe56-4919-8acb-8489cdd30ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522539549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3522539549
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.4268573651
Short name T791
Test name
Test status
Simulation time 10265284345 ps
CPU time 60.06 seconds
Started Aug 11 06:19:48 PM PDT 24
Finished Aug 11 06:20:48 PM PDT 24
Peak memory 233444 kb
Host smart-19d5f8d0-3599-4852-85e9-2627a3992176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268573651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4268573651
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.439390685
Short name T273
Test name
Test status
Simulation time 746749266 ps
CPU time 5.93 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:19:52 PM PDT 24
Peak memory 233452 kb
Host smart-ec13e683-6b66-4b3c-94a8-70dc030388be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439390685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.439390685
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3534652464
Short name T202
Test name
Test status
Simulation time 529242945 ps
CPU time 7.38 seconds
Started Aug 11 06:19:47 PM PDT 24
Finished Aug 11 06:19:54 PM PDT 24
Peak memory 233436 kb
Host smart-aee97fe4-6a6f-48ec-a410-56bfc7346e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534652464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3534652464
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.4089990652
Short name T973
Test name
Test status
Simulation time 747889480 ps
CPU time 3.87 seconds
Started Aug 11 06:19:45 PM PDT 24
Finished Aug 11 06:19:49 PM PDT 24
Peak memory 219920 kb
Host smart-f6925b32-27f9-4d8d-84e2-0ad70369c648
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4089990652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.4089990652
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.917394572
Short name T833
Test name
Test status
Simulation time 1171958058 ps
CPU time 11.22 seconds
Started Aug 11 06:19:44 PM PDT 24
Finished Aug 11 06:19:56 PM PDT 24
Peak memory 216956 kb
Host smart-e146f8f7-d35d-4778-9555-5bd941f7688b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917394572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.917394572
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1902756084
Short name T1029
Test name
Test status
Simulation time 1479774332 ps
CPU time 4.81 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:19:51 PM PDT 24
Peak memory 217012 kb
Host smart-c6bd9af0-8e58-4599-9c13-ee76118794d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902756084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1902756084
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3144425060
Short name T148
Test name
Test status
Simulation time 125227842 ps
CPU time 1.08 seconds
Started Aug 11 06:19:47 PM PDT 24
Finished Aug 11 06:19:48 PM PDT 24
Peak memory 208512 kb
Host smart-85c873ba-604f-417a-bfc6-df08b43af739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144425060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3144425060
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.326192323
Short name T832
Test name
Test status
Simulation time 18233059 ps
CPU time 0.73 seconds
Started Aug 11 06:19:47 PM PDT 24
Finished Aug 11 06:19:48 PM PDT 24
Peak memory 206592 kb
Host smart-8c4f01de-af6f-4e39-a95e-bbc811749ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326192323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.326192323
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2309581696
Short name T444
Test name
Test status
Simulation time 40013144 ps
CPU time 2.43 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:19:49 PM PDT 24
Peak memory 224752 kb
Host smart-1bfce16d-1da0-4521-9630-4cbc61f50474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309581696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2309581696
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2103480913
Short name T367
Test name
Test status
Simulation time 48895375 ps
CPU time 0.72 seconds
Started Aug 11 06:19:47 PM PDT 24
Finished Aug 11 06:19:47 PM PDT 24
Peak memory 205284 kb
Host smart-d4703185-f9e1-4754-a575-43daf7b73464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103480913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2103480913
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3038632137
Short name T253
Test name
Test status
Simulation time 560249565 ps
CPU time 5 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:19:51 PM PDT 24
Peak memory 225200 kb
Host smart-bdf6431f-068a-4f65-b47f-47bdc0bbd793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038632137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3038632137
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3924510353
Short name T332
Test name
Test status
Simulation time 66439869 ps
CPU time 0.79 seconds
Started Aug 11 06:19:47 PM PDT 24
Finished Aug 11 06:19:48 PM PDT 24
Peak memory 207420 kb
Host smart-98e4bb93-41ab-4bd0-8d5a-916820511ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924510353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3924510353
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.50688669
Short name T297
Test name
Test status
Simulation time 262771486026 ps
CPU time 174.95 seconds
Started Aug 11 06:19:47 PM PDT 24
Finished Aug 11 06:22:43 PM PDT 24
Peak memory 267520 kb
Host smart-1b196aef-08ef-4410-82a8-69f64644db27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50688669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.50688669
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3122047468
Short name T801
Test name
Test status
Simulation time 30547073173 ps
CPU time 306.27 seconds
Started Aug 11 06:19:56 PM PDT 24
Finished Aug 11 06:25:03 PM PDT 24
Peak memory 258116 kb
Host smart-999231ae-6da4-4665-8d2c-517cf6ff7fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122047468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3122047468
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3470344272
Short name T587
Test name
Test status
Simulation time 36421852756 ps
CPU time 79.79 seconds
Started Aug 11 06:19:47 PM PDT 24
Finished Aug 11 06:21:07 PM PDT 24
Peak memory 234736 kb
Host smart-1c5ca97d-27e0-4619-9554-3ac288c814b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470344272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3470344272
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3358288595
Short name T466
Test name
Test status
Simulation time 268769092 ps
CPU time 5.93 seconds
Started Aug 11 06:19:49 PM PDT 24
Finished Aug 11 06:19:55 PM PDT 24
Peak memory 225236 kb
Host smart-69bcdfae-5e6c-4bb1-b715-731cb9947757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358288595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3358288595
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3697557394
Short name T197
Test name
Test status
Simulation time 21175119326 ps
CPU time 96.33 seconds
Started Aug 11 06:19:54 PM PDT 24
Finished Aug 11 06:21:31 PM PDT 24
Peak memory 253148 kb
Host smart-4fb23420-ef67-47c8-89dc-f4a04b288e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697557394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3697557394
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1448186981
Short name T262
Test name
Test status
Simulation time 491461965 ps
CPU time 6.71 seconds
Started Aug 11 06:19:54 PM PDT 24
Finished Aug 11 06:20:01 PM PDT 24
Peak memory 225184 kb
Host smart-9de60227-52ef-49d9-8421-82d664e76e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448186981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1448186981
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2933235189
Short name T54
Test name
Test status
Simulation time 36737396897 ps
CPU time 31.25 seconds
Started Aug 11 06:19:49 PM PDT 24
Finished Aug 11 06:20:21 PM PDT 24
Peak memory 237884 kb
Host smart-44707e02-5e9a-4a3d-9bf8-578b880a0f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933235189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2933235189
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1557026166
Short name T882
Test name
Test status
Simulation time 126837420 ps
CPU time 2.24 seconds
Started Aug 11 06:19:53 PM PDT 24
Finished Aug 11 06:19:56 PM PDT 24
Peak memory 233076 kb
Host smart-e5eef1ae-7890-4268-a90e-73bd3dbd014a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557026166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1557026166
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1653394264
Short name T96
Test name
Test status
Simulation time 12412960760 ps
CPU time 34.23 seconds
Started Aug 11 06:19:54 PM PDT 24
Finished Aug 11 06:20:29 PM PDT 24
Peak memory 233112 kb
Host smart-9aa2b145-9c6c-450e-b42f-2dad57d7e228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653394264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1653394264
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.587729793
Short name T141
Test name
Test status
Simulation time 3169886938 ps
CPU time 11.9 seconds
Started Aug 11 06:19:52 PM PDT 24
Finished Aug 11 06:20:04 PM PDT 24
Peak memory 223928 kb
Host smart-5b69a277-035d-4281-85c8-a5e102ed8c32
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=587729793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.587729793
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.944800266
Short name T199
Test name
Test status
Simulation time 36182724397 ps
CPU time 162.34 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:22:28 PM PDT 24
Peak memory 256768 kb
Host smart-d64e9ce2-099d-4116-82dd-db0580aa1682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944800266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.944800266
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4034890923
Short name T841
Test name
Test status
Simulation time 1403995739 ps
CPU time 6.39 seconds
Started Aug 11 06:19:48 PM PDT 24
Finished Aug 11 06:19:54 PM PDT 24
Peak memory 217120 kb
Host smart-abeb6dbe-742a-4bb3-89b5-f3c59ba6b357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034890923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4034890923
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4209410439
Short name T539
Test name
Test status
Simulation time 4053559291 ps
CPU time 16.39 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:20:02 PM PDT 24
Peak memory 217056 kb
Host smart-a7c7fbec-6671-4108-8110-38679347417e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209410439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4209410439
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1187076083
Short name T336
Test name
Test status
Simulation time 404673539 ps
CPU time 1.87 seconds
Started Aug 11 06:19:47 PM PDT 24
Finished Aug 11 06:19:49 PM PDT 24
Peak memory 216960 kb
Host smart-332aeffa-9e82-4304-9e26-5ea680548fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187076083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1187076083
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3995789644
Short name T931
Test name
Test status
Simulation time 25451972 ps
CPU time 0.72 seconds
Started Aug 11 06:19:45 PM PDT 24
Finished Aug 11 06:19:45 PM PDT 24
Peak memory 206600 kb
Host smart-b976f707-bf35-4ba1-8257-dc1c7503b8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995789644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3995789644
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1349270637
Short name T247
Test name
Test status
Simulation time 49567118 ps
CPU time 2.58 seconds
Started Aug 11 06:19:52 PM PDT 24
Finished Aug 11 06:19:55 PM PDT 24
Peak memory 233504 kb
Host smart-fa04e7c7-cfda-40ef-bacc-2fa601deeae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349270637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1349270637
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.749966676
Short name T73
Test name
Test status
Simulation time 10909360 ps
CPU time 0.73 seconds
Started Aug 11 06:20:03 PM PDT 24
Finished Aug 11 06:20:03 PM PDT 24
Peak memory 206188 kb
Host smart-02f94d5c-3268-4fb1-a3a6-de6bd77ac6b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749966676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.749966676
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1520274776
Short name T633
Test name
Test status
Simulation time 141344175 ps
CPU time 3.37 seconds
Started Aug 11 06:19:49 PM PDT 24
Finished Aug 11 06:19:52 PM PDT 24
Peak memory 233352 kb
Host smart-9f87997d-824f-43fa-87f9-edef5deeddcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520274776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1520274776
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.87881417
Short name T544
Test name
Test status
Simulation time 173959443 ps
CPU time 0.77 seconds
Started Aug 11 06:19:47 PM PDT 24
Finished Aug 11 06:19:48 PM PDT 24
Peak memory 207080 kb
Host smart-af37c1ac-ac2f-48e8-acc0-36d6241cedcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87881417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.87881417
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1113183853
Short name T651
Test name
Test status
Simulation time 60906365784 ps
CPU time 251.64 seconds
Started Aug 11 06:19:54 PM PDT 24
Finished Aug 11 06:24:05 PM PDT 24
Peak memory 254532 kb
Host smart-2c19984f-1749-4b5f-9cfd-b1f06504636d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113183853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1113183853
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1689202832
Short name T219
Test name
Test status
Simulation time 49084587513 ps
CPU time 474.34 seconds
Started Aug 11 06:19:58 PM PDT 24
Finished Aug 11 06:27:52 PM PDT 24
Peak memory 250920 kb
Host smart-d8b92ce1-477a-4844-a8c7-ff003e7ab5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689202832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1689202832
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.230036133
Short name T902
Test name
Test status
Simulation time 69870370924 ps
CPU time 135.11 seconds
Started Aug 11 06:19:55 PM PDT 24
Finished Aug 11 06:22:10 PM PDT 24
Peak memory 250176 kb
Host smart-d3a5ceca-15cf-474c-b85e-91210de54996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230036133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.230036133
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.365247284
Short name T304
Test name
Test status
Simulation time 397701553 ps
CPU time 6.54 seconds
Started Aug 11 06:19:52 PM PDT 24
Finished Aug 11 06:19:58 PM PDT 24
Peak memory 225256 kb
Host smart-1a3f215c-cd0a-41d8-84c3-79d4e81b46f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365247284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.365247284
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2444494873
Short name T509
Test name
Test status
Simulation time 3700514399 ps
CPU time 26.95 seconds
Started Aug 11 06:19:55 PM PDT 24
Finished Aug 11 06:20:22 PM PDT 24
Peak memory 250156 kb
Host smart-84ebba37-791e-4e88-8a1b-847b94f5f23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444494873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2444494873
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.175838707
Short name T278
Test name
Test status
Simulation time 672367303 ps
CPU time 2.97 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:19:49 PM PDT 24
Peak memory 225208 kb
Host smart-7ac47b64-af9a-4e4b-97fb-4e055c24b0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175838707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.175838707
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.496370596
Short name T418
Test name
Test status
Simulation time 105311722 ps
CPU time 4.86 seconds
Started Aug 11 06:19:48 PM PDT 24
Finished Aug 11 06:19:53 PM PDT 24
Peak memory 233488 kb
Host smart-7cb27733-d6db-41c3-99fe-3c67d1dd9302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496370596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.496370596
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3102386434
Short name T149
Test name
Test status
Simulation time 7440535689 ps
CPU time 28.33 seconds
Started Aug 11 06:19:54 PM PDT 24
Finished Aug 11 06:20:23 PM PDT 24
Peak memory 249500 kb
Host smart-5c5ecd72-b984-4dc0-81f7-fe21e3c4ba3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102386434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3102386434
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.801462626
Short name T251
Test name
Test status
Simulation time 8356115660 ps
CPU time 26.43 seconds
Started Aug 11 06:19:52 PM PDT 24
Finished Aug 11 06:20:19 PM PDT 24
Peak memory 249652 kb
Host smart-65a9864f-278c-4091-80b1-83d16ac3259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801462626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.801462626
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1975233697
Short name T824
Test name
Test status
Simulation time 2988038806 ps
CPU time 9.43 seconds
Started Aug 11 06:19:55 PM PDT 24
Finished Aug 11 06:20:05 PM PDT 24
Peak memory 223108 kb
Host smart-133889f5-bfa2-4c59-ba94-ef069b995ac6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1975233697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1975233697
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3903213946
Short name T797
Test name
Test status
Simulation time 9565119925 ps
CPU time 24.91 seconds
Started Aug 11 06:19:48 PM PDT 24
Finished Aug 11 06:20:13 PM PDT 24
Peak memory 217012 kb
Host smart-835a85c3-1a7f-437b-b461-effeea682bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903213946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3903213946
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1243364200
Short name T517
Test name
Test status
Simulation time 3291692942 ps
CPU time 11.86 seconds
Started Aug 11 06:19:46 PM PDT 24
Finished Aug 11 06:19:58 PM PDT 24
Peak memory 217044 kb
Host smart-a3a1ff51-7906-4b8b-a655-e41492c38d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243364200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1243364200
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3664003223
Short name T600
Test name
Test status
Simulation time 176912402 ps
CPU time 4.7 seconds
Started Aug 11 06:19:52 PM PDT 24
Finished Aug 11 06:19:57 PM PDT 24
Peak memory 216984 kb
Host smart-2e0c3188-6c46-4915-bf2d-b53942edab74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664003223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3664003223
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2585693273
Short name T966
Test name
Test status
Simulation time 95947878 ps
CPU time 0.78 seconds
Started Aug 11 06:19:54 PM PDT 24
Finished Aug 11 06:19:55 PM PDT 24
Peak memory 206592 kb
Host smart-07fa6826-a8dc-4e9c-bca2-ae9509d54a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585693273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2585693273
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.877589672
Short name T548
Test name
Test status
Simulation time 5248406353 ps
CPU time 6.68 seconds
Started Aug 11 06:19:51 PM PDT 24
Finished Aug 11 06:19:58 PM PDT 24
Peak memory 233480 kb
Host smart-cb626638-ffb9-43bc-8cc0-c285adafc6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877589672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.877589672
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.911275245
Short name T80
Test name
Test status
Simulation time 14552872 ps
CPU time 0.73 seconds
Started Aug 11 06:18:18 PM PDT 24
Finished Aug 11 06:18:19 PM PDT 24
Peak memory 206180 kb
Host smart-b2d11033-ee6f-40db-a2ba-0737ffb49ec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911275245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.911275245
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3707000762
Short name T498
Test name
Test status
Simulation time 36622098 ps
CPU time 2.34 seconds
Started Aug 11 06:18:16 PM PDT 24
Finished Aug 11 06:18:19 PM PDT 24
Peak memory 233088 kb
Host smart-20b80697-cc9d-4835-b01a-c66b8d2b8c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707000762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3707000762
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3671359080
Short name T877
Test name
Test status
Simulation time 33134396 ps
CPU time 0.81 seconds
Started Aug 11 06:18:08 PM PDT 24
Finished Aug 11 06:18:09 PM PDT 24
Peak memory 207028 kb
Host smart-7cb16d90-a27a-4d2d-91c7-f94f69de1933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671359080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3671359080
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.990754331
Short name T235
Test name
Test status
Simulation time 29907421312 ps
CPU time 120.31 seconds
Started Aug 11 06:18:12 PM PDT 24
Finished Aug 11 06:20:13 PM PDT 24
Peak memory 249916 kb
Host smart-c919f0ff-026b-415c-8b44-b6831aa09beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990754331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.990754331
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.368024398
Short name T440
Test name
Test status
Simulation time 40465305911 ps
CPU time 61.28 seconds
Started Aug 11 06:18:13 PM PDT 24
Finished Aug 11 06:19:14 PM PDT 24
Peak memory 252176 kb
Host smart-ebb8f4e5-fd27-4f30-affd-2f20aea2deaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368024398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.368024398
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1689201126
Short name T985
Test name
Test status
Simulation time 9985379270 ps
CPU time 78.26 seconds
Started Aug 11 06:18:16 PM PDT 24
Finished Aug 11 06:19:34 PM PDT 24
Peak memory 266308 kb
Host smart-e3fda314-0b63-4f05-9356-1807ccad2214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689201126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1689201126
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1989282039
Short name T905
Test name
Test status
Simulation time 2939970376 ps
CPU time 29.48 seconds
Started Aug 11 06:18:14 PM PDT 24
Finished Aug 11 06:18:44 PM PDT 24
Peak memory 250128 kb
Host smart-7feabb13-65e3-4b46-bf29-0a8bd4c09ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989282039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1989282039
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2560993486
Short name T204
Test name
Test status
Simulation time 1291053990 ps
CPU time 13.56 seconds
Started Aug 11 06:18:13 PM PDT 24
Finished Aug 11 06:18:26 PM PDT 24
Peak memory 233392 kb
Host smart-d2ac905b-ab32-4650-88ce-eec43ea8cf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560993486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2560993486
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3042737560
Short name T207
Test name
Test status
Simulation time 51097046068 ps
CPU time 93.82 seconds
Started Aug 11 06:18:10 PM PDT 24
Finished Aug 11 06:19:44 PM PDT 24
Peak memory 241364 kb
Host smart-3d98791b-354f-45cd-8ce9-447d14198d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042737560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3042737560
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1996530248
Short name T726
Test name
Test status
Simulation time 34902020 ps
CPU time 1.09 seconds
Started Aug 11 06:18:13 PM PDT 24
Finished Aug 11 06:18:14 PM PDT 24
Peak memory 217120 kb
Host smart-01b7c517-3cc7-45ca-ae26-d1c109363b87
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996530248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1996530248
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3672601906
Short name T747
Test name
Test status
Simulation time 1439099127 ps
CPU time 6.21 seconds
Started Aug 11 06:18:10 PM PDT 24
Finished Aug 11 06:18:17 PM PDT 24
Peak memory 225220 kb
Host smart-50546f11-9fa3-4807-ab7b-74b928ae4c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672601906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3672601906
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1779818142
Short name T23
Test name
Test status
Simulation time 127720163 ps
CPU time 2.93 seconds
Started Aug 11 06:18:14 PM PDT 24
Finished Aug 11 06:18:17 PM PDT 24
Peak memory 225132 kb
Host smart-1dfac553-2ccb-4ade-93f4-aca78be36028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779818142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1779818142
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2740033602
Short name T818
Test name
Test status
Simulation time 568521222 ps
CPU time 8.28 seconds
Started Aug 11 06:18:10 PM PDT 24
Finished Aug 11 06:18:19 PM PDT 24
Peak memory 219940 kb
Host smart-b81c4be4-33f3-4265-8746-3b14ac66afcf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2740033602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2740033602
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.44999988
Short name T76
Test name
Test status
Simulation time 55662346 ps
CPU time 1.08 seconds
Started Aug 11 06:18:10 PM PDT 24
Finished Aug 11 06:18:12 PM PDT 24
Peak memory 235964 kb
Host smart-742aa1dc-f374-4f5e-9ae2-4c67f1ceaed6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44999988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.44999988
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1696414680
Short name T844
Test name
Test status
Simulation time 1688049166 ps
CPU time 5.99 seconds
Started Aug 11 06:18:16 PM PDT 24
Finished Aug 11 06:18:22 PM PDT 24
Peak memory 216952 kb
Host smart-6947b782-d96f-4c74-957a-4ce41b160794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696414680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1696414680
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1257286645
Short name T502
Test name
Test status
Simulation time 3416063587 ps
CPU time 5.58 seconds
Started Aug 11 06:18:16 PM PDT 24
Finished Aug 11 06:18:22 PM PDT 24
Peak memory 217016 kb
Host smart-c21647ce-5026-4121-80ba-6ba076b75145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257286645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1257286645
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1233397062
Short name T983
Test name
Test status
Simulation time 38546206 ps
CPU time 0.7 seconds
Started Aug 11 06:18:09 PM PDT 24
Finished Aug 11 06:18:10 PM PDT 24
Peak memory 206132 kb
Host smart-5ff929cc-e887-4999-b558-02df673a4cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233397062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1233397062
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3065349285
Short name T699
Test name
Test status
Simulation time 26947378 ps
CPU time 0.7 seconds
Started Aug 11 06:18:09 PM PDT 24
Finished Aug 11 06:18:10 PM PDT 24
Peak memory 206084 kb
Host smart-05e2d91a-5849-4b62-9851-1a6cf4238ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065349285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3065349285
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2526102031
Short name T377
Test name
Test status
Simulation time 2340459191 ps
CPU time 7.79 seconds
Started Aug 11 06:18:12 PM PDT 24
Finished Aug 11 06:18:20 PM PDT 24
Peak memory 225320 kb
Host smart-19b29233-accd-4bcb-9406-342466b3816b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526102031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2526102031
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.726827916
Short name T491
Test name
Test status
Simulation time 23910119 ps
CPU time 0.71 seconds
Started Aug 11 06:19:54 PM PDT 24
Finished Aug 11 06:19:55 PM PDT 24
Peak memory 205860 kb
Host smart-9218fa16-9470-4019-a479-5ebca72a18d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726827916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.726827916
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2433573114
Short name T366
Test name
Test status
Simulation time 651813981 ps
CPU time 4.88 seconds
Started Aug 11 06:19:54 PM PDT 24
Finished Aug 11 06:19:59 PM PDT 24
Peak memory 233408 kb
Host smart-10d2e649-959c-413c-b02c-afe5a83eec72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433573114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2433573114
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2595220447
Short name T596
Test name
Test status
Simulation time 109569807 ps
CPU time 0.76 seconds
Started Aug 11 06:20:02 PM PDT 24
Finished Aug 11 06:20:03 PM PDT 24
Peak memory 206056 kb
Host smart-3844533d-2ca0-4227-8ba3-a18de5338e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595220447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2595220447
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3457577375
Short name T609
Test name
Test status
Simulation time 16304716389 ps
CPU time 137.12 seconds
Started Aug 11 06:19:56 PM PDT 24
Finished Aug 11 06:22:14 PM PDT 24
Peak memory 258080 kb
Host smart-28cd51b5-a850-4177-92bd-a9314f59a5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457577375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3457577375
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1151342018
Short name T681
Test name
Test status
Simulation time 36028550850 ps
CPU time 153.48 seconds
Started Aug 11 06:19:53 PM PDT 24
Finished Aug 11 06:22:27 PM PDT 24
Peak memory 251380 kb
Host smart-8b1f22ac-50cd-46bf-bac5-337f84774cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151342018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1151342018
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3027129859
Short name T195
Test name
Test status
Simulation time 26850004858 ps
CPU time 119.72 seconds
Started Aug 11 06:19:55 PM PDT 24
Finished Aug 11 06:21:55 PM PDT 24
Peak memory 251860 kb
Host smart-0f36dda8-1425-4e6a-8cf5-85afeee33bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027129859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3027129859
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.122198476
Short name T671
Test name
Test status
Simulation time 736760954 ps
CPU time 6.66 seconds
Started Aug 11 06:19:55 PM PDT 24
Finished Aug 11 06:20:02 PM PDT 24
Peak memory 250964 kb
Host smart-56cb5f78-76f9-4fe9-9df0-bc810039c871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122198476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.122198476
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.267976814
Short name T234
Test name
Test status
Simulation time 29857384215 ps
CPU time 48.58 seconds
Started Aug 11 06:19:55 PM PDT 24
Finished Aug 11 06:20:44 PM PDT 24
Peak memory 241700 kb
Host smart-aaf5ea48-733c-4ca3-944c-9ceb61fca86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267976814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.267976814
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.717037155
Short name T999
Test name
Test status
Simulation time 503732604 ps
CPU time 3.25 seconds
Started Aug 11 06:19:54 PM PDT 24
Finished Aug 11 06:19:57 PM PDT 24
Peak memory 233436 kb
Host smart-6cffac3b-dd7d-4b0c-b258-71cc4b99aaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717037155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.717037155
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1602316099
Short name T601
Test name
Test status
Simulation time 34133479417 ps
CPU time 39.56 seconds
Started Aug 11 06:20:02 PM PDT 24
Finished Aug 11 06:20:42 PM PDT 24
Peak memory 233548 kb
Host smart-4dac8a09-b0dd-4968-bb9c-bd20e8d28809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602316099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1602316099
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1874820586
Short name T894
Test name
Test status
Simulation time 6532365484 ps
CPU time 20.45 seconds
Started Aug 11 06:20:00 PM PDT 24
Finished Aug 11 06:20:20 PM PDT 24
Peak memory 237996 kb
Host smart-6ab60fdb-e10a-4d35-bedc-4b288eb856ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874820586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1874820586
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1641191220
Short name T87
Test name
Test status
Simulation time 57922605653 ps
CPU time 37.44 seconds
Started Aug 11 06:19:55 PM PDT 24
Finished Aug 11 06:20:33 PM PDT 24
Peak memory 241456 kb
Host smart-195abedf-6291-468e-9551-78fd47c55b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641191220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1641191220
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.457634769
Short name T162
Test name
Test status
Simulation time 277800707 ps
CPU time 5.11 seconds
Started Aug 11 06:19:57 PM PDT 24
Finished Aug 11 06:20:02 PM PDT 24
Peak memory 223760 kb
Host smart-47e00cc3-d5b3-4525-a2d4-29e881488a6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=457634769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.457634769
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2499653857
Short name T455
Test name
Test status
Simulation time 3889096826 ps
CPU time 39.56 seconds
Started Aug 11 06:20:00 PM PDT 24
Finished Aug 11 06:20:40 PM PDT 24
Peak memory 240716 kb
Host smart-706525b1-2bf3-46f4-8d48-e53636923b4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499653857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2499653857
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3273880720
Short name T920
Test name
Test status
Simulation time 31150720452 ps
CPU time 36.52 seconds
Started Aug 11 06:19:55 PM PDT 24
Finished Aug 11 06:20:32 PM PDT 24
Peak memory 217036 kb
Host smart-a8560518-2204-4dee-839b-74daf34731e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273880720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3273880720
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3048373127
Short name T459
Test name
Test status
Simulation time 478251219 ps
CPU time 3.67 seconds
Started Aug 11 06:19:55 PM PDT 24
Finished Aug 11 06:19:59 PM PDT 24
Peak memory 216884 kb
Host smart-2fb7fe26-6351-4020-a8cd-81c9d0dea91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048373127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3048373127
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2694866784
Short name T723
Test name
Test status
Simulation time 31703712 ps
CPU time 1.12 seconds
Started Aug 11 06:19:50 PM PDT 24
Finished Aug 11 06:19:52 PM PDT 24
Peak memory 216736 kb
Host smart-37e1b9b1-6ee9-4ddf-b734-c20c93a1651e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694866784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2694866784
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3473028593
Short name T528
Test name
Test status
Simulation time 78524179 ps
CPU time 0.91 seconds
Started Aug 11 06:19:56 PM PDT 24
Finished Aug 11 06:19:57 PM PDT 24
Peak memory 207592 kb
Host smart-56f66651-8aeb-4385-a3da-091cf24c1e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473028593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3473028593
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3680694873
Short name T615
Test name
Test status
Simulation time 705784167 ps
CPU time 5.23 seconds
Started Aug 11 06:20:00 PM PDT 24
Finished Aug 11 06:20:05 PM PDT 24
Peak memory 241588 kb
Host smart-9f8a9181-e574-4096-ae83-2d7d45e8868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680694873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3680694873
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4168966779
Short name T355
Test name
Test status
Simulation time 89117381 ps
CPU time 0.68 seconds
Started Aug 11 06:19:59 PM PDT 24
Finished Aug 11 06:20:00 PM PDT 24
Peak memory 205260 kb
Host smart-567e6d55-6926-4102-a10e-2d13b304aff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168966779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4168966779
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3173957011
Short name T673
Test name
Test status
Simulation time 142451576 ps
CPU time 2.92 seconds
Started Aug 11 06:19:54 PM PDT 24
Finished Aug 11 06:19:57 PM PDT 24
Peak memory 224904 kb
Host smart-3734e46e-e100-48d9-a63c-037a9abd8e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173957011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3173957011
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1122352614
Short name T1018
Test name
Test status
Simulation time 14727419 ps
CPU time 0.76 seconds
Started Aug 11 06:19:54 PM PDT 24
Finished Aug 11 06:19:55 PM PDT 24
Peak memory 205956 kb
Host smart-4d253932-f1a7-4019-875d-accbf951cd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122352614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1122352614
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3610071210
Short name T760
Test name
Test status
Simulation time 11664401860 ps
CPU time 110.08 seconds
Started Aug 11 06:20:00 PM PDT 24
Finished Aug 11 06:21:50 PM PDT 24
Peak memory 256476 kb
Host smart-afc2a4c1-21c3-48e0-abd2-214c530915e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610071210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3610071210
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.346202149
Short name T227
Test name
Test status
Simulation time 12190825409 ps
CPU time 83.4 seconds
Started Aug 11 06:20:04 PM PDT 24
Finished Aug 11 06:21:27 PM PDT 24
Peak memory 256772 kb
Host smart-b87d45e7-5670-4340-9a30-16c8484bd906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346202149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.346202149
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.71246142
Short name T545
Test name
Test status
Simulation time 958006242 ps
CPU time 5.42 seconds
Started Aug 11 06:19:52 PM PDT 24
Finished Aug 11 06:19:58 PM PDT 24
Peak memory 233636 kb
Host smart-d1912c1f-13bb-442d-91be-83435d48fd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71246142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.71246142
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1676051072
Short name T63
Test name
Test status
Simulation time 2114648932 ps
CPU time 7.35 seconds
Started Aug 11 06:20:03 PM PDT 24
Finished Aug 11 06:20:11 PM PDT 24
Peak memory 225272 kb
Host smart-1c2c012c-e408-43a9-97c6-9daacb340775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676051072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1676051072
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.637299912
Short name T413
Test name
Test status
Simulation time 95429878 ps
CPU time 2.83 seconds
Started Aug 11 06:19:55 PM PDT 24
Finished Aug 11 06:19:57 PM PDT 24
Peak memory 233476 kb
Host smart-812e13af-d29d-4f66-a819-349acecd1d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637299912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.637299912
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3236970883
Short name T317
Test name
Test status
Simulation time 3623706404 ps
CPU time 38.05 seconds
Started Aug 11 06:20:02 PM PDT 24
Finished Aug 11 06:20:40 PM PDT 24
Peak memory 235352 kb
Host smart-aa515a99-43e4-4ddc-b45b-d936fa58db67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236970883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3236970883
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3166181781
Short name T300
Test name
Test status
Simulation time 7573935540 ps
CPU time 12.41 seconds
Started Aug 11 06:19:55 PM PDT 24
Finished Aug 11 06:20:07 PM PDT 24
Peak memory 241144 kb
Host smart-a04cfbc5-8ca8-4451-97d4-7cd8c4bf2433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166181781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3166181781
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3143109741
Short name T1028
Test name
Test status
Simulation time 5828717186 ps
CPU time 17.51 seconds
Started Aug 11 06:19:55 PM PDT 24
Finished Aug 11 06:20:12 PM PDT 24
Peak memory 225284 kb
Host smart-f396101d-cf27-4906-b7c4-e4c8c0878621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143109741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3143109741
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3736824588
Short name T475
Test name
Test status
Simulation time 662158886 ps
CPU time 8.36 seconds
Started Aug 11 06:19:59 PM PDT 24
Finished Aug 11 06:20:08 PM PDT 24
Peak memory 222836 kb
Host smart-2d8ce0a9-edcf-405a-9ccb-d3d07b358273
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3736824588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3736824588
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2742609381
Short name T142
Test name
Test status
Simulation time 223363711796 ps
CPU time 558.31 seconds
Started Aug 11 06:19:57 PM PDT 24
Finished Aug 11 06:29:16 PM PDT 24
Peak memory 258140 kb
Host smart-be266c04-c340-4b86-9a68-800572739896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742609381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2742609381
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3028340598
Short name T773
Test name
Test status
Simulation time 807351471 ps
CPU time 6.32 seconds
Started Aug 11 06:19:55 PM PDT 24
Finished Aug 11 06:20:01 PM PDT 24
Peak memory 216972 kb
Host smart-8463497e-b47c-4021-b49e-cba1f549d0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028340598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3028340598
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1489045020
Short name T10
Test name
Test status
Simulation time 240539590 ps
CPU time 2.08 seconds
Started Aug 11 06:19:55 PM PDT 24
Finished Aug 11 06:19:57 PM PDT 24
Peak memory 216936 kb
Host smart-1e3f9557-ed4c-49ce-9334-3b715b76537a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489045020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1489045020
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.837880173
Short name T357
Test name
Test status
Simulation time 244466209 ps
CPU time 5.18 seconds
Started Aug 11 06:19:54 PM PDT 24
Finished Aug 11 06:20:00 PM PDT 24
Peak memory 217004 kb
Host smart-868eae0c-0953-4f7c-9026-6c1da48b9bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837880173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.837880173
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3235877868
Short name T629
Test name
Test status
Simulation time 28892290 ps
CPU time 0.85 seconds
Started Aug 11 06:19:55 PM PDT 24
Finished Aug 11 06:19:56 PM PDT 24
Peak memory 206544 kb
Host smart-d12a9896-0a89-4703-a753-1724d9196623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235877868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3235877868
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2094751436
Short name T182
Test name
Test status
Simulation time 167181799 ps
CPU time 2.22 seconds
Started Aug 11 06:20:02 PM PDT 24
Finished Aug 11 06:20:05 PM PDT 24
Peak memory 225272 kb
Host smart-b6e5d0ac-8e5e-4403-86c6-77cd06b086c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094751436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2094751436
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2892369640
Short name T496
Test name
Test status
Simulation time 12795515 ps
CPU time 0.76 seconds
Started Aug 11 06:20:00 PM PDT 24
Finished Aug 11 06:20:01 PM PDT 24
Peak memory 205276 kb
Host smart-04d42947-2658-40bd-af0a-111d1b561679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892369640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2892369640
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2748701570
Short name T642
Test name
Test status
Simulation time 464593875 ps
CPU time 7.95 seconds
Started Aug 11 06:20:01 PM PDT 24
Finished Aug 11 06:20:09 PM PDT 24
Peak memory 233332 kb
Host smart-0e41223f-c13b-4010-8049-e3da5d1063cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748701570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2748701570
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3535839029
Short name T727
Test name
Test status
Simulation time 18151628 ps
CPU time 0.77 seconds
Started Aug 11 06:19:59 PM PDT 24
Finished Aug 11 06:20:00 PM PDT 24
Peak memory 207404 kb
Host smart-b259e50c-1721-441d-b009-3cb145565700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535839029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3535839029
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1976048731
Short name T53
Test name
Test status
Simulation time 17515126566 ps
CPU time 34.16 seconds
Started Aug 11 06:20:04 PM PDT 24
Finished Aug 11 06:20:38 PM PDT 24
Peak memory 241684 kb
Host smart-b0c54ce3-b743-4ac2-9d94-8c83cbcf6cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976048731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1976048731
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1860805378
Short name T190
Test name
Test status
Simulation time 19457024419 ps
CPU time 109.83 seconds
Started Aug 11 06:20:01 PM PDT 24
Finished Aug 11 06:21:51 PM PDT 24
Peak memory 256544 kb
Host smart-244b3cd9-058d-44b0-99a5-bee453617960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860805378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1860805378
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3704472949
Short name T445
Test name
Test status
Simulation time 3801286481 ps
CPU time 12.79 seconds
Started Aug 11 06:20:00 PM PDT 24
Finished Aug 11 06:20:13 PM PDT 24
Peak memory 233556 kb
Host smart-9ae7bd65-77d0-49a3-a9e9-5cc19c84fb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704472949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3704472949
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1555125818
Short name T967
Test name
Test status
Simulation time 29707272137 ps
CPU time 110.6 seconds
Started Aug 11 06:20:00 PM PDT 24
Finished Aug 11 06:21:51 PM PDT 24
Peak memory 252496 kb
Host smart-cb68fd9e-b147-41bc-8f15-c9bb2b4c3681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555125818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1555125818
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.934677472
Short name T711
Test name
Test status
Simulation time 715873537 ps
CPU time 6.68 seconds
Started Aug 11 06:20:01 PM PDT 24
Finished Aug 11 06:20:08 PM PDT 24
Peak memory 233392 kb
Host smart-dabc657e-3238-409f-a1be-9ab765940050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934677472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.934677472
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3502144192
Short name T223
Test name
Test status
Simulation time 784257555 ps
CPU time 10.11 seconds
Started Aug 11 06:19:59 PM PDT 24
Finished Aug 11 06:20:10 PM PDT 24
Peak memory 233284 kb
Host smart-ca446bcb-2c9b-49a1-ac2b-c94ec5f34cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502144192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3502144192
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3557093822
Short name T962
Test name
Test status
Simulation time 344130513 ps
CPU time 4.91 seconds
Started Aug 11 06:20:02 PM PDT 24
Finished Aug 11 06:20:07 PM PDT 24
Peak memory 225212 kb
Host smart-b3285177-18cf-483f-804f-d500530eeb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557093822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3557093822
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3125398414
Short name T940
Test name
Test status
Simulation time 2054475601 ps
CPU time 8.74 seconds
Started Aug 11 06:20:02 PM PDT 24
Finished Aug 11 06:20:10 PM PDT 24
Peak memory 233420 kb
Host smart-8903dc8a-ce61-4db0-bde2-463b6f3f174a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125398414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3125398414
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4085873492
Short name T83
Test name
Test status
Simulation time 1016058520 ps
CPU time 4.42 seconds
Started Aug 11 06:20:04 PM PDT 24
Finished Aug 11 06:20:09 PM PDT 24
Peak memory 219964 kb
Host smart-5017e306-65d5-4721-b48a-94437ed2eac9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4085873492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4085873492
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3291843189
Short name T483
Test name
Test status
Simulation time 5324927983 ps
CPU time 77.58 seconds
Started Aug 11 06:19:58 PM PDT 24
Finished Aug 11 06:21:16 PM PDT 24
Peak memory 249944 kb
Host smart-bf9d14f8-af9c-48a8-878c-fe18823bb2d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291843189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3291843189
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.677029682
Short name T618
Test name
Test status
Simulation time 1328352212 ps
CPU time 20.72 seconds
Started Aug 11 06:19:59 PM PDT 24
Finished Aug 11 06:20:20 PM PDT 24
Peak memory 216996 kb
Host smart-d148f85a-3279-4a8a-9f29-34fa8f4cd759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677029682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.677029682
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2949008792
Short name T402
Test name
Test status
Simulation time 2714220185 ps
CPU time 9.16 seconds
Started Aug 11 06:20:01 PM PDT 24
Finished Aug 11 06:20:10 PM PDT 24
Peak memory 216952 kb
Host smart-b9a59541-8c1e-4dba-b4c6-b9fa551e2c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949008792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2949008792
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.221268275
Short name T632
Test name
Test status
Simulation time 40361210 ps
CPU time 0.96 seconds
Started Aug 11 06:20:01 PM PDT 24
Finished Aug 11 06:20:02 PM PDT 24
Peak memory 208600 kb
Host smart-adccaacb-17eb-47ae-a186-9a317455090b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221268275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.221268275
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3737538987
Short name T602
Test name
Test status
Simulation time 176137910 ps
CPU time 1.03 seconds
Started Aug 11 06:19:58 PM PDT 24
Finished Aug 11 06:19:59 PM PDT 24
Peak memory 207592 kb
Host smart-4b44b727-0e61-4482-912e-d230bd7416af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737538987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3737538987
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3145024956
Short name T213
Test name
Test status
Simulation time 6608773655 ps
CPU time 12.38 seconds
Started Aug 11 06:19:58 PM PDT 24
Finished Aug 11 06:20:10 PM PDT 24
Peak memory 233380 kb
Host smart-aa264a59-e262-418d-856e-750dee907abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145024956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3145024956
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.648238899
Short name T982
Test name
Test status
Simulation time 103348517 ps
CPU time 0.73 seconds
Started Aug 11 06:20:07 PM PDT 24
Finished Aug 11 06:20:08 PM PDT 24
Peak memory 205468 kb
Host smart-ec218794-973e-4f79-ac98-859054de441a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648238899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.648238899
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2125478210
Short name T429
Test name
Test status
Simulation time 570631131 ps
CPU time 2.61 seconds
Started Aug 11 06:20:07 PM PDT 24
Finished Aug 11 06:20:10 PM PDT 24
Peak memory 225208 kb
Host smart-b86d969d-c119-4c09-92b2-6962ee62393d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125478210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2125478210
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1763670909
Short name T597
Test name
Test status
Simulation time 69910927 ps
CPU time 0.73 seconds
Started Aug 11 06:20:06 PM PDT 24
Finished Aug 11 06:20:07 PM PDT 24
Peak memory 206040 kb
Host smart-155f122f-39f2-4536-802b-5d24ce40b63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763670909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1763670909
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3195367843
Short name T616
Test name
Test status
Simulation time 19303550159 ps
CPU time 40.89 seconds
Started Aug 11 06:20:07 PM PDT 24
Finished Aug 11 06:20:48 PM PDT 24
Peak memory 238900 kb
Host smart-d5fdae1b-35bf-4ad3-9ca9-1689ee5fd3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195367843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3195367843
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3730047473
Short name T868
Test name
Test status
Simulation time 59741388783 ps
CPU time 149.16 seconds
Started Aug 11 06:20:08 PM PDT 24
Finished Aug 11 06:22:38 PM PDT 24
Peak memory 239984 kb
Host smart-cd5212c8-45fe-4437-a062-e4c40d66aa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730047473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3730047473
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1873695401
Short name T783
Test name
Test status
Simulation time 21125201760 ps
CPU time 197.91 seconds
Started Aug 11 06:20:07 PM PDT 24
Finished Aug 11 06:23:25 PM PDT 24
Peak memory 254552 kb
Host smart-5dece68e-cadb-4072-959d-06a23d9b84d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873695401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1873695401
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.4293876768
Short name T85
Test name
Test status
Simulation time 2612110916 ps
CPU time 38.58 seconds
Started Aug 11 06:20:05 PM PDT 24
Finished Aug 11 06:20:44 PM PDT 24
Peak memory 233552 kb
Host smart-322b9908-ade5-45f8-abc9-6310ca8b5607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293876768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.4293876768
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.4044689254
Short name T397
Test name
Test status
Simulation time 46359679 ps
CPU time 0.74 seconds
Started Aug 11 06:20:13 PM PDT 24
Finished Aug 11 06:20:14 PM PDT 24
Peak memory 216420 kb
Host smart-b57acca4-c23f-4840-b5fe-465bb8341146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044689254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.4044689254
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1073434281
Short name T929
Test name
Test status
Simulation time 5889932873 ps
CPU time 14.17 seconds
Started Aug 11 06:20:10 PM PDT 24
Finished Aug 11 06:20:24 PM PDT 24
Peak memory 233520 kb
Host smart-e48b95e1-4589-48b0-95bf-ef61c6e29ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073434281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1073434281
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.298649497
Short name T581
Test name
Test status
Simulation time 63991589733 ps
CPU time 166.35 seconds
Started Aug 11 06:20:07 PM PDT 24
Finished Aug 11 06:22:54 PM PDT 24
Peak memory 237908 kb
Host smart-71a2df3a-80b1-48c3-9bb7-947bb3437b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298649497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.298649497
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1120904409
Short name T265
Test name
Test status
Simulation time 19599003725 ps
CPU time 16.66 seconds
Started Aug 11 06:20:08 PM PDT 24
Finished Aug 11 06:20:25 PM PDT 24
Peak memory 241376 kb
Host smart-9ceb3756-aa40-472d-a303-1f3f041fb0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120904409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1120904409
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1166149388
Short name T208
Test name
Test status
Simulation time 1119366522 ps
CPU time 7.74 seconds
Started Aug 11 06:20:05 PM PDT 24
Finished Aug 11 06:20:13 PM PDT 24
Peak memory 233428 kb
Host smart-34ad8738-78db-4c4b-a8e8-98d4ed16219b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166149388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1166149388
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1335835126
Short name T927
Test name
Test status
Simulation time 529339384 ps
CPU time 5.15 seconds
Started Aug 11 06:20:09 PM PDT 24
Finished Aug 11 06:20:14 PM PDT 24
Peak memory 220852 kb
Host smart-97ccc291-c544-4d26-897b-0e7dc6d75932
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1335835126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1335835126
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3246696514
Short name T1000
Test name
Test status
Simulation time 63507735 ps
CPU time 1.1 seconds
Started Aug 11 06:20:08 PM PDT 24
Finished Aug 11 06:20:10 PM PDT 24
Peak memory 207408 kb
Host smart-6e3173ab-386c-4902-bb59-4a9d9c4d79e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246696514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3246696514
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1833242925
Short name T605
Test name
Test status
Simulation time 31032747457 ps
CPU time 22.69 seconds
Started Aug 11 06:20:07 PM PDT 24
Finished Aug 11 06:20:30 PM PDT 24
Peak memory 217016 kb
Host smart-6517b356-e251-4f31-ba38-ca626342f1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833242925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1833242925
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.372238501
Short name T351
Test name
Test status
Simulation time 5208657157 ps
CPU time 15.18 seconds
Started Aug 11 06:20:09 PM PDT 24
Finished Aug 11 06:20:24 PM PDT 24
Peak memory 216980 kb
Host smart-05f99eb9-f7fa-401e-bc14-083660e4176e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372238501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.372238501
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.452855128
Short name T353
Test name
Test status
Simulation time 53824479 ps
CPU time 1.22 seconds
Started Aug 11 06:20:06 PM PDT 24
Finished Aug 11 06:20:07 PM PDT 24
Peak memory 208544 kb
Host smart-27eb24e9-c18a-4c46-bb2c-f4fc29faca69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452855128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.452855128
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.852760968
Short name T669
Test name
Test status
Simulation time 210775840 ps
CPU time 0.88 seconds
Started Aug 11 06:20:06 PM PDT 24
Finished Aug 11 06:20:07 PM PDT 24
Peak memory 206540 kb
Host smart-c597999e-37f7-4200-99b4-d28b834fe250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852760968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.852760968
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1998134167
Short name T407
Test name
Test status
Simulation time 21317875502 ps
CPU time 18.94 seconds
Started Aug 11 06:20:09 PM PDT 24
Finished Aug 11 06:20:28 PM PDT 24
Peak memory 233432 kb
Host smart-873aa305-4d41-4d8e-8370-bae54459e5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998134167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1998134167
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2123035089
Short name T777
Test name
Test status
Simulation time 48326283 ps
CPU time 0.71 seconds
Started Aug 11 06:20:14 PM PDT 24
Finished Aug 11 06:20:15 PM PDT 24
Peak memory 206368 kb
Host smart-9fd6d61e-a05a-4b30-8c63-d076ad59d890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123035089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2123035089
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1487974422
Short name T685
Test name
Test status
Simulation time 83084604 ps
CPU time 3.07 seconds
Started Aug 11 06:20:13 PM PDT 24
Finished Aug 11 06:20:16 PM PDT 24
Peak memory 233368 kb
Host smart-1d9c7d01-017c-4124-8acb-337ab6884c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487974422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1487974422
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1269195904
Short name T1002
Test name
Test status
Simulation time 33250709 ps
CPU time 0.81 seconds
Started Aug 11 06:20:05 PM PDT 24
Finished Aug 11 06:20:05 PM PDT 24
Peak memory 207028 kb
Host smart-610a5421-f1ca-4257-8869-04069046935c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269195904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1269195904
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1647842101
Short name T891
Test name
Test status
Simulation time 67742387656 ps
CPU time 123.01 seconds
Started Aug 11 06:20:10 PM PDT 24
Finished Aug 11 06:22:13 PM PDT 24
Peak memory 251492 kb
Host smart-c313d8ed-e43b-4209-a2d3-d892ff7f6e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647842101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1647842101
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1517689102
Short name T998
Test name
Test status
Simulation time 27837989730 ps
CPU time 75.71 seconds
Started Aug 11 06:20:13 PM PDT 24
Finished Aug 11 06:21:29 PM PDT 24
Peak memory 257900 kb
Host smart-db466663-ef70-48ef-a919-2c016f27dea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517689102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1517689102
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3810965408
Short name T64
Test name
Test status
Simulation time 1536308112 ps
CPU time 11.68 seconds
Started Aug 11 06:20:09 PM PDT 24
Finished Aug 11 06:20:21 PM PDT 24
Peak memory 225156 kb
Host smart-eb11f080-7ac1-47c2-b635-de871d501b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810965408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3810965408
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2292904334
Short name T761
Test name
Test status
Simulation time 1975523922 ps
CPU time 50.23 seconds
Started Aug 11 06:20:06 PM PDT 24
Finished Aug 11 06:20:56 PM PDT 24
Peak memory 255212 kb
Host smart-3b34cd7b-cdeb-4154-92f1-3c8b5d3a3148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292904334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2292904334
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.31603074
Short name T465
Test name
Test status
Simulation time 129840126 ps
CPU time 2.86 seconds
Started Aug 11 06:20:08 PM PDT 24
Finished Aug 11 06:20:11 PM PDT 24
Peak memory 233484 kb
Host smart-02ad5770-2712-4be8-a4ec-6e8b2f3b7f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31603074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.31603074
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3161016935
Short name T514
Test name
Test status
Simulation time 26244601280 ps
CPU time 19.04 seconds
Started Aug 11 06:20:09 PM PDT 24
Finished Aug 11 06:20:28 PM PDT 24
Peak memory 225228 kb
Host smart-ff88acd7-9405-45e2-8eca-d024e5f8d6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161016935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3161016935
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1135962006
Short name T437
Test name
Test status
Simulation time 14094325958 ps
CPU time 17.59 seconds
Started Aug 11 06:20:09 PM PDT 24
Finished Aug 11 06:20:26 PM PDT 24
Peak memory 233408 kb
Host smart-4b2e26af-fd95-416f-8f35-b6d89e74592c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135962006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1135962006
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3116516190
Short name T819
Test name
Test status
Simulation time 10546075916 ps
CPU time 8.51 seconds
Started Aug 11 06:20:07 PM PDT 24
Finished Aug 11 06:20:16 PM PDT 24
Peak memory 233384 kb
Host smart-25ecc7cb-7909-4d77-9ddf-140a341261a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116516190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3116516190
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1901954457
Short name T858
Test name
Test status
Simulation time 1508788906 ps
CPU time 12.34 seconds
Started Aug 11 06:20:10 PM PDT 24
Finished Aug 11 06:20:22 PM PDT 24
Peak memory 221312 kb
Host smart-b8f3aae8-1f9e-4004-92bd-cbfbee79c48c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1901954457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1901954457
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2205458287
Short name T152
Test name
Test status
Simulation time 1675082762 ps
CPU time 40.75 seconds
Started Aug 11 06:20:16 PM PDT 24
Finished Aug 11 06:20:57 PM PDT 24
Peak memory 258096 kb
Host smart-9496ae4a-6bff-4646-b360-1bd1ff65c927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205458287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2205458287
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.4030943807
Short name T1017
Test name
Test status
Simulation time 240513381 ps
CPU time 4.52 seconds
Started Aug 11 06:20:06 PM PDT 24
Finished Aug 11 06:20:11 PM PDT 24
Peak memory 217184 kb
Host smart-f4c6eef7-c2cc-4cd3-9f61-e4439eeff818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030943807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4030943807
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1870773416
Short name T535
Test name
Test status
Simulation time 3714872147 ps
CPU time 6.27 seconds
Started Aug 11 06:20:06 PM PDT 24
Finished Aug 11 06:20:12 PM PDT 24
Peak memory 216992 kb
Host smart-a3ff92df-0261-4253-b89b-730b1b45a3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870773416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1870773416
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1489498555
Short name T352
Test name
Test status
Simulation time 31921089 ps
CPU time 0.74 seconds
Started Aug 11 06:20:07 PM PDT 24
Finished Aug 11 06:20:08 PM PDT 24
Peak memory 206076 kb
Host smart-14784670-69eb-434a-aba2-bbe0dd4ff490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489498555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1489498555
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3622491550
Short name T731
Test name
Test status
Simulation time 59487585 ps
CPU time 0.94 seconds
Started Aug 11 06:20:06 PM PDT 24
Finished Aug 11 06:20:07 PM PDT 24
Peak memory 207068 kb
Host smart-1801e311-d0a4-43b3-9691-0b7fef5ac342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622491550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3622491550
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3995541330
Short name T935
Test name
Test status
Simulation time 4401520296 ps
CPU time 15.04 seconds
Started Aug 11 06:20:08 PM PDT 24
Finished Aug 11 06:20:24 PM PDT 24
Peak memory 235900 kb
Host smart-f16edf42-268b-4535-9054-926545ba029c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995541330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3995541330
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2511470008
Short name T734
Test name
Test status
Simulation time 53285629 ps
CPU time 0.73 seconds
Started Aug 11 06:20:13 PM PDT 24
Finished Aug 11 06:20:14 PM PDT 24
Peak memory 205804 kb
Host smart-5aa920ed-6301-4da4-b5c2-d459438f95f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511470008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2511470008
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.973935553
Short name T11
Test name
Test status
Simulation time 71320728 ps
CPU time 3.41 seconds
Started Aug 11 06:20:13 PM PDT 24
Finished Aug 11 06:20:16 PM PDT 24
Peak memory 233392 kb
Host smart-66641d71-0043-4e39-bd34-d4769603005a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973935553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.973935553
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1384222015
Short name T628
Test name
Test status
Simulation time 60901938 ps
CPU time 0.78 seconds
Started Aug 11 06:20:14 PM PDT 24
Finished Aug 11 06:20:15 PM PDT 24
Peak memory 207092 kb
Host smart-b72348ab-56cf-4ba6-8a9f-6ca5230d5bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384222015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1384222015
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1231122335
Short name T706
Test name
Test status
Simulation time 158842975373 ps
CPU time 288.85 seconds
Started Aug 11 06:20:14 PM PDT 24
Finished Aug 11 06:25:04 PM PDT 24
Peak memory 249912 kb
Host smart-f181c2ed-6094-47bf-9f9b-36ed71d1f8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231122335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1231122335
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3444302725
Short name T751
Test name
Test status
Simulation time 6927209312 ps
CPU time 56.86 seconds
Started Aug 11 06:20:12 PM PDT 24
Finished Aug 11 06:21:09 PM PDT 24
Peak memory 241728 kb
Host smart-c2778583-65d5-41f7-ae4c-8777fdcb4ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444302725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3444302725
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2609766173
Short name T193
Test name
Test status
Simulation time 72401968402 ps
CPU time 389.11 seconds
Started Aug 11 06:20:16 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 267928 kb
Host smart-8efbcd50-44b7-41c1-a2f0-ce729dca2085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609766173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2609766173
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.122957544
Short name T808
Test name
Test status
Simulation time 2937121725 ps
CPU time 17.59 seconds
Started Aug 11 06:20:17 PM PDT 24
Finished Aug 11 06:20:35 PM PDT 24
Peak memory 250708 kb
Host smart-8fcc121b-6156-42fd-8a8a-222c346dcf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122957544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.122957544
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.732621196
Short name T743
Test name
Test status
Simulation time 1464888271 ps
CPU time 33.87 seconds
Started Aug 11 06:20:11 PM PDT 24
Finished Aug 11 06:20:45 PM PDT 24
Peak memory 250988 kb
Host smart-f5a5f2a7-86cc-4324-8a63-3202bb8b236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732621196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.732621196
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3674854166
Short name T1015
Test name
Test status
Simulation time 326356959 ps
CPU time 5.8 seconds
Started Aug 11 06:20:14 PM PDT 24
Finished Aug 11 06:20:20 PM PDT 24
Peak memory 225140 kb
Host smart-6634e050-98ef-4abf-b27d-2b01aba5ff12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674854166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3674854166
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.4012055002
Short name T224
Test name
Test status
Simulation time 4118706882 ps
CPU time 9.84 seconds
Started Aug 11 06:20:12 PM PDT 24
Finished Aug 11 06:20:22 PM PDT 24
Peak memory 225200 kb
Host smart-cde9a9a3-9b40-4c96-97ca-41cd4398b47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012055002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4012055002
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3478696112
Short name T655
Test name
Test status
Simulation time 8632418062 ps
CPU time 15.09 seconds
Started Aug 11 06:20:12 PM PDT 24
Finished Aug 11 06:20:27 PM PDT 24
Peak memory 233288 kb
Host smart-48c52b10-3665-48f6-85eb-0ed1f4399292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478696112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3478696112
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2014154807
Short name T595
Test name
Test status
Simulation time 1126213665 ps
CPU time 3.62 seconds
Started Aug 11 06:20:12 PM PDT 24
Finished Aug 11 06:20:16 PM PDT 24
Peak memory 233512 kb
Host smart-4843d587-8e92-4bef-a35f-9012a98af2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014154807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2014154807
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3773787724
Short name T436
Test name
Test status
Simulation time 5297970331 ps
CPU time 5.08 seconds
Started Aug 11 06:20:14 PM PDT 24
Finished Aug 11 06:20:19 PM PDT 24
Peak memory 221896 kb
Host smart-930565f2-d6f6-4909-9716-a59c91c65ef5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3773787724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3773787724
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.832110108
Short name T283
Test name
Test status
Simulation time 23276211275 ps
CPU time 263 seconds
Started Aug 11 06:20:14 PM PDT 24
Finished Aug 11 06:24:37 PM PDT 24
Peak memory 265940 kb
Host smart-0fa15847-58f6-4fb3-9951-5cb32add32f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832110108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.832110108
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.815950041
Short name T314
Test name
Test status
Simulation time 1235181828 ps
CPU time 8.75 seconds
Started Aug 11 06:20:16 PM PDT 24
Finished Aug 11 06:20:25 PM PDT 24
Peak memory 217028 kb
Host smart-7ec8501e-ceb6-42f8-8cb5-59d2bb6bfdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815950041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.815950041
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1737183140
Short name T322
Test name
Test status
Simulation time 6009500271 ps
CPU time 4.35 seconds
Started Aug 11 06:20:15 PM PDT 24
Finished Aug 11 06:20:19 PM PDT 24
Peak memory 216992 kb
Host smart-f7ab5d29-5ce1-46f3-937a-14065e79ad5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737183140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1737183140
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1567459523
Short name T374
Test name
Test status
Simulation time 139119497 ps
CPU time 1.69 seconds
Started Aug 11 06:20:11 PM PDT 24
Finished Aug 11 06:20:13 PM PDT 24
Peak memory 217012 kb
Host smart-b8117406-5242-4ee3-a0bf-eba7e23e41b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567459523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1567459523
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4163601785
Short name T68
Test name
Test status
Simulation time 879792973 ps
CPU time 0.84 seconds
Started Aug 11 06:20:14 PM PDT 24
Finished Aug 11 06:20:15 PM PDT 24
Peak memory 206536 kb
Host smart-3379024f-8e30-4150-a7be-49e1e020831c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163601785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4163601785
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3641860858
Short name T442
Test name
Test status
Simulation time 11101063793 ps
CPU time 18.29 seconds
Started Aug 11 06:20:12 PM PDT 24
Finished Aug 11 06:20:31 PM PDT 24
Peak memory 233508 kb
Host smart-1bc540fb-d39e-4a5a-895a-4ecc4ccddbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641860858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3641860858
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.4061514474
Short name T668
Test name
Test status
Simulation time 12685862 ps
CPU time 0.73 seconds
Started Aug 11 06:20:20 PM PDT 24
Finished Aug 11 06:20:21 PM PDT 24
Peak memory 205300 kb
Host smart-b53dd2fd-cb10-4841-999b-60af6f41e766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061514474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
4061514474
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.108315629
Short name T381
Test name
Test status
Simulation time 292066457 ps
CPU time 3.58 seconds
Started Aug 11 06:20:15 PM PDT 24
Finished Aug 11 06:20:19 PM PDT 24
Peak memory 225208 kb
Host smart-f3c9bac3-a609-4986-b7ee-a65d26a8b060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108315629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.108315629
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1457030985
Short name T626
Test name
Test status
Simulation time 15075408 ps
CPU time 0.77 seconds
Started Aug 11 06:20:14 PM PDT 24
Finished Aug 11 06:20:15 PM PDT 24
Peak memory 207040 kb
Host smart-09d458e7-8830-44b2-97a8-98852a2819a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457030985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1457030985
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3822155467
Short name T1012
Test name
Test status
Simulation time 30251617186 ps
CPU time 59.48 seconds
Started Aug 11 06:20:16 PM PDT 24
Finished Aug 11 06:21:16 PM PDT 24
Peak memory 241616 kb
Host smart-551a51c3-981f-4da7-b0c3-b409e7f38ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822155467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3822155467
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3328931445
Short name T308
Test name
Test status
Simulation time 19943490983 ps
CPU time 96.15 seconds
Started Aug 11 06:20:20 PM PDT 24
Finished Aug 11 06:21:57 PM PDT 24
Peak memory 249972 kb
Host smart-bc83e14a-f277-48d6-9380-a50934a844b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328931445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3328931445
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2166769292
Short name T689
Test name
Test status
Simulation time 3222219912 ps
CPU time 38.49 seconds
Started Aug 11 06:20:20 PM PDT 24
Finished Aug 11 06:20:59 PM PDT 24
Peak memory 241200 kb
Host smart-2692d692-d1eb-4aa2-a8ff-561d0d908413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166769292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2166769292
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3885432321
Short name T354
Test name
Test status
Simulation time 95661893 ps
CPU time 2.85 seconds
Started Aug 11 06:20:12 PM PDT 24
Finished Aug 11 06:20:15 PM PDT 24
Peak memory 233348 kb
Host smart-9a42ca52-7d02-4f6f-9c7d-5b8983727738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885432321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3885432321
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1329723415
Short name T147
Test name
Test status
Simulation time 3639886640 ps
CPU time 46.77 seconds
Started Aug 11 06:20:15 PM PDT 24
Finished Aug 11 06:21:02 PM PDT 24
Peak memory 250956 kb
Host smart-12d36eaa-2f6a-421e-b99d-7a2f9e8f5298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329723415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1329723415
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1328747540
Short name T677
Test name
Test status
Simulation time 724149872 ps
CPU time 4.07 seconds
Started Aug 11 06:20:11 PM PDT 24
Finished Aug 11 06:20:15 PM PDT 24
Peak memory 225148 kb
Host smart-5c2e9bc8-ee42-4b63-aab3-deaff78f35e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328747540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1328747540
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.935066891
Short name T173
Test name
Test status
Simulation time 137590569 ps
CPU time 2.15 seconds
Started Aug 11 06:20:15 PM PDT 24
Finished Aug 11 06:20:18 PM PDT 24
Peak memory 224976 kb
Host smart-98aeacab-688b-4793-9ca5-c5f8f338580d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935066891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.935066891
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2538442932
Short name T45
Test name
Test status
Simulation time 3704008756 ps
CPU time 11.8 seconds
Started Aug 11 06:20:14 PM PDT 24
Finished Aug 11 06:20:26 PM PDT 24
Peak memory 233476 kb
Host smart-afc1ed06-551e-4383-a9c8-3b3bfb55c803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538442932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2538442932
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3475855156
Short name T665
Test name
Test status
Simulation time 116733479 ps
CPU time 2.42 seconds
Started Aug 11 06:20:16 PM PDT 24
Finished Aug 11 06:20:19 PM PDT 24
Peak memory 233076 kb
Host smart-a4d8f60f-0fd2-4d7a-8ada-93174d69aad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475855156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3475855156
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3945817016
Short name T513
Test name
Test status
Simulation time 223907283 ps
CPU time 3.87 seconds
Started Aug 11 06:20:16 PM PDT 24
Finished Aug 11 06:20:20 PM PDT 24
Peak memory 219460 kb
Host smart-0854ade6-fb83-4178-9938-0ff73cc9de12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3945817016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3945817016
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3903327393
Short name T84
Test name
Test status
Simulation time 11845913667 ps
CPU time 53.59 seconds
Started Aug 11 06:20:22 PM PDT 24
Finished Aug 11 06:21:16 PM PDT 24
Peak memory 241340 kb
Host smart-d3c5bf8e-e5c5-45c8-beba-32137a62df34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903327393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3903327393
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1110402427
Short name T473
Test name
Test status
Simulation time 24809460311 ps
CPU time 34 seconds
Started Aug 11 06:20:12 PM PDT 24
Finished Aug 11 06:20:46 PM PDT 24
Peak memory 217092 kb
Host smart-d07dd34e-9dd4-418e-bfac-d4b9dd70e29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110402427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1110402427
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3527310648
Short name T480
Test name
Test status
Simulation time 11397488354 ps
CPU time 16.58 seconds
Started Aug 11 06:20:15 PM PDT 24
Finished Aug 11 06:20:32 PM PDT 24
Peak memory 217008 kb
Host smart-d835bbe0-598b-46c3-ac4a-09e6fa479586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527310648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3527310648
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.4198745296
Short name T908
Test name
Test status
Simulation time 16446415 ps
CPU time 0.68 seconds
Started Aug 11 06:20:13 PM PDT 24
Finished Aug 11 06:20:14 PM PDT 24
Peak memory 205936 kb
Host smart-e3ad9d58-5957-4a46-ae4c-57b519f7885c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198745296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4198745296
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.415648487
Short name T779
Test name
Test status
Simulation time 19613801 ps
CPU time 0.79 seconds
Started Aug 11 06:20:14 PM PDT 24
Finished Aug 11 06:20:15 PM PDT 24
Peak memory 206536 kb
Host smart-2d679be2-e031-4c51-95ca-e87270e8c9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415648487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.415648487
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1354228762
Short name T67
Test name
Test status
Simulation time 71135760 ps
CPU time 3.19 seconds
Started Aug 11 06:20:12 PM PDT 24
Finished Aug 11 06:20:16 PM PDT 24
Peak memory 233416 kb
Host smart-994e5c61-ce20-4737-a5a1-ee3da9754f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354228762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1354228762
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.928549101
Short name T704
Test name
Test status
Simulation time 16374383 ps
CPU time 0.73 seconds
Started Aug 11 06:20:20 PM PDT 24
Finished Aug 11 06:20:21 PM PDT 24
Peak memory 205308 kb
Host smart-cfb41477-59de-40e6-9848-c207d6f0d5c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928549101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.928549101
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.873997695
Short name T755
Test name
Test status
Simulation time 1181790710 ps
CPU time 2.98 seconds
Started Aug 11 06:20:24 PM PDT 24
Finished Aug 11 06:20:27 PM PDT 24
Peak memory 233404 kb
Host smart-fbcb32c4-b95d-4257-ad58-92f159ce157a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873997695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.873997695
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1420051528
Short name T895
Test name
Test status
Simulation time 177298325 ps
CPU time 0.82 seconds
Started Aug 11 06:20:21 PM PDT 24
Finished Aug 11 06:20:22 PM PDT 24
Peak memory 207052 kb
Host smart-0b1910f6-e0cf-4972-9441-356ed14b098f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420051528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1420051528
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.266628038
Short name T61
Test name
Test status
Simulation time 3375841373 ps
CPU time 20.44 seconds
Started Aug 11 06:20:25 PM PDT 24
Finished Aug 11 06:20:46 PM PDT 24
Peak memory 241704 kb
Host smart-8b153d98-97b7-4fee-81b0-c7b6bd5c7f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266628038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.266628038
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1729732150
Short name T144
Test name
Test status
Simulation time 22696652018 ps
CPU time 43.04 seconds
Started Aug 11 06:20:18 PM PDT 24
Finished Aug 11 06:21:01 PM PDT 24
Peak memory 239136 kb
Host smart-911e130e-bf84-47de-ac7e-db23658a51e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729732150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1729732150
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.822496339
Short name T552
Test name
Test status
Simulation time 36770048805 ps
CPU time 71.76 seconds
Started Aug 11 06:20:24 PM PDT 24
Finished Aug 11 06:21:36 PM PDT 24
Peak memory 256020 kb
Host smart-bd2cbba3-8df7-4f32-8dd8-f4a737572b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822496339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.822496339
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.4264459185
Short name T412
Test name
Test status
Simulation time 33168557 ps
CPU time 2.95 seconds
Started Aug 11 06:20:21 PM PDT 24
Finished Aug 11 06:20:24 PM PDT 24
Peak memory 233472 kb
Host smart-a71714b6-5576-4d5e-999e-5ae989bfe580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264459185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.4264459185
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.270469953
Short name T555
Test name
Test status
Simulation time 8143643388 ps
CPU time 68.7 seconds
Started Aug 11 06:20:26 PM PDT 24
Finished Aug 11 06:21:35 PM PDT 24
Peak memory 256908 kb
Host smart-bbff8e9b-a847-43b0-9022-2f8bba703f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270469953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.270469953
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1947403550
Short name T44
Test name
Test status
Simulation time 1403000969 ps
CPU time 15.73 seconds
Started Aug 11 06:20:26 PM PDT 24
Finished Aug 11 06:20:42 PM PDT 24
Peak memory 229532 kb
Host smart-89803e47-93c5-4ad0-969b-7de92edece00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947403550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1947403550
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.949093459
Short name T582
Test name
Test status
Simulation time 73284642831 ps
CPU time 140.91 seconds
Started Aug 11 06:20:25 PM PDT 24
Finished Aug 11 06:22:46 PM PDT 24
Peak memory 233484 kb
Host smart-b9040a1d-7962-419a-bf7a-a220c77b4829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949093459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.949093459
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.885570783
Short name T188
Test name
Test status
Simulation time 1319524752 ps
CPU time 5.29 seconds
Started Aug 11 06:20:18 PM PDT 24
Finished Aug 11 06:20:23 PM PDT 24
Peak memory 225184 kb
Host smart-f3e9ca53-4283-415c-a1b0-306fdebd5d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885570783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.885570783
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1412365891
Short name T175
Test name
Test status
Simulation time 25293450681 ps
CPU time 19.29 seconds
Started Aug 11 06:20:19 PM PDT 24
Finished Aug 11 06:20:38 PM PDT 24
Peak memory 249556 kb
Host smart-bc1b03b6-4b89-4bfb-90e7-ee04e836946b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412365891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1412365891
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3237551227
Short name T690
Test name
Test status
Simulation time 912720744 ps
CPU time 10.92 seconds
Started Aug 11 06:20:26 PM PDT 24
Finished Aug 11 06:20:37 PM PDT 24
Peak memory 220060 kb
Host smart-534d83d9-3bf8-4700-8ac3-1cc7aec799ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3237551227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3237551227
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3823881679
Short name T299
Test name
Test status
Simulation time 8721444923 ps
CPU time 46.33 seconds
Started Aug 11 06:20:19 PM PDT 24
Finished Aug 11 06:21:05 PM PDT 24
Peak memory 249860 kb
Host smart-ca8a5e32-8ca9-4567-98c5-cf0ff5b14362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823881679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3823881679
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3107925517
Short name T494
Test name
Test status
Simulation time 1969352117 ps
CPU time 5.15 seconds
Started Aug 11 06:20:17 PM PDT 24
Finished Aug 11 06:20:22 PM PDT 24
Peak memory 216944 kb
Host smart-849a272a-f875-4be0-a436-142b81ceff7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107925517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3107925517
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.262370046
Short name T527
Test name
Test status
Simulation time 450496003 ps
CPU time 3.66 seconds
Started Aug 11 06:20:25 PM PDT 24
Finished Aug 11 06:20:28 PM PDT 24
Peak memory 216940 kb
Host smart-12e92cc2-7f51-422d-bf4f-47f615373190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262370046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.262370046
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2915019129
Short name T884
Test name
Test status
Simulation time 221191234 ps
CPU time 1.93 seconds
Started Aug 11 06:20:19 PM PDT 24
Finished Aug 11 06:20:21 PM PDT 24
Peak memory 216932 kb
Host smart-4fe3a036-d191-4b92-852c-a36500e59f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915019129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2915019129
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.598927780
Short name T452
Test name
Test status
Simulation time 508167340 ps
CPU time 0.99 seconds
Started Aug 11 06:20:20 PM PDT 24
Finished Aug 11 06:20:21 PM PDT 24
Peak memory 206568 kb
Host smart-24c2b7b8-d77a-4081-b0c1-99cad83cb102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598927780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.598927780
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.4106626031
Short name T823
Test name
Test status
Simulation time 549271820 ps
CPU time 2.28 seconds
Started Aug 11 06:20:19 PM PDT 24
Finished Aug 11 06:20:21 PM PDT 24
Peak memory 225232 kb
Host smart-5d9b119c-b9a1-43cb-a4da-3bfa462e7be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106626031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.4106626031
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4181159377
Short name T398
Test name
Test status
Simulation time 14812459 ps
CPU time 0.75 seconds
Started Aug 11 06:20:27 PM PDT 24
Finished Aug 11 06:20:28 PM PDT 24
Peak memory 206160 kb
Host smart-5c0646ce-aed4-40d2-a870-8583cc5d89b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181159377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4181159377
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2335330155
Short name T848
Test name
Test status
Simulation time 524504349 ps
CPU time 2.44 seconds
Started Aug 11 06:20:25 PM PDT 24
Finished Aug 11 06:20:27 PM PDT 24
Peak memory 233060 kb
Host smart-5d2cf933-0604-4924-b525-72467513be85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335330155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2335330155
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.4255489613
Short name T520
Test name
Test status
Simulation time 15854949 ps
CPU time 0.8 seconds
Started Aug 11 06:20:19 PM PDT 24
Finished Aug 11 06:20:20 PM PDT 24
Peak memory 207404 kb
Host smart-80c64d38-550d-4302-9d20-59065d2e28e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255489613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.4255489613
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2047479727
Short name T260
Test name
Test status
Simulation time 294228538772 ps
CPU time 409.25 seconds
Started Aug 11 06:20:28 PM PDT 24
Finished Aug 11 06:27:17 PM PDT 24
Peak memory 270220 kb
Host smart-ae6832ba-886f-49ff-abe8-741e91462768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047479727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2047479727
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.587241328
Short name T427
Test name
Test status
Simulation time 22480632 ps
CPU time 0.79 seconds
Started Aug 11 06:20:29 PM PDT 24
Finished Aug 11 06:20:29 PM PDT 24
Peak memory 217964 kb
Host smart-908642fe-abd3-44e7-8705-81dcb20f50dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587241328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.587241328
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.119165878
Short name T293
Test name
Test status
Simulation time 78917654821 ps
CPU time 745.3 seconds
Started Aug 11 06:20:29 PM PDT 24
Finished Aug 11 06:32:54 PM PDT 24
Peak memory 272304 kb
Host smart-c815a69d-fe89-4c11-bf6a-2057313e3a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119165878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.119165878
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4113299481
Short name T899
Test name
Test status
Simulation time 93911215 ps
CPU time 4.28 seconds
Started Aug 11 06:20:24 PM PDT 24
Finished Aug 11 06:20:28 PM PDT 24
Peak memory 237724 kb
Host smart-d96137dd-7d0b-47e6-b226-e80345e12dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113299481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4113299481
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.3028365297
Short name T48
Test name
Test status
Simulation time 241907347231 ps
CPU time 312.77 seconds
Started Aug 11 06:20:25 PM PDT 24
Finished Aug 11 06:25:38 PM PDT 24
Peak memory 254980 kb
Host smart-1c4b06b0-1ebf-4a36-b902-925f9efd4358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028365297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.3028365297
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2757920844
Short name T399
Test name
Test status
Simulation time 33121676 ps
CPU time 2.46 seconds
Started Aug 11 06:20:17 PM PDT 24
Finished Aug 11 06:20:20 PM PDT 24
Peak memory 233036 kb
Host smart-1dd1af69-cc18-4bb0-8d59-e968d4723a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757920844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2757920844
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1882555682
Short name T461
Test name
Test status
Simulation time 4516445465 ps
CPU time 38.79 seconds
Started Aug 11 06:20:21 PM PDT 24
Finished Aug 11 06:21:00 PM PDT 24
Peak memory 241124 kb
Host smart-94c62c3c-6f2e-4df0-a6a5-7859ae0b0fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882555682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1882555682
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.302411722
Short name T52
Test name
Test status
Simulation time 23051237319 ps
CPU time 16.4 seconds
Started Aug 11 06:20:17 PM PDT 24
Finished Aug 11 06:20:34 PM PDT 24
Peak memory 225264 kb
Host smart-8bfc6ae3-09d2-4ea4-8297-8aa7532581fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302411722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.302411722
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.38142610
Short name T1027
Test name
Test status
Simulation time 155425337 ps
CPU time 2.59 seconds
Started Aug 11 06:20:19 PM PDT 24
Finished Aug 11 06:20:22 PM PDT 24
Peak memory 233420 kb
Host smart-7df3acfd-319f-4e21-acc8-16bc0a330ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38142610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.38142610
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1306886021
Short name T503
Test name
Test status
Simulation time 82965770 ps
CPU time 3.63 seconds
Started Aug 11 06:20:25 PM PDT 24
Finished Aug 11 06:20:28 PM PDT 24
Peak memory 222832 kb
Host smart-29c1bd2b-238b-4ce2-b18e-18cd94a9fd61
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1306886021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1306886021
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2513001460
Short name T499
Test name
Test status
Simulation time 139145528 ps
CPU time 0.91 seconds
Started Aug 11 06:20:29 PM PDT 24
Finished Aug 11 06:20:30 PM PDT 24
Peak memory 206136 kb
Host smart-e583ffb8-2976-45b2-8cce-af62d32a53f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513001460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2513001460
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1446068959
Short name T1001
Test name
Test status
Simulation time 1280210357 ps
CPU time 2.13 seconds
Started Aug 11 06:20:21 PM PDT 24
Finished Aug 11 06:20:23 PM PDT 24
Peak memory 217008 kb
Host smart-c8e06df4-639e-4ba6-892c-8ca6b4a6060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446068959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1446068959
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1033632173
Short name T65
Test name
Test status
Simulation time 50213114111 ps
CPU time 14.29 seconds
Started Aug 11 06:20:26 PM PDT 24
Finished Aug 11 06:20:40 PM PDT 24
Peak memory 217000 kb
Host smart-1f0d01f5-4d55-4f9b-920a-2007882fdf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033632173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1033632173
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3758575453
Short name T795
Test name
Test status
Simulation time 53535065 ps
CPU time 2.06 seconds
Started Aug 11 06:20:17 PM PDT 24
Finished Aug 11 06:20:20 PM PDT 24
Peak memory 216956 kb
Host smart-e225a3bc-7fe2-4469-a555-1376502f6bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758575453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3758575453
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1802389456
Short name T852
Test name
Test status
Simulation time 14632335 ps
CPU time 0.74 seconds
Started Aug 11 06:20:21 PM PDT 24
Finished Aug 11 06:20:22 PM PDT 24
Peak memory 206760 kb
Host smart-a45918a9-eb74-4187-bfc8-7354431eebb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802389456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1802389456
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1696014958
Short name T631
Test name
Test status
Simulation time 143811180 ps
CPU time 2.19 seconds
Started Aug 11 06:20:23 PM PDT 24
Finished Aug 11 06:20:26 PM PDT 24
Peak memory 224772 kb
Host smart-17a4bd8a-60f4-4202-8c56-5d49e90b63af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696014958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1696014958
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1232117201
Short name T547
Test name
Test status
Simulation time 44771303 ps
CPU time 0.76 seconds
Started Aug 11 06:20:28 PM PDT 24
Finished Aug 11 06:20:28 PM PDT 24
Peak memory 205848 kb
Host smart-1b3518fa-d738-472a-834e-ad2fd557d013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232117201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1232117201
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2565343842
Short name T25
Test name
Test status
Simulation time 168295773 ps
CPU time 4.05 seconds
Started Aug 11 06:20:26 PM PDT 24
Finished Aug 11 06:20:30 PM PDT 24
Peak memory 225408 kb
Host smart-b9b40dce-1f4e-4669-a91a-15f6b6a9cb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565343842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2565343842
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2424868614
Short name T525
Test name
Test status
Simulation time 20935731 ps
CPU time 0.84 seconds
Started Aug 11 06:20:27 PM PDT 24
Finished Aug 11 06:20:28 PM PDT 24
Peak memory 207040 kb
Host smart-8b66217e-8e93-4148-815c-ffb469bff68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424868614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2424868614
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3924693570
Short name T39
Test name
Test status
Simulation time 3137713243 ps
CPU time 10.85 seconds
Started Aug 11 06:20:27 PM PDT 24
Finished Aug 11 06:20:38 PM PDT 24
Peak memory 225272 kb
Host smart-e50bea05-f523-4b8b-8455-122f25e07cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924693570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3924693570
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1247686519
Short name T971
Test name
Test status
Simulation time 3314270295 ps
CPU time 40.02 seconds
Started Aug 11 06:20:27 PM PDT 24
Finished Aug 11 06:21:07 PM PDT 24
Peak memory 255512 kb
Host smart-a2f0a119-55aa-4536-8e97-ddacf3e69c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247686519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1247686519
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4080856512
Short name T443
Test name
Test status
Simulation time 4081623314 ps
CPU time 58.42 seconds
Started Aug 11 06:20:25 PM PDT 24
Finished Aug 11 06:21:24 PM PDT 24
Peak memory 249952 kb
Host smart-be252d5c-5ca9-46f1-aa5b-e365fd91fa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080856512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4080856512
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2381132494
Short name T590
Test name
Test status
Simulation time 233711005 ps
CPU time 5.24 seconds
Started Aug 11 06:20:23 PM PDT 24
Finished Aug 11 06:20:28 PM PDT 24
Peak memory 249812 kb
Host smart-7bdd0ee8-2063-4408-bfc5-d7fe2a204725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381132494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2381132494
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.123797510
Short name T356
Test name
Test status
Simulation time 2841870378 ps
CPU time 6.34 seconds
Started Aug 11 06:20:28 PM PDT 24
Finished Aug 11 06:20:34 PM PDT 24
Peak memory 233488 kb
Host smart-8be95f7d-219b-4ce3-8548-b75d52d80247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123797510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.123797510
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.23189496
Short name T716
Test name
Test status
Simulation time 13768084498 ps
CPU time 41.3 seconds
Started Aug 11 06:20:26 PM PDT 24
Finished Aug 11 06:21:08 PM PDT 24
Peak memory 233548 kb
Host smart-b0a0691a-d98b-46ac-bfba-79f40261c9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23189496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.23189496
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2844155483
Short name T959
Test name
Test status
Simulation time 8878986189 ps
CPU time 16.09 seconds
Started Aug 11 06:20:26 PM PDT 24
Finished Aug 11 06:20:42 PM PDT 24
Peak memory 233444 kb
Host smart-438701ea-6129-40e4-89c4-fc616840c5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844155483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2844155483
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3601049965
Short name T860
Test name
Test status
Simulation time 3422136123 ps
CPU time 7.82 seconds
Started Aug 11 06:20:28 PM PDT 24
Finished Aug 11 06:20:36 PM PDT 24
Peak memory 233480 kb
Host smart-f5317ed3-6c4e-4b8a-8114-e0db58642ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601049965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3601049965
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3675453535
Short name T558
Test name
Test status
Simulation time 2491814379 ps
CPU time 15.48 seconds
Started Aug 11 06:20:27 PM PDT 24
Finished Aug 11 06:20:42 PM PDT 24
Peak memory 221732 kb
Host smart-9f4022a1-1934-4a4f-a5d3-3afa66b4f1b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3675453535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3675453535
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4211072010
Short name T171
Test name
Test status
Simulation time 8739998957 ps
CPU time 164.25 seconds
Started Aug 11 06:20:24 PM PDT 24
Finished Aug 11 06:23:09 PM PDT 24
Peak memory 274416 kb
Host smart-5691a6f9-2366-40e2-ad6a-c05423edb6a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211072010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4211072010
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.20764690
Short name T69
Test name
Test status
Simulation time 3410740299 ps
CPU time 5.79 seconds
Started Aug 11 06:20:25 PM PDT 24
Finished Aug 11 06:20:31 PM PDT 24
Peak memory 216848 kb
Host smart-95ca0511-80f5-4912-833c-780a4e0f3ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20764690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.20764690
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2483346981
Short name T553
Test name
Test status
Simulation time 23673785 ps
CPU time 0.69 seconds
Started Aug 11 06:20:27 PM PDT 24
Finished Aug 11 06:20:28 PM PDT 24
Peak memory 206184 kb
Host smart-f633c8f2-fb1b-4723-81aa-b38d8d254616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483346981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2483346981
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1330239143
Short name T315
Test name
Test status
Simulation time 51689143 ps
CPU time 1.02 seconds
Started Aug 11 06:20:27 PM PDT 24
Finished Aug 11 06:20:28 PM PDT 24
Peak memory 208564 kb
Host smart-0072afcb-5262-4bea-ab66-0713fbd3c01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330239143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1330239143
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2234910530
Short name T327
Test name
Test status
Simulation time 73145212 ps
CPU time 0.74 seconds
Started Aug 11 06:20:22 PM PDT 24
Finished Aug 11 06:20:23 PM PDT 24
Peak memory 206544 kb
Host smart-461e9ce5-d990-4ddd-b5c6-87dae5799cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234910530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2234910530
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2067515566
Short name T945
Test name
Test status
Simulation time 3939034252 ps
CPU time 18.35 seconds
Started Aug 11 06:20:23 PM PDT 24
Finished Aug 11 06:20:41 PM PDT 24
Peak memory 233508 kb
Host smart-06cb2188-5ea6-4c64-9cbb-4330c0b81269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067515566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2067515566
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1546708999
Short name T363
Test name
Test status
Simulation time 14475457 ps
CPU time 0.71 seconds
Started Aug 11 06:18:18 PM PDT 24
Finished Aug 11 06:18:19 PM PDT 24
Peak memory 205320 kb
Host smart-0b45cec0-61c9-4fc0-b85d-7f33d748e75a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546708999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
546708999
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1967690883
Short name T1006
Test name
Test status
Simulation time 188185024 ps
CPU time 4.76 seconds
Started Aug 11 06:18:15 PM PDT 24
Finished Aug 11 06:18:20 PM PDT 24
Peak memory 233424 kb
Host smart-113e3a18-f98e-40dd-847f-21dc80aaa05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967690883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1967690883
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3264322084
Short name T588
Test name
Test status
Simulation time 20596299 ps
CPU time 0.83 seconds
Started Aug 11 06:18:14 PM PDT 24
Finished Aug 11 06:18:15 PM PDT 24
Peak memory 207024 kb
Host smart-a750880c-5cae-4cd8-965d-0d8671ffb5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264322084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3264322084
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3986631143
Short name T717
Test name
Test status
Simulation time 46897357567 ps
CPU time 62.3 seconds
Started Aug 11 06:18:19 PM PDT 24
Finished Aug 11 06:19:21 PM PDT 24
Peak memory 249916 kb
Host smart-7674ff75-713e-424e-adb5-73466c2c0a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986631143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3986631143
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3034434701
Short name T140
Test name
Test status
Simulation time 25704759599 ps
CPU time 106.66 seconds
Started Aug 11 06:18:13 PM PDT 24
Finished Aug 11 06:20:00 PM PDT 24
Peak memory 265228 kb
Host smart-14a20774-63cf-428d-a2a8-01ea3c8a73f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034434701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3034434701
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3635283585
Short name T198
Test name
Test status
Simulation time 33655586422 ps
CPU time 77.06 seconds
Started Aug 11 06:18:17 PM PDT 24
Finished Aug 11 06:19:34 PM PDT 24
Peak memory 255704 kb
Host smart-41d20223-a1ed-4cb7-8c05-4517a65cfe9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635283585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3635283585
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2122220018
Short name T158
Test name
Test status
Simulation time 338075353 ps
CPU time 4.59 seconds
Started Aug 11 06:18:21 PM PDT 24
Finished Aug 11 06:18:25 PM PDT 24
Peak memory 233468 kb
Host smart-0c9db466-c58d-4d36-a208-92fb2c43fdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122220018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2122220018
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.234608911
Short name T654
Test name
Test status
Simulation time 15718634 ps
CPU time 0.8 seconds
Started Aug 11 06:18:17 PM PDT 24
Finished Aug 11 06:18:18 PM PDT 24
Peak memory 216420 kb
Host smart-c787cbf4-3119-49cd-95a0-86d5809d43d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234608911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
234608911
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.4187987664
Short name T918
Test name
Test status
Simulation time 441922480 ps
CPU time 4.94 seconds
Started Aug 11 06:18:17 PM PDT 24
Finished Aug 11 06:18:22 PM PDT 24
Peak memory 225276 kb
Host smart-39d07550-8d0d-40fc-bda3-bb3b345f6553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187987664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4187987664
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1363349986
Short name T242
Test name
Test status
Simulation time 3380659109 ps
CPU time 4.27 seconds
Started Aug 11 06:18:18 PM PDT 24
Finished Aug 11 06:18:23 PM PDT 24
Peak memory 233456 kb
Host smart-c086a6f3-13d6-4938-9301-eb7c0e81652d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363349986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1363349986
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.904454700
Short name T556
Test name
Test status
Simulation time 29158942 ps
CPU time 1.05 seconds
Started Aug 11 06:18:17 PM PDT 24
Finished Aug 11 06:18:18 PM PDT 24
Peak memory 217188 kb
Host smart-a386cd05-360d-4162-86a3-1120d05488ae
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904454700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.904454700
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1274361056
Short name T652
Test name
Test status
Simulation time 1513491659 ps
CPU time 6.15 seconds
Started Aug 11 06:18:21 PM PDT 24
Finished Aug 11 06:18:27 PM PDT 24
Peak memory 233284 kb
Host smart-93e6daa9-3762-4c95-aea6-a2cdfe451a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274361056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1274361056
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1973711479
Short name T913
Test name
Test status
Simulation time 464884255 ps
CPU time 4.2 seconds
Started Aug 11 06:18:21 PM PDT 24
Finished Aug 11 06:18:25 PM PDT 24
Peak memory 234600 kb
Host smart-740b5ea7-5f8b-4408-9fea-ba42a1aae9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973711479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1973711479
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3576140173
Short name T720
Test name
Test status
Simulation time 354184369 ps
CPU time 3.82 seconds
Started Aug 11 06:18:19 PM PDT 24
Finished Aug 11 06:18:23 PM PDT 24
Peak memory 220696 kb
Host smart-95251c03-07e0-40e4-949d-9b09f5e93c80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3576140173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3576140173
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.622942610
Short name T79
Test name
Test status
Simulation time 329130655 ps
CPU time 1.26 seconds
Started Aug 11 06:18:17 PM PDT 24
Finished Aug 11 06:18:18 PM PDT 24
Peak memory 236596 kb
Host smart-91fdf72f-930f-4da9-a9d0-b4b29e6d58ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622942610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.622942610
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.297367254
Short name T17
Test name
Test status
Simulation time 18267943531 ps
CPU time 217.7 seconds
Started Aug 11 06:18:15 PM PDT 24
Finished Aug 11 06:21:53 PM PDT 24
Peak memory 257348 kb
Host smart-b7cbe563-f185-430c-bd09-ce88719a3c6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297367254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.297367254
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3371149622
Short name T647
Test name
Test status
Simulation time 6419352757 ps
CPU time 29.03 seconds
Started Aug 11 06:18:16 PM PDT 24
Finished Aug 11 06:18:45 PM PDT 24
Peak memory 217284 kb
Host smart-1d678e15-2b94-42aa-bc7e-f3cbc359fdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371149622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3371149622
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3498844614
Short name T883
Test name
Test status
Simulation time 6365255877 ps
CPU time 19.13 seconds
Started Aug 11 06:18:19 PM PDT 24
Finished Aug 11 06:18:38 PM PDT 24
Peak memory 217084 kb
Host smart-1ac42df1-f69f-4be9-b540-25949f044216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498844614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3498844614
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4174013621
Short name T405
Test name
Test status
Simulation time 93600518 ps
CPU time 1.04 seconds
Started Aug 11 06:18:16 PM PDT 24
Finished Aug 11 06:18:17 PM PDT 24
Peak memory 208564 kb
Host smart-a33b8abb-b2ed-4b46-9784-b39a3585bd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174013621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4174013621
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.492376263
Short name T622
Test name
Test status
Simulation time 247726517 ps
CPU time 0.87 seconds
Started Aug 11 06:18:17 PM PDT 24
Finished Aug 11 06:18:18 PM PDT 24
Peak memory 206544 kb
Host smart-70b44ce0-d224-45ae-9638-c73976c32e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492376263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.492376263
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3033503632
Short name T965
Test name
Test status
Simulation time 7346077085 ps
CPU time 6.54 seconds
Started Aug 11 06:18:19 PM PDT 24
Finished Aug 11 06:18:26 PM PDT 24
Peak memory 233536 kb
Host smart-98b400e6-3fdd-4cfa-ae59-3341faab70e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033503632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3033503632
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2444083976
Short name T478
Test name
Test status
Simulation time 38385034 ps
CPU time 0.73 seconds
Started Aug 11 06:20:30 PM PDT 24
Finished Aug 11 06:20:31 PM PDT 24
Peak memory 206192 kb
Host smart-d95be2bf-f966-4e28-a6c4-0875c9ae0a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444083976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2444083976
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1028714154
Short name T623
Test name
Test status
Simulation time 326679386 ps
CPU time 3.56 seconds
Started Aug 11 06:20:33 PM PDT 24
Finished Aug 11 06:20:37 PM PDT 24
Peak memory 225204 kb
Host smart-3bd75776-3e4d-488d-bf50-0c27fbac49ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028714154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1028714154
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.456394981
Short name T938
Test name
Test status
Simulation time 111207970 ps
CPU time 0.79 seconds
Started Aug 11 06:20:40 PM PDT 24
Finished Aug 11 06:20:40 PM PDT 24
Peak memory 207068 kb
Host smart-5d525ac9-5bf7-4e88-821f-c8593d5187aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456394981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.456394981
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3133123352
Short name T86
Test name
Test status
Simulation time 3972221014 ps
CPU time 39.36 seconds
Started Aug 11 06:20:32 PM PDT 24
Finished Aug 11 06:21:12 PM PDT 24
Peak memory 249304 kb
Host smart-f1ade35d-fe96-4cde-ab0d-2d4abf2f1772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133123352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3133123352
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.77702950
Short name T821
Test name
Test status
Simulation time 22723831670 ps
CPU time 62.67 seconds
Started Aug 11 06:20:32 PM PDT 24
Finished Aug 11 06:21:35 PM PDT 24
Peak memory 249980 kb
Host smart-630bd17f-9f01-4424-b8ea-f289d4334dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77702950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.77702950
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1668962326
Short name T641
Test name
Test status
Simulation time 27984453024 ps
CPU time 115.49 seconds
Started Aug 11 06:20:30 PM PDT 24
Finished Aug 11 06:22:26 PM PDT 24
Peak memory 250084 kb
Host smart-dd8022a8-3628-4304-89ed-ffb7a0012eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668962326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1668962326
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.262080905
Short name T346
Test name
Test status
Simulation time 39942145 ps
CPU time 2.98 seconds
Started Aug 11 06:20:39 PM PDT 24
Finished Aug 11 06:20:42 PM PDT 24
Peak memory 233460 kb
Host smart-6580aec5-ef03-44ea-b821-23e64b69a863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262080905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.262080905
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.587100245
Short name T946
Test name
Test status
Simulation time 32764255113 ps
CPU time 74.07 seconds
Started Aug 11 06:20:34 PM PDT 24
Finished Aug 11 06:21:48 PM PDT 24
Peak memory 241660 kb
Host smart-41a60fba-c763-4135-b58a-6e49a7c102c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587100245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.587100245
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3540023605
Short name T718
Test name
Test status
Simulation time 1269413956 ps
CPU time 4.43 seconds
Started Aug 11 06:20:33 PM PDT 24
Finished Aug 11 06:20:38 PM PDT 24
Peak memory 233360 kb
Host smart-727d39be-3dbc-4089-ab64-4cf88c52fbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540023605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3540023605
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3803258549
Short name T667
Test name
Test status
Simulation time 297477230 ps
CPU time 2.49 seconds
Started Aug 11 06:20:36 PM PDT 24
Finished Aug 11 06:20:39 PM PDT 24
Peak memory 233080 kb
Host smart-f06dcb17-5ccc-4acf-970e-195e524b59b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803258549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3803258549
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.4041947706
Short name T269
Test name
Test status
Simulation time 38355444 ps
CPU time 2.6 seconds
Started Aug 11 06:20:36 PM PDT 24
Finished Aug 11 06:20:38 PM PDT 24
Peak memory 233432 kb
Host smart-02606c28-0746-40d1-a6cd-99cc5b70af4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041947706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.4041947706
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3319881039
Short name T672
Test name
Test status
Simulation time 2033291100 ps
CPU time 9.52 seconds
Started Aug 11 06:20:33 PM PDT 24
Finished Aug 11 06:20:43 PM PDT 24
Peak memory 235520 kb
Host smart-efcc8944-f4c5-4508-b8f8-622fef035a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319881039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3319881039
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.553313519
Short name T843
Test name
Test status
Simulation time 410815277 ps
CPU time 7.57 seconds
Started Aug 11 06:20:33 PM PDT 24
Finished Aug 11 06:20:41 PM PDT 24
Peak memory 222212 kb
Host smart-4d8c62e5-5861-4af8-90eb-c50528d70535
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=553313519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.553313519
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1091857586
Short name T951
Test name
Test status
Simulation time 424472651069 ps
CPU time 450.63 seconds
Started Aug 11 06:20:31 PM PDT 24
Finished Aug 11 06:28:02 PM PDT 24
Peak memory 253708 kb
Host smart-8cd40998-2406-4732-8da7-0452b762cac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091857586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1091857586
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3224437776
Short name T919
Test name
Test status
Simulation time 1349078466 ps
CPU time 10.91 seconds
Started Aug 11 06:20:34 PM PDT 24
Finished Aug 11 06:20:45 PM PDT 24
Peak memory 217076 kb
Host smart-b545569c-d1ef-4cd6-9a39-9bc0b95ed8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224437776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3224437776
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2014501540
Short name T392
Test name
Test status
Simulation time 9331632621 ps
CPU time 26.95 seconds
Started Aug 11 06:20:32 PM PDT 24
Finished Aug 11 06:20:59 PM PDT 24
Peak memory 216988 kb
Host smart-4546d9fb-d187-4a61-8bbc-043f0cc7ba31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014501540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2014501540
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.496817098
Short name T401
Test name
Test status
Simulation time 74603943 ps
CPU time 0.87 seconds
Started Aug 11 06:20:33 PM PDT 24
Finished Aug 11 06:20:34 PM PDT 24
Peak memory 206600 kb
Host smart-2a842262-605c-4685-989a-bbb8b98ed26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496817098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.496817098
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3618347730
Short name T786
Test name
Test status
Simulation time 35213703 ps
CPU time 0.83 seconds
Started Aug 11 06:20:32 PM PDT 24
Finished Aug 11 06:20:33 PM PDT 24
Peak memory 206448 kb
Host smart-5b9ce834-03d4-46ce-86b9-f3450f1e9def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618347730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3618347730
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.886916919
Short name T763
Test name
Test status
Simulation time 2926490114 ps
CPU time 12.29 seconds
Started Aug 11 06:20:33 PM PDT 24
Finished Aug 11 06:20:45 PM PDT 24
Peak memory 225280 kb
Host smart-94b29b7f-4abe-4847-a183-e74229f8b61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886916919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.886916919
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3067608051
Short name T767
Test name
Test status
Simulation time 49505788 ps
CPU time 0.7 seconds
Started Aug 11 06:20:41 PM PDT 24
Finished Aug 11 06:20:42 PM PDT 24
Peak memory 206192 kb
Host smart-46fe8823-b880-4e2c-a590-3087f3ac1b25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067608051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3067608051
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.804846571
Short name T325
Test name
Test status
Simulation time 34893757 ps
CPU time 2.37 seconds
Started Aug 11 06:20:33 PM PDT 24
Finished Aug 11 06:20:36 PM PDT 24
Peak memory 233088 kb
Host smart-2c0f1bac-3ed5-4f1f-9977-3d747ca5eea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804846571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.804846571
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3001483612
Short name T430
Test name
Test status
Simulation time 60472215 ps
CPU time 0.78 seconds
Started Aug 11 06:20:35 PM PDT 24
Finished Aug 11 06:20:36 PM PDT 24
Peak memory 207028 kb
Host smart-0dedd186-b1dc-4bfe-923a-7845c41164ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001483612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3001483612
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3366761213
Short name T793
Test name
Test status
Simulation time 14154356 ps
CPU time 0.76 seconds
Started Aug 11 06:20:33 PM PDT 24
Finished Aug 11 06:20:34 PM PDT 24
Peak memory 216392 kb
Host smart-3a5d80f4-87dd-45b3-ad50-63410cff8f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366761213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3366761213
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2088960780
Short name T194
Test name
Test status
Simulation time 73905833702 ps
CPU time 575.73 seconds
Started Aug 11 06:20:31 PM PDT 24
Finished Aug 11 06:30:07 PM PDT 24
Peak memory 268292 kb
Host smart-178fae53-73e5-4e6e-a69b-faee64c29ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088960780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2088960780
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2474643060
Short name T310
Test name
Test status
Simulation time 31625535683 ps
CPU time 252.03 seconds
Started Aug 11 06:20:40 PM PDT 24
Finished Aug 11 06:24:53 PM PDT 24
Peak memory 233592 kb
Host smart-4cc4bc67-8197-4788-a962-b55eb0a3dd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474643060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2474643060
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.787995741
Short name T371
Test name
Test status
Simulation time 2073488590 ps
CPU time 16.16 seconds
Started Aug 11 06:20:33 PM PDT 24
Finished Aug 11 06:20:50 PM PDT 24
Peak memory 225252 kb
Host smart-da850039-283b-4f2c-be49-1b7678851292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787995741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.787995741
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.4109208715
Short name T792
Test name
Test status
Simulation time 70301534230 ps
CPU time 266.52 seconds
Started Aug 11 06:20:33 PM PDT 24
Finished Aug 11 06:24:59 PM PDT 24
Peak memory 272368 kb
Host smart-07363c8c-8a3d-4602-9f98-b74ff68aaedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109208715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.4109208715
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1477057862
Short name T611
Test name
Test status
Simulation time 839316839 ps
CPU time 7.77 seconds
Started Aug 11 06:20:39 PM PDT 24
Finished Aug 11 06:20:47 PM PDT 24
Peak memory 233452 kb
Host smart-9a4be55b-c93c-469c-b56d-59e9a82f34fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477057862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1477057862
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.78219830
Short name T230
Test name
Test status
Simulation time 12492595645 ps
CPU time 23.47 seconds
Started Aug 11 06:20:32 PM PDT 24
Finished Aug 11 06:20:55 PM PDT 24
Peak memory 225340 kb
Host smart-1b0a80d8-b92d-421c-a666-f1cf33067c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78219830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.78219830
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1375397239
Short name T625
Test name
Test status
Simulation time 1421792891 ps
CPU time 2.32 seconds
Started Aug 11 06:20:39 PM PDT 24
Finished Aug 11 06:20:42 PM PDT 24
Peak memory 224316 kb
Host smart-baa60b76-d10c-462e-bcdf-a4e656ed70f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375397239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1375397239
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2220313837
Short name T329
Test name
Test status
Simulation time 594069960 ps
CPU time 2.16 seconds
Started Aug 11 06:20:33 PM PDT 24
Finished Aug 11 06:20:35 PM PDT 24
Peak memory 225204 kb
Host smart-6e843b3e-1157-4041-a466-73b506fbad48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220313837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2220313837
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2317168258
Short name T5
Test name
Test status
Simulation time 83504899 ps
CPU time 3.8 seconds
Started Aug 11 06:20:33 PM PDT 24
Finished Aug 11 06:20:37 PM PDT 24
Peak memory 223792 kb
Host smart-56b69f05-d050-42de-a293-b681be6c713b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2317168258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2317168258
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.612317106
Short name T290
Test name
Test status
Simulation time 303835195405 ps
CPU time 472.05 seconds
Started Aug 11 06:20:38 PM PDT 24
Finished Aug 11 06:28:30 PM PDT 24
Peak memory 266600 kb
Host smart-43491c9c-361b-47f1-971a-52a11160b942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612317106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.612317106
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3186130634
Short name T887
Test name
Test status
Simulation time 1283585593 ps
CPU time 19.2 seconds
Started Aug 11 06:20:33 PM PDT 24
Finished Aug 11 06:20:52 PM PDT 24
Peak memory 217024 kb
Host smart-875f3d21-17f8-4bbc-9d63-d64e6a9ce83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186130634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3186130634
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1459121709
Short name T1013
Test name
Test status
Simulation time 2697330340 ps
CPU time 8.13 seconds
Started Aug 11 06:20:32 PM PDT 24
Finished Aug 11 06:20:40 PM PDT 24
Peak memory 217008 kb
Host smart-603db997-af7c-4756-8f9a-b9e70e7f72e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459121709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1459121709
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3991517867
Short name T426
Test name
Test status
Simulation time 800642641 ps
CPU time 1.68 seconds
Started Aug 11 06:20:39 PM PDT 24
Finished Aug 11 06:20:41 PM PDT 24
Peak memory 216996 kb
Host smart-87d55831-1715-422b-924a-8981c6fe3f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991517867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3991517867
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2066356272
Short name T341
Test name
Test status
Simulation time 56035247 ps
CPU time 0.84 seconds
Started Aug 11 06:20:36 PM PDT 24
Finished Aug 11 06:20:37 PM PDT 24
Peak memory 206544 kb
Host smart-4b6acdb5-bf49-4b3a-ab97-d8ece4419e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066356272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2066356272
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1706998218
Short name T222
Test name
Test status
Simulation time 2478880445 ps
CPU time 9.94 seconds
Started Aug 11 06:20:35 PM PDT 24
Finished Aug 11 06:20:45 PM PDT 24
Peak memory 225272 kb
Host smart-7fdd8aea-9bd6-4bae-9610-d42af81268b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706998218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1706998218
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3174759913
Short name T387
Test name
Test status
Simulation time 105549312 ps
CPU time 0.73 seconds
Started Aug 11 06:20:38 PM PDT 24
Finished Aug 11 06:20:39 PM PDT 24
Peak memory 205888 kb
Host smart-6102ca9e-f327-4f81-a116-5e30aa7884fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174759913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3174759913
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1482161948
Short name T255
Test name
Test status
Simulation time 66688930 ps
CPU time 2.59 seconds
Started Aug 11 06:20:38 PM PDT 24
Finished Aug 11 06:20:41 PM PDT 24
Peak memory 225260 kb
Host smart-51c0ac13-10e2-47cd-965c-92a8b9bf39c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482161948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1482161948
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1335756176
Short name T620
Test name
Test status
Simulation time 60037315 ps
CPU time 0.72 seconds
Started Aug 11 06:20:38 PM PDT 24
Finished Aug 11 06:20:39 PM PDT 24
Peak memory 206032 kb
Host smart-e2347e0b-8575-428d-9b5e-bd66cbe1309e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335756176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1335756176
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2445282552
Short name T975
Test name
Test status
Simulation time 834935733747 ps
CPU time 352.73 seconds
Started Aug 11 06:20:41 PM PDT 24
Finished Aug 11 06:26:34 PM PDT 24
Peak memory 255252 kb
Host smart-0b14f1ad-c22a-42d5-be74-7fbcf224f1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445282552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2445282552
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2956689843
Short name T291
Test name
Test status
Simulation time 72372876955 ps
CPU time 708.83 seconds
Started Aug 11 06:20:37 PM PDT 24
Finished Aug 11 06:32:26 PM PDT 24
Peak memory 265012 kb
Host smart-a4b29e17-7f53-4927-856f-4675a8084c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956689843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2956689843
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4166059782
Short name T524
Test name
Test status
Simulation time 10282000602 ps
CPU time 45.82 seconds
Started Aug 11 06:20:38 PM PDT 24
Finished Aug 11 06:21:24 PM PDT 24
Peak memory 250472 kb
Host smart-8fa10b0a-e32e-4043-88a6-5f1783ec4e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166059782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4166059782
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.736678810
Short name T956
Test name
Test status
Simulation time 779549328 ps
CPU time 9.2 seconds
Started Aug 11 06:20:41 PM PDT 24
Finished Aug 11 06:20:50 PM PDT 24
Peak memory 225280 kb
Host smart-a64a2f9a-c768-4803-8e35-50c446a546d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736678810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.736678810
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1066841996
Short name T780
Test name
Test status
Simulation time 36611460051 ps
CPU time 156.29 seconds
Started Aug 11 06:20:40 PM PDT 24
Finished Aug 11 06:23:17 PM PDT 24
Peak memory 250540 kb
Host smart-ad98a017-3d5a-463c-b5c0-67110190eade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066841996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1066841996
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2679329227
Short name T732
Test name
Test status
Simulation time 272032552 ps
CPU time 2.18 seconds
Started Aug 11 06:20:40 PM PDT 24
Finished Aug 11 06:20:42 PM PDT 24
Peak memory 224184 kb
Host smart-167055d8-7b5c-4596-90a6-3eb7dd33b355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679329227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2679329227
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.167838343
Short name T279
Test name
Test status
Simulation time 23906498249 ps
CPU time 40.17 seconds
Started Aug 11 06:20:39 PM PDT 24
Finished Aug 11 06:21:19 PM PDT 24
Peak memory 233356 kb
Host smart-3d998d47-4a86-4ccb-9cd4-8eec547215be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167838343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.167838343
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1509840254
Short name T937
Test name
Test status
Simulation time 6332782957 ps
CPU time 10.88 seconds
Started Aug 11 06:20:38 PM PDT 24
Finished Aug 11 06:20:49 PM PDT 24
Peak memory 233472 kb
Host smart-b39621e3-8580-4ef5-8680-1ab6c254f089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509840254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1509840254
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3575585188
Short name T229
Test name
Test status
Simulation time 1144580157 ps
CPU time 4.55 seconds
Started Aug 11 06:20:40 PM PDT 24
Finished Aug 11 06:20:45 PM PDT 24
Peak memory 233452 kb
Host smart-b94ff6db-55c8-4a75-ba53-74c5d7510433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575585188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3575585188
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.949553948
Short name T420
Test name
Test status
Simulation time 576109242 ps
CPU time 4.18 seconds
Started Aug 11 06:20:38 PM PDT 24
Finished Aug 11 06:20:42 PM PDT 24
Peak memory 219968 kb
Host smart-65b5cbc6-1223-44d0-a9f1-0545b46858fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=949553948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.949553948
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.4139911275
Short name T16
Test name
Test status
Simulation time 11376155698 ps
CPU time 38.12 seconds
Started Aug 11 06:20:40 PM PDT 24
Finished Aug 11 06:21:19 PM PDT 24
Peak memory 249176 kb
Host smart-70152bef-8da5-481b-b453-0bff3e5f5a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139911275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.4139911275
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2980745311
Short name T914
Test name
Test status
Simulation time 2385161896 ps
CPU time 11.99 seconds
Started Aug 11 06:20:36 PM PDT 24
Finished Aug 11 06:20:48 PM PDT 24
Peak memory 217096 kb
Host smart-c03c8b9d-0df9-4e0b-9665-4aa172612440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980745311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2980745311
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.847249507
Short name T532
Test name
Test status
Simulation time 1422702124 ps
CPU time 2.78 seconds
Started Aug 11 06:20:38 PM PDT 24
Finished Aug 11 06:20:41 PM PDT 24
Peak memory 216972 kb
Host smart-65cdda00-c7ce-44c1-8e75-bc4cf536236e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847249507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.847249507
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3826204393
Short name T378
Test name
Test status
Simulation time 56259750 ps
CPU time 1.03 seconds
Started Aug 11 06:20:38 PM PDT 24
Finished Aug 11 06:20:39 PM PDT 24
Peak memory 208572 kb
Host smart-c911f49a-8de6-40a5-8594-5c7863ae80d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826204393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3826204393
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3411995634
Short name T594
Test name
Test status
Simulation time 700701332 ps
CPU time 1.01 seconds
Started Aug 11 06:20:40 PM PDT 24
Finished Aug 11 06:20:41 PM PDT 24
Peak memory 207592 kb
Host smart-1cd2fdc8-1c5b-4277-a00f-09f961911276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411995634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3411995634
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3818219192
Short name T245
Test name
Test status
Simulation time 1344574577 ps
CPU time 5.98 seconds
Started Aug 11 06:20:40 PM PDT 24
Finished Aug 11 06:20:46 PM PDT 24
Peak memory 225280 kb
Host smart-ca74b66f-d744-4f40-9e48-31704ee346dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818219192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3818219192
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3781341213
Short name T933
Test name
Test status
Simulation time 16632429 ps
CPU time 0.68 seconds
Started Aug 11 06:20:45 PM PDT 24
Finished Aug 11 06:20:46 PM PDT 24
Peak memory 205840 kb
Host smart-8a7c6f89-93f8-4453-b113-72b81285bc58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781341213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3781341213
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1801855993
Short name T739
Test name
Test status
Simulation time 372162737 ps
CPU time 6.88 seconds
Started Aug 11 06:20:47 PM PDT 24
Finished Aug 11 06:20:54 PM PDT 24
Peak memory 225208 kb
Host smart-a4de9373-8489-4279-a246-92a8ff16a9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801855993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1801855993
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2892937447
Short name T619
Test name
Test status
Simulation time 76579361 ps
CPU time 0.83 seconds
Started Aug 11 06:20:39 PM PDT 24
Finished Aug 11 06:20:39 PM PDT 24
Peak memory 207032 kb
Host smart-03e7f622-f217-48f4-af1a-a2f6b13f6344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892937447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2892937447
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1270471703
Short name T460
Test name
Test status
Simulation time 832897139 ps
CPU time 9.09 seconds
Started Aug 11 06:20:46 PM PDT 24
Finished Aug 11 06:20:56 PM PDT 24
Peak memory 237616 kb
Host smart-fb6ff89f-71a2-4259-982e-6dee8e579463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270471703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1270471703
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3854090180
Short name T769
Test name
Test status
Simulation time 5004721090 ps
CPU time 57.13 seconds
Started Aug 11 06:20:47 PM PDT 24
Finished Aug 11 06:21:44 PM PDT 24
Peak memory 257800 kb
Host smart-ad3e88aa-c345-4aff-9a66-1fd5cfbab163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854090180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3854090180
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1447020295
Short name T232
Test name
Test status
Simulation time 6753048359 ps
CPU time 33.79 seconds
Started Aug 11 06:20:43 PM PDT 24
Finished Aug 11 06:21:17 PM PDT 24
Peak memory 233576 kb
Host smart-4e9ccd47-b87e-4357-b68d-b66746d94488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447020295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1447020295
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1542458522
Short name T303
Test name
Test status
Simulation time 2175143758 ps
CPU time 14.18 seconds
Started Aug 11 06:20:45 PM PDT 24
Finished Aug 11 06:20:59 PM PDT 24
Peak memory 235304 kb
Host smart-edfc6660-19e1-4d9c-9828-8d93453ab534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542458522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1542458522
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2295010793
Short name T231
Test name
Test status
Simulation time 2119125709 ps
CPU time 22.98 seconds
Started Aug 11 06:20:46 PM PDT 24
Finished Aug 11 06:21:10 PM PDT 24
Peak memory 239976 kb
Host smart-f19ff80a-ab15-4ce9-8a06-7a9ecf6bc1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295010793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2295010793
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3565476503
Short name T557
Test name
Test status
Simulation time 1596192333 ps
CPU time 14.36 seconds
Started Aug 11 06:20:41 PM PDT 24
Finished Aug 11 06:20:56 PM PDT 24
Peak memory 233440 kb
Host smart-004376de-4aa0-465e-b22d-fe10f17742c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565476503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3565476503
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1866379172
Short name T421
Test name
Test status
Simulation time 8570609414 ps
CPU time 44.25 seconds
Started Aug 11 06:20:42 PM PDT 24
Finished Aug 11 06:21:26 PM PDT 24
Peak memory 241700 kb
Host smart-10e95c82-a9ca-4439-8b83-1a6dd1ddccfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866379172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1866379172
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.4116681807
Short name T268
Test name
Test status
Simulation time 510344992 ps
CPU time 4.56 seconds
Started Aug 11 06:20:36 PM PDT 24
Finished Aug 11 06:20:40 PM PDT 24
Peak memory 233464 kb
Host smart-8353b042-5586-4367-acfe-401fc03e77a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116681807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.4116681807
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.773535342
Short name T661
Test name
Test status
Simulation time 2981506405 ps
CPU time 13.75 seconds
Started Aug 11 06:20:37 PM PDT 24
Finished Aug 11 06:20:51 PM PDT 24
Peak memory 233500 kb
Host smart-9b56d6a0-5506-423c-8665-9c3b382fd630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773535342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.773535342
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3816465192
Short name T630
Test name
Test status
Simulation time 96418742 ps
CPU time 3.03 seconds
Started Aug 11 06:20:46 PM PDT 24
Finished Aug 11 06:20:49 PM PDT 24
Peak memory 219380 kb
Host smart-0c5c44a8-f1f2-4716-99d2-53c8ae7a2062
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3816465192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3816465192
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.317247717
Short name T1008
Test name
Test status
Simulation time 7865427920 ps
CPU time 107.94 seconds
Started Aug 11 06:20:44 PM PDT 24
Finished Aug 11 06:22:32 PM PDT 24
Peak memory 241708 kb
Host smart-d92a8e19-ec7b-4178-9739-b80325a50b6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317247717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.317247717
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.257276567
Short name T686
Test name
Test status
Simulation time 3799814637 ps
CPU time 8.3 seconds
Started Aug 11 06:20:41 PM PDT 24
Finished Aug 11 06:20:50 PM PDT 24
Peak memory 217196 kb
Host smart-3ea2ebef-5ff5-4b47-9bd8-2317651a9b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257276567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.257276567
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.787798975
Short name T400
Test name
Test status
Simulation time 12084825 ps
CPU time 0.68 seconds
Started Aug 11 06:20:39 PM PDT 24
Finished Aug 11 06:20:40 PM PDT 24
Peak memory 206116 kb
Host smart-964e3049-74e3-447c-9c44-a146cbc3ac78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787798975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.787798975
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2538596737
Short name T831
Test name
Test status
Simulation time 147228528 ps
CPU time 1.6 seconds
Started Aug 11 06:20:39 PM PDT 24
Finished Aug 11 06:20:40 PM PDT 24
Peak memory 217024 kb
Host smart-032737c8-a76e-46fc-bee8-fc0571a6b978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538596737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2538596737
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.501807817
Short name T492
Test name
Test status
Simulation time 21959700 ps
CPU time 0.77 seconds
Started Aug 11 06:20:39 PM PDT 24
Finished Aug 11 06:20:39 PM PDT 24
Peak memory 206560 kb
Host smart-94f99fe8-e953-4d50-9d23-a3d1c1aaaa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501807817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.501807817
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1350556932
Short name T853
Test name
Test status
Simulation time 10607622681 ps
CPU time 10.3 seconds
Started Aug 11 06:20:45 PM PDT 24
Finished Aug 11 06:20:55 PM PDT 24
Peak memory 233492 kb
Host smart-b76df471-be93-4069-86d4-ae1e2a5ebcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350556932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1350556932
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4202170342
Short name T928
Test name
Test status
Simulation time 28497621 ps
CPU time 0.77 seconds
Started Aug 11 06:20:45 PM PDT 24
Finished Aug 11 06:20:46 PM PDT 24
Peak memory 205868 kb
Host smart-0255e078-8dd6-4442-85f5-4f513c2c5241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202170342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4202170342
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2706603339
Short name T758
Test name
Test status
Simulation time 167969647 ps
CPU time 2.9 seconds
Started Aug 11 06:20:46 PM PDT 24
Finished Aug 11 06:20:49 PM PDT 24
Peak memory 233616 kb
Host smart-1883d197-1eef-4e4f-a4a1-a9d790388108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706603339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2706603339
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1418514557
Short name T885
Test name
Test status
Simulation time 63081444 ps
CPU time 0.78 seconds
Started Aug 11 06:20:43 PM PDT 24
Finished Aug 11 06:20:44 PM PDT 24
Peak memory 207040 kb
Host smart-e20547ec-ffa8-4793-83de-950cb1ef8fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418514557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1418514557
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3826391521
Short name T457
Test name
Test status
Simulation time 66816456382 ps
CPU time 230.77 seconds
Started Aug 11 06:20:47 PM PDT 24
Finished Aug 11 06:24:38 PM PDT 24
Peak memory 257904 kb
Host smart-aea24b65-1cd6-4924-b3da-a26d3fdc5251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826391521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3826391521
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.4050356817
Short name T192
Test name
Test status
Simulation time 116842739042 ps
CPU time 251.19 seconds
Started Aug 11 06:20:45 PM PDT 24
Finished Aug 11 06:24:56 PM PDT 24
Peak memory 267592 kb
Host smart-5a53abc7-1a0f-46ec-8430-c2ca30977ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050356817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.4050356817
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2532255640
Short name T568
Test name
Test status
Simulation time 423841378 ps
CPU time 4.67 seconds
Started Aug 11 06:20:43 PM PDT 24
Finished Aug 11 06:20:48 PM PDT 24
Peak memory 238348 kb
Host smart-120c1a82-3de8-433a-b0fa-21fae674427e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532255640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2532255640
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2560482014
Short name T288
Test name
Test status
Simulation time 21323428371 ps
CPU time 187.97 seconds
Started Aug 11 06:20:44 PM PDT 24
Finished Aug 11 06:23:52 PM PDT 24
Peak memory 250108 kb
Host smart-d2f5f43d-46c3-4a61-8823-88caf9899801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560482014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2560482014
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.192627191
Short name T584
Test name
Test status
Simulation time 278573954 ps
CPU time 5.19 seconds
Started Aug 11 06:20:47 PM PDT 24
Finished Aug 11 06:20:53 PM PDT 24
Peak memory 225236 kb
Host smart-9ceece35-6b97-49ce-a78f-53ff7e8e89de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192627191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.192627191
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.491936876
Short name T448
Test name
Test status
Simulation time 40137752107 ps
CPU time 50.55 seconds
Started Aug 11 06:20:46 PM PDT 24
Finished Aug 11 06:21:37 PM PDT 24
Peak memory 233492 kb
Host smart-f89301a7-6ccb-4742-a62c-ec65559177c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491936876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.491936876
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1784171229
Short name T698
Test name
Test status
Simulation time 106054133 ps
CPU time 2.05 seconds
Started Aug 11 06:20:45 PM PDT 24
Finished Aug 11 06:20:47 PM PDT 24
Peak memory 223616 kb
Host smart-4b41530c-a22a-40e8-840f-4a09e470d870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784171229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1784171229
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.357934736
Short name T794
Test name
Test status
Simulation time 466891094 ps
CPU time 6.2 seconds
Started Aug 11 06:20:43 PM PDT 24
Finished Aug 11 06:20:50 PM PDT 24
Peak memory 249868 kb
Host smart-c008d67d-d89f-4641-9f1e-2e0b55a3dd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357934736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.357934736
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.217765910
Short name T382
Test name
Test status
Simulation time 2524745842 ps
CPU time 15.59 seconds
Started Aug 11 06:20:43 PM PDT 24
Finished Aug 11 06:20:59 PM PDT 24
Peak memory 219844 kb
Host smart-eea2664d-5283-4cd1-bf0b-cf2583487c20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=217765910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.217765910
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1960947241
Short name T281
Test name
Test status
Simulation time 2862701248 ps
CPU time 40.27 seconds
Started Aug 11 06:20:45 PM PDT 24
Finished Aug 11 06:21:25 PM PDT 24
Peak memory 241620 kb
Host smart-19f942b7-8eaa-4bb7-b61b-f7772af0ed47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960947241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1960947241
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3878800937
Short name T728
Test name
Test status
Simulation time 3548445431 ps
CPU time 12.73 seconds
Started Aug 11 06:20:46 PM PDT 24
Finished Aug 11 06:20:59 PM PDT 24
Peak memory 217036 kb
Host smart-3b2deb4f-9eb6-4d96-8673-f93298f121d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878800937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3878800937
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3945074454
Short name T362
Test name
Test status
Simulation time 32242988 ps
CPU time 0.74 seconds
Started Aug 11 06:20:47 PM PDT 24
Finished Aug 11 06:20:48 PM PDT 24
Peak memory 206156 kb
Host smart-916b61ce-e48d-4209-8304-4f4b72ca950c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945074454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3945074454
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3523999581
Short name T360
Test name
Test status
Simulation time 149605088 ps
CPU time 2.62 seconds
Started Aug 11 06:20:46 PM PDT 24
Finished Aug 11 06:20:48 PM PDT 24
Peak memory 217056 kb
Host smart-7f71a241-cb94-40a7-b585-c37fa7615d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523999581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3523999581
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.600818633
Short name T950
Test name
Test status
Simulation time 63092988 ps
CPU time 0.76 seconds
Started Aug 11 06:20:45 PM PDT 24
Finished Aug 11 06:20:46 PM PDT 24
Peak memory 206608 kb
Host smart-ac548a27-a2a9-4506-b99b-d6cedae4931f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600818633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.600818633
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2102163165
Short name T948
Test name
Test status
Simulation time 86872477 ps
CPU time 2.39 seconds
Started Aug 11 06:20:46 PM PDT 24
Finished Aug 11 06:20:48 PM PDT 24
Peak memory 224144 kb
Host smart-b6ee6660-db3d-4749-ab01-1fe248900ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102163165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2102163165
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.618961886
Short name T71
Test name
Test status
Simulation time 18678930 ps
CPU time 0.73 seconds
Started Aug 11 06:20:55 PM PDT 24
Finished Aug 11 06:20:56 PM PDT 24
Peak memory 205272 kb
Host smart-6859bbab-24c4-4e9f-b667-843b4cf90aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618961886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.618961886
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.854323615
Short name T932
Test name
Test status
Simulation time 432835993 ps
CPU time 7.42 seconds
Started Aug 11 06:20:56 PM PDT 24
Finished Aug 11 06:21:04 PM PDT 24
Peak memory 233352 kb
Host smart-016d3bd9-7b3c-4380-a05f-42f5cb7d7e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854323615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.854323615
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2192376419
Short name T319
Test name
Test status
Simulation time 14650351 ps
CPU time 0.76 seconds
Started Aug 11 06:20:46 PM PDT 24
Finished Aug 11 06:20:46 PM PDT 24
Peak memory 207416 kb
Host smart-55a13c6e-2686-4ae1-8cc4-a211ae4cc97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192376419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2192376419
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1544938911
Short name T233
Test name
Test status
Simulation time 54126887197 ps
CPU time 98.06 seconds
Started Aug 11 06:20:52 PM PDT 24
Finished Aug 11 06:22:30 PM PDT 24
Peak memory 237796 kb
Host smart-45a3c394-e1e2-4211-bc7b-94416765d179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544938911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1544938911
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1961665397
Short name T846
Test name
Test status
Simulation time 13187740031 ps
CPU time 145.9 seconds
Started Aug 11 06:20:52 PM PDT 24
Finished Aug 11 06:23:18 PM PDT 24
Peak memory 258084 kb
Host smart-f4468d19-805b-4fd1-9a58-d31cde2e8cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961665397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1961665397
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.798716317
Short name T862
Test name
Test status
Simulation time 845900558 ps
CPU time 6.29 seconds
Started Aug 11 06:20:55 PM PDT 24
Finished Aug 11 06:21:02 PM PDT 24
Peak memory 234956 kb
Host smart-6f11302a-53a0-4c50-84e4-8c1a8042a8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798716317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.798716317
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.438579849
Short name T94
Test name
Test status
Simulation time 32793796366 ps
CPU time 63.93 seconds
Started Aug 11 06:20:50 PM PDT 24
Finished Aug 11 06:21:54 PM PDT 24
Peak memory 241736 kb
Host smart-215c3dbc-cfe0-453f-b37d-6e9c7a5885fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438579849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.438579849
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1437523073
Short name T228
Test name
Test status
Simulation time 2058798387 ps
CPU time 22.66 seconds
Started Aug 11 06:20:52 PM PDT 24
Finished Aug 11 06:21:15 PM PDT 24
Peak memory 233432 kb
Host smart-37cd1af7-412a-4376-a5e9-ffd33277ea44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437523073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1437523073
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4108396300
Short name T249
Test name
Test status
Simulation time 4395190305 ps
CPU time 43.62 seconds
Started Aug 11 06:20:47 PM PDT 24
Finished Aug 11 06:21:31 PM PDT 24
Peak memory 241464 kb
Host smart-11ae33d2-3800-4699-b378-ef5e510b63bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108396300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4108396300
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2309250215
Short name T51
Test name
Test status
Simulation time 1840476516 ps
CPU time 13.24 seconds
Started Aug 11 06:20:50 PM PDT 24
Finished Aug 11 06:21:03 PM PDT 24
Peak memory 234848 kb
Host smart-264f87df-0e15-4f2c-b21a-260310d81129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309250215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2309250215
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.251056881
Short name T449
Test name
Test status
Simulation time 35146447409 ps
CPU time 22.6 seconds
Started Aug 11 06:20:50 PM PDT 24
Finished Aug 11 06:21:13 PM PDT 24
Peak memory 233448 kb
Host smart-6cc18e7e-6578-4f11-8df2-880107657c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251056881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.251056881
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2142618219
Short name T926
Test name
Test status
Simulation time 1773311358 ps
CPU time 12.09 seconds
Started Aug 11 06:20:48 PM PDT 24
Finished Aug 11 06:21:01 PM PDT 24
Peak memory 219296 kb
Host smart-49b0bc66-e2c0-4661-b6bd-87ddc7db0e26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2142618219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2142618219
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2694347083
Short name T988
Test name
Test status
Simulation time 57393771 ps
CPU time 1.1 seconds
Started Aug 11 06:20:52 PM PDT 24
Finished Aug 11 06:20:53 PM PDT 24
Peak memory 207636 kb
Host smart-40f3ad74-d2bd-4a7a-878b-ce5da5f49dc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694347083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2694347083
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1331242035
Short name T974
Test name
Test status
Simulation time 4837679771 ps
CPU time 9.97 seconds
Started Aug 11 06:20:52 PM PDT 24
Finished Aug 11 06:21:02 PM PDT 24
Peak memory 217096 kb
Host smart-2a718585-2bca-4405-82b7-90419e7bc102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331242035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1331242035
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1251390279
Short name T990
Test name
Test status
Simulation time 771059912 ps
CPU time 3.41 seconds
Started Aug 11 06:20:42 PM PDT 24
Finished Aug 11 06:20:45 PM PDT 24
Peak memory 216912 kb
Host smart-8de791b0-1b82-43e5-bbbd-7d9042face82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251390279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1251390279
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2946264406
Short name T414
Test name
Test status
Simulation time 30927721 ps
CPU time 1.13 seconds
Started Aug 11 06:20:52 PM PDT 24
Finished Aug 11 06:20:53 PM PDT 24
Peak memory 216992 kb
Host smart-926e1b20-e02a-461d-8d93-6aac042c8000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946264406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2946264406
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1517341717
Short name T24
Test name
Test status
Simulation time 17729635 ps
CPU time 0.71 seconds
Started Aug 11 06:20:49 PM PDT 24
Finished Aug 11 06:20:49 PM PDT 24
Peak memory 206064 kb
Host smart-daebd3c4-9f3d-47f8-9357-587a376e8c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517341717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1517341717
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3403842108
Short name T724
Test name
Test status
Simulation time 62361922 ps
CPU time 2.29 seconds
Started Aug 11 06:20:51 PM PDT 24
Finished Aug 11 06:20:53 PM PDT 24
Peak memory 232928 kb
Host smart-217cb739-786b-464c-a4f2-3ab74ecf1d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403842108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3403842108
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.4114185722
Short name T866
Test name
Test status
Simulation time 12446839 ps
CPU time 0.78 seconds
Started Aug 11 06:20:53 PM PDT 24
Finished Aug 11 06:20:54 PM PDT 24
Peak memory 205184 kb
Host smart-ff29f85f-e0eb-416b-9d14-a05bef02890d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114185722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
4114185722
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2468409881
Short name T1003
Test name
Test status
Simulation time 1285996412 ps
CPU time 4.4 seconds
Started Aug 11 06:20:50 PM PDT 24
Finished Aug 11 06:20:55 PM PDT 24
Peak memory 225256 kb
Host smart-2a3ab11c-2f32-4eaf-9204-d05fc3af573c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468409881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2468409881
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2417682732
Short name T650
Test name
Test status
Simulation time 80084328 ps
CPU time 0.81 seconds
Started Aug 11 06:20:53 PM PDT 24
Finished Aug 11 06:20:53 PM PDT 24
Peak memory 207064 kb
Host smart-8c1aec45-ebcc-4c7d-b17f-3cf1bbf0a446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417682732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2417682732
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1339325771
Short name T42
Test name
Test status
Simulation time 1685909957 ps
CPU time 24.92 seconds
Started Aug 11 06:20:51 PM PDT 24
Finished Aug 11 06:21:16 PM PDT 24
Peak memory 237804 kb
Host smart-96cdd3a2-20cd-4386-affb-a30f5934d6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339325771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1339325771
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1432976281
Short name T176
Test name
Test status
Simulation time 18190217644 ps
CPU time 167.09 seconds
Started Aug 11 06:20:50 PM PDT 24
Finished Aug 11 06:23:38 PM PDT 24
Peak memory 255928 kb
Host smart-a209db70-3042-4758-9291-94446e5ee96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432976281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1432976281
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2154024669
Short name T729
Test name
Test status
Simulation time 13386630631 ps
CPU time 153.38 seconds
Started Aug 11 06:20:53 PM PDT 24
Finished Aug 11 06:23:26 PM PDT 24
Peak memory 254072 kb
Host smart-2071df07-f8d2-4f80-9907-87f14be516cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154024669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2154024669
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.540616053
Short name T537
Test name
Test status
Simulation time 409251723 ps
CPU time 8.8 seconds
Started Aug 11 06:20:54 PM PDT 24
Finished Aug 11 06:21:03 PM PDT 24
Peak memory 241680 kb
Host smart-758a7691-abc3-4d4d-a878-a2159f3b4889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540616053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.540616053
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.198195225
Short name T890
Test name
Test status
Simulation time 4528131975 ps
CPU time 63.95 seconds
Started Aug 11 06:20:56 PM PDT 24
Finished Aug 11 06:22:00 PM PDT 24
Peak memory 249872 kb
Host smart-ce225902-3a72-43ac-83fc-c81ed75a4c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198195225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.198195225
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.311146726
Short name T1021
Test name
Test status
Simulation time 115928653 ps
CPU time 3.56 seconds
Started Aug 11 06:20:50 PM PDT 24
Finished Aug 11 06:20:54 PM PDT 24
Peak memory 225256 kb
Host smart-aabc9947-1d33-45ed-a792-fcb5d832183f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311146726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.311146726
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2481443482
Short name T648
Test name
Test status
Simulation time 100815593 ps
CPU time 2.19 seconds
Started Aug 11 06:20:51 PM PDT 24
Finished Aug 11 06:20:54 PM PDT 24
Peak memory 225272 kb
Host smart-119a6b64-980b-4b84-b211-e2e59bf91599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481443482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2481443482
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.568314382
Short name T893
Test name
Test status
Simulation time 8191792260 ps
CPU time 10.13 seconds
Started Aug 11 06:20:56 PM PDT 24
Finished Aug 11 06:21:07 PM PDT 24
Peak memory 225260 kb
Host smart-32ebb146-acbb-4aa6-ae29-62236d94050a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568314382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.568314382
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2215433779
Short name T936
Test name
Test status
Simulation time 142947523 ps
CPU time 2.68 seconds
Started Aug 11 06:20:52 PM PDT 24
Finished Aug 11 06:20:54 PM PDT 24
Peak memory 233400 kb
Host smart-f1ea190b-c602-46a3-97c1-5b964806f11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215433779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2215433779
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.750583682
Short name T957
Test name
Test status
Simulation time 183348048 ps
CPU time 4.2 seconds
Started Aug 11 06:20:50 PM PDT 24
Finished Aug 11 06:20:54 PM PDT 24
Peak memory 223172 kb
Host smart-6e304ebd-d274-4eec-906e-367b936911b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=750583682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.750583682
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1850425305
Short name T521
Test name
Test status
Simulation time 38339140 ps
CPU time 0.94 seconds
Started Aug 11 06:20:50 PM PDT 24
Finished Aug 11 06:20:51 PM PDT 24
Peak memory 208040 kb
Host smart-d040daa3-e23e-4f8c-8581-c2577da3a0df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850425305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1850425305
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4012166084
Short name T27
Test name
Test status
Simulation time 3240882342 ps
CPU time 25.95 seconds
Started Aug 11 06:20:53 PM PDT 24
Finished Aug 11 06:21:19 PM PDT 24
Peak memory 217072 kb
Host smart-646222cc-0856-4243-a242-c4ec4f4f2488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012166084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4012166084
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.4027632724
Short name T575
Test name
Test status
Simulation time 2212271979 ps
CPU time 5.59 seconds
Started Aug 11 06:20:49 PM PDT 24
Finished Aug 11 06:20:55 PM PDT 24
Peak memory 216920 kb
Host smart-219c8925-5199-4a3d-919c-4d3cbc01e78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027632724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.4027632724
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3099474151
Short name T709
Test name
Test status
Simulation time 25933637 ps
CPU time 0.78 seconds
Started Aug 11 06:20:53 PM PDT 24
Finished Aug 11 06:20:54 PM PDT 24
Peak memory 206592 kb
Host smart-ebed2cc4-d8d2-4213-ba92-056a6b5b6369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099474151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3099474151
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3913342343
Short name T320
Test name
Test status
Simulation time 27693562 ps
CPU time 0.74 seconds
Started Aug 11 06:20:50 PM PDT 24
Finished Aug 11 06:20:51 PM PDT 24
Peak memory 206544 kb
Host smart-73af3dc3-cf1e-45bd-a714-7abc256b1cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913342343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3913342343
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1641438349
Short name T947
Test name
Test status
Simulation time 1689743204 ps
CPU time 3.75 seconds
Started Aug 11 06:20:53 PM PDT 24
Finished Aug 11 06:20:57 PM PDT 24
Peak memory 233384 kb
Host smart-e42350be-0153-4c34-a355-95972c093c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641438349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1641438349
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2101294644
Short name T342
Test name
Test status
Simulation time 26508991 ps
CPU time 0.68 seconds
Started Aug 11 06:20:58 PM PDT 24
Finished Aug 11 06:20:59 PM PDT 24
Peak memory 205792 kb
Host smart-8e2dea0e-8ef5-498c-b04d-620ec595847c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101294644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2101294644
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2347473211
Short name T634
Test name
Test status
Simulation time 7320547565 ps
CPU time 23.87 seconds
Started Aug 11 06:21:03 PM PDT 24
Finished Aug 11 06:21:27 PM PDT 24
Peak memory 225300 kb
Host smart-38c21f9a-90b7-4612-8adf-bbbfedbec7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347473211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2347473211
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2290119022
Short name T523
Test name
Test status
Simulation time 15328779 ps
CPU time 0.76 seconds
Started Aug 11 06:20:52 PM PDT 24
Finished Aug 11 06:20:53 PM PDT 24
Peak memory 206028 kb
Host smart-1b2e929a-4146-411f-868f-bffb6d3eed10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290119022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2290119022
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2405953916
Short name T666
Test name
Test status
Simulation time 162764100063 ps
CPU time 168.25 seconds
Started Aug 11 06:20:58 PM PDT 24
Finished Aug 11 06:23:47 PM PDT 24
Peak memory 249868 kb
Host smart-446f05b9-bad7-4fb8-930e-cf68ccae4503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405953916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2405953916
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.826474393
Short name T275
Test name
Test status
Simulation time 10551376698 ps
CPU time 64.86 seconds
Started Aug 11 06:21:00 PM PDT 24
Finished Aug 11 06:22:05 PM PDT 24
Peak memory 257772 kb
Host smart-f47dc828-ff20-40bd-bf48-fb1a6d5ddccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826474393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.826474393
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1721807010
Short name T778
Test name
Test status
Simulation time 33182500964 ps
CPU time 95.49 seconds
Started Aug 11 06:21:00 PM PDT 24
Finished Aug 11 06:22:36 PM PDT 24
Peak memory 255596 kb
Host smart-5f28c6a8-f8ae-4214-acdc-29d122b79ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721807010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1721807010
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.4051244585
Short name T369
Test name
Test status
Simulation time 67126538 ps
CPU time 4 seconds
Started Aug 11 06:20:59 PM PDT 24
Finished Aug 11 06:21:03 PM PDT 24
Peak memory 233344 kb
Host smart-c2a0ad92-4ec1-4690-8d1e-e6981392715d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051244585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.4051244585
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3940405180
Short name T236
Test name
Test status
Simulation time 10448227115 ps
CPU time 15.61 seconds
Started Aug 11 06:20:59 PM PDT 24
Finished Aug 11 06:21:15 PM PDT 24
Peak memory 240368 kb
Host smart-b12ba9f0-109b-408e-b53f-2fd34181813e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940405180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3940405180
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.59815256
Short name T185
Test name
Test status
Simulation time 238677914 ps
CPU time 5.18 seconds
Started Aug 11 06:20:59 PM PDT 24
Finished Aug 11 06:21:04 PM PDT 24
Peak memory 225420 kb
Host smart-94865035-4b56-452a-b758-92730a94816c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59815256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.59815256
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2890705614
Short name T221
Test name
Test status
Simulation time 21962480188 ps
CPU time 56.82 seconds
Started Aug 11 06:21:03 PM PDT 24
Finished Aug 11 06:22:00 PM PDT 24
Peak memory 233572 kb
Host smart-8599ab95-4252-44ed-8b9d-e82ac03ba61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890705614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2890705614
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2135813133
Short name T292
Test name
Test status
Simulation time 1528645407 ps
CPU time 4.64 seconds
Started Aug 11 06:20:56 PM PDT 24
Finished Aug 11 06:21:01 PM PDT 24
Peak memory 233328 kb
Host smart-3f12df35-25db-4c89-8fa1-2814a505708c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135813133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2135813133
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2862921727
Short name T802
Test name
Test status
Simulation time 3951125706 ps
CPU time 4.91 seconds
Started Aug 11 06:20:57 PM PDT 24
Finished Aug 11 06:21:02 PM PDT 24
Peak memory 233492 kb
Host smart-4c728f75-d9fa-47b3-b71a-c19679d0681e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862921727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2862921727
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1093948071
Short name T692
Test name
Test status
Simulation time 626087773 ps
CPU time 3.57 seconds
Started Aug 11 06:20:59 PM PDT 24
Finished Aug 11 06:21:03 PM PDT 24
Peak memory 220824 kb
Host smart-28586cfc-22e0-40a2-852d-745e6ad05941
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1093948071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1093948071
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.4168377164
Short name T60
Test name
Test status
Simulation time 15313397407 ps
CPU time 221.01 seconds
Started Aug 11 06:20:59 PM PDT 24
Finished Aug 11 06:24:40 PM PDT 24
Peak memory 273564 kb
Host smart-58f53de0-93d8-4e47-bbf7-70568558c52d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168377164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.4168377164
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3587771669
Short name T952
Test name
Test status
Simulation time 36352382169 ps
CPU time 24.52 seconds
Started Aug 11 06:20:53 PM PDT 24
Finished Aug 11 06:21:18 PM PDT 24
Peak memory 217300 kb
Host smart-f1b7d419-fa95-499e-bc0c-f3f70bcdbc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587771669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3587771669
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2774718967
Short name T746
Test name
Test status
Simulation time 5410131993 ps
CPU time 9.18 seconds
Started Aug 11 06:20:50 PM PDT 24
Finished Aug 11 06:20:59 PM PDT 24
Peak memory 217048 kb
Host smart-17d10477-a216-4605-a1b4-a72cec510b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774718967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2774718967
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3794479411
Short name T817
Test name
Test status
Simulation time 43768814 ps
CPU time 1.34 seconds
Started Aug 11 06:20:57 PM PDT 24
Finished Aug 11 06:20:58 PM PDT 24
Peak memory 216980 kb
Host smart-80b6d568-04cb-4728-999c-c0756ec59ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794479411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3794479411
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.143518020
Short name T324
Test name
Test status
Simulation time 27335666 ps
CPU time 0.79 seconds
Started Aug 11 06:20:54 PM PDT 24
Finished Aug 11 06:20:55 PM PDT 24
Peak memory 206576 kb
Host smart-eed0d18b-31c3-417d-94aa-6707888f86a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143518020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.143518020
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3871673768
Short name T621
Test name
Test status
Simulation time 701373535 ps
CPU time 4.1 seconds
Started Aug 11 06:21:00 PM PDT 24
Finished Aug 11 06:21:04 PM PDT 24
Peak memory 233400 kb
Host smart-f2a5ae70-0dc2-483b-ad7b-8aed91b64fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871673768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3871673768
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.4049137982
Short name T416
Test name
Test status
Simulation time 122038285 ps
CPU time 0.75 seconds
Started Aug 11 06:20:58 PM PDT 24
Finished Aug 11 06:20:59 PM PDT 24
Peak memory 205304 kb
Host smart-71d9b9ca-365f-42ac-be27-88bc454d16ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049137982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
4049137982
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1225000956
Short name T847
Test name
Test status
Simulation time 511694512 ps
CPU time 6.89 seconds
Started Aug 11 06:20:58 PM PDT 24
Finished Aug 11 06:21:05 PM PDT 24
Peak memory 233284 kb
Host smart-fb428597-20bf-4518-9d3b-00c5e9992c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225000956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1225000956
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1647638522
Short name T435
Test name
Test status
Simulation time 72958451 ps
CPU time 0.85 seconds
Started Aug 11 06:20:59 PM PDT 24
Finished Aug 11 06:21:00 PM PDT 24
Peak memory 207020 kb
Host smart-683daa0c-8db3-49f1-84e5-344ed986aad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647638522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1647638522
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1579354148
Short name T954
Test name
Test status
Simulation time 39897487 ps
CPU time 0.73 seconds
Started Aug 11 06:20:58 PM PDT 24
Finished Aug 11 06:20:59 PM PDT 24
Peak memory 216464 kb
Host smart-e007fde2-befd-46ce-921e-ae6cd5887160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579354148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1579354148
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.4239777609
Short name T307
Test name
Test status
Simulation time 36836676405 ps
CPU time 24.53 seconds
Started Aug 11 06:21:00 PM PDT 24
Finished Aug 11 06:21:25 PM PDT 24
Peak memory 223620 kb
Host smart-b69557a5-cffc-4da4-87ff-a4f0d3db62db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239777609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.4239777609
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3196525392
Short name T417
Test name
Test status
Simulation time 4724733160 ps
CPU time 13.39 seconds
Started Aug 11 06:20:59 PM PDT 24
Finished Aug 11 06:21:12 PM PDT 24
Peak memory 232536 kb
Host smart-66b459b7-e1a7-4020-a1f9-fccd8ac6ded5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196525392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3196525392
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.41277636
Short name T302
Test name
Test status
Simulation time 996640958 ps
CPU time 5.69 seconds
Started Aug 11 06:21:02 PM PDT 24
Finished Aug 11 06:21:07 PM PDT 24
Peak memory 225388 kb
Host smart-52434407-2360-4b68-8227-0fdb9cc379a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41277636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.41277636
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.984453263
Short name T798
Test name
Test status
Simulation time 6547727013 ps
CPU time 19.56 seconds
Started Aug 11 06:20:58 PM PDT 24
Finished Aug 11 06:21:17 PM PDT 24
Peak memory 225304 kb
Host smart-9b091726-66d1-446a-b73d-2adb8d19fa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984453263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.984453263
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3511900675
Short name T391
Test name
Test status
Simulation time 733657413 ps
CPU time 11.23 seconds
Started Aug 11 06:21:01 PM PDT 24
Finished Aug 11 06:21:12 PM PDT 24
Peak memory 233428 kb
Host smart-b1cb4c79-c606-49cc-b8af-72a84bd116da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511900675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3511900675
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1840456973
Short name T987
Test name
Test status
Simulation time 3370886832 ps
CPU time 8.66 seconds
Started Aug 11 06:21:00 PM PDT 24
Finished Aug 11 06:21:09 PM PDT 24
Peak memory 225268 kb
Host smart-8ab56725-c774-42a5-8b79-82d34ac7a849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840456973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1840456973
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.327879016
Short name T406
Test name
Test status
Simulation time 659648696 ps
CPU time 3.2 seconds
Started Aug 11 06:20:58 PM PDT 24
Finished Aug 11 06:21:01 PM PDT 24
Peak memory 225212 kb
Host smart-5a3f4f57-3918-4530-a441-b0c76f81f4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327879016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.327879016
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2126631155
Short name T453
Test name
Test status
Simulation time 396970531 ps
CPU time 6.41 seconds
Started Aug 11 06:20:59 PM PDT 24
Finished Aug 11 06:21:06 PM PDT 24
Peak memory 221112 kb
Host smart-6447639c-4db2-4554-b308-ebb13c116228
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2126631155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2126631155
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2310015832
Short name T170
Test name
Test status
Simulation time 75285533407 ps
CPU time 168.24 seconds
Started Aug 11 06:20:59 PM PDT 24
Finished Aug 11 06:23:47 PM PDT 24
Peak memory 254068 kb
Host smart-0654ae3b-3c7f-4402-8cda-73cb6ca3fa5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310015832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2310015832
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.380592014
Short name T872
Test name
Test status
Simulation time 781144163 ps
CPU time 11.91 seconds
Started Aug 11 06:20:58 PM PDT 24
Finished Aug 11 06:21:10 PM PDT 24
Peak memory 217020 kb
Host smart-99581823-b2ac-4457-893a-38a09ab090ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380592014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.380592014
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3716858066
Short name T326
Test name
Test status
Simulation time 653284856 ps
CPU time 1.96 seconds
Started Aug 11 06:21:03 PM PDT 24
Finished Aug 11 06:21:05 PM PDT 24
Peak memory 216776 kb
Host smart-0a6462f7-1ab4-45fc-b645-76225d6698a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716858066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3716858066
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.943479963
Short name T815
Test name
Test status
Simulation time 12465978 ps
CPU time 0.84 seconds
Started Aug 11 06:21:00 PM PDT 24
Finished Aug 11 06:21:01 PM PDT 24
Peak memory 207692 kb
Host smart-422d8997-0ef3-4a6f-83de-4fb2258473dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943479963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.943479963
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2174182606
Short name T984
Test name
Test status
Simulation time 247771631 ps
CPU time 0.85 seconds
Started Aug 11 06:20:58 PM PDT 24
Finished Aug 11 06:20:59 PM PDT 24
Peak memory 206520 kb
Host smart-e60df66d-9f1f-489d-85d0-271d5793847b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174182606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2174182606
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1059451571
Short name T996
Test name
Test status
Simulation time 12101238684 ps
CPU time 39.9 seconds
Started Aug 11 06:20:56 PM PDT 24
Finished Aug 11 06:21:36 PM PDT 24
Peak memory 249936 kb
Host smart-c8bfa235-37d0-4c82-be6c-daef7befb660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059451571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1059451571
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.4279296572
Short name T1009
Test name
Test status
Simulation time 11888976 ps
CPU time 0.75 seconds
Started Aug 11 06:21:03 PM PDT 24
Finished Aug 11 06:21:04 PM PDT 24
Peak memory 205308 kb
Host smart-eed764d4-e492-4606-8b6e-60b8d0106eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279296572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
4279296572
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1629393420
Short name T799
Test name
Test status
Simulation time 161442407 ps
CPU time 3.84 seconds
Started Aug 11 06:21:04 PM PDT 24
Finished Aug 11 06:21:08 PM PDT 24
Peak memory 225260 kb
Host smart-3523ac86-03e2-425b-b008-bd2a443e83a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629393420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1629393420
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.4241964372
Short name T809
Test name
Test status
Simulation time 41483603 ps
CPU time 0.74 seconds
Started Aug 11 06:20:56 PM PDT 24
Finished Aug 11 06:20:57 PM PDT 24
Peak memory 206348 kb
Host smart-fa229ca0-8273-4cb2-82d9-e044c22b742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241964372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4241964372
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3681778453
Short name T608
Test name
Test status
Simulation time 27520931538 ps
CPU time 106.81 seconds
Started Aug 11 06:21:06 PM PDT 24
Finished Aug 11 06:22:53 PM PDT 24
Peak memory 250888 kb
Host smart-cd8494af-33e4-4d80-8ab9-403558c5120e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681778453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3681778453
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2902077909
Short name T26
Test name
Test status
Simulation time 33439553139 ps
CPU time 147.07 seconds
Started Aug 11 06:21:07 PM PDT 24
Finished Aug 11 06:23:34 PM PDT 24
Peak memory 250764 kb
Host smart-166c6d9c-c50a-48f0-8b5b-dc8333ffd18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902077909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2902077909
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3839051093
Short name T510
Test name
Test status
Simulation time 11864495664 ps
CPU time 52.23 seconds
Started Aug 11 06:21:05 PM PDT 24
Finished Aug 11 06:21:57 PM PDT 24
Peak memory 250832 kb
Host smart-6056451a-85e8-41f0-988a-8b07236a7b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839051093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3839051093
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1802440814
Short name T159
Test name
Test status
Simulation time 892227249 ps
CPU time 11.63 seconds
Started Aug 11 06:21:04 PM PDT 24
Finished Aug 11 06:21:15 PM PDT 24
Peak memory 233468 kb
Host smart-f352fde5-eef8-4cc5-8d47-4ba80d31ae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802440814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1802440814
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3044245091
Short name T476
Test name
Test status
Simulation time 26234130733 ps
CPU time 74.29 seconds
Started Aug 11 06:21:04 PM PDT 24
Finished Aug 11 06:22:18 PM PDT 24
Peak memory 250208 kb
Host smart-5686c43c-a4b1-4e28-8c0a-c10f18e65d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044245091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3044245091
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.4169625173
Short name T604
Test name
Test status
Simulation time 324334021 ps
CPU time 5.3 seconds
Started Aug 11 06:21:05 PM PDT 24
Finished Aug 11 06:21:11 PM PDT 24
Peak memory 233348 kb
Host smart-c2e380cd-c95b-4618-b540-09a327260d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169625173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4169625173
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2277900467
Short name T897
Test name
Test status
Simulation time 2627745308 ps
CPU time 35.62 seconds
Started Aug 11 06:21:06 PM PDT 24
Finished Aug 11 06:21:42 PM PDT 24
Peak memory 233520 kb
Host smart-1eec7436-7ce2-47b4-98b8-5261110a0f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277900467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2277900467
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.297290366
Short name T97
Test name
Test status
Simulation time 2145034805 ps
CPU time 3.86 seconds
Started Aug 11 06:21:06 PM PDT 24
Finished Aug 11 06:21:10 PM PDT 24
Peak memory 233516 kb
Host smart-622eb99c-6d01-4f8e-bd1b-51dc8a97248e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297290366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.297290366
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1257567364
Short name T493
Test name
Test status
Simulation time 1578858953 ps
CPU time 6.78 seconds
Started Aug 11 06:21:08 PM PDT 24
Finished Aug 11 06:21:15 PM PDT 24
Peak memory 235876 kb
Host smart-44e296e3-62e4-4919-8649-c3c1286f710a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257567364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1257567364
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2262413488
Short name T649
Test name
Test status
Simulation time 4388576948 ps
CPU time 15.86 seconds
Started Aug 11 06:21:06 PM PDT 24
Finished Aug 11 06:21:22 PM PDT 24
Peak memory 219980 kb
Host smart-9f0ea4db-1646-413e-a4b1-8a6b3d949ff1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2262413488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2262413488
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1218783513
Short name T614
Test name
Test status
Simulation time 115969704194 ps
CPU time 206.77 seconds
Started Aug 11 06:21:07 PM PDT 24
Finished Aug 11 06:24:34 PM PDT 24
Peak memory 255892 kb
Host smart-ffd2ed68-a973-4a2e-bf74-66955702f580
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218783513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1218783513
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1458521591
Short name T439
Test name
Test status
Simulation time 10959756200 ps
CPU time 28.64 seconds
Started Aug 11 06:20:58 PM PDT 24
Finished Aug 11 06:21:27 PM PDT 24
Peak memory 217060 kb
Host smart-d74d21be-7f66-4dea-b2d7-ce3cdf13a0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458521591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1458521591
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2564088549
Short name T368
Test name
Test status
Simulation time 599435418 ps
CPU time 4.88 seconds
Started Aug 11 06:20:58 PM PDT 24
Finished Aug 11 06:21:03 PM PDT 24
Peak memory 216920 kb
Host smart-67ec8a9b-07bc-4f87-8a24-dc895195f8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564088549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2564088549
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2410954373
Short name T994
Test name
Test status
Simulation time 56449777 ps
CPU time 1.78 seconds
Started Aug 11 06:21:04 PM PDT 24
Finished Aug 11 06:21:06 PM PDT 24
Peak memory 217208 kb
Host smart-8814042a-ca7d-4858-ade9-e43676ad4194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410954373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2410954373
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3619190399
Short name T339
Test name
Test status
Simulation time 202347455 ps
CPU time 1.03 seconds
Started Aug 11 06:20:57 PM PDT 24
Finished Aug 11 06:20:58 PM PDT 24
Peak memory 207060 kb
Host smart-6d0f62cf-c763-4eba-8fc4-05ffceec159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619190399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3619190399
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1861094586
Short name T981
Test name
Test status
Simulation time 1439126890 ps
CPU time 4.69 seconds
Started Aug 11 06:21:05 PM PDT 24
Finished Aug 11 06:21:10 PM PDT 24
Peak memory 225208 kb
Host smart-842ebcde-9f26-4949-8072-33d4c27f9d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861094586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1861094586
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1039168203
Short name T438
Test name
Test status
Simulation time 49321623 ps
CPU time 0.7 seconds
Started Aug 11 06:18:24 PM PDT 24
Finished Aug 11 06:18:25 PM PDT 24
Peak memory 205896 kb
Host smart-c9f04bcf-c205-44cf-b340-60b5ebdb6c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039168203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
039168203
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1243637747
Short name T181
Test name
Test status
Simulation time 1276230190 ps
CPU time 12.2 seconds
Started Aug 11 06:18:23 PM PDT 24
Finished Aug 11 06:18:35 PM PDT 24
Peak memory 225108 kb
Host smart-d6e45e84-efd0-4cfe-abbd-d0b4c142fda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243637747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1243637747
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2802541471
Short name T670
Test name
Test status
Simulation time 18095134 ps
CPU time 0.83 seconds
Started Aug 11 06:18:19 PM PDT 24
Finished Aug 11 06:18:20 PM PDT 24
Peak memory 206008 kb
Host smart-0f26e757-d612-4844-89cb-7ba45b018d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802541471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2802541471
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2105565640
Short name T695
Test name
Test status
Simulation time 4288827036 ps
CPU time 21.67 seconds
Started Aug 11 06:18:23 PM PDT 24
Finished Aug 11 06:18:44 PM PDT 24
Peak memory 256796 kb
Host smart-227f6884-d090-494a-9789-bdafd6ee928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105565640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2105565640
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3651909352
Short name T59
Test name
Test status
Simulation time 41840806868 ps
CPU time 215.82 seconds
Started Aug 11 06:18:25 PM PDT 24
Finished Aug 11 06:22:01 PM PDT 24
Peak memory 270024 kb
Host smart-07995095-a880-4546-8592-0ff16958120f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651909352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3651909352
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.512187770
Short name T150
Test name
Test status
Simulation time 64070244993 ps
CPU time 151.1 seconds
Started Aug 11 06:18:25 PM PDT 24
Finished Aug 11 06:20:57 PM PDT 24
Peak memory 258152 kb
Host smart-646dff5b-35de-4112-9b18-f11dac24d36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512187770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
512187770
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2221203453
Short name T730
Test name
Test status
Simulation time 289454585 ps
CPU time 6.41 seconds
Started Aug 11 06:18:24 PM PDT 24
Finished Aug 11 06:18:31 PM PDT 24
Peak memory 233432 kb
Host smart-a090390d-9f63-46c1-807a-c7a2a76c54c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221203453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2221203453
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.4015714508
Short name T203
Test name
Test status
Simulation time 54830606503 ps
CPU time 113.16 seconds
Started Aug 11 06:18:25 PM PDT 24
Finished Aug 11 06:20:19 PM PDT 24
Peak memory 251852 kb
Host smart-222034d2-3585-4208-990c-2cff3c059e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015714508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.4015714508
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3935515389
Short name T563
Test name
Test status
Simulation time 1750924095 ps
CPU time 6.69 seconds
Started Aug 11 06:18:21 PM PDT 24
Finished Aug 11 06:18:28 PM PDT 24
Peak memory 225216 kb
Host smart-96627778-d463-4986-92da-c2f66c312983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935515389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3935515389
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1764928422
Short name T904
Test name
Test status
Simulation time 110160310 ps
CPU time 4.73 seconds
Started Aug 11 06:18:23 PM PDT 24
Finished Aug 11 06:18:28 PM PDT 24
Peak memory 233332 kb
Host smart-e0b4c474-bb1b-4966-b703-930b973a6b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764928422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1764928422
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3358532127
Short name T901
Test name
Test status
Simulation time 111629961 ps
CPU time 1.15 seconds
Started Aug 11 06:18:18 PM PDT 24
Finished Aug 11 06:18:19 PM PDT 24
Peak memory 217404 kb
Host smart-50191ba5-a443-41e9-a857-3df7cd9c495a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358532127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3358532127
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2959022329
Short name T645
Test name
Test status
Simulation time 859589242 ps
CPU time 5.3 seconds
Started Aug 11 06:18:24 PM PDT 24
Finished Aug 11 06:18:30 PM PDT 24
Peak memory 233428 kb
Host smart-a4379639-7cb1-4134-8560-246303cc64f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959022329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2959022329
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1042823688
Short name T551
Test name
Test status
Simulation time 7405963589 ps
CPU time 21.77 seconds
Started Aug 11 06:18:25 PM PDT 24
Finished Aug 11 06:18:47 PM PDT 24
Peak memory 233676 kb
Host smart-94f7b4e1-e0fc-4d7e-9e77-59ab48bfcc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042823688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1042823688
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3807312260
Short name T870
Test name
Test status
Simulation time 732985104 ps
CPU time 7.96 seconds
Started Aug 11 06:18:24 PM PDT 24
Finished Aug 11 06:18:32 PM PDT 24
Peak memory 219708 kb
Host smart-3a3089d2-b6d2-4d19-8b0c-6b3dc1cbbaf9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3807312260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3807312260
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.635245950
Short name T38
Test name
Test status
Simulation time 27749768163 ps
CPU time 266.29 seconds
Started Aug 11 06:18:27 PM PDT 24
Finished Aug 11 06:22:54 PM PDT 24
Peak memory 266260 kb
Host smart-592b1b32-c650-416d-9b56-6cfc1740f77c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635245950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.635245950
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3396655590
Short name T656
Test name
Test status
Simulation time 5568928005 ps
CPU time 18.27 seconds
Started Aug 11 06:18:21 PM PDT 24
Finished Aug 11 06:18:40 PM PDT 24
Peak memory 217020 kb
Host smart-ab4060f1-b54d-4cbc-829f-653cdb1a7719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396655590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3396655590
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.218220737
Short name T916
Test name
Test status
Simulation time 12669661267 ps
CPU time 7.79 seconds
Started Aug 11 06:18:14 PM PDT 24
Finished Aug 11 06:18:22 PM PDT 24
Peak memory 218156 kb
Host smart-8cb3260d-3637-4d64-acc4-900f6e04de33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218220737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.218220737
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3477929673
Short name T961
Test name
Test status
Simulation time 730058609 ps
CPU time 2.36 seconds
Started Aug 11 06:18:21 PM PDT 24
Finished Aug 11 06:18:23 PM PDT 24
Peak memory 216932 kb
Host smart-3d6d026a-fe5f-4313-a37d-130b2e79e2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477929673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3477929673
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.574916113
Short name T579
Test name
Test status
Simulation time 163762746 ps
CPU time 1.02 seconds
Started Aug 11 06:18:21 PM PDT 24
Finished Aug 11 06:18:22 PM PDT 24
Peak memory 206504 kb
Host smart-7fb51f9c-5ba4-41aa-bf12-91a86b98c966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574916113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.574916113
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.350671355
Short name T955
Test name
Test status
Simulation time 6702701730 ps
CPU time 8.88 seconds
Started Aug 11 06:18:22 PM PDT 24
Finished Aug 11 06:18:31 PM PDT 24
Peak memory 233496 kb
Host smart-eb3f3d00-5877-469f-b2bf-2644491989a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350671355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.350671355
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.466768387
Short name T512
Test name
Test status
Simulation time 30337677 ps
CPU time 0.68 seconds
Started Aug 11 06:18:34 PM PDT 24
Finished Aug 11 06:18:35 PM PDT 24
Peak memory 205208 kb
Host smart-58948458-3408-40b2-92f6-0d4adc0790f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466768387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.466768387
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2522425223
Short name T7
Test name
Test status
Simulation time 648552431 ps
CPU time 6.21 seconds
Started Aug 11 06:18:32 PM PDT 24
Finished Aug 11 06:18:38 PM PDT 24
Peak memory 233408 kb
Host smart-a93b3d04-daa5-44db-b2da-c0c91b6c2fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522425223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2522425223
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2397558554
Short name T393
Test name
Test status
Simulation time 48108550 ps
CPU time 0.78 seconds
Started Aug 11 06:18:27 PM PDT 24
Finished Aug 11 06:18:28 PM PDT 24
Peak memory 206052 kb
Host smart-2990ed46-75f9-4e10-b6dc-4b810445832f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397558554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2397558554
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1819114557
Short name T564
Test name
Test status
Simulation time 7452303071 ps
CPU time 22.54 seconds
Started Aug 11 06:18:36 PM PDT 24
Finished Aug 11 06:18:58 PM PDT 24
Peak memory 235320 kb
Host smart-37bdb52c-1f9f-4174-ae6b-9768914faefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819114557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1819114557
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3065203580
Short name T210
Test name
Test status
Simulation time 165791634694 ps
CPU time 158.9 seconds
Started Aug 11 06:18:33 PM PDT 24
Finished Aug 11 06:21:12 PM PDT 24
Peak memory 256608 kb
Host smart-b7d86932-33cc-4516-ac2a-d2a067165d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065203580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3065203580
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3176848226
Short name T447
Test name
Test status
Simulation time 3139929905 ps
CPU time 18.6 seconds
Started Aug 11 06:18:32 PM PDT 24
Finished Aug 11 06:18:51 PM PDT 24
Peak memory 239284 kb
Host smart-7a77a044-72d6-40c1-8a0e-883a957559cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176848226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3176848226
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3008001784
Short name T585
Test name
Test status
Simulation time 95246482780 ps
CPU time 168.53 seconds
Started Aug 11 06:18:31 PM PDT 24
Finished Aug 11 06:21:20 PM PDT 24
Peak memory 266288 kb
Host smart-26f68e89-febf-4c17-b7de-f3f70ad1b01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008001784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3008001784
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1650572361
Short name T708
Test name
Test status
Simulation time 423681593 ps
CPU time 3.35 seconds
Started Aug 11 06:18:34 PM PDT 24
Finished Aug 11 06:18:38 PM PDT 24
Peak memory 225148 kb
Host smart-dd903a1a-be2d-4714-9145-c3d9bc8aaa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650572361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1650572361
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.126585573
Short name T991
Test name
Test status
Simulation time 970985309 ps
CPU time 11.63 seconds
Started Aug 11 06:18:28 PM PDT 24
Finished Aug 11 06:18:40 PM PDT 24
Peak memory 225224 kb
Host smart-30dec631-d0df-41d3-8b94-156679820cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126585573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.126585573
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2941429864
Short name T1004
Test name
Test status
Simulation time 84510884 ps
CPU time 1.01 seconds
Started Aug 11 06:18:23 PM PDT 24
Finished Aug 11 06:18:24 PM PDT 24
Peak memory 218416 kb
Host smart-f1d5586f-091d-4db5-93a1-8e64a00e0e3c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941429864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2941429864
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3389299244
Short name T263
Test name
Test status
Simulation time 32020633706 ps
CPU time 9.82 seconds
Started Aug 11 06:18:23 PM PDT 24
Finished Aug 11 06:18:33 PM PDT 24
Peak memory 233480 kb
Host smart-312c2191-1064-46e8-8ab5-bd779c85238e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389299244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3389299244
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3241140703
Short name T277
Test name
Test status
Simulation time 13514189485 ps
CPU time 36.16 seconds
Started Aug 11 06:18:23 PM PDT 24
Finished Aug 11 06:19:00 PM PDT 24
Peak memory 252416 kb
Host smart-edc97b3e-5e21-482a-9991-3f674322f88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241140703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3241140703
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.950512696
Short name T1025
Test name
Test status
Simulation time 8731617148 ps
CPU time 12.78 seconds
Started Aug 11 06:18:34 PM PDT 24
Finished Aug 11 06:18:47 PM PDT 24
Peak memory 221156 kb
Host smart-731e03a1-4942-4fd8-acdc-80a89ab08738
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=950512696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.950512696
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.4006637318
Short name T82
Test name
Test status
Simulation time 24726402387 ps
CPU time 272.61 seconds
Started Aug 11 06:18:31 PM PDT 24
Finished Aug 11 06:23:04 PM PDT 24
Peak memory 256840 kb
Host smart-6b90cdcd-4259-4f34-a969-51e3908a7c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006637318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.4006637318
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3159233594
Short name T432
Test name
Test status
Simulation time 4430740234 ps
CPU time 21.57 seconds
Started Aug 11 06:18:28 PM PDT 24
Finished Aug 11 06:18:49 PM PDT 24
Peak memory 217160 kb
Host smart-7c4849a7-5f56-490d-96f2-00dbbd8b5380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159233594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3159233594
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3402121188
Short name T55
Test name
Test status
Simulation time 13824901261 ps
CPU time 9.44 seconds
Started Aug 11 06:18:26 PM PDT 24
Finished Aug 11 06:18:36 PM PDT 24
Peak memory 217224 kb
Host smart-292fa718-f98e-42a7-9c2d-233b3bdfe18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402121188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3402121188
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1785810506
Short name T855
Test name
Test status
Simulation time 448363045 ps
CPU time 1.74 seconds
Started Aug 11 06:18:28 PM PDT 24
Finished Aug 11 06:18:30 PM PDT 24
Peak memory 216988 kb
Host smart-2e0993b9-9936-453f-8553-c0fa1bc70a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785810506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1785810506
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1055220922
Short name T997
Test name
Test status
Simulation time 169091242 ps
CPU time 0.84 seconds
Started Aug 11 06:18:27 PM PDT 24
Finished Aug 11 06:18:28 PM PDT 24
Peak memory 206576 kb
Host smart-3252f3ce-f685-43bd-8a55-9eb65778fc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055220922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1055220922
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3535237792
Short name T560
Test name
Test status
Simulation time 508354853 ps
CPU time 4.13 seconds
Started Aug 11 06:18:32 PM PDT 24
Finished Aug 11 06:18:37 PM PDT 24
Peak memory 225248 kb
Host smart-33b53fca-9320-4f28-859d-ce347ec41396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535237792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3535237792
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3580040414
Short name T573
Test name
Test status
Simulation time 52310159 ps
CPU time 0.72 seconds
Started Aug 11 06:18:38 PM PDT 24
Finished Aug 11 06:18:39 PM PDT 24
Peak memory 206212 kb
Host smart-26fa65bc-b6d4-46b4-bd00-6969acf10f3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580040414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
580040414
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2297134619
Short name T95
Test name
Test status
Simulation time 126015195 ps
CPU time 3.32 seconds
Started Aug 11 06:18:37 PM PDT 24
Finished Aug 11 06:18:40 PM PDT 24
Peak memory 233460 kb
Host smart-781e6005-626d-46f3-8d1f-03aa745b2d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297134619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2297134619
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1602451517
Short name T675
Test name
Test status
Simulation time 30279491 ps
CPU time 0.82 seconds
Started Aug 11 06:18:33 PM PDT 24
Finished Aug 11 06:18:34 PM PDT 24
Peak memory 207388 kb
Host smart-af862d2d-8d99-437c-8768-7e51dfec6509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602451517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1602451517
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3218484685
Short name T358
Test name
Test status
Simulation time 4095451618 ps
CPU time 37.56 seconds
Started Aug 11 06:18:30 PM PDT 24
Finished Aug 11 06:19:08 PM PDT 24
Peak memory 249920 kb
Host smart-9e88d42e-4098-42bb-bae1-ce3b989c312a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218484685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3218484685
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2971056946
Short name T915
Test name
Test status
Simulation time 4001324072 ps
CPU time 32.24 seconds
Started Aug 11 06:18:35 PM PDT 24
Finished Aug 11 06:19:07 PM PDT 24
Peak memory 225368 kb
Host smart-c3414d83-f828-4323-b8ec-934926ee5a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971056946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2971056946
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1040488608
Short name T976
Test name
Test status
Simulation time 34660805651 ps
CPU time 305.09 seconds
Started Aug 11 06:18:36 PM PDT 24
Finished Aug 11 06:23:42 PM PDT 24
Peak memory 258124 kb
Host smart-0f372d2a-48e8-488f-bb7d-9709651270ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040488608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1040488608
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1021189349
Short name T488
Test name
Test status
Simulation time 113748336 ps
CPU time 4.02 seconds
Started Aug 11 06:18:33 PM PDT 24
Finished Aug 11 06:18:38 PM PDT 24
Peak memory 233424 kb
Host smart-e5372ec4-62a4-4fc8-b5c3-d887697f3fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021189349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1021189349
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3788116562
Short name T179
Test name
Test status
Simulation time 30581089114 ps
CPU time 102.06 seconds
Started Aug 11 06:18:33 PM PDT 24
Finished Aug 11 06:20:15 PM PDT 24
Peak memory 266272 kb
Host smart-6e5415b1-7a68-42e2-bba4-60513ce15cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788116562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3788116562
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2413758030
Short name T796
Test name
Test status
Simulation time 113125008 ps
CPU time 4.05 seconds
Started Aug 11 06:18:31 PM PDT 24
Finished Aug 11 06:18:35 PM PDT 24
Peak memory 233436 kb
Host smart-3bda98a9-b77f-4773-8ee3-8364a33a2851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413758030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2413758030
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.821731679
Short name T1023
Test name
Test status
Simulation time 17528829654 ps
CPU time 23.11 seconds
Started Aug 11 06:18:37 PM PDT 24
Finished Aug 11 06:19:00 PM PDT 24
Peak memory 234476 kb
Host smart-69138e3d-a72e-45a2-bf11-d25301851e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821731679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.821731679
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3756827710
Short name T411
Test name
Test status
Simulation time 32192259 ps
CPU time 1.04 seconds
Started Aug 11 06:18:35 PM PDT 24
Finished Aug 11 06:18:36 PM PDT 24
Peak memory 217172 kb
Host smart-c5633461-f31b-4e3c-800b-9996ca40f5ce
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756827710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3756827710
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1037618964
Short name T264
Test name
Test status
Simulation time 22535252102 ps
CPU time 19.16 seconds
Started Aug 11 06:18:32 PM PDT 24
Finished Aug 11 06:18:51 PM PDT 24
Peak memory 241728 kb
Host smart-e6893adf-8926-4c7c-a765-04906a904290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037618964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1037618964
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.732768105
Short name T970
Test name
Test status
Simulation time 6336524752 ps
CPU time 19.52 seconds
Started Aug 11 06:18:28 PM PDT 24
Finished Aug 11 06:18:48 PM PDT 24
Peak memory 228924 kb
Host smart-3bfd6034-6eef-473f-ae0e-a0055c6f595e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732768105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.732768105
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3283797364
Short name T701
Test name
Test status
Simulation time 1541024586 ps
CPU time 14.83 seconds
Started Aug 11 06:18:34 PM PDT 24
Finished Aug 11 06:18:49 PM PDT 24
Peak memory 222388 kb
Host smart-2282ecaa-1e42-4829-a21e-217d49b012cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3283797364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3283797364
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1533891121
Short name T892
Test name
Test status
Simulation time 85556121584 ps
CPU time 229.83 seconds
Started Aug 11 06:18:34 PM PDT 24
Finished Aug 11 06:22:24 PM PDT 24
Peak memory 268344 kb
Host smart-c1995958-5f42-4153-9cf9-b2554161623b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533891121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1533891121
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3360228260
Short name T662
Test name
Test status
Simulation time 9281174472 ps
CPU time 17.63 seconds
Started Aug 11 06:18:31 PM PDT 24
Finished Aug 11 06:18:49 PM PDT 24
Peak memory 220748 kb
Host smart-1fde306e-fb45-4b45-b20b-a7eb51d0369b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360228260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3360228260
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2667983120
Short name T603
Test name
Test status
Simulation time 1123192442 ps
CPU time 7.75 seconds
Started Aug 11 06:18:34 PM PDT 24
Finished Aug 11 06:18:42 PM PDT 24
Peak memory 216856 kb
Host smart-dc4c0ee7-c8ec-45fb-8129-5a7c7381e9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667983120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2667983120
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2972232469
Short name T888
Test name
Test status
Simulation time 16864701 ps
CPU time 0.69 seconds
Started Aug 11 06:18:31 PM PDT 24
Finished Aug 11 06:18:32 PM PDT 24
Peak memory 206120 kb
Host smart-278cdc2e-1b4b-48a0-95a8-78f14507932a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972232469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2972232469
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2032062606
Short name T764
Test name
Test status
Simulation time 109461526 ps
CPU time 0.84 seconds
Started Aug 11 06:18:33 PM PDT 24
Finished Aug 11 06:18:34 PM PDT 24
Peak memory 206572 kb
Host smart-473417ec-ce80-460b-8b57-8c143e1ff03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032062606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2032062606
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2887201286
Short name T486
Test name
Test status
Simulation time 3023250075 ps
CPU time 3.68 seconds
Started Aug 11 06:18:29 PM PDT 24
Finished Aug 11 06:18:33 PM PDT 24
Peak memory 225300 kb
Host smart-40008437-82c0-47ec-ab6d-8fa19f089544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887201286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2887201286
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2724599284
Short name T576
Test name
Test status
Simulation time 12381919 ps
CPU time 0.72 seconds
Started Aug 11 06:18:38 PM PDT 24
Finished Aug 11 06:18:39 PM PDT 24
Peak memory 205296 kb
Host smart-52f690e1-83c3-4df9-bf02-bd3a98c1920c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724599284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
724599284
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2873112540
Short name T259
Test name
Test status
Simulation time 2125861289 ps
CPU time 4.79 seconds
Started Aug 11 06:18:40 PM PDT 24
Finished Aug 11 06:18:45 PM PDT 24
Peak memory 225228 kb
Host smart-e3f79b1b-281f-4f5f-9914-1a37ccc01f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873112540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2873112540
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1576050369
Short name T463
Test name
Test status
Simulation time 60859469 ps
CPU time 0.8 seconds
Started Aug 11 06:18:39 PM PDT 24
Finished Aug 11 06:18:39 PM PDT 24
Peak memory 207076 kb
Host smart-15928fdb-10cb-47a8-b3ee-fd673bbf13c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576050369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1576050369
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1517500878
Short name T911
Test name
Test status
Simulation time 3302279572 ps
CPU time 25.63 seconds
Started Aug 11 06:18:38 PM PDT 24
Finished Aug 11 06:19:04 PM PDT 24
Peak memory 225592 kb
Host smart-18314b4d-2d4a-4ceb-b544-9aca987fab92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517500878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1517500878
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.661643852
Short name T33
Test name
Test status
Simulation time 57513108681 ps
CPU time 223.39 seconds
Started Aug 11 06:18:38 PM PDT 24
Finished Aug 11 06:22:22 PM PDT 24
Peak memory 266408 kb
Host smart-411a6a94-1219-49b9-baf7-fc98f4b0ff6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661643852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.661643852
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.562992618
Short name T271
Test name
Test status
Simulation time 11578312906 ps
CPU time 133.76 seconds
Started Aug 11 06:18:41 PM PDT 24
Finished Aug 11 06:20:54 PM PDT 24
Peak memory 250960 kb
Host smart-2f521505-e3a6-4e02-aded-f74a8bfe2c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562992618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
562992618
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2695906113
Short name T722
Test name
Test status
Simulation time 392990718 ps
CPU time 4.14 seconds
Started Aug 11 06:18:36 PM PDT 24
Finished Aug 11 06:18:41 PM PDT 24
Peak memory 241616 kb
Host smart-990ee90c-c8a7-48b8-b995-3b027c94845d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695906113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2695906113
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1531613449
Short name T396
Test name
Test status
Simulation time 2867428470 ps
CPU time 53.56 seconds
Started Aug 11 06:18:38 PM PDT 24
Finished Aug 11 06:19:31 PM PDT 24
Peak memory 249916 kb
Host smart-7bb725b0-3f29-4771-9873-e1ef0f93e91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531613449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1531613449
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3600125839
Short name T567
Test name
Test status
Simulation time 443466004 ps
CPU time 3.37 seconds
Started Aug 11 06:18:44 PM PDT 24
Finished Aug 11 06:18:47 PM PDT 24
Peak memory 225224 kb
Host smart-a3a8d885-5dd3-4dbc-991d-892639243d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600125839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3600125839
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1815555527
Short name T534
Test name
Test status
Simulation time 5719418550 ps
CPU time 23.36 seconds
Started Aug 11 06:18:37 PM PDT 24
Finished Aug 11 06:19:01 PM PDT 24
Peak memory 225312 kb
Host smart-a5994365-7792-4e3a-8f8b-f9f578bba210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815555527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1815555527
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3736466866
Short name T586
Test name
Test status
Simulation time 43184411 ps
CPU time 1.06 seconds
Started Aug 11 06:18:38 PM PDT 24
Finished Aug 11 06:18:39 PM PDT 24
Peak memory 217100 kb
Host smart-99fd5830-831c-4987-b527-0b48701c5472
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736466866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3736466866
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2104547507
Short name T775
Test name
Test status
Simulation time 1502134646 ps
CPU time 6.92 seconds
Started Aug 11 06:18:41 PM PDT 24
Finished Aug 11 06:18:48 PM PDT 24
Peak memory 233416 kb
Host smart-3a47032a-df09-46b9-b50f-40cfbe6a7c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104547507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2104547507
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3878811791
Short name T688
Test name
Test status
Simulation time 8318102705 ps
CPU time 16 seconds
Started Aug 11 06:18:44 PM PDT 24
Finished Aug 11 06:19:00 PM PDT 24
Peak memory 233540 kb
Host smart-f4570442-636e-4578-985a-cf2178948fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878811791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3878811791
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3048172228
Short name T782
Test name
Test status
Simulation time 557569106 ps
CPU time 4.78 seconds
Started Aug 11 06:18:44 PM PDT 24
Finished Aug 11 06:18:49 PM PDT 24
Peak memory 223148 kb
Host smart-1d674be7-7f2d-4c49-9ca3-11aa931cd455
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3048172228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3048172228
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3618028283
Short name T816
Test name
Test status
Simulation time 5999230353 ps
CPU time 12.58 seconds
Started Aug 11 06:18:41 PM PDT 24
Finished Aug 11 06:18:54 PM PDT 24
Peak memory 217208 kb
Host smart-7c0545c2-08e2-4145-954f-f9d41031930b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618028283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3618028283
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1273485001
Short name T471
Test name
Test status
Simulation time 31700966970 ps
CPU time 22.13 seconds
Started Aug 11 06:18:38 PM PDT 24
Finished Aug 11 06:19:01 PM PDT 24
Peak memory 216848 kb
Host smart-8defab0d-d181-44c7-9e03-cdef27bc260b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273485001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1273485001
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3112981659
Short name T842
Test name
Test status
Simulation time 143710702 ps
CPU time 1.64 seconds
Started Aug 11 06:18:38 PM PDT 24
Finished Aug 11 06:18:40 PM PDT 24
Peak memory 217024 kb
Host smart-024ca858-f2d4-4fec-a4e8-824f24a72fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112981659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3112981659
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2649908114
Short name T806
Test name
Test status
Simulation time 117122807 ps
CPU time 0.89 seconds
Started Aug 11 06:18:39 PM PDT 24
Finished Aug 11 06:18:40 PM PDT 24
Peak memory 206608 kb
Host smart-cfe6f048-4b56-43a8-8fb4-9d56ce7aa60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649908114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2649908114
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3077596418
Short name T177
Test name
Test status
Simulation time 4537429577 ps
CPU time 10.14 seconds
Started Aug 11 06:18:37 PM PDT 24
Finished Aug 11 06:18:47 PM PDT 24
Peak memory 233492 kb
Host smart-a175fec8-6ee9-4be5-ab18-249a1ee8de57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077596418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3077596418
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.710443304
Short name T577
Test name
Test status
Simulation time 34057161 ps
CPU time 0.74 seconds
Started Aug 11 06:18:44 PM PDT 24
Finished Aug 11 06:18:45 PM PDT 24
Peak memory 205276 kb
Host smart-3ab52b3d-1f74-4015-a3e1-c5693d8d63f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710443304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.710443304
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.644173032
Short name T851
Test name
Test status
Simulation time 2846710209 ps
CPU time 8.59 seconds
Started Aug 11 06:18:36 PM PDT 24
Finished Aug 11 06:18:44 PM PDT 24
Peak memory 233452 kb
Host smart-8f6452cf-a57a-4cbb-bd76-97fef3fc269a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644173032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.644173032
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.334989486
Short name T737
Test name
Test status
Simulation time 53020503 ps
CPU time 0.76 seconds
Started Aug 11 06:18:38 PM PDT 24
Finished Aug 11 06:18:39 PM PDT 24
Peak memory 206000 kb
Host smart-e1c694c8-cbf5-4b17-9e81-7e532bcf5c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334989486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.334989486
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3980237059
Short name T653
Test name
Test status
Simulation time 7692217573 ps
CPU time 32.4 seconds
Started Aug 11 06:18:39 PM PDT 24
Finished Aug 11 06:19:12 PM PDT 24
Peak memory 239912 kb
Host smart-aa89da2a-d829-403a-8583-0fc7ef71b862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980237059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3980237059
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1149962498
Short name T834
Test name
Test status
Simulation time 27275085118 ps
CPU time 185.36 seconds
Started Aug 11 06:18:39 PM PDT 24
Finished Aug 11 06:21:45 PM PDT 24
Peak memory 265236 kb
Host smart-fa3be580-ca2a-43b8-9a93-9b237c1f4059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149962498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1149962498
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1394635681
Short name T580
Test name
Test status
Simulation time 77725171830 ps
CPU time 215.12 seconds
Started Aug 11 06:18:42 PM PDT 24
Finished Aug 11 06:22:17 PM PDT 24
Peak memory 267352 kb
Host smart-d79242cc-5645-440c-b919-2fc5cf4027e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394635681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1394635681
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.234703490
Short name T789
Test name
Test status
Simulation time 288315085 ps
CPU time 5.13 seconds
Started Aug 11 06:18:40 PM PDT 24
Finished Aug 11 06:18:45 PM PDT 24
Peak memory 233496 kb
Host smart-8c48fdc2-242a-4345-94eb-73f2a7c74666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234703490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.234703490
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.383852531
Short name T296
Test name
Test status
Simulation time 217579715424 ps
CPU time 274.81 seconds
Started Aug 11 06:18:40 PM PDT 24
Finished Aug 11 06:23:15 PM PDT 24
Peak memory 262532 kb
Host smart-8f01ee5e-fdf0-4925-bc26-2c18bbfa25b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383852531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
383852531
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.44453803
Short name T986
Test name
Test status
Simulation time 200268138 ps
CPU time 3.38 seconds
Started Aug 11 06:18:40 PM PDT 24
Finished Aug 11 06:18:43 PM PDT 24
Peak memory 233684 kb
Host smart-8001e2ca-f6c5-433d-ae96-22bfb8d2fb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44453803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.44453803
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2828831196
Short name T825
Test name
Test status
Simulation time 5644279698 ps
CPU time 17.49 seconds
Started Aug 11 06:18:40 PM PDT 24
Finished Aug 11 06:18:57 PM PDT 24
Peak memory 225252 kb
Host smart-8c5f450e-7f69-4003-b12a-311fe66d1336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828831196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2828831196
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.996417043
Short name T1010
Test name
Test status
Simulation time 33237879 ps
CPU time 1.04 seconds
Started Aug 11 06:18:36 PM PDT 24
Finished Aug 11 06:18:37 PM PDT 24
Peak memory 218416 kb
Host smart-ab5ddfda-282d-4008-90c0-d039e7d35aea
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996417043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.996417043
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2099166383
Short name T419
Test name
Test status
Simulation time 495468919 ps
CPU time 2.86 seconds
Started Aug 11 06:18:40 PM PDT 24
Finished Aug 11 06:18:43 PM PDT 24
Peak memory 225208 kb
Host smart-a61b3bb2-f255-4c70-8836-bc2637ca6cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099166383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2099166383
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2981031334
Short name T583
Test name
Test status
Simulation time 39911773 ps
CPU time 2.41 seconds
Started Aug 11 06:18:39 PM PDT 24
Finished Aug 11 06:18:42 PM PDT 24
Peak memory 233488 kb
Host smart-844a8b7d-7e5d-4f74-b15e-7b608aba0a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981031334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2981031334
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1308308972
Short name T495
Test name
Test status
Simulation time 1412052741 ps
CPU time 13.71 seconds
Started Aug 11 06:18:41 PM PDT 24
Finished Aug 11 06:18:55 PM PDT 24
Peak memory 222776 kb
Host smart-8f2b4eba-18d2-400a-8c4c-dcd40dbd45c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1308308972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1308308972
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3159198329
Short name T639
Test name
Test status
Simulation time 40912220300 ps
CPU time 20.09 seconds
Started Aug 11 06:18:39 PM PDT 24
Finished Aug 11 06:18:59 PM PDT 24
Peak memory 225360 kb
Host smart-0800479f-848c-44c2-9955-6f3a5f367a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159198329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3159198329
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.235669227
Short name T742
Test name
Test status
Simulation time 1910157376 ps
CPU time 12.09 seconds
Started Aug 11 06:18:40 PM PDT 24
Finished Aug 11 06:18:53 PM PDT 24
Peak memory 217164 kb
Host smart-e666446e-fc39-4200-a7a4-42b13a35d02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235669227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.235669227
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.548307031
Short name T810
Test name
Test status
Simulation time 993094538 ps
CPU time 2.72 seconds
Started Aug 11 06:18:37 PM PDT 24
Finished Aug 11 06:18:40 PM PDT 24
Peak memory 216944 kb
Host smart-5ae4e519-9837-482a-ad6c-4635004d4434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548307031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.548307031
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2957991639
Short name T748
Test name
Test status
Simulation time 69773722 ps
CPU time 1.1 seconds
Started Aug 11 06:18:36 PM PDT 24
Finished Aug 11 06:18:38 PM PDT 24
Peak memory 208204 kb
Host smart-ca867997-e112-48d2-9cbb-ca6eb23ce128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957991639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2957991639
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1869335104
Short name T365
Test name
Test status
Simulation time 43360723 ps
CPU time 0.78 seconds
Started Aug 11 06:18:37 PM PDT 24
Finished Aug 11 06:18:38 PM PDT 24
Peak memory 206548 kb
Host smart-7714fa5f-dd35-4bce-8be9-fd38d4b235c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869335104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1869335104
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2467138127
Short name T66
Test name
Test status
Simulation time 343998831 ps
CPU time 5.29 seconds
Started Aug 11 06:18:41 PM PDT 24
Finished Aug 11 06:18:46 PM PDT 24
Peak memory 238996 kb
Host smart-d06a4aa8-9205-4258-8684-8d61404cdf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467138127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2467138127
Directory /workspace/9.spi_device_upload/latest
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