Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2309364	1			T1	1		T2	1		T3	1
all_values[1]	2309364	1			T1	1		T2	1		T3	1
all_values[2]	2309364	1			T1	1		T2	1		T3	1
all_values[3]	2309364	1			T1	1		T2	1		T3	1
all_values[4]	2309364	1			T1	1		T2	1		T3	1
all_values[5]	2309364	1			T1	1		T2	1		T3	1
all_values[6]	2309364	1			T1	1		T2	1		T3	1
all_values[7]	2309364	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17785473

1

T1

8

T2

8

T3

8

auto[1]

689439

1

T16

56599

T17

52

T18

15468

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18450751

1

T1

8

T2

8

T3

8

auto[1]

24161

1

T16

477

T23

249

T26

28

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2218890	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	10854	1			T16	22		T23	121		T26	16
all_values[0]	auto[1]	auto[0]	79118	1			T16	18655		T17	6		T19	9
all_values[0]	auto[1]	auto[1]	502	1			T16	209		T17	4		T18	1
all_values[1]	auto[0]	auto[0]	2162708	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	7080	1			T16	15		T23	101		T26	12
all_values[1]	auto[1]	auto[0]	138830	1			T16	18711		T17	1		T18	7665
all_values[1]	auto[1]	auto[1]	746	1			T16	153		T18	66		T19	13
all_values[2]	auto[0]	auto[0]	2215600	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2686	1			T16	1		T23	27		T18	43
all_values[2]	auto[1]	auto[0]	90778	1			T16	18808		T17	8		T18	2
all_values[2]	auto[1]	auto[1]	300	1			T16	55		T17	2		T19	7
all_values[3]	auto[0]	auto[0]	2242416	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	210	1			T16	3		T17	2		T19	5
all_values[3]	auto[1]	auto[0]	66544	1			T17	4		T18	1		T19	10
all_values[3]	auto[1]	auto[1]	194	1			T16	1		T17	1		T18	1
all_values[4]	auto[0]	auto[0]	2218369	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	238	1			T16	5		T17	2		T18	4
all_values[4]	auto[1]	auto[0]	90553	1			T17	2		T19	4		T20	3
all_values[4]	auto[1]	auto[1]	204	1			T16	2		T17	2		T19	10
all_values[5]	auto[0]	auto[0]	2211181	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	174	1			T16	2		T17	2		T19	5
all_values[5]	auto[1]	auto[0]	97815	1			T16	2		T17	4		T18	7730
all_values[5]	auto[1]	auto[1]	194	1			T17	2		T18	1		T19	6
all_values[6]	auto[0]	auto[0]	2263680	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	197	1			T16	4		T17	3		T18	2
all_values[6]	auto[1]	auto[0]	45307	1			T16	1		T17	4		T19	11
all_values[6]	auto[1]	auto[1]	180	1			T17	2		T18	1		T19	12
all_values[7]	auto[0]	auto[0]	2230998	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	192	1			T16	3		T18	3		T19	3
all_values[7]	auto[1]	auto[0]	77964	1			T17	7		T19	5		T20	3
all_values[7]	auto[1]	auto[1]	210	1			T16	2		T17	3		T19	3