Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35547	1			T4	4		T5	2		T7	2
auto[SpiFlashAddrCfg]	7773	1			T5	2		T10	6		T14	6
auto[SpiFlashAddr3b]	9159	1			T5	4		T7	8		T11	2
auto[SpiFlashAddr4b]	7620	1			T5	2		T7	2		T49	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34721

1

T4

4

T7

12

T8

12

auto[1]

25378

1

T5

10

T11

2

T49

12

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32013

1

T4

4

T5

4

T7

6

auto[1]

28086

1

T5

6

T7

6

T10

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40031	1			T4	4		T5	6		T7	4
values[1]	1222	1			T31	4		T16	7		T23	3
values[2]	1461	1			T14	2		T49	2		T31	3
values[3]	1428	1			T31	3		T42	1		T16	3
values[4]	1415	1			T42	3		T16	6		T23	6
values[5]	1570	1			T7	2		T42	3		T16	12
values[6]	1493	1			T14	2		T49	4		T31	2
values[7]	1444	1			T10	2		T49	4		T31	3
values[8]	10035	1			T5	4		T7	6		T10	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32578

1

T4

4

T5

10

T7

12

auto[1]

27521

1

T31

161

T16

164

T48

160

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56760

1

T4

4

T5

6

T7

12

write

3339

1

T5

4

T14

2

T49

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19183

1

T4

4

T5

2

T7

6

valids[0x1]

40916

1

T5

8

T7

6

T11

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1593	1			T31	6		T42	2		T16	7
internal_process_ops[0x5a]	1611	1			T5	2		T7	2		T31	2
internal_process_ops[0x05]	21616	1			T7	2		T31	86		T42	3
internal_process_ops[0x35]	1521	1			T13	2		T31	1		T16	9
internal_process_ops[0x15]	1511	1			T5	2		T31	2		T42	1
internal_process_ops[0x03]	1177	1			T7	2		T14	2		T31	1
internal_process_ops[0x0b]	1042	1			T49	4		T31	2		T42	6
internal_process_ops[0x3b]	1079	1			T7	2		T42	3		T16	8
internal_process_ops[0x6b]	1051	1			T31	1		T16	5		T23	11
internal_process_ops[0xbb]	1083	1			T42	1		T16	7		T23	6
internal_process_ops[0xeb]	1131	1			T5	2		T7	4		T10	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58492

1

T4

4

T5

6

T7

12

auto[1]

1607

1

T5

4

T49

2

T31

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57696

1

T4

4

T5

10

T7

12

auto[1]

2403

1

T31

4

T42

14

T16

19

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11582

1

T4

4

T7

2

T8

12

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6195

1

T5

2

T42

3

T16

7

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2205

1

T10

6

T14

4

T42

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1941

1

T49

4

T42

8

T16

12

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2576

1

T7

8

T14

2

T42

7

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2324

1

T5

2

T11

2

T49

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2190

1

T7

2

T42

3

T16

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1874

1

T5

2

T49

4

T42

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

117

1

T103

1

T193

1

T50

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

124

1

T42

2

T16

2

T23

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

98

1

T16

1

T23

4

T24

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

114

1

T49

2

T42

4

T16

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

104

1

T14

2

T40

1

T53

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

101

1

T42

4

T17

3

T53

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

130

1

T42

1

T23

2

T26

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

103

1

T5

2

T16

2

T23

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

123

1

T26

4

T18

1

T53

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

77

1

T23

1

T17

1

T53

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

111

1

T23

2

T17

1

T148

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

121

1

T5

2

T42

2

T40

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

108

1

T23

2

T26

3

T17

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

63

1

T55

1

T101

4

T194

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

89

1

T42

1

T23

2

T26

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

108

1

T17

1

T53

2

T195

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10056

1

T31

26

T16

34

T48

41

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6866

1

T31

91

T16

56

T48

18

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1388

1

T31

8

T16

9

T48

13

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1390

1

T31

2

T16

5

T48

23

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1719

1

T31

8

T16

17

T48

17

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1704

1

T31

9

T16

6

T48

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1421

1

T31

4

T16

17

T48

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1329

1

T31

4

T16

4

T48

13

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

91

1

T18

1

T111

4

T196

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

98

1

T16

1

T48

1

T111

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

97

1

T31

2

T67

1

T18

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

109

1

T16

2

T18

4

T111

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

117

1

T48

3

T18

2

T88

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

80

1

T31

3

T88

1

T197

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T31

1

T16

1

T48

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

119

1

T16

2

T111

1

T57

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

88

1

T48

2

T18

3

T111

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

91

1

T48

1

T67

1

T88

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

133

1

T31

2

T48

1

T68

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

92

1

T16

2

T48

1

T18

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

101

1

T16

1

T196

1

T88

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

101

1

T16

2

T67

3

T18

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

130

1

T31

1

T16

2

T18

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

106

1

T16

3

T18

1

T196

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3995	1			T4	4		T8	12		T12	8
auto[0]	values[0]	valids[0x1]	16659	1			T5	6		T7	4		T13	2
auto[0]	values[1]	valids[0x1]	657	1			T16	3		T23	3		T26	3
auto[0]	values[2]	valids[0x0]	572	1			T14	2		T16	4		T23	5
auto[0]	values[2]	valids[0x1]	289	1			T49	2		T42	2		T16	1
auto[0]	values[3]	valids[0x0]	606	1			T42	1		T23	3		T24	1
auto[0]	values[3]	valids[0x1]	276	1			T23	2		T24	2		T17	3
auto[0]	values[4]	valids[0x0]	535	1			T42	2		T16	3		T23	4
auto[0]	values[4]	valids[0x1]	351	1			T42	1		T16	2		T23	2
auto[0]	values[5]	valids[0x0]	576	1			T7	2		T42	1		T16	6
auto[0]	values[5]	valids[0x1]	352	1			T42	2		T16	1		T23	1
auto[0]	values[6]	valids[0x0]	537	1			T49	4		T16	3		T23	13
auto[0]	values[6]	valids[0x1]	325	1			T14	2		T16	1		T23	5
auto[0]	values[7]	valids[0x0]	539	1			T10	2		T42	1		T16	5
auto[0]	values[7]	valids[0x1]	315	1			T49	4		T16	2		T23	1
auto[0]	values[8]	valids[0x0]	3666	1			T5	2		T7	4		T10	4
auto[0]	values[8]	valids[0x1]	2328	1			T5	2		T7	2		T11	2
auto[1]	values[0]	valids[0x0]	3708	1			T31	19		T16	23		T48	34
auto[1]	values[0]	valids[0x1]	15669	1			T31	118		T16	86		T48	53
auto[1]	values[1]	valids[0x1]	565	1			T31	4		T16	4		T48	5
auto[1]	values[2]	valids[0x0]	379	1			T31	3		T16	3		T48	4
auto[1]	values[2]	valids[0x1]	221	1			T16	3		T48	1		T67	1
auto[1]	values[3]	valids[0x0]	324	1			T31	3		T16	3		T48	1
auto[1]	values[3]	valids[0x1]	222	1			T48	2		T18	3		T111	1
auto[1]	values[4]	valids[0x0]	298	1			T48	3		T18	2		T111	2
auto[1]	values[4]	valids[0x1]	231	1			T16	1		T48	3		T67	1
auto[1]	values[5]	valids[0x0]	362	1			T16	1		T48	5		T68	1
auto[1]	values[5]	valids[0x1]	280	1			T16	4		T48	2		T67	1
auto[1]	values[6]	valids[0x0]	370	1			T31	2		T16	3		T48	6
auto[1]	values[6]	valids[0x1]	261	1			T16	1		T48	2		T68	3
auto[1]	values[7]	valids[0x0]	345	1			T31	2		T16	1		T48	1
auto[1]	values[7]	valids[0x1]	245	1			T31	1		T16	3		T18	6
auto[1]	values[8]	valids[0x0]	2371	1			T31	6		T16	10		T48	21
auto[1]	values[8]	valids[0x1]	1670	1			T31	3		T16	18		T48	17