Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3431495

1

T4

2490

T5

1

T7

11053

auto[1]

32601

1

T31

81

T42

274

T16

50

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

988442

1

T4

2490

T5

1

T7

11053

auto[1]

2475654

1

T31

4328

T42

4053

T16

20198

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	672737	1			T4	17		T5	1		T7	1033
auto[524288:1048575]	429585	1			T4	4		T7	1794		T8	157
auto[1048576:1572863]	388186	1			T7	3240		T8	291		T12	6
auto[1572864:2097151]	381833	1			T7	87		T8	198		T13	5
auto[2097152:2621439]	405802	1			T7	2653		T13	389		T31	2365
auto[2621440:3145727]	397971	1			T4	2		T7	1162		T13	400
auto[3145728:3670015]	393420	1			T7	22		T8	285		T13	5911
auto[3670016:4194303]	394562	1			T4	2467		T7	1062		T8	2

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2513669

1

T4

20

T5

1

T7

86

auto[1]

950427

1

T4

2470

T7

10967

T8

874

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2972141

1

T4

1225

T5

1

T7

11053

auto[1]

491955

1

T4

1265

T8

632

T15

26

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	187853	1			T4	2		T5	1		T7	1033
auto[0]	auto[0]	auto[0:524287]	auto[1]	397860	1			T42	256		T16	4154		T23	6
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	113461	1			T7	1794		T8	157		T12	120
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	247460	1			T31	1329		T16	337		T23	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	132618	1			T7	3240		T8	1		T12	6
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	187135	1			T16	132		T23	3356		T26	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	105437	1			T7	87		T8	144		T13	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	222135	1			T42	2795		T16	2184		T26	4003
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	99424	1			T7	2653		T13	389		T42	6
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	246038	1			T16	262		T23	5037		T24	256
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	116111	1			T4	2		T7	1162		T13	400
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	229173	1			T31	589		T16	3094		T23	3495
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	125998	1			T7	22		T13	5911		T31	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	207327	1			T31	3		T42	775		T16	2284
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	89556	1			T4	1221		T7	1062		T12	105
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	237654	1			T16	1777		T23	257		T17	10631
auto[0]	auto[1]	auto[0:524287]	auto[0]	3215	1			T4	15		T8	1		T15	5
auto[0]	auto[1]	auto[0:524287]	auto[1]	78502	1			T26	1		T18	21		T111	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1080	1			T4	4		T26	2		T48	10
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	63506	1			T26	1		T18	722		T111	448
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2526	1			T8	290		T16	2		T23	7
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	62357	1			T23	2467		T26	1361		T48	63
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	856	1			T8	54		T16	5		T23	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	49973	1			T16	4773		T40	82		T196	752
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	633	1			T31	2		T16	1		T23	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	55754	1			T31	2330		T23	4724		T26	29
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	623	1			T15	17		T16	2		T23	7
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	47821	1			T16	1170		T23	1489		T26	6499
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2242	1			T8	285		T42	2		T48	9
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	53881	1			T26	1005		T48	256		T68	256
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2829	1			T4	1246		T8	2		T15	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	60457	1			T26	512		T101	2813		T20	2778
auto[1]	auto[0]	auto[0:524287]	auto[0]	548	1			T42	5		T16	2		T23	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	4327	1			T16	7		T23	1		T18	7
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	408	1			T16	3		T23	1		T48	4
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2945	1			T16	7		T48	4		T17	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	397	1			T42	17		T23	2		T26	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2646	1			T23	2		T26	28		T17	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	429	1			T42	15		T48	17		T17	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2490	1			T42	227		T17	60		T53	17
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	417	1			T42	3		T16	6		T23	6
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2929	1			T16	7		T23	14		T26	26
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	389	1			T31	1		T16	2		T23	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3427	1			T31	13		T17	42		T53	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	401	1			T31	1		T42	2		T16	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3020	1			T31	33		T16	1		T26	10
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	352	1			T16	1		T23	1		T17	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1776	1			T17	1		T18	6		T111	2
auto[1]	auto[1]	auto[0:524287]	auto[0]	95	1			T26	1		T18	1		T111	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	337	1			T26	1		T18	3		T111	9
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	77	1			T26	1		T111	1		T196	6
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	648	1			T26	2		T111	2		T196	124
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	84	1			T23	1		T48	3		T17	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	423	1			T17	23		T60	52		T149	13
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	61	1			T16	4		T196	1		T32	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	452	1			T16	9		T196	15		T63	16
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	62	1			T31	2		T111	3		T35	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	545	1			T31	31		T111	4		T90	12
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	67	1			T23	2		T111	1		T88	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	360	1			T23	2		T218	25		T259	8
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	99	1			T48	3		T196	1		T101	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	452	1			T196	32		T101	73		T21	17
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	94	1			T42	5		T50	2		T60	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1844	1			T50	17		T60	14		T244	128

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2004348	1			T4	4		T5	1		T7	86
auto[0]	auto[0]	auto[1]	940892	1			T4	1221		T7	10967		T8	301
auto[0]	auto[1]	auto[0]	477481	1			T4	16		T8	59		T15	13
auto[0]	auto[1]	auto[1]	8774	1			T4	1249		T8	573		T15	13
auto[1]	auto[0]	auto[0]	26280	1			T31	48		T42	262		T16	37
auto[1]	auto[0]	auto[1]	621	1			T42	7		T26	3		T48	4
auto[1]	auto[1]	auto[0]	5560	1			T31	33		T42	4		T16	13
auto[1]	auto[1]	auto[1]	140	1			T42	1		T48	2		T17	1