Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2309364	1			T1	1		T2	1		T3	1
all_pins[1]	2309364	1			T1	1		T2	1		T3	1
all_pins[2]	2309364	1			T1	1		T2	1		T3	1
all_pins[3]	2309364	1			T1	1		T2	1		T3	1
all_pins[4]	2309364	1			T1	1		T2	1		T3	1
all_pins[5]	2309364	1			T1	1		T2	1		T3	1
all_pins[6]	2309364	1			T1	1		T2	1		T3	1
all_pins[7]	2309364	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18425405	1			T1	8		T2	8		T3	8
values[0x1]	49507	1			T16	448		T17	16		T18	770
transitions[0x0=>0x1]	48735	1			T16	233		T17	11		T18	770
transitions[0x1=>0x0]	48754	1			T16	233		T17	11		T18	770

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2308827	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	537	1			T16	224		T17	4		T18	1
all_pins[0]	transitions[0x0=>0x1]	227	1			T16	66		T17	4		T18	1
all_pins[0]	transitions[0x1=>0x0]	478	1			T16	3		T18	72		T19	8
all_pins[1]	values[0x0]	2308576	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	788	1			T16	161		T18	72		T19	13
all_pins[1]	transitions[0x0=>0x1]	606	1			T16	105		T18	72		T19	9
all_pins[1]	transitions[0x1=>0x0]	131	1			T16	2		T17	2		T19	3
all_pins[2]	values[0x0]	2309051	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	313	1			T16	58		T17	2		T19	7
all_pins[2]	transitions[0x0=>0x1]	272	1			T16	58		T17	1		T19	7
all_pins[2]	transitions[0x1=>0x0]	153	1			T16	1		T18	1		T19	4
all_pins[3]	values[0x0]	2309170	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	194	1			T16	1		T17	1		T18	1
all_pins[3]	transitions[0x0=>0x1]	151	1			T16	1		T17	1		T18	1
all_pins[3]	transitions[0x1=>0x0]	161	1			T16	2		T17	2		T19	10
all_pins[4]	values[0x0]	2309160	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	204	1			T16	2		T17	2		T19	10
all_pins[4]	transitions[0x0=>0x1]	161	1			T16	2		T17	1		T19	7
all_pins[4]	transitions[0x1=>0x0]	2027	1			T17	1		T18	695		T19	3
all_pins[5]	values[0x0]	2307294	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	2070	1			T17	2		T18	695		T19	6
all_pins[5]	transitions[0x0=>0x1]	2029	1			T17	1		T18	695		T19	4
all_pins[5]	transitions[0x1=>0x0]	45150	1			T17	1		T18	1		T19	10
all_pins[6]	values[0x0]	2264173	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	45191	1			T17	2		T18	1		T19	12
all_pins[6]	transitions[0x0=>0x1]	45146	1			T17	2		T18	1		T19	11
all_pins[6]	transitions[0x1=>0x0]	165	1			T16	2		T17	3		T19	2
all_pins[7]	values[0x0]	2309154	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	210	1			T16	2		T17	3		T19	3
all_pins[7]	transitions[0x0=>0x1]	143	1			T16	1		T17	1		T19	2
all_pins[7]	transitions[0x1=>0x0]	489	1			T16	223		T17	2		T18	1