Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19370

1

T4

4

T7

12

T8

12

auto[1]

13208

1

T5

10

T11

2

T49

12

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3751	1			T16	21		T40	27		T17	156
values[1]	3551	1			T5	10		T16	45		T23	53
values[2]	4547	1			T4	4		T7	12		T10	6
values[3]	4195	1			T8	12		T23	51		T26	40
values[4]	4684	1			T13	2		T15	12		T42	20
values[5]	4160	1			T42	20		T23	64		T26	23
values[6]	3680	1			T49	12		T42	20		T23	20
values[7]	4010	1			T16	40		T23	21		T24	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4236	1			T16	23		T23	21		T24	20
values[1]	3741	1			T42	20		T23	22		T26	23
values[2]	3391	1			T5	10		T16	21		T23	61
values[3]	3660	1			T4	4		T12	8		T14	10
values[4]	4254	1			T7	12		T10	6		T13	2
values[5]	4528	1			T11	2		T16	22		T17	20
values[6]	4387	1			T42	20		T16	20		T26	67
values[7]	4381	1			T8	12		T49	12		T42	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	406	1			T18	11		T224	10		T260	99
auto[0]	values[0]	values[1]	125	1			T244	10		T261	7		T246	14
auto[0]	values[0]	values[2]	178	1			T16	9		T17	13		T33	11
auto[0]	values[0]	values[3]	234	1			T103	9		T224	11		T233	13
auto[0]	values[0]	values[4]	427	1			T40	26		T17	96		T20	10
auto[0]	values[0]	values[5]	179	1			T101	12		T248	12		T229	10
auto[0]	values[0]	values[6]	244	1			T223	6		T101	9		T193	10
auto[0]	values[0]	values[7]	172	1			T227	8		T33	13		T208	4
auto[0]	values[1]	values[0]	273	1			T16	16		T23	8		T53	13
auto[0]	values[1]	values[1]	148	1			T53	13		T240	7		T262	10
auto[0]	values[1]	values[2]	272	1			T40	10		T101	14		T50	39
auto[0]	values[1]	values[3]	184	1			T23	25		T195	10		T194	9
auto[0]	values[1]	values[4]	373	1			T193	12		T195	18		T208	25
auto[0]	values[1]	values[5]	399	1			T16	11		T263	14		T179	12
auto[0]	values[1]	values[6]	190	1			T89	14		T264	8		T231	44
auto[0]	values[1]	values[7]	437	1			T173	4		T195	15		T89	14
auto[0]	values[2]	values[0]	222	1			T40	10		T101	5		T224	15
auto[0]	values[2]	values[1]	323	1			T23	16		T101	8		T20	25
auto[0]	values[2]	values[2]	214	1			T40	8		T148	13		T208	5
auto[0]	values[2]	values[3]	282	1			T4	4		T12	8		T14	10
auto[0]	values[2]	values[4]	464	1			T7	12		T10	6		T23	17
auto[0]	values[2]	values[5]	416	1			T243	14		T53	14		T265	4
auto[0]	values[2]	values[6]	535	1			T26	40		T50	22		T60	12
auto[0]	values[2]	values[7]	270	1			T194	9		T89	23		T256	32
auto[0]	values[3]	values[0]	348	1			T26	7		T17	9		T53	7
auto[0]	values[3]	values[1]	310	1			T266	18		T194	15		T267	6
auto[0]	values[3]	values[2]	279	1			T237	11		T268	2		T231	31
auto[0]	values[3]	values[3]	414	1			T23	23		T193	11		T50	62
auto[0]	values[3]	values[4]	180	1			T17	25		T20	19		T218	8
auto[0]	values[3]	values[5]	336	1			T269	2		T50	10		T270	9
auto[0]	values[3]	values[6]	519	1			T195	12		T218	22		T208	10
auto[0]	values[3]	values[7]	401	1			T8	12		T26	14		T60	12
auto[0]	values[4]	values[0]	297	1			T17	12		T20	38		T208	11
auto[0]	values[4]	values[1]	533	1			T26	15		T20	10		T232	10
auto[0]	values[4]	values[2]	262	1			T23	8		T148	12		T53	12
auto[0]	values[4]	values[3]	308	1			T15	12		T20	10		T258	23
auto[0]	values[4]	values[4]	295	1			T13	2		T224	12		T271	15
auto[0]	values[4]	values[5]	286	1			T101	12		T20	11		T271	8
auto[0]	values[4]	values[6]	277	1			T42	8		T16	10		T26	12
auto[0]	values[4]	values[7]	358	1			T53	31		T272	4		T101	15
auto[0]	values[5]	values[0]	207	1			T26	13		T273	18		T149	17
auto[0]	values[5]	values[1]	214	1			T53	12		T101	14		T224	11
auto[0]	values[5]	values[2]	230	1			T23	20		T53	9		T101	14
auto[0]	values[5]	values[3]	449	1			T17	13		T224	11		T60	63
auto[0]	values[5]	values[4]	533	1			T23	17		T220	12		T274	18
auto[0]	values[5]	values[5]	260	1			T251	10		T20	9		T50	11
auto[0]	values[5]	values[6]	308	1			T36	4		T142	12		T89	19
auto[0]	values[5]	values[7]	237	1			T42	15		T193	25		T224	9
auto[0]	values[6]	values[0]	327	1			T103	13		T149	47		T240	12
auto[0]	values[6]	values[1]	296	1			T42	7		T89	11		T244	13
auto[0]	values[6]	values[2]	249	1			T226	10		T275	6		T231	15
auto[0]	values[6]	values[3]	279	1			T103	12		T53	17		T149	12
auto[0]	values[6]	values[4]	189	1			T23	12		T53	21		T33	12
auto[0]	values[6]	values[5]	339	1			T17	8		T101	12		T20	9
auto[0]	values[6]	values[6]	306	1			T242	24		T89	6		T235	17
auto[0]	values[6]	values[7]	195	1			T17	50		T229	8		T240	7
auto[0]	values[7]	values[0]	254	1			T24	12		T89	14		T256	9
auto[0]	values[7]	values[1]	370	1			T17	15		T55	24		T208	8
auto[0]	values[7]	values[2]	237	1			T17	20		T258	9		T250	11
auto[0]	values[7]	values[3]	192	1			T55	16		T254	4		T195	21
auto[0]	values[7]	values[4]	278	1			T16	14		T149	14		T230	13
auto[0]	values[7]	values[5]	395	1			T20	18		T89	10		T229	10
auto[0]	values[7]	values[6]	202	1			T276	2		T277	6		T278	2
auto[0]	values[7]	values[7]	454	1			T16	16		T23	11		T248	12
auto[1]	values[0]	values[0]	338	1			T18	14		T224	10		T89	6
auto[1]	values[0]	values[1]	135	1			T244	10		T261	13		T279	7
auto[1]	values[0]	values[2]	148	1			T16	12		T17	32		T33	14
auto[1]	values[0]	values[3]	127	1			T103	11		T224	9		T233	7
auto[1]	values[0]	values[4]	234	1			T40	1		T17	15		T54	18
auto[1]	values[0]	values[5]	432	1			T101	8		T247	14		T248	104
auto[1]	values[0]	values[6]	240	1			T101	11		T193	10		T224	8
auto[1]	values[0]	values[7]	132	1			T33	12		T208	16		T271	15
auto[1]	values[1]	values[0]	233	1			T16	7		T23	13		T53	17
auto[1]	values[1]	values[1]	124	1			T53	16		T240	13		T80	18
auto[1]	values[1]	values[2]	142	1			T5	10		T40	10		T101	6
auto[1]	values[1]	values[3]	139	1			T23	7		T195	10		T194	18
auto[1]	values[1]	values[4]	251	1			T193	8		T195	37		T208	35
auto[1]	values[1]	values[5]	156	1			T16	11		T258	8		T194	7
auto[1]	values[1]	values[6]	87	1			T89	6		T231	10		T210	10
auto[1]	values[1]	values[7]	143	1			T195	5		T89	6		T240	12
auto[1]	values[2]	values[0]	217	1			T40	10		T101	15		T224	5
auto[1]	values[2]	values[1]	240	1			T23	6		T101	12		T20	15
auto[1]	values[2]	values[2]	137	1			T40	12		T148	7		T208	15
auto[1]	values[2]	values[3]	174	1			T26	50		T193	13		T218	12
auto[1]	values[2]	values[4]	154	1			T23	7		T208	7		T194	15
auto[1]	values[2]	values[5]	222	1			T11	2		T53	6		T101	9
auto[1]	values[2]	values[6]	280	1			T26	7		T50	6		T60	76
auto[1]	values[2]	values[7]	397	1			T194	11		T89	95		T280	12
auto[1]	values[3]	values[0]	128	1			T26	13		T17	16		T53	13
auto[1]	values[3]	values[1]	115	1			T194	8		T233	6		T149	14
auto[1]	values[3]	values[2]	190	1			T237	9		T231	22		T213	6
auto[1]	values[3]	values[3]	148	1			T23	28		T193	9		T50	11
auto[1]	values[3]	values[4]	168	1			T17	4		T20	2		T218	23
auto[1]	values[3]	values[5]	243	1			T50	10		T270	11		T213	32
auto[1]	values[3]	values[6]	251	1			T215	26		T195	16		T218	18
auto[1]	values[3]	values[7]	165	1			T26	6		T60	8		T222	8
auto[1]	values[4]	values[0]	425	1			T17	10		T20	19		T208	9
auto[1]	values[4]	values[1]	166	1			T26	8		T20	10		T50	10
auto[1]	values[4]	values[2]	282	1			T23	12		T148	8		T53	13
auto[1]	values[4]	values[3]	224	1			T281	18		T20	10		T258	6
auto[1]	values[4]	values[4]	162	1			T224	8		T271	5		T248	10
auto[1]	values[4]	values[5]	206	1			T101	8		T20	9		T271	12
auto[1]	values[4]	values[6]	381	1			T42	12		T16	10		T26	8
auto[1]	values[4]	values[7]	222	1			T53	9		T101	5		T33	16
auto[1]	values[5]	values[0]	149	1			T26	10		T228	24		T149	3
auto[1]	values[5]	values[1]	131	1			T53	30		T101	6		T224	9
auto[1]	values[5]	values[2]	232	1			T23	21		T53	11		T101	6
auto[1]	values[5]	values[3]	223	1			T17	10		T224	9		T60	6
auto[1]	values[5]	values[4]	214	1			T23	6		T220	12		T101	8
auto[1]	values[5]	values[5]	204	1			T20	11		T50	20		T222	8
auto[1]	values[5]	values[6]	238	1			T89	21		T244	18		T229	11
auto[1]	values[5]	values[7]	331	1			T42	5		T193	15		T224	11
auto[1]	values[6]	values[0]	211	1			T103	7		T149	4		T240	17
auto[1]	values[6]	values[1]	404	1			T42	13		T89	9		T244	7
auto[1]	values[6]	values[2]	88	1			T231	5		T250	9		T282	9
auto[1]	values[6]	values[3]	164	1			T103	8		T53	5		T149	8
auto[1]	values[6]	values[4]	114	1			T23	8		T53	2		T33	8
auto[1]	values[6]	values[5]	225	1			T17	12		T101	8		T20	14
auto[1]	values[6]	values[6]	155	1			T89	16		T235	5		T283	42
auto[1]	values[6]	values[7]	139	1			T49	12		T17	6		T229	12
auto[1]	values[7]	values[0]	201	1			T24	8		T39	24		T89	6
auto[1]	values[7]	values[1]	107	1			T17	5		T55	10		T208	12
auto[1]	values[7]	values[2]	251	1			T17	7		T258	41		T250	9
auto[1]	values[7]	values[3]	119	1			T55	8		T195	11		T248	13
auto[1]	values[7]	values[4]	218	1			T16	6		T149	6		T230	8
auto[1]	values[7]	values[5]	230	1			T257	10		T20	2		T89	10
auto[1]	values[7]	values[6]	174	1			T20	7		T244	9		T229	13
auto[1]	values[7]	values[7]	328	1			T16	4		T23	10		T248	8