Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	415	1			T7	8		T16	7		T23	2
auto[ReadAddrCrossIntoMailbox]	283	1			T16	5		T23	1		T17	6
auto[ReadAddrCrossOutOfMailbox]	298	1			T16	7		T26	1		T17	2
auto[ReadAddrCrossAllMailbox]	229	1			T16	1		T23	3		T17	4
auto[ReadAddrOutsideMailbox]	3809	1			T5	2		T10	4		T14	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2480

1

T5

1

T7

4

T10

2

auto[1]

2554

1

T5

1

T7

4

T10

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	897	1			T7	2		T14	2		T42	1
read_ops[0x0b]	798	1			T49	4		T42	6		T16	2
read_ops[0x3b]	824	1			T7	2		T42	3		T16	4
read_ops[0x6b]	834	1			T16	5		T23	11		T26	6
read_ops[0xbb]	813	1			T42	1		T16	5		T23	6
read_ops[0xeb]	868	1			T5	2		T7	4		T10	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T7	1		T16	2		T26	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T7	1		T193	1		T224	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T89	1		T261	1		T231	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T16	1		T17	1		T103	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T17	1		T20	2		T50	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T103	1		T53	1		T224	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T16	1		T193	1		T89	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T224	1		T194	1		T244	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	350	1			T14	1		T16	5		T23	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	336	1			T14	1		T42	1		T23	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T23	2		T33	1		T258	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T16	1		T24	1		T101	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T16	1		T17	1		T218	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T224	2		T195	2		T218	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T53	1		T33	1		T258	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T20	1		T89	2		T261	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T20	1		T208	1		T194	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T17	1		T224	1		T218	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	305	1			T49	2		T42	3		T23	5
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T49	2		T42	3		T26	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T7	1		T16	1		T142	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T7	1		T142	1		T179	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T17	2		T50	1		T89	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T20	1		T208	1		T60	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T16	1		T193	1		T20	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T16	1		T218	1		T273	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T224	1		T258	1		T149	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T208	1		T194	1		T256	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	318	1			T42	3		T16	1		T23	6
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	323	1			T23	6		T26	2		T39	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T16	1		T193	1		T224	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T26	1		T17	2		T20	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T16	1		T23	1		T149	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T224	1		T195	1		T218	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T16	1		T20	1		T224	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T17	1		T224	1		T218	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T23	1		T195	1		T208	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T53	1		T193	2		T20	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	306	1			T16	1		T23	7		T26	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	314	1			T16	1		T23	2		T26	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T53	1		T193	1		T244	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T16	1		T193	1		T20	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T101	1		T255	1		T284	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T17	1		T103	1		T193	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T16	3		T193	1		T218	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T193	1		T33	1		T271	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T23	2		T193	1		T89	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T17	2		T224	1		T33	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	303	1			T23	3		T40	1		T17	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	324	1			T42	1		T16	1		T23	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T7	2		T142	2		T179	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T7	2		T16	1		T142	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T17	1		T244	1		T149	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T16	2		T20	1		T224	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T101	1		T224	1		T195	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T16	1		T26	1		T193	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T17	1		T53	2		T224	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T194	1		T271	1		T244	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	299	1			T5	1		T10	2		T16	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	333	1			T5	1		T10	2		T42	2