Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4370	1			T16	21		T36	4		T40	60
values[1]	4917	1			T42	20		T16	23		T23	77
values[2]	4078	1			T7	12		T12	8		T42	20
values[3]	4321	1			T4	4		T8	12		T13	2
values[4]	3785	1			T5	10		T10	6		T16	20
values[5]	4061	1			T15	12		T16	20		T23	20
values[6]	3301	1			T11	2		T26	67		T223	6
values[7]	3745	1			T23	21		T17	25		T276	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3738	1			T16	20		T148	20		T242	24
values[1]	4412	1			T8	12		T49	12		T16	42
values[2]	4257	1			T7	12		T26	23		T17	20
values[3]	4398	1			T4	4		T5	10		T16	20
values[4]	4206	1			T11	2		T12	8		T15	12
values[5]	3653	1			T10	6		T42	20		T23	31
values[6]	3988	1			T14	10		T16	21		T23	40
values[7]	3926	1			T13	2		T42	40		T23	95

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31767

1

T4

4

T5

6

T7

12

auto[1]

811

1

T5

4

T49

2

T42

12

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	320	1			T195	20		T194	20		T285	10
auto[0]	values[0]	values[1]	786	1			T260	99		T271	18		T229	20
auto[0]	values[0]	values[2]	464	1			T17	19		T218	43		T89	19
auto[0]	values[0]	values[3]	681	1			T40	39		T269	2		T18	25
auto[0]	values[0]	values[4]	609	1			T17	45		T208	18		T244	18
auto[0]	values[0]	values[5]	327	1			T17	19		T224	20		T286	4
auto[0]	values[0]	values[6]	486	1			T16	18		T193	20		T236	12
auto[0]	values[0]	values[7]	598	1			T36	4		T40	17		T17	20
auto[0]	values[1]	values[0]	487	1			T215	26		T20	20		T287	18
auto[0]	values[1]	values[1]	435	1			T142	12		T263	14		T193	20
auto[0]	values[1]	values[2]	861	1			T20	21		T232	10		T50	31
auto[0]	values[1]	values[3]	514	1			T23	23		T26	20		T195	20
auto[0]	values[1]	values[4]	528	1			T16	23		T101	20		T224	20
auto[0]	values[1]	values[5]	601	1			T17	55		T281	18		T101	18
auto[0]	values[1]	values[6]	810	1			T24	20		T53	19		T20	20
auto[0]	values[1]	values[7]	563	1			T42	16		T23	54		T26	20
auto[0]	values[2]	values[0]	626	1			T193	16		T266	18		T218	39
auto[0]	values[2]	values[1]	478	1			T226	10		T244	20		T149	20
auto[0]	values[2]	values[2]	493	1			T7	12		T103	20		T179	12
auto[0]	values[2]	values[3]	349	1			T20	20		T244	19		T288	28
auto[0]	values[2]	values[4]	518	1			T12	8		T17	29		T272	4
auto[0]	values[2]	values[5]	516	1			T42	16		T53	21		T101	20
auto[0]	values[2]	values[6]	573	1			T23	19		T60	21		T271	20
auto[0]	values[2]	values[7]	418	1			T23	21		T231	39		T210	17
auto[0]	values[3]	values[0]	157	1			T271	19		T237	40		T166	36
auto[0]	values[3]	values[1]	467	1			T8	12		T49	10		T16	20
auto[0]	values[3]	values[2]	523	1			T101	20		T60	66		T89	98
auto[0]	values[3]	values[3]	910	1			T4	4		T16	20		T23	21
auto[0]	values[3]	values[4]	638	1			T243	14		T101	20		T224	20
auto[0]	values[3]	values[5]	439	1			T23	31		T149	20		T237	20
auto[0]	values[3]	values[6]	490	1			T14	10		T23	20		T26	60
auto[0]	values[3]	values[7]	604	1			T13	2		T42	16		T53	29
auto[0]	values[4]	values[0]	596	1			T242	24		T101	16		T60	20
auto[0]	values[4]	values[1]	736	1			T16	19		T23	22		T193	85
auto[0]	values[4]	values[2]	408	1			T26	22		T224	20		T271	18
auto[0]	values[4]	values[3]	317	1			T5	6		T193	20		T89	19
auto[0]	values[4]	values[4]	443	1			T20	20		T273	18		T149	20
auto[0]	values[4]	values[5]	447	1			T10	6		T244	20		T289	20
auto[0]	values[4]	values[6]	308	1			T17	26		T103	20		T53	20
auto[0]	values[4]	values[7]	440	1			T23	20		T101	20		T224	20
auto[0]	values[5]	values[0]	498	1			T16	19		T148	20		T280	12
auto[0]	values[5]	values[1]	708	1			T23	20		T17	23		T50	73
auto[0]	values[5]	values[2]	451	1			T257	10		T53	38		T251	10
auto[0]	values[5]	values[3]	498	1			T17	88		T247	10		T59	8
auto[0]	values[5]	values[4]	432	1			T15	12		T227	8		T53	22
auto[0]	values[5]	values[5]	418	1			T53	42		T101	17		T193	18
auto[0]	values[5]	values[6]	441	1			T39	24		T101	20		T208	17
auto[0]	values[5]	values[7]	505	1			T26	23		T278	2		T244	20
auto[0]	values[6]	values[0]	493	1			T195	33		T194	22		T229	20
auto[0]	values[6]	values[1]	362	1			T26	47		T277	6		T20	17
auto[0]	values[6]	values[2]	493	1			T223	6		T241	20		T50	31
auto[0]	values[6]	values[3]	413	1			T220	24		T89	20		T229	25
auto[0]	values[6]	values[4]	470	1			T11	2		T20	19		T195	30
auto[0]	values[6]	values[5]	188	1			T101	18		T20	20		T290	2
auto[0]	values[6]	values[6]	423	1			T195	19		T60	17		T194	41
auto[0]	values[6]	values[7]	371	1			T26	20		T53	20		T50	27
auto[0]	values[7]	values[0]	470	1			T55	33		T195	20		T258	22
auto[0]	values[7]	values[1]	341	1			T248	19		T240	47		T291	43
auto[0]	values[7]	values[2]	468	1			T55	22		T274	18		T261	19
auto[0]	values[7]	values[3]	630	1			T101	20		T256	42		T230	21
auto[0]	values[7]	values[4]	440	1			T23	19		T276	2		T148	20
auto[0]	values[7]	values[5]	606	1			T193	18		T50	20		T224	19
auto[0]	values[7]	values[6]	355	1			T17	25		T101	20		T292	22
auto[0]	values[7]	values[7]	329	1			T103	20		T148	20		T20	26
auto[1]	values[0]	values[0]	8	1			T58	4		T293	3		T294	1
auto[1]	values[0]	values[1]	20	1			T271	2		T295	4		T296	2
auto[1]	values[0]	values[2]	10	1			T17	1		T218	4		T89	1
auto[1]	values[0]	values[3]	12	1			T40	1		T224	2		T33	1
auto[1]	values[0]	values[4]	17	1			T208	2		T244	2		T213	1
auto[1]	values[0]	values[5]	10	1			T17	1		T270	1		T284	4
auto[1]	values[0]	values[6]	11	1			T16	3		T297	1		T298	3
auto[1]	values[0]	values[7]	11	1			T40	3		T195	2		T208	3
auto[1]	values[1]	values[0]	16	1			T229	2		T221	3		T210	5
auto[1]	values[1]	values[1]	12	1			T20	1		T60	1		T261	1
auto[1]	values[1]	values[2]	16	1			T20	3		T50	1		T250	1
auto[1]	values[1]	values[3]	11	1			T237	3		T299	1		T169	2
auto[1]	values[1]	values[4]	15	1			T208	1		T248	1		T233	1
auto[1]	values[1]	values[5]	17	1			T17	1		T101	2		T208	2
auto[1]	values[1]	values[6]	18	1			T53	1		T208	2		T149	1
auto[1]	values[1]	values[7]	13	1			T42	4		T17	1		T60	1
auto[1]	values[2]	values[0]	17	1			T193	4		T218	1		T89	1
auto[1]	values[2]	values[1]	1	1			T58	1		-	-		-	-
auto[1]	values[2]	values[2]	13	1			T258	3		T244	3		T237	1
auto[1]	values[2]	values[3]	9	1			T244	1		T288	3		T300	1
auto[1]	values[2]	values[4]	17	1			T149	5		T58	1		T279	1
auto[1]	values[2]	values[5]	20	1			T42	4		T53	1		T33	1
auto[1]	values[2]	values[6]	18	1			T23	1		T60	1		T221	1
auto[1]	values[2]	values[7]	12	1			T231	2		T210	3		T284	3
auto[1]	values[3]	values[0]	4	1			T271	1		T166	3		-	-
auto[1]	values[3]	values[1]	19	1			T49	2		T16	2		T240	4
auto[1]	values[3]	values[2]	9	1			T60	3		T210	2		T245	2
auto[1]	values[3]	values[3]	12	1			T218	2		T60	1		T230	3
auto[1]	values[3]	values[4]	15	1			T218	2		T244	1		T231	3
auto[1]	values[3]	values[5]	9	1			T231	1		T166	1		T301	1
auto[1]	values[3]	values[6]	8	1			T228	2		T210	1		T255	2
auto[1]	values[3]	values[7]	17	1			T42	4		T53	1		T222	1
auto[1]	values[4]	values[0]	12	1			T101	4		T270	2		T216	1
auto[1]	values[4]	values[1]	17	1			T16	1		T23	2		T193	1
auto[1]	values[4]	values[2]	18	1			T26	1		T271	2		T149	2
auto[1]	values[4]	values[3]	8	1			T5	4		T89	1		T302	3
auto[1]	values[4]	values[4]	5	1			T256	1		T240	2		T303	2
auto[1]	values[4]	values[5]	7	1			T250	3		T288	2		T302	1
auto[1]	values[4]	values[6]	11	1			T17	1		T271	3		T89	1
auto[1]	values[4]	values[7]	12	1			T237	2		T231	2		T282	3
auto[1]	values[5]	values[0]	8	1			T16	1		T237	1		T231	2
auto[1]	values[5]	values[1]	8	1			T225	2		T304	4		T305	2
auto[1]	values[5]	values[2]	18	1			T53	2		T218	5		T248	1
auto[1]	values[5]	values[3]	13	1			T17	3		T247	4		T60	2
auto[1]	values[5]	values[4]	18	1			T53	3		T54	2		T101	1
auto[1]	values[5]	values[5]	17	1			T101	3		T193	2		T258	1
auto[1]	values[5]	values[6]	11	1			T208	3		T149	2		T256	2
auto[1]	values[5]	values[7]	17	1			T250	3		T282	1		T166	3
auto[1]	values[6]	values[0]	10	1			T195	2		T194	1		T306	1
auto[1]	values[6]	values[1]	16	1			T20	3		T50	3		T229	1
auto[1]	values[6]	values[2]	3	1			T89	1		T240	1		T255	1
auto[1]	values[6]	values[3]	9	1			T166	1		T279	1		T217	2
auto[1]	values[6]	values[4]	23	1			T20	1		T195	2		T89	2
auto[1]	values[6]	values[5]	4	1			T101	2		T297	2		-	-
auto[1]	values[6]	values[6]	13	1			T195	1		T60	3		T221	1
auto[1]	values[6]	values[7]	10	1			T50	1		T149	2		T307	6
auto[1]	values[7]	values[0]	16	1			T55	1		T218	1		T208	3
auto[1]	values[7]	values[1]	6	1			T248	1		T240	2		T308	2
auto[1]	values[7]	values[2]	9	1			T55	2		T261	1		T217	1
auto[1]	values[7]	values[3]	12	1			T256	2		T166	1		T309	2
auto[1]	values[7]	values[4]	18	1			T23	2		T53	2		T222	5
auto[1]	values[7]	values[5]	27	1			T193	2		T224	1		T33	2
auto[1]	values[7]	values[6]	12	1			T213	3		T283	4		T303	2
auto[1]	values[7]	values[7]	6	1			T89	1		T244	1		T302	1