Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1682

1

T1

8

T2

3

T3

6

auto[1]

1735

1

T1

12

T2

1

T3

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1897

1

T30

28

T16

35

T23

5

auto[1]

1520

1

T1

20

T2

4

T3

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2655

1

T1

20

T2

4

T3

9

auto[1]

762

1

T30

13

T16

17

T23

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	701	1			T1	3		T2	1		T3	2
valid[1]	693	1			T1	4		T2	2		T3	3
valid[2]	706	1			T1	4		T3	1		T6	1
valid[3]	660	1			T1	4		T2	1		T6	1
valid[4]	657	1			T1	5		T3	3		T9	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	127	1			T30	2		T16	2		T26	1
auto[0]	auto[0]	valid[0]	auto[1]	149	1			T1	1		T2	1		T3	1
auto[0]	auto[0]	valid[1]	auto[0]	134	1			T16	4		T40	2		T68	1
auto[0]	auto[0]	valid[1]	auto[1]	161	1			T1	3		T2	2		T3	3
auto[0]	auto[0]	valid[2]	auto[0]	101	1			T30	3		T16	2		T23	1
auto[0]	auto[0]	valid[2]	auto[1]	136	1			T1	2		T3	1		T6	1
auto[0]	auto[0]	valid[3]	auto[0]	95	1			T30	2		T16	3		T40	1
auto[0]	auto[0]	valid[3]	auto[1]	148	1			T1	1		T6	1		T9	3
auto[0]	auto[0]	valid[4]	auto[0]	115	1			T30	1		T16	1		T37	2
auto[0]	auto[0]	valid[4]	auto[1]	131	1			T1	1		T3	1		T9	3
auto[0]	auto[1]	valid[0]	auto[0]	108	1			T40	2		T68	1		T97	2
auto[0]	auto[1]	valid[0]	auto[1]	170	1			T1	2		T3	1		T6	1
auto[0]	auto[1]	valid[1]	auto[0]	103	1			T30	2		T23	1		T37	1
auto[0]	auto[1]	valid[1]	auto[1]	156	1			T1	1		T9	2		T16	1
auto[0]	auto[1]	valid[2]	auto[0]	132	1			T30	4		T16	3		T23	1
auto[0]	auto[1]	valid[2]	auto[1]	171	1			T1	2		T9	1		T22	1
auto[0]	auto[1]	valid[3]	auto[0]	108	1			T18	2		T111	2		T143	2
auto[0]	auto[1]	valid[3]	auto[1]	147	1			T1	3		T2	1		T16	1
auto[0]	auto[1]	valid[4]	auto[0]	112	1			T30	1		T16	3		T40	2
auto[0]	auto[1]	valid[4]	auto[1]	151	1			T1	4		T3	2		T22	1
auto[1]	auto[0]	valid[0]	auto[0]	65	1			T30	2		T16	4		T23	1
auto[1]	auto[0]	valid[1]	auto[0]	79	1			T30	2		T16	2		T23	1
auto[1]	auto[0]	valid[2]	auto[0]	79	1			T16	1		T37	1		T97	1
auto[1]	auto[0]	valid[3]	auto[0]	82	1			T30	2		T16	2		T111	1
auto[1]	auto[0]	valid[4]	auto[0]	80	1			T16	1		T26	1		T40	1
auto[1]	auto[1]	valid[0]	auto[0]	82	1			T16	3		T40	1		T111	1
auto[1]	auto[1]	valid[1]	auto[0]	60	1			T16	2		T111	1		T177	1
auto[1]	auto[1]	valid[2]	auto[0]	87	1			T30	2		T16	2		T40	2
auto[1]	auto[1]	valid[3]	auto[0]	80	1			T30	3		T68	1		T97	1
auto[1]	auto[1]	valid[4]	auto[0]	68	1			T30	2		T37	1		T97	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal