Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47361

1

T27

13

T29

4

T30

600

auto[1]

16327

1

T1

251

T2

4

T3

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46352

1

T1

251

T2

4

T3

9

auto[1]

17336

1

T27

5

T29

1

T30

188

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32830	1			T1	140		T2	4		T3	9
others[1]	5345	1			T1	26		T9	27		T30	38
others[2]	5437	1			T1	19		T9	27		T27	2
others[3]	6045	1			T1	19		T9	40		T30	56
interest[1]	3572	1			T1	10		T9	18		T27	1
interest[4]	21502	1			T1	81		T2	4		T3	9
interest[64]	10459	1			T1	37		T9	49		T27	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15435	1			T27	6		T29	3		T30	224
auto[0]	auto[0]	others[1]	2555	1			T30	27		T31	3		T16	37
auto[0]	auto[0]	others[2]	2567	1			T27	1		T30	37		T31	1
auto[0]	auto[0]	others[3]	2872	1			T30	37		T31	2		T16	61
auto[0]	auto[0]	interest[1]	1658	1			T27	1		T30	24		T16	25
auto[0]	auto[0]	interest[4]	10066	1			T27	3		T29	1		T30	149
auto[0]	auto[0]	interest[64]	4938	1			T30	63		T31	2		T16	84
auto[0]	auto[1]	others[0]	8686	1			T1	140		T2	4		T3	9
auto[0]	auto[1]	others[1]	1307	1			T1	26		T9	27		T16	6
auto[0]	auto[1]	others[2]	1322	1			T1	19		T9	27		T16	2
auto[0]	auto[1]	others[3]	1474	1			T1	19		T9	40		T16	9
auto[0]	auto[1]	interest[1]	912	1			T1	10		T9	18		T16	6
auto[0]	auto[1]	interest[4]	5804	1			T1	81		T2	4		T3	9
auto[0]	auto[1]	interest[64]	2626	1			T1	37		T9	49		T16	14
auto[1]	auto[0]	others[0]	8709	1			T27	3		T29	1		T30	90
auto[1]	auto[0]	others[1]	1483	1			T30	11		T16	30		T23	5
auto[1]	auto[0]	others[2]	1548	1			T27	1		T30	22		T31	1
auto[1]	auto[0]	others[3]	1699	1			T30	19		T16	23		T23	12
auto[1]	auto[0]	interest[1]	1002	1			T30	14		T31	2		T16	14
auto[1]	auto[0]	interest[4]	5632	1			T27	2		T30	57		T16	86
auto[1]	auto[0]	interest[64]	2895	1			T27	1		T30	32		T31	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal