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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.08 98.62 89.36 97.28 95.43 99.21


Total test records in report: 1151
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T119 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1816744413 Aug 12 05:34:56 PM PDT 24 Aug 12 05:34:59 PM PDT 24 398581994 ps
T109 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1563517708 Aug 12 05:35:24 PM PDT 24 Aug 12 05:35:45 PM PDT 24 838707260 ps
T1046 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.475168088 Aug 12 05:35:29 PM PDT 24 Aug 12 05:35:30 PM PDT 24 11824665 ps
T1047 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.153444416 Aug 12 05:34:52 PM PDT 24 Aug 12 05:34:53 PM PDT 24 99861950 ps
T155 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1298782505 Aug 12 05:35:22 PM PDT 24 Aug 12 05:35:23 PM PDT 24 90714674 ps
T1048 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2068796452 Aug 12 05:35:24 PM PDT 24 Aug 12 05:35:28 PM PDT 24 64474636 ps
T110 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1922152701 Aug 12 05:34:53 PM PDT 24 Aug 12 05:35:01 PM PDT 24 69167144 ps
T129 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4146087687 Aug 12 05:35:15 PM PDT 24 Aug 12 05:35:32 PM PDT 24 2222749337 ps
T1049 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3176111057 Aug 12 05:35:32 PM PDT 24 Aug 12 05:35:33 PM PDT 24 55397274 ps
T130 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3690909048 Aug 12 05:35:20 PM PDT 24 Aug 12 05:35:22 PM PDT 24 125642651 ps
T1050 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4236679176 Aug 12 05:34:47 PM PDT 24 Aug 12 05:34:49 PM PDT 24 205123091 ps
T131 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2574605661 Aug 12 05:35:27 PM PDT 24 Aug 12 05:35:29 PM PDT 24 52382559 ps
T1051 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.413164716 Aug 12 05:35:11 PM PDT 24 Aug 12 05:35:12 PM PDT 24 54650207 ps
T1052 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2163119886 Aug 12 05:35:54 PM PDT 24 Aug 12 05:35:55 PM PDT 24 14456559 ps
T126 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.219609733 Aug 12 05:35:19 PM PDT 24 Aug 12 05:35:26 PM PDT 24 216189585 ps
T125 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3316352995 Aug 12 05:35:17 PM PDT 24 Aug 12 05:35:20 PM PDT 24 50848293 ps
T1053 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1779196771 Aug 12 05:35:32 PM PDT 24 Aug 12 05:35:32 PM PDT 24 19244906 ps
T112 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3554880400 Aug 12 05:35:06 PM PDT 24 Aug 12 05:35:10 PM PDT 24 465807293 ps
T1054 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2181344039 Aug 12 05:35:26 PM PDT 24 Aug 12 05:35:27 PM PDT 24 12241105 ps
T1055 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.318815413 Aug 12 05:35:31 PM PDT 24 Aug 12 05:35:34 PM PDT 24 105607671 ps
T205 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2509195499 Aug 12 05:35:03 PM PDT 24 Aug 12 05:35:09 PM PDT 24 104637605 ps
T1056 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3435002138 Aug 12 05:35:16 PM PDT 24 Aug 12 05:35:19 PM PDT 24 46566163 ps
T1057 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4183450486 Aug 12 05:35:25 PM PDT 24 Aug 12 05:35:26 PM PDT 24 72147288 ps
T113 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2151766908 Aug 12 05:35:15 PM PDT 24 Aug 12 05:35:21 PM PDT 24 258779439 ps
T1058 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4168101500 Aug 12 05:35:25 PM PDT 24 Aug 12 05:35:25 PM PDT 24 42383851 ps
T120 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2767615150 Aug 12 05:35:13 PM PDT 24 Aug 12 05:35:15 PM PDT 24 106276306 ps
T1059 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1015177555 Aug 12 05:35:42 PM PDT 24 Aug 12 05:35:44 PM PDT 24 105339528 ps
T1060 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.946469601 Aug 12 05:34:49 PM PDT 24 Aug 12 05:35:26 PM PDT 24 1882630233 ps
T1061 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.363523985 Aug 12 05:35:18 PM PDT 24 Aug 12 05:35:18 PM PDT 24 14841493 ps
T132 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3750584833 Aug 12 05:35:06 PM PDT 24 Aug 12 05:35:08 PM PDT 24 37777190 ps
T162 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4191332160 Aug 12 05:35:26 PM PDT 24 Aug 12 05:35:30 PM PDT 24 576504204 ps
T133 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3872471400 Aug 12 05:35:02 PM PDT 24 Aug 12 05:35:14 PM PDT 24 754813004 ps
T1062 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1533352476 Aug 12 05:35:18 PM PDT 24 Aug 12 05:35:19 PM PDT 24 34283794 ps
T1063 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2355708438 Aug 12 05:34:51 PM PDT 24 Aug 12 05:35:14 PM PDT 24 1588692097 ps
T163 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.975774484 Aug 12 05:35:22 PM PDT 24 Aug 12 05:35:26 PM PDT 24 183263692 ps
T134 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4111100529 Aug 12 05:35:26 PM PDT 24 Aug 12 05:35:41 PM PDT 24 719047260 ps
T1064 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.996473238 Aug 12 05:36:02 PM PDT 24 Aug 12 05:36:03 PM PDT 24 24173496 ps
T1065 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3714249506 Aug 12 05:35:45 PM PDT 24 Aug 12 05:35:46 PM PDT 24 56571909 ps
T135 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2190772071 Aug 12 05:35:17 PM PDT 24 Aug 12 05:35:19 PM PDT 24 280722505 ps
T164 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.70663399 Aug 12 05:34:54 PM PDT 24 Aug 12 05:34:57 PM PDT 24 419783699 ps
T1066 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3782967813 Aug 12 05:35:25 PM PDT 24 Aug 12 05:35:26 PM PDT 24 78963604 ps
T1067 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1297473316 Aug 12 05:35:27 PM PDT 24 Aug 12 05:35:28 PM PDT 24 56641898 ps
T1068 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4082865770 Aug 12 05:35:28 PM PDT 24 Aug 12 05:35:28 PM PDT 24 58666779 ps
T1069 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1865792807 Aug 12 05:35:44 PM PDT 24 Aug 12 05:35:45 PM PDT 24 53313086 ps
T136 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2179747161 Aug 12 05:35:52 PM PDT 24 Aug 12 05:35:54 PM PDT 24 31822530 ps
T1070 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2752727856 Aug 12 05:35:26 PM PDT 24 Aug 12 05:35:28 PM PDT 24 94153327 ps
T1071 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.927346724 Aug 12 05:35:15 PM PDT 24 Aug 12 05:35:18 PM PDT 24 204260340 ps
T199 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1295419828 Aug 12 05:35:35 PM PDT 24 Aug 12 05:35:50 PM PDT 24 2651688430 ps
T137 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3480421052 Aug 12 05:35:21 PM PDT 24 Aug 12 05:35:23 PM PDT 24 562219715 ps
T114 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2601425301 Aug 12 05:35:13 PM PDT 24 Aug 12 05:35:22 PM PDT 24 562300168 ps
T1072 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.174839153 Aug 12 05:35:08 PM PDT 24 Aug 12 05:35:09 PM PDT 24 25033676 ps
T138 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2263205207 Aug 12 05:35:14 PM PDT 24 Aug 12 05:35:26 PM PDT 24 188701860 ps
T200 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2834678130 Aug 12 05:35:30 PM PDT 24 Aug 12 05:35:44 PM PDT 24 1338595153 ps
T1073 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.349467505 Aug 12 05:35:26 PM PDT 24 Aug 12 05:35:30 PM PDT 24 270412761 ps
T1074 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.26979743 Aug 12 05:35:33 PM PDT 24 Aug 12 05:35:33 PM PDT 24 12857570 ps
T115 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1897522427 Aug 12 05:35:28 PM PDT 24 Aug 12 05:35:33 PM PDT 24 323297934 ps
T1075 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.547701638 Aug 12 05:35:17 PM PDT 24 Aug 12 05:35:20 PM PDT 24 668393696 ps
T116 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4279539006 Aug 12 05:35:33 PM PDT 24 Aug 12 05:35:39 PM PDT 24 241803091 ps
T1076 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2324409354 Aug 12 05:35:26 PM PDT 24 Aug 12 05:35:27 PM PDT 24 13783756 ps
T203 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1740217649 Aug 12 05:34:53 PM PDT 24 Aug 12 05:35:00 PM PDT 24 223414441 ps
T117 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3026279981 Aug 12 05:35:16 PM PDT 24 Aug 12 05:35:18 PM PDT 24 99451853 ps
T1077 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3420379729 Aug 12 05:35:39 PM PDT 24 Aug 12 05:35:41 PM PDT 24 68626378 ps
T1078 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3405368121 Aug 12 05:35:20 PM PDT 24 Aug 12 05:35:22 PM PDT 24 47364086 ps
T1079 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3563371155 Aug 12 05:35:23 PM PDT 24 Aug 12 05:35:30 PM PDT 24 67585833 ps
T1080 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3305360811 Aug 12 05:35:01 PM PDT 24 Aug 12 05:35:02 PM PDT 24 11911258 ps
T93 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1026060047 Aug 12 05:35:09 PM PDT 24 Aug 12 05:35:11 PM PDT 24 99297298 ps
T1081 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2332796420 Aug 12 05:35:00 PM PDT 24 Aug 12 05:35:07 PM PDT 24 255255322 ps
T94 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.93762817 Aug 12 05:35:01 PM PDT 24 Aug 12 05:35:02 PM PDT 24 22930744 ps
T1082 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2838959114 Aug 12 05:35:37 PM PDT 24 Aug 12 05:35:38 PM PDT 24 52626170 ps
T1083 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3795457816 Aug 12 05:35:12 PM PDT 24 Aug 12 05:35:15 PM PDT 24 41569953 ps
T1084 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2094226266 Aug 12 05:35:26 PM PDT 24 Aug 12 05:35:26 PM PDT 24 111518146 ps
T1085 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1145919834 Aug 12 05:35:08 PM PDT 24 Aug 12 05:35:10 PM PDT 24 61442678 ps
T1086 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1010783977 Aug 12 05:35:25 PM PDT 24 Aug 12 05:35:25 PM PDT 24 31271965 ps
T1087 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.298436480 Aug 12 05:35:06 PM PDT 24 Aug 12 05:35:08 PM PDT 24 58251929 ps
T121 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2815086499 Aug 12 05:35:08 PM PDT 24 Aug 12 05:35:11 PM PDT 24 1410736370 ps
T201 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1943577294 Aug 12 05:35:11 PM PDT 24 Aug 12 05:35:33 PM PDT 24 9178239484 ps
T1088 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2079834582 Aug 12 05:35:15 PM PDT 24 Aug 12 05:35:17 PM PDT 24 65185893 ps
T1089 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4146227516 Aug 12 05:35:17 PM PDT 24 Aug 12 05:35:18 PM PDT 24 14382284 ps
T139 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4062841723 Aug 12 05:35:18 PM PDT 24 Aug 12 05:35:34 PM PDT 24 12431745639 ps
T140 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1433974845 Aug 12 05:35:08 PM PDT 24 Aug 12 05:35:10 PM PDT 24 39856697 ps
T204 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2274599522 Aug 12 05:34:51 PM PDT 24 Aug 12 05:35:10 PM PDT 24 551645420 ps
T1090 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2395957485 Aug 12 05:35:24 PM PDT 24 Aug 12 05:35:37 PM PDT 24 809801730 ps
T1091 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2156135056 Aug 12 05:35:31 PM PDT 24 Aug 12 05:35:34 PM PDT 24 511544239 ps
T1092 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1796875008 Aug 12 05:35:02 PM PDT 24 Aug 12 05:35:06 PM PDT 24 611242054 ps
T1093 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1308559220 Aug 12 05:35:20 PM PDT 24 Aug 12 05:35:21 PM PDT 24 22612389 ps
T202 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1499292003 Aug 12 05:35:05 PM PDT 24 Aug 12 05:35:16 PM PDT 24 741869170 ps
T141 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.473433859 Aug 12 05:35:13 PM PDT 24 Aug 12 05:35:15 PM PDT 24 36578982 ps
T1094 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3916582825 Aug 12 05:34:52 PM PDT 24 Aug 12 05:34:53 PM PDT 24 14153624 ps
T1095 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2046241867 Aug 12 05:34:54 PM PDT 24 Aug 12 05:34:58 PM PDT 24 236404372 ps
T1096 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2447040502 Aug 12 05:35:58 PM PDT 24 Aug 12 05:35:58 PM PDT 24 14816407 ps
T1097 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1069987062 Aug 12 05:35:24 PM PDT 24 Aug 12 05:35:25 PM PDT 24 11534486 ps
T1098 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3298036627 Aug 12 05:35:27 PM PDT 24 Aug 12 05:35:28 PM PDT 24 14969897 ps
T1099 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2508967519 Aug 12 05:34:54 PM PDT 24 Aug 12 05:34:56 PM PDT 24 39146423 ps
T1100 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2956619968 Aug 12 05:35:26 PM PDT 24 Aug 12 05:35:27 PM PDT 24 83512587 ps
T95 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2525279190 Aug 12 05:35:20 PM PDT 24 Aug 12 05:35:21 PM PDT 24 74286433 ps
T1101 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.322225985 Aug 12 05:35:42 PM PDT 24 Aug 12 05:35:43 PM PDT 24 31933920 ps
T1102 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.304874775 Aug 12 05:35:46 PM PDT 24 Aug 12 05:35:48 PM PDT 24 286218058 ps
T1103 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.366227076 Aug 12 05:35:15 PM PDT 24 Aug 12 05:35:17 PM PDT 24 130893311 ps
T1104 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2954021383 Aug 12 05:35:18 PM PDT 24 Aug 12 05:35:20 PM PDT 24 164058016 ps
T1105 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1657344130 Aug 12 05:35:24 PM PDT 24 Aug 12 05:35:25 PM PDT 24 91233231 ps
T1106 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4085000245 Aug 12 05:35:01 PM PDT 24 Aug 12 05:35:23 PM PDT 24 9017583113 ps
T1107 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2414059961 Aug 12 05:35:06 PM PDT 24 Aug 12 05:35:08 PM PDT 24 215840130 ps
T1108 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3714048489 Aug 12 05:35:49 PM PDT 24 Aug 12 05:35:50 PM PDT 24 66315700 ps
T96 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.165511054 Aug 12 05:35:04 PM PDT 24 Aug 12 05:35:05 PM PDT 24 81131862 ps
T1109 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3195462900 Aug 12 05:35:16 PM PDT 24 Aug 12 05:35:19 PM PDT 24 135067606 ps
T1110 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2505033121 Aug 12 05:35:12 PM PDT 24 Aug 12 05:35:16 PM PDT 24 304037423 ps
T1111 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2064945603 Aug 12 05:35:07 PM PDT 24 Aug 12 05:35:18 PM PDT 24 979318463 ps
T1112 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3098911520 Aug 12 05:35:15 PM PDT 24 Aug 12 05:35:16 PM PDT 24 19380652 ps
T1113 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3318159189 Aug 12 05:35:35 PM PDT 24 Aug 12 05:35:35 PM PDT 24 61044716 ps
T1114 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2078481492 Aug 12 05:35:41 PM PDT 24 Aug 12 05:35:42 PM PDT 24 96993141 ps
T118 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2764718693 Aug 12 05:35:23 PM PDT 24 Aug 12 05:35:26 PM PDT 24 1432900612 ps
T1115 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1260917918 Aug 12 05:35:26 PM PDT 24 Aug 12 05:35:26 PM PDT 24 14389509 ps
T1116 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1474109167 Aug 12 05:35:16 PM PDT 24 Aug 12 05:35:19 PM PDT 24 94479688 ps
T1117 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1853734461 Aug 12 05:35:25 PM PDT 24 Aug 12 05:35:26 PM PDT 24 27098765 ps
T1118 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1330344264 Aug 12 05:35:05 PM PDT 24 Aug 12 05:35:06 PM PDT 24 649350281 ps
T1119 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.286968276 Aug 12 05:35:14 PM PDT 24 Aug 12 05:35:17 PM PDT 24 53353775 ps
T206 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.548782306 Aug 12 05:35:14 PM PDT 24 Aug 12 05:35:26 PM PDT 24 564472580 ps
T1120 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.973357817 Aug 12 05:35:30 PM PDT 24 Aug 12 05:35:32 PM PDT 24 28490607 ps
T1121 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2150733735 Aug 12 05:35:05 PM PDT 24 Aug 12 05:35:08 PM PDT 24 406441540 ps
T198 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.353312259 Aug 12 05:34:59 PM PDT 24 Aug 12 05:35:04 PM PDT 24 297860592 ps
T1122 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.4054654545 Aug 12 05:35:04 PM PDT 24 Aug 12 05:35:09 PM PDT 24 144346937 ps
T1123 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3548954142 Aug 12 05:35:24 PM PDT 24 Aug 12 05:35:24 PM PDT 24 38686321 ps
T1124 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2705120289 Aug 12 05:35:13 PM PDT 24 Aug 12 05:35:16 PM PDT 24 118502645 ps
T1125 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2675063082 Aug 12 05:35:19 PM PDT 24 Aug 12 05:35:21 PM PDT 24 28462078 ps
T1126 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1187526960 Aug 12 05:35:26 PM PDT 24 Aug 12 05:35:27 PM PDT 24 33488249 ps
T1127 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3289440421 Aug 12 05:35:01 PM PDT 24 Aug 12 05:35:04 PM PDT 24 75818335 ps
T1128 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.693798556 Aug 12 05:35:27 PM PDT 24 Aug 12 05:35:29 PM PDT 24 33283596 ps
T1129 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2355412692 Aug 12 05:35:01 PM PDT 24 Aug 12 05:35:15 PM PDT 24 1222619027 ps
T1130 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1985103686 Aug 12 05:35:44 PM PDT 24 Aug 12 05:35:48 PM PDT 24 571936387 ps
T1131 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1541897331 Aug 12 05:35:14 PM PDT 24 Aug 12 05:35:18 PM PDT 24 76466616 ps
T207 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.208058608 Aug 12 05:35:29 PM PDT 24 Aug 12 05:35:44 PM PDT 24 665605419 ps
T1132 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2801257136 Aug 12 05:35:19 PM PDT 24 Aug 12 05:35:20 PM PDT 24 13731452 ps
T1133 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.121836323 Aug 12 05:34:57 PM PDT 24 Aug 12 05:35:02 PM PDT 24 270400149 ps
T1134 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1567451629 Aug 12 05:35:16 PM PDT 24 Aug 12 05:35:20 PM PDT 24 368959718 ps
T1135 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4141571068 Aug 12 05:35:13 PM PDT 24 Aug 12 05:35:14 PM PDT 24 46633196 ps
T1136 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3118503754 Aug 12 05:34:51 PM PDT 24 Aug 12 05:34:59 PM PDT 24 361308378 ps
T1137 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.236356886 Aug 12 05:35:20 PM PDT 24 Aug 12 05:35:20 PM PDT 24 17213011 ps
T1138 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4028517418 Aug 12 05:34:53 PM PDT 24 Aug 12 05:34:57 PM PDT 24 151894120 ps
T1139 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.316383224 Aug 12 05:35:17 PM PDT 24 Aug 12 05:35:24 PM PDT 24 1232261692 ps
T1140 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4058477752 Aug 12 05:35:29 PM PDT 24 Aug 12 05:35:31 PM PDT 24 92385412 ps
T1141 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.649465724 Aug 12 05:35:24 PM PDT 24 Aug 12 05:35:30 PM PDT 24 408099387 ps
T1142 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3752784795 Aug 12 05:35:06 PM PDT 24 Aug 12 05:35:22 PM PDT 24 754871577 ps
T1143 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1394050385 Aug 12 05:35:26 PM PDT 24 Aug 12 05:35:27 PM PDT 24 23141288 ps
T1144 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1617611303 Aug 12 05:35:02 PM PDT 24 Aug 12 05:35:04 PM PDT 24 32919835 ps
T1145 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1131539482 Aug 12 05:35:07 PM PDT 24 Aug 12 05:35:12 PM PDT 24 134766986 ps
T1146 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3968704744 Aug 12 05:35:32 PM PDT 24 Aug 12 05:35:34 PM PDT 24 121974609 ps
T1147 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1391596299 Aug 12 05:35:33 PM PDT 24 Aug 12 05:35:33 PM PDT 24 41737256 ps
T1148 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3724263167 Aug 12 05:35:27 PM PDT 24 Aug 12 05:35:28 PM PDT 24 19449113 ps
T1149 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3286666103 Aug 12 05:35:23 PM PDT 24 Aug 12 05:35:50 PM PDT 24 938623933 ps
T1150 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1839671920 Aug 12 05:35:08 PM PDT 24 Aug 12 05:35:09 PM PDT 24 19676307 ps
T1151 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.394149530 Aug 12 05:35:06 PM PDT 24 Aug 12 05:35:07 PM PDT 24 38727299 ps

Test location /workspace/coverage/default/20.spi_device_intercept.1558328583
Short name T7
Test name
Test status
Simulation time 11679986437 ps
CPU time 23.95 seconds
Started Aug 12 05:36:32 PM PDT 24
Finished Aug 12 05:36:56 PM PDT 24
Peak memory 224720 kb
Host smart-51f5d259-ace0-4cfb-91e7-5e0fdc980c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558328583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1558328583
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2924496639
Short name T16
Test name
Test status
Simulation time 110592160873 ps
CPU time 328.37 seconds
Started Aug 12 05:35:47 PM PDT 24
Finished Aug 12 05:41:15 PM PDT 24
Peak memory 267824 kb
Host smart-d09fac25-9519-43cf-a11c-edddf485929a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924496639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2924496639
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.559067222
Short name T27
Test name
Test status
Simulation time 705060626 ps
CPU time 3.16 seconds
Started Aug 12 05:35:27 PM PDT 24
Finished Aug 12 05:35:31 PM PDT 24
Peak memory 216432 kb
Host smart-d1a55742-4c0a-4a9e-a2ca-9ba51ba4001c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559067222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.559067222
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.894223410
Short name T20
Test name
Test status
Simulation time 34142799333 ps
CPU time 311.23 seconds
Started Aug 12 05:37:03 PM PDT 24
Finished Aug 12 05:42:14 PM PDT 24
Peak memory 273112 kb
Host smart-e2715271-cfde-496c-a515-4643765fa909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894223410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.894223410
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1652206752
Short name T107
Test name
Test status
Simulation time 4424558139 ps
CPU time 14.41 seconds
Started Aug 12 05:35:46 PM PDT 24
Finished Aug 12 05:36:01 PM PDT 24
Peak memory 215824 kb
Host smart-7dcdcf44-74bf-4e76-8169-8a10177990f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652206752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1652206752
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.903125640
Short name T18
Test name
Test status
Simulation time 26368242636 ps
CPU time 109.95 seconds
Started Aug 12 05:36:23 PM PDT 24
Finished Aug 12 05:38:13 PM PDT 24
Peak memory 257404 kb
Host smart-7dc2ca7f-2e3b-4d74-8b28-622dd3a43cb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903125640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.903125640
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3417977680
Short name T89
Test name
Test status
Simulation time 377524832997 ps
CPU time 890.49 seconds
Started Aug 12 05:36:45 PM PDT 24
Finished Aug 12 05:51:36 PM PDT 24
Peak memory 273976 kb
Host smart-0d425576-de46-47c2-8c48-12c949771439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417977680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3417977680
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2809503789
Short name T38
Test name
Test status
Simulation time 174686299 ps
CPU time 0.73 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:27 PM PDT 24
Peak memory 216144 kb
Host smart-36dd5f39-b3cd-4959-ac7b-537d9ac058f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809503789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2809503789
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2024357739
Short name T23
Test name
Test status
Simulation time 151588430475 ps
CPU time 724.53 seconds
Started Aug 12 05:37:15 PM PDT 24
Finished Aug 12 05:49:19 PM PDT 24
Peak memory 266744 kb
Host smart-a970e5bf-4daa-4696-8f3d-9cedb410ca83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024357739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2024357739
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1413141166
Short name T231
Test name
Test status
Simulation time 120597427715 ps
CPU time 684.74 seconds
Started Aug 12 05:36:12 PM PDT 24
Finished Aug 12 05:47:37 PM PDT 24
Peak memory 302372 kb
Host smart-463d351b-8b00-449d-80f5-61f3c402f26d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413141166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1413141166
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3671992787
Short name T195
Test name
Test status
Simulation time 3204696897 ps
CPU time 91.88 seconds
Started Aug 12 05:36:50 PM PDT 24
Finished Aug 12 05:38:22 PM PDT 24
Peak memory 250744 kb
Host smart-8a72dc1a-be51-4c8c-aae7-422d24ca4eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671992787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3671992787
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2523341825
Short name T8
Test name
Test status
Simulation time 955728818 ps
CPU time 5.01 seconds
Started Aug 12 05:35:35 PM PDT 24
Finished Aug 12 05:35:40 PM PDT 24
Peak memory 232900 kb
Host smart-80a7c49a-e861-4969-ad67-0e5c272d5051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523341825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2523341825
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.921305644
Short name T104
Test name
Test status
Simulation time 150243712 ps
CPU time 2.2 seconds
Started Aug 12 05:35:13 PM PDT 24
Finished Aug 12 05:35:15 PM PDT 24
Peak memory 215528 kb
Host smart-ceea911b-3710-4358-a1a7-986c6a39df62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921305644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.921305644
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1032286919
Short name T149
Test name
Test status
Simulation time 73941808472 ps
CPU time 623.31 seconds
Started Aug 12 05:37:06 PM PDT 24
Finished Aug 12 05:47:30 PM PDT 24
Peak memory 265612 kb
Host smart-0e0ff1aa-fc9a-4782-96ca-041da1125bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032286919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1032286919
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2587574394
Short name T338
Test name
Test status
Simulation time 21559495 ps
CPU time 0.71 seconds
Started Aug 12 05:36:32 PM PDT 24
Finished Aug 12 05:36:33 PM PDT 24
Peak memory 205284 kb
Host smart-2c55924a-9948-4a49-9fbe-22bf5046b7e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587574394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2587574394
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3547849938
Short name T157
Test name
Test status
Simulation time 1856681470 ps
CPU time 9.67 seconds
Started Aug 12 05:36:18 PM PDT 24
Finished Aug 12 05:36:28 PM PDT 24
Peak memory 232852 kb
Host smart-369495ff-fb7f-44f4-8841-69d64a20c26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547849938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3547849938
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3425189152
Short name T17
Test name
Test status
Simulation time 51523712802 ps
CPU time 214.71 seconds
Started Aug 12 05:36:44 PM PDT 24
Finished Aug 12 05:40:19 PM PDT 24
Peak memory 265712 kb
Host smart-eb2eed2a-06f0-4588-93d2-b55e45be8803
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425189152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3425189152
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2067103670
Short name T244
Test name
Test status
Simulation time 23089486461 ps
CPU time 90.4 seconds
Started Aug 12 05:36:22 PM PDT 24
Finished Aug 12 05:37:53 PM PDT 24
Peak memory 267564 kb
Host smart-2468a345-e679-4b13-939d-7a52c0b79c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067103670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2067103670
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3872471400
Short name T133
Test name
Test status
Simulation time 754813004 ps
CPU time 12.16 seconds
Started Aug 12 05:35:02 PM PDT 24
Finished Aug 12 05:35:14 PM PDT 24
Peak memory 206900 kb
Host smart-22bcb1ab-f203-48f9-b856-d71a326f777c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872471400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3872471400
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1674766580
Short name T240
Test name
Test status
Simulation time 1719891054078 ps
CPU time 1107.6 seconds
Started Aug 12 05:37:12 PM PDT 24
Finished Aug 12 05:55:40 PM PDT 24
Peak memory 283216 kb
Host smart-842a48fa-aa7c-467f-81e2-aba987bdff21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674766580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1674766580
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3706673059
Short name T166
Test name
Test status
Simulation time 13795732870 ps
CPU time 241.32 seconds
Started Aug 12 05:37:16 PM PDT 24
Finished Aug 12 05:41:18 PM PDT 24
Peak memory 282144 kb
Host smart-a7386ace-609f-4f07-a09f-f67fb1a40afc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706673059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3706673059
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1131796160
Short name T371
Test name
Test status
Simulation time 28005385 ps
CPU time 1.02 seconds
Started Aug 12 05:35:36 PM PDT 24
Finished Aug 12 05:35:37 PM PDT 24
Peak memory 216648 kb
Host smart-9f6dcc01-cdbc-4825-918b-f21fe89009f3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131796160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1131796160
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.391703582
Short name T58
Test name
Test status
Simulation time 8048332800 ps
CPU time 109.83 seconds
Started Aug 12 05:36:40 PM PDT 24
Finished Aug 12 05:38:30 PM PDT 24
Peak memory 264236 kb
Host smart-b17dcd06-3244-4719-bb89-4808e2bf340a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391703582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.391703582
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3554880400
Short name T112
Test name
Test status
Simulation time 465807293 ps
CPU time 4.74 seconds
Started Aug 12 05:35:06 PM PDT 24
Finished Aug 12 05:35:10 PM PDT 24
Peak memory 215488 kb
Host smart-e5a186da-ee5d-4227-8161-006478223efc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554880400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
554880400
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.116344979
Short name T76
Test name
Test status
Simulation time 84417517 ps
CPU time 1.13 seconds
Started Aug 12 05:35:32 PM PDT 24
Finished Aug 12 05:35:34 PM PDT 24
Peak memory 235348 kb
Host smart-5bbd68ec-9c41-4a43-83fe-9b31f1b32dac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116344979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.116344979
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.924847512
Short name T101
Test name
Test status
Simulation time 141957442615 ps
CPU time 295.85 seconds
Started Aug 12 05:36:11 PM PDT 24
Finished Aug 12 05:41:07 PM PDT 24
Peak memory 257004 kb
Host smart-999347c9-a13b-4e52-846a-79e240c7804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924847512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
924847512
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.4109951313
Short name T57
Test name
Test status
Simulation time 21397655767 ps
CPU time 231.08 seconds
Started Aug 12 05:36:18 PM PDT 24
Finished Aug 12 05:40:09 PM PDT 24
Peak memory 263280 kb
Host smart-e1d3b27b-d0fb-45f3-87ff-31fb4dd441a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109951313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.4109951313
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3124069077
Short name T210
Test name
Test status
Simulation time 203136259876 ps
CPU time 420.73 seconds
Started Aug 12 05:35:38 PM PDT 24
Finished Aug 12 05:42:39 PM PDT 24
Peak memory 265812 kb
Host smart-605f3697-ccee-43eb-b7f1-cbda34ac3f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124069077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3124069077
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1943577294
Short name T201
Test name
Test status
Simulation time 9178239484 ps
CPU time 22.19 seconds
Started Aug 12 05:35:11 PM PDT 24
Finished Aug 12 05:35:33 PM PDT 24
Peak memory 223536 kb
Host smart-dbdfb403-5f20-4c60-a7ad-06872402b2fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943577294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1943577294
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3428471853
Short name T299
Test name
Test status
Simulation time 228440610405 ps
CPU time 372.08 seconds
Started Aug 12 05:36:42 PM PDT 24
Finished Aug 12 05:42:54 PM PDT 24
Peak memory 257548 kb
Host smart-06cda85b-669d-4624-960f-6338f0cd4efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428471853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3428471853
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.282307626
Short name T9
Test name
Test status
Simulation time 3020486037 ps
CPU time 4.78 seconds
Started Aug 12 05:36:04 PM PDT 24
Finished Aug 12 05:36:09 PM PDT 24
Peak memory 216480 kb
Host smart-b9e137b9-f38c-48ca-9d77-b25f4496ae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282307626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.282307626
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1365789327
Short name T33
Test name
Test status
Simulation time 58677277095 ps
CPU time 170.64 seconds
Started Aug 12 05:35:38 PM PDT 24
Finished Aug 12 05:38:28 PM PDT 24
Peak memory 257540 kb
Host smart-71a43f35-0f3d-4298-b9be-2688f92603e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365789327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1365789327
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3470448048
Short name T230
Test name
Test status
Simulation time 26559342831 ps
CPU time 187.51 seconds
Started Aug 12 05:36:30 PM PDT 24
Finished Aug 12 05:39:38 PM PDT 24
Peak memory 250452 kb
Host smart-d3f0cc29-b8df-4be0-bcd6-292efdf85b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470448048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3470448048
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1055007196
Short name T305
Test name
Test status
Simulation time 15142959256 ps
CPU time 149.06 seconds
Started Aug 12 05:36:05 PM PDT 24
Finished Aug 12 05:38:34 PM PDT 24
Peak memory 269400 kb
Host smart-ee1c677a-fff7-4551-bde1-98fc424fa012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055007196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1055007196
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2479135519
Short name T288
Test name
Test status
Simulation time 11488451351 ps
CPU time 98.97 seconds
Started Aug 12 05:36:33 PM PDT 24
Finished Aug 12 05:38:18 PM PDT 24
Peak memory 262544 kb
Host smart-d30ff450-6671-4371-a46c-81cfc237cc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479135519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2479135519
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.977025063
Short name T90
Test name
Test status
Simulation time 5045849850 ps
CPU time 85.86 seconds
Started Aug 12 05:36:41 PM PDT 24
Finished Aug 12 05:38:08 PM PDT 24
Peak memory 273928 kb
Host smart-a8658fe1-0382-4d3d-af47-ee870d887f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977025063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.977025063
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1050392630
Short name T215
Test name
Test status
Simulation time 1485383367 ps
CPU time 4.29 seconds
Started Aug 12 05:37:07 PM PDT 24
Finished Aug 12 05:37:12 PM PDT 24
Peak memory 224680 kb
Host smart-130b6ab6-36f0-4fbf-bf4c-edc3b4dfa2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050392630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1050392630
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1254977295
Short name T184
Test name
Test status
Simulation time 29714524084 ps
CPU time 49.4 seconds
Started Aug 12 05:35:59 PM PDT 24
Finished Aug 12 05:36:49 PM PDT 24
Peak memory 232904 kb
Host smart-e47aaf00-eb8a-4c3c-bb25-f7b94a9edb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254977295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1254977295
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2764718693
Short name T118
Test name
Test status
Simulation time 1432900612 ps
CPU time 3.38 seconds
Started Aug 12 05:35:23 PM PDT 24
Finished Aug 12 05:35:26 PM PDT 24
Peak memory 215420 kb
Host smart-1d02c5d1-b07a-487a-a7ed-749f93d969f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764718693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2764718693
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2834678130
Short name T200
Test name
Test status
Simulation time 1338595153 ps
CPU time 14.41 seconds
Started Aug 12 05:35:30 PM PDT 24
Finished Aug 12 05:35:44 PM PDT 24
Peak memory 215324 kb
Host smart-24ee79d0-b647-4a07-bef3-16373f85f242
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834678130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2834678130
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1966615619
Short name T279
Test name
Test status
Simulation time 146072953352 ps
CPU time 306.79 seconds
Started Aug 12 05:36:07 PM PDT 24
Finished Aug 12 05:41:14 PM PDT 24
Peak memory 266416 kb
Host smart-7cba1ee5-aba2-4b1b-a453-7b01b69f2556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966615619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1966615619
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.849576705
Short name T773
Test name
Test status
Simulation time 3239039749 ps
CPU time 8.04 seconds
Started Aug 12 05:36:23 PM PDT 24
Finished Aug 12 05:36:32 PM PDT 24
Peak memory 232964 kb
Host smart-68c94b6c-257e-43c8-8a68-21ba56cfe31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849576705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.849576705
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2794846127
Short name T320
Test name
Test status
Simulation time 16998552662 ps
CPU time 64.93 seconds
Started Aug 12 05:37:00 PM PDT 24
Finished Aug 12 05:38:05 PM PDT 24
Peak memory 224864 kb
Host smart-8a03eb0e-9eea-44e1-851d-0f2bdcbda6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794846127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2794846127
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.571870670
Short name T189
Test name
Test status
Simulation time 362352471 ps
CPU time 6.11 seconds
Started Aug 12 05:36:35 PM PDT 24
Finished Aug 12 05:36:41 PM PDT 24
Peak memory 232856 kb
Host smart-91c3923c-81c1-492d-b318-15730bda62a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571870670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.571870670
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3754795182
Short name T159
Test name
Test status
Simulation time 472792495 ps
CPU time 15.83 seconds
Started Aug 12 05:35:31 PM PDT 24
Finished Aug 12 05:35:47 PM PDT 24
Peak memory 249244 kb
Host smart-577e785d-186d-41ed-9361-8bf195b2d02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754795182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3754795182
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2525279190
Short name T95
Test name
Test status
Simulation time 74286433 ps
CPU time 1.38 seconds
Started Aug 12 05:35:20 PM PDT 24
Finished Aug 12 05:35:21 PM PDT 24
Peak memory 216072 kb
Host smart-705dadbf-7cab-4e55-8056-611bfc1732a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525279190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2525279190
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1744977582
Short name T823
Test name
Test status
Simulation time 115636258696 ps
CPU time 295.51 seconds
Started Aug 12 05:36:03 PM PDT 24
Finished Aug 12 05:40:59 PM PDT 24
Peak memory 255820 kb
Host smart-e950fa6f-7a71-4597-85d7-229ffabecdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744977582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1744977582
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2507836646
Short name T103
Test name
Test status
Simulation time 8120405516 ps
CPU time 64.12 seconds
Started Aug 12 05:36:31 PM PDT 24
Finished Aug 12 05:37:35 PM PDT 24
Peak memory 239528 kb
Host smart-e9e222c0-e69a-44d8-afd3-2ffedcf5059f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507836646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2507836646
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3707152846
Short name T127
Test name
Test status
Simulation time 2921038216 ps
CPU time 16.74 seconds
Started Aug 12 05:34:57 PM PDT 24
Finished Aug 12 05:35:14 PM PDT 24
Peak memory 206952 kb
Host smart-fd3c7861-7396-4116-9aa2-0e8bfc89d5d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707152846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3707152846
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2157258675
Short name T92
Test name
Test status
Simulation time 22171047 ps
CPU time 0.97 seconds
Started Aug 12 05:35:20 PM PDT 24
Finished Aug 12 05:35:21 PM PDT 24
Peak memory 206748 kb
Host smart-1ef436a7-c1bb-4bc9-a22f-85790542805c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157258675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2157258675
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1505190310
Short name T105
Test name
Test status
Simulation time 342779861 ps
CPU time 2.57 seconds
Started Aug 12 05:35:02 PM PDT 24
Finished Aug 12 05:35:05 PM PDT 24
Peak memory 217532 kb
Host smart-87cdfedb-acc7-4064-8188-11739cca7a37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505190310 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1505190310
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3563371155
Short name T1079
Test name
Test status
Simulation time 67585833 ps
CPU time 1.25 seconds
Started Aug 12 05:35:23 PM PDT 24
Finished Aug 12 05:35:30 PM PDT 24
Peak memory 207072 kb
Host smart-3fbc396a-036f-4b39-b3bb-bbb715b03a93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563371155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
563371155
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1069987062
Short name T1097
Test name
Test status
Simulation time 11534486 ps
CPU time 0.67 seconds
Started Aug 12 05:35:24 PM PDT 24
Finished Aug 12 05:35:25 PM PDT 24
Peak memory 204016 kb
Host smart-d6dc846c-a205-49a5-86bf-17a5c956438b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069987062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
069987062
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.693798556
Short name T1128
Test name
Test status
Simulation time 33283596 ps
CPU time 1.21 seconds
Started Aug 12 05:35:27 PM PDT 24
Finished Aug 12 05:35:29 PM PDT 24
Peak memory 215304 kb
Host smart-43b50886-a3e8-48e8-b4eb-ef4f962028af
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693798556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.693798556
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.174839153
Short name T1072
Test name
Test status
Simulation time 25033676 ps
CPU time 0.66 seconds
Started Aug 12 05:35:08 PM PDT 24
Finished Aug 12 05:35:09 PM PDT 24
Peak memory 203556 kb
Host smart-f30c7701-6b30-4826-af90-a030c4500c4a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174839153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.174839153
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4236679176
Short name T1050
Test name
Test status
Simulation time 205123091 ps
CPU time 1.72 seconds
Started Aug 12 05:34:47 PM PDT 24
Finished Aug 12 05:34:49 PM PDT 24
Peak memory 215140 kb
Host smart-65bc0b72-cda0-4d52-b745-eff9791b25c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236679176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.4236679176
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.121836323
Short name T1133
Test name
Test status
Simulation time 270400149 ps
CPU time 4.82 seconds
Started Aug 12 05:34:57 PM PDT 24
Finished Aug 12 05:35:02 PM PDT 24
Peak memory 215304 kb
Host smart-9fcb2039-0568-4986-9f3b-7fa6793c7848
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121836323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.121836323
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2509195499
Short name T205
Test name
Test status
Simulation time 104637605 ps
CPU time 6.43 seconds
Started Aug 12 05:35:03 PM PDT 24
Finished Aug 12 05:35:09 PM PDT 24
Peak memory 215280 kb
Host smart-fe083492-d2b1-4182-b5e1-3ed706256dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509195499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2509195499
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4146087687
Short name T129
Test name
Test status
Simulation time 2222749337 ps
CPU time 16.61 seconds
Started Aug 12 05:35:15 PM PDT 24
Finished Aug 12 05:35:32 PM PDT 24
Peak memory 205952 kb
Host smart-1866d24e-5dc3-4edd-81d4-7d8d90410fd6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146087687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4146087687
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.946469601
Short name T1060
Test name
Test status
Simulation time 1882630233 ps
CPU time 36.97 seconds
Started Aug 12 05:34:49 PM PDT 24
Finished Aug 12 05:35:26 PM PDT 24
Peak memory 207004 kb
Host smart-0de738c5-7a76-4388-a92c-9b0298d6000a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946469601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.946469601
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1026060047
Short name T93
Test name
Test status
Simulation time 99297298 ps
CPU time 0.98 seconds
Started Aug 12 05:35:09 PM PDT 24
Finished Aug 12 05:35:11 PM PDT 24
Peak memory 206744 kb
Host smart-87236b1b-a099-442f-a258-ed039b4c250d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026060047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1026060047
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.70663399
Short name T164
Test name
Test status
Simulation time 419783699 ps
CPU time 2.75 seconds
Started Aug 12 05:34:54 PM PDT 24
Finished Aug 12 05:34:57 PM PDT 24
Peak memory 216472 kb
Host smart-4dd1d8f3-aff2-408a-858f-29d6a30ac316
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70663399 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.70663399
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2508967519
Short name T1099
Test name
Test status
Simulation time 39146423 ps
CPU time 1.2 seconds
Started Aug 12 05:34:54 PM PDT 24
Finished Aug 12 05:34:56 PM PDT 24
Peak memory 215060 kb
Host smart-ece5e4d2-4c9e-403b-b2d7-c7656b552ca2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508967519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
508967519
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1297473316
Short name T1067
Test name
Test status
Simulation time 56641898 ps
CPU time 0.67 seconds
Started Aug 12 05:35:27 PM PDT 24
Finished Aug 12 05:35:28 PM PDT 24
Peak memory 203744 kb
Host smart-fab34511-1c9d-4cc3-be79-53177d8d12a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297473316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
297473316
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3098911520
Short name T1112
Test name
Test status
Simulation time 19380652 ps
CPU time 1.24 seconds
Started Aug 12 05:35:15 PM PDT 24
Finished Aug 12 05:35:16 PM PDT 24
Peak memory 215260 kb
Host smart-4cc0c026-03b3-4fc2-ab1f-ce720d332927
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098911520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3098911520
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3305360811
Short name T1080
Test name
Test status
Simulation time 11911258 ps
CPU time 0.69 seconds
Started Aug 12 05:35:01 PM PDT 24
Finished Aug 12 05:35:02 PM PDT 24
Peak memory 202428 kb
Host smart-79c0834f-1626-48b4-b287-9fea99497f75
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305360811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3305360811
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2675063082
Short name T1125
Test name
Test status
Simulation time 28462078 ps
CPU time 1.79 seconds
Started Aug 12 05:35:19 PM PDT 24
Finished Aug 12 05:35:21 PM PDT 24
Peak memory 215024 kb
Host smart-7ee13f7b-f01a-47f9-8b0c-ad9f098e7ed2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675063082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2675063082
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.353312259
Short name T198
Test name
Test status
Simulation time 297860592 ps
CPU time 4.75 seconds
Started Aug 12 05:34:59 PM PDT 24
Finished Aug 12 05:35:04 PM PDT 24
Peak memory 215556 kb
Host smart-df4cdf79-7a26-461e-b884-8f83e9ca2151
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353312259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.353312259
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2064945603
Short name T1111
Test name
Test status
Simulation time 979318463 ps
CPU time 11.72 seconds
Started Aug 12 05:35:07 PM PDT 24
Finished Aug 12 05:35:18 PM PDT 24
Peak memory 215532 kb
Host smart-93f9fc76-adfc-4a1f-9234-f1dc8b099528
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064945603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2064945603
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3195462900
Short name T1109
Test name
Test status
Simulation time 135067606 ps
CPU time 2.24 seconds
Started Aug 12 05:35:16 PM PDT 24
Finished Aug 12 05:35:19 PM PDT 24
Peak memory 216364 kb
Host smart-fd2fc6aa-55a7-4a52-bba4-bf990ba83ae4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195462900 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3195462900
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3872536210
Short name T150
Test name
Test status
Simulation time 69875886 ps
CPU time 1.91 seconds
Started Aug 12 05:35:37 PM PDT 24
Finished Aug 12 05:35:39 PM PDT 24
Peak memory 215136 kb
Host smart-a9e3ed75-94b5-4cfa-8fb4-b7262cd385ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872536210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3872536210
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1487865352
Short name T1040
Test name
Test status
Simulation time 31950295 ps
CPU time 0.74 seconds
Started Aug 12 05:35:18 PM PDT 24
Finished Aug 12 05:35:19 PM PDT 24
Peak memory 203804 kb
Host smart-7ee3b7f9-1f12-4761-9d6c-ba61d10b8e36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487865352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1487865352
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.318815413
Short name T1055
Test name
Test status
Simulation time 105607671 ps
CPU time 2.85 seconds
Started Aug 12 05:35:31 PM PDT 24
Finished Aug 12 05:35:34 PM PDT 24
Peak memory 215068 kb
Host smart-2117ad70-0f2b-4021-9a29-e67768ff8ba7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318815413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.318815413
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1897522427
Short name T115
Test name
Test status
Simulation time 323297934 ps
CPU time 4.94 seconds
Started Aug 12 05:35:28 PM PDT 24
Finished Aug 12 05:35:33 PM PDT 24
Peak memory 215436 kb
Host smart-7d268a8a-68f5-4c8f-b8d9-12808bab7c2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897522427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1897522427
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1567451629
Short name T1134
Test name
Test status
Simulation time 368959718 ps
CPU time 3.11 seconds
Started Aug 12 05:35:16 PM PDT 24
Finished Aug 12 05:35:20 PM PDT 24
Peak memory 217792 kb
Host smart-ca8c0709-794b-4957-a27c-357d51acf62a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567451629 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1567451629
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.304874775
Short name T1102
Test name
Test status
Simulation time 286218058 ps
CPU time 2.01 seconds
Started Aug 12 05:35:46 PM PDT 24
Finished Aug 12 05:35:48 PM PDT 24
Peak memory 215248 kb
Host smart-4f44aa90-5f72-4f69-9f89-cfd504704d74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304874775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.304874775
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1308559220
Short name T1093
Test name
Test status
Simulation time 22612389 ps
CPU time 0.72 seconds
Started Aug 12 05:35:20 PM PDT 24
Finished Aug 12 05:35:21 PM PDT 24
Peak memory 204064 kb
Host smart-8f368d95-a22a-4e8d-b8ee-eaa36f029217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308559220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1308559220
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2156135056
Short name T1091
Test name
Test status
Simulation time 511544239 ps
CPU time 2.91 seconds
Started Aug 12 05:35:31 PM PDT 24
Finished Aug 12 05:35:34 PM PDT 24
Peak memory 215288 kb
Host smart-babfcb39-4550-4421-b741-26d3d78b5125
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156135056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2156135056
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.219609733
Short name T126
Test name
Test status
Simulation time 216189585 ps
CPU time 6.42 seconds
Started Aug 12 05:35:19 PM PDT 24
Finished Aug 12 05:35:26 PM PDT 24
Peak memory 215304 kb
Host smart-d6a73947-5f2a-4e5e-a665-bcd7c9d1786f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219609733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.219609733
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2767615150
Short name T120
Test name
Test status
Simulation time 106276306 ps
CPU time 1.67 seconds
Started Aug 12 05:35:13 PM PDT 24
Finished Aug 12 05:35:15 PM PDT 24
Peak memory 215476 kb
Host smart-3679a605-8016-440c-897b-0aebc5d77a6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767615150 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2767615150
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.366227076
Short name T1103
Test name
Test status
Simulation time 130893311 ps
CPU time 1.95 seconds
Started Aug 12 05:35:15 PM PDT 24
Finished Aug 12 05:35:17 PM PDT 24
Peak memory 215204 kb
Host smart-5d4a8ef9-60b1-42a1-bbc5-0d7e6f352c2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366227076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.366227076
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1853734461
Short name T1117
Test name
Test status
Simulation time 27098765 ps
CPU time 0.77 seconds
Started Aug 12 05:35:25 PM PDT 24
Finished Aug 12 05:35:26 PM PDT 24
Peak memory 203748 kb
Host smart-a707f2a7-6bee-4afa-b39d-bb47ff490106
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853734461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1853734461
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1298782505
Short name T155
Test name
Test status
Simulation time 90714674 ps
CPU time 1.63 seconds
Started Aug 12 05:35:22 PM PDT 24
Finished Aug 12 05:35:23 PM PDT 24
Peak memory 215192 kb
Host smart-1971298b-ba84-4117-a8a4-21c602650a4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298782505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1298782505
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2815086499
Short name T121
Test name
Test status
Simulation time 1410736370 ps
CPU time 2.49 seconds
Started Aug 12 05:35:08 PM PDT 24
Finished Aug 12 05:35:11 PM PDT 24
Peak memory 215432 kb
Host smart-2d3ebb9e-2397-4be7-8b45-c6f310ca7986
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815086499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2815086499
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.316383224
Short name T1139
Test name
Test status
Simulation time 1232261692 ps
CPU time 6.48 seconds
Started Aug 12 05:35:17 PM PDT 24
Finished Aug 12 05:35:24 PM PDT 24
Peak memory 215844 kb
Host smart-5d274f41-d84c-4b57-bb4f-a40af697ccc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316383224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.316383224
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.927346724
Short name T1071
Test name
Test status
Simulation time 204260340 ps
CPU time 2.57 seconds
Started Aug 12 05:35:15 PM PDT 24
Finished Aug 12 05:35:18 PM PDT 24
Peak memory 216804 kb
Host smart-534dec6f-6dc9-4ae5-832f-86e5a643ac0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927346724 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.927346724
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.559426682
Short name T128
Test name
Test status
Simulation time 64898895 ps
CPU time 2.15 seconds
Started Aug 12 05:35:05 PM PDT 24
Finished Aug 12 05:35:08 PM PDT 24
Peak memory 215148 kb
Host smart-d0088d9b-4bdf-4087-897a-4ade595d6edf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559426682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.559426682
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2353311581
Short name T1041
Test name
Test status
Simulation time 12273075 ps
CPU time 0.73 seconds
Started Aug 12 05:35:22 PM PDT 24
Finished Aug 12 05:35:22 PM PDT 24
Peak memory 203644 kb
Host smart-bafb7062-5bc2-4411-9511-bfc463a636d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353311581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2353311581
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.975774484
Short name T163
Test name
Test status
Simulation time 183263692 ps
CPU time 3.78 seconds
Started Aug 12 05:35:22 PM PDT 24
Finished Aug 12 05:35:26 PM PDT 24
Peak memory 215144 kb
Host smart-f8e2747d-2ae3-40c9-9237-e9e3fbbae04a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975774484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.975774484
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2601425301
Short name T114
Test name
Test status
Simulation time 562300168 ps
CPU time 3.21 seconds
Started Aug 12 05:35:13 PM PDT 24
Finished Aug 12 05:35:22 PM PDT 24
Peak memory 215440 kb
Host smart-c0e4ef24-df31-45c4-bcdc-fe256e61a4ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601425301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2601425301
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1295419828
Short name T199
Test name
Test status
Simulation time 2651688430 ps
CPU time 15.25 seconds
Started Aug 12 05:35:35 PM PDT 24
Finished Aug 12 05:35:50 PM PDT 24
Peak memory 215840 kb
Host smart-e8b758ff-ec9c-44a4-8757-1d5e2b372cbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295419828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1295419828
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4191332160
Short name T162
Test name
Test status
Simulation time 576504204 ps
CPU time 3.4 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:30 PM PDT 24
Peak memory 216776 kb
Host smart-0447c411-f3cc-4f96-8c46-da150f829eaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191332160 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4191332160
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1330344264
Short name T1118
Test name
Test status
Simulation time 649350281 ps
CPU time 1.28 seconds
Started Aug 12 05:35:05 PM PDT 24
Finished Aug 12 05:35:06 PM PDT 24
Peak memory 215356 kb
Host smart-8d405720-7be3-473a-92a7-86b751e6338a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330344264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1330344264
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2801257136
Short name T1132
Test name
Test status
Simulation time 13731452 ps
CPU time 0.71 seconds
Started Aug 12 05:35:19 PM PDT 24
Finished Aug 12 05:35:20 PM PDT 24
Peak memory 204056 kb
Host smart-bbbb6208-0e10-4221-88a0-5d38c9a656a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801257136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2801257136
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.545167243
Short name T153
Test name
Test status
Simulation time 305745245 ps
CPU time 4.09 seconds
Started Aug 12 05:35:21 PM PDT 24
Finished Aug 12 05:35:25 PM PDT 24
Peak memory 215260 kb
Host smart-77a245ba-ee58-4e5f-9b38-9290d8e1f986
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545167243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.545167243
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3420379729
Short name T1077
Test name
Test status
Simulation time 68626378 ps
CPU time 1.96 seconds
Started Aug 12 05:35:39 PM PDT 24
Finished Aug 12 05:35:41 PM PDT 24
Peak memory 216768 kb
Host smart-6600b444-31bf-46ba-82d9-83810ae374ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420379729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3420379729
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1866568584
Short name T108
Test name
Test status
Simulation time 320200921 ps
CPU time 7.87 seconds
Started Aug 12 05:35:31 PM PDT 24
Finished Aug 12 05:35:38 PM PDT 24
Peak memory 215308 kb
Host smart-8a78e8a1-0825-4bba-aef0-b4bdeb65696d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866568584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1866568584
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2332796420
Short name T1081
Test name
Test status
Simulation time 255255322 ps
CPU time 1.88 seconds
Started Aug 12 05:35:00 PM PDT 24
Finished Aug 12 05:35:07 PM PDT 24
Peak memory 216256 kb
Host smart-fc6cc84e-ed42-4f8d-864b-4b41280344dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332796420 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2332796420
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3289440421
Short name T1127
Test name
Test status
Simulation time 75818335 ps
CPU time 2.52 seconds
Started Aug 12 05:35:01 PM PDT 24
Finished Aug 12 05:35:04 PM PDT 24
Peak memory 215144 kb
Host smart-99df2bf3-4565-44cd-ac91-52283ee6443d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289440421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3289440421
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1394050385
Short name T1143
Test name
Test status
Simulation time 23141288 ps
CPU time 0.73 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:27 PM PDT 24
Peak memory 204020 kb
Host smart-d27fdf20-3894-4e89-a71f-723ecf06f2b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394050385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1394050385
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2954021383
Short name T1104
Test name
Test status
Simulation time 164058016 ps
CPU time 2.13 seconds
Started Aug 12 05:35:18 PM PDT 24
Finished Aug 12 05:35:20 PM PDT 24
Peak memory 215232 kb
Host smart-f0025e74-2e40-4d03-a3c1-fa9179bd8cf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954021383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2954021383
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1131539482
Short name T1145
Test name
Test status
Simulation time 134766986 ps
CPU time 4.33 seconds
Started Aug 12 05:35:07 PM PDT 24
Finished Aug 12 05:35:12 PM PDT 24
Peak memory 215476 kb
Host smart-294de58b-c2d3-4842-bee9-d27a4679adb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131539482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1131539482
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3760874637
Short name T123
Test name
Test status
Simulation time 83130997 ps
CPU time 2.44 seconds
Started Aug 12 05:35:20 PM PDT 24
Finished Aug 12 05:35:22 PM PDT 24
Peak memory 216844 kb
Host smart-c5f513cc-ddf8-4596-8504-2f5c546e2550
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760874637 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3760874637
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2574605661
Short name T131
Test name
Test status
Simulation time 52382559 ps
CPU time 1.8 seconds
Started Aug 12 05:35:27 PM PDT 24
Finished Aug 12 05:35:29 PM PDT 24
Peak memory 215144 kb
Host smart-6d9f7e85-3597-44e1-9980-77ad7535f884
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574605661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2574605661
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4141571068
Short name T1135
Test name
Test status
Simulation time 46633196 ps
CPU time 0.77 seconds
Started Aug 12 05:35:13 PM PDT 24
Finished Aug 12 05:35:14 PM PDT 24
Peak memory 203744 kb
Host smart-3e2d8919-2d62-4796-bb44-2ecee1b7d32b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141571068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4141571068
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2752727856
Short name T1070
Test name
Test status
Simulation time 94153327 ps
CPU time 1.82 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:28 PM PDT 24
Peak memory 215156 kb
Host smart-883bc09e-bd70-434b-bd34-d7cb93c3448a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752727856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2752727856
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.973357817
Short name T1120
Test name
Test status
Simulation time 28490607 ps
CPU time 1.84 seconds
Started Aug 12 05:35:30 PM PDT 24
Finished Aug 12 05:35:32 PM PDT 24
Peak memory 215600 kb
Host smart-eeab0441-b9db-4c28-92d9-a0015e5aaf9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973357817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.973357817
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.208058608
Short name T207
Test name
Test status
Simulation time 665605419 ps
CPU time 14.82 seconds
Started Aug 12 05:35:29 PM PDT 24
Finished Aug 12 05:35:44 PM PDT 24
Peak memory 215276 kb
Host smart-dbd9f40f-86ac-4fef-a03c-a64433c88758
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208058608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.208058608
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3316352995
Short name T125
Test name
Test status
Simulation time 50848293 ps
CPU time 2.1 seconds
Started Aug 12 05:35:17 PM PDT 24
Finished Aug 12 05:35:20 PM PDT 24
Peak memory 216360 kb
Host smart-6145e545-214c-49c8-af09-8c9932df6138
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316352995 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3316352995
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3968704744
Short name T1146
Test name
Test status
Simulation time 121974609 ps
CPU time 1.75 seconds
Started Aug 12 05:35:32 PM PDT 24
Finished Aug 12 05:35:34 PM PDT 24
Peak memory 206936 kb
Host smart-b0ce898a-dba5-450c-8141-0746c2631314
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968704744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3968704744
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2447040502
Short name T1096
Test name
Test status
Simulation time 14816407 ps
CPU time 0.76 seconds
Started Aug 12 05:35:58 PM PDT 24
Finished Aug 12 05:35:58 PM PDT 24
Peak memory 204068 kb
Host smart-f95fa641-288f-4eba-a0ea-f07daf47483f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447040502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2447040502
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1015177555
Short name T1059
Test name
Test status
Simulation time 105339528 ps
CPU time 1.76 seconds
Started Aug 12 05:35:42 PM PDT 24
Finished Aug 12 05:35:44 PM PDT 24
Peak memory 215176 kb
Host smart-3ac1e485-655c-4208-959d-8a065f233e21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015177555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1015177555
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2151766908
Short name T113
Test name
Test status
Simulation time 258779439 ps
CPU time 5.49 seconds
Started Aug 12 05:35:15 PM PDT 24
Finished Aug 12 05:35:21 PM PDT 24
Peak memory 215512 kb
Host smart-03a48483-5b17-47e9-a302-6502ed43fd41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151766908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2151766908
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3286666103
Short name T1149
Test name
Test status
Simulation time 938623933 ps
CPU time 21.43 seconds
Started Aug 12 05:35:23 PM PDT 24
Finished Aug 12 05:35:50 PM PDT 24
Peak memory 215388 kb
Host smart-07a9e0b7-5c1f-4117-bcef-7b71a3e7d2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286666103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3286666103
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.543869706
Short name T122
Test name
Test status
Simulation time 341721043 ps
CPU time 2.56 seconds
Started Aug 12 05:35:25 PM PDT 24
Finished Aug 12 05:35:27 PM PDT 24
Peak memory 217524 kb
Host smart-2ac4fe09-2c64-47ce-a0f8-970d6cb400d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543869706 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.543869706
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2179747161
Short name T136
Test name
Test status
Simulation time 31822530 ps
CPU time 1.95 seconds
Started Aug 12 05:35:52 PM PDT 24
Finished Aug 12 05:35:54 PM PDT 24
Peak memory 215144 kb
Host smart-c73d8f74-0fd5-4077-9f7f-3c0fb025849e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179747161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2179747161
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3724263167
Short name T1148
Test name
Test status
Simulation time 19449113 ps
CPU time 0.7 seconds
Started Aug 12 05:35:27 PM PDT 24
Finished Aug 12 05:35:28 PM PDT 24
Peak memory 203708 kb
Host smart-a7073ae1-eb80-42ba-ad93-0d36c7962ec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724263167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3724263167
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.349467505
Short name T1073
Test name
Test status
Simulation time 270412761 ps
CPU time 3.19 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:30 PM PDT 24
Peak memory 215288 kb
Host smart-662a11f4-4678-419a-a478-2c7182421d26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349467505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.349467505
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1474109167
Short name T1116
Test name
Test status
Simulation time 94479688 ps
CPU time 2.64 seconds
Started Aug 12 05:35:16 PM PDT 24
Finished Aug 12 05:35:19 PM PDT 24
Peak memory 215392 kb
Host smart-d99f4eec-c74c-433a-8e7b-4f28a1403c03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474109167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1474109167
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1563517708
Short name T109
Test name
Test status
Simulation time 838707260 ps
CPU time 21.05 seconds
Started Aug 12 05:35:24 PM PDT 24
Finished Aug 12 05:35:45 PM PDT 24
Peak memory 215236 kb
Host smart-fb7ed86c-8073-4918-a024-9834b8f0aa6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563517708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1563517708
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1985103686
Short name T1130
Test name
Test status
Simulation time 571936387 ps
CPU time 3.58 seconds
Started Aug 12 05:35:44 PM PDT 24
Finished Aug 12 05:35:48 PM PDT 24
Peak memory 218092 kb
Host smart-851d6639-b754-4f60-91dd-1c5e950888db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985103686 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1985103686
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3176111057
Short name T1049
Test name
Test status
Simulation time 55397274 ps
CPU time 1.36 seconds
Started Aug 12 05:35:32 PM PDT 24
Finished Aug 12 05:35:33 PM PDT 24
Peak memory 206924 kb
Host smart-7068ba10-e84f-4fc5-9404-1e25dc67e0d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176111057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3176111057
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3047689956
Short name T1043
Test name
Test status
Simulation time 27749573 ps
CPU time 0.68 seconds
Started Aug 12 05:35:44 PM PDT 24
Finished Aug 12 05:35:44 PM PDT 24
Peak memory 204072 kb
Host smart-1d0f7abe-7e2a-46ec-8e59-ba180706b7e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047689956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3047689956
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2068796452
Short name T1048
Test name
Test status
Simulation time 64474636 ps
CPU time 3.98 seconds
Started Aug 12 05:35:24 PM PDT 24
Finished Aug 12 05:35:28 PM PDT 24
Peak memory 215268 kb
Host smart-d34c1f28-4c2f-44d3-bc13-55a6e8e97834
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068796452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2068796452
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4279539006
Short name T116
Test name
Test status
Simulation time 241803091 ps
CPU time 5.5 seconds
Started Aug 12 05:35:33 PM PDT 24
Finished Aug 12 05:35:39 PM PDT 24
Peak memory 215476 kb
Host smart-cc8c3712-7244-47dc-bbdb-b739b0a78ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279539006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4279539006
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2395957485
Short name T1090
Test name
Test status
Simulation time 809801730 ps
CPU time 13.21 seconds
Started Aug 12 05:35:24 PM PDT 24
Finished Aug 12 05:35:37 PM PDT 24
Peak memory 215856 kb
Host smart-f8ac6024-17a0-43ca-86d1-2c983b9a9515
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395957485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2395957485
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3752784795
Short name T1142
Test name
Test status
Simulation time 754871577 ps
CPU time 14.77 seconds
Started Aug 12 05:35:06 PM PDT 24
Finished Aug 12 05:35:22 PM PDT 24
Peak memory 215252 kb
Host smart-9028767e-94a9-44a4-95d6-47a12f8ccd40
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752784795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3752784795
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2355708438
Short name T1063
Test name
Test status
Simulation time 1588692097 ps
CPU time 22.37 seconds
Started Aug 12 05:34:51 PM PDT 24
Finished Aug 12 05:35:14 PM PDT 24
Peak memory 215084 kb
Host smart-1b389c93-fc53-4054-b0f1-cba19f49bca8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355708438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2355708438
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.298436480
Short name T1087
Test name
Test status
Simulation time 58251929 ps
CPU time 1.67 seconds
Started Aug 12 05:35:06 PM PDT 24
Finished Aug 12 05:35:08 PM PDT 24
Peak memory 215372 kb
Host smart-bb42930c-b900-4d8c-a64e-229b492ec146
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298436480 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.298436480
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2150733735
Short name T1121
Test name
Test status
Simulation time 406441540 ps
CPU time 2.42 seconds
Started Aug 12 05:35:05 PM PDT 24
Finished Aug 12 05:35:08 PM PDT 24
Peak memory 215060 kb
Host smart-c3c99d92-eb31-4f47-951b-2d63b76d85c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150733735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
150733735
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1010783977
Short name T1086
Test name
Test status
Simulation time 31271965 ps
CPU time 0.69 seconds
Started Aug 12 05:35:25 PM PDT 24
Finished Aug 12 05:35:25 PM PDT 24
Peak memory 203736 kb
Host smart-a070bc6e-0d22-4701-8734-73d481127c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010783977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
010783977
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1617611303
Short name T1144
Test name
Test status
Simulation time 32919835 ps
CPU time 1.26 seconds
Started Aug 12 05:35:02 PM PDT 24
Finished Aug 12 05:35:04 PM PDT 24
Peak memory 215340 kb
Host smart-29342d3f-95b7-473b-a287-cce571a57fab
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617611303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1617611303
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.236356886
Short name T1137
Test name
Test status
Simulation time 17213011 ps
CPU time 0.65 seconds
Started Aug 12 05:35:20 PM PDT 24
Finished Aug 12 05:35:20 PM PDT 24
Peak memory 203484 kb
Host smart-92b3b49c-b1b0-46ce-9bda-5fb44fb353e2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236356886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.236356886
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3435002138
Short name T1056
Test name
Test status
Simulation time 46566163 ps
CPU time 2.79 seconds
Started Aug 12 05:35:16 PM PDT 24
Finished Aug 12 05:35:19 PM PDT 24
Peak memory 215232 kb
Host smart-d26025c1-bb1b-476f-ac19-a84245b0c27c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435002138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3435002138
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1922152701
Short name T110
Test name
Test status
Simulation time 69167144 ps
CPU time 2.19 seconds
Started Aug 12 05:34:53 PM PDT 24
Finished Aug 12 05:35:01 PM PDT 24
Peak memory 216608 kb
Host smart-46405fac-6579-4863-b302-15465f8dc305
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922152701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
922152701
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1740217649
Short name T203
Test name
Test status
Simulation time 223414441 ps
CPU time 6.94 seconds
Started Aug 12 05:34:53 PM PDT 24
Finished Aug 12 05:35:00 PM PDT 24
Peak memory 215448 kb
Host smart-e32550d8-3ae1-4066-8f0d-003e6c15952a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740217649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1740217649
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4168101500
Short name T1058
Test name
Test status
Simulation time 42383851 ps
CPU time 0.73 seconds
Started Aug 12 05:35:25 PM PDT 24
Finished Aug 12 05:35:25 PM PDT 24
Peak memory 203576 kb
Host smart-4ab821ed-f370-4a5f-ac84-3383064acd59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168101500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
4168101500
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2078481492
Short name T1114
Test name
Test status
Simulation time 96993141 ps
CPU time 0.78 seconds
Started Aug 12 05:35:41 PM PDT 24
Finished Aug 12 05:35:42 PM PDT 24
Peak memory 203672 kb
Host smart-9be9a650-13aa-400b-ad2a-c000dc75c6f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078481492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2078481492
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1865792807
Short name T1069
Test name
Test status
Simulation time 53313086 ps
CPU time 0.73 seconds
Started Aug 12 05:35:44 PM PDT 24
Finished Aug 12 05:35:45 PM PDT 24
Peak memory 203752 kb
Host smart-9b38735a-050a-4f01-aa24-41a1b20b3d74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865792807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1865792807
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2324409354
Short name T1076
Test name
Test status
Simulation time 13783756 ps
CPU time 0.76 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:27 PM PDT 24
Peak memory 203652 kb
Host smart-6be90d3e-8c13-4d72-9353-10970105e04c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324409354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2324409354
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3065684533
Short name T1045
Test name
Test status
Simulation time 89167514 ps
CPU time 0.73 seconds
Started Aug 12 05:35:23 PM PDT 24
Finished Aug 12 05:35:23 PM PDT 24
Peak memory 203736 kb
Host smart-ce685676-0581-4e8d-a48e-d1241ca71558
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065684533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3065684533
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3714249506
Short name T1065
Test name
Test status
Simulation time 56571909 ps
CPU time 0.73 seconds
Started Aug 12 05:35:45 PM PDT 24
Finished Aug 12 05:35:46 PM PDT 24
Peak memory 204076 kb
Host smart-860c24d4-4930-433d-b821-ae5bcc260b43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714249506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3714249506
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1199009455
Short name T1039
Test name
Test status
Simulation time 17268117 ps
CPU time 0.71 seconds
Started Aug 12 05:35:31 PM PDT 24
Finished Aug 12 05:35:32 PM PDT 24
Peak memory 203644 kb
Host smart-04777d5c-4ce3-4bc8-bb64-782f238a3fc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199009455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1199009455
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2163119886
Short name T1052
Test name
Test status
Simulation time 14456559 ps
CPU time 0.73 seconds
Started Aug 12 05:35:54 PM PDT 24
Finished Aug 12 05:35:55 PM PDT 24
Peak memory 204048 kb
Host smart-9cfdd706-b7f5-43c2-8c20-460bb2e0cc8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163119886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2163119886
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1657344130
Short name T1105
Test name
Test status
Simulation time 91233231 ps
CPU time 0.71 seconds
Started Aug 12 05:35:24 PM PDT 24
Finished Aug 12 05:35:25 PM PDT 24
Peak memory 203728 kb
Host smart-f807f075-e6b6-4d04-8e32-c645a390ed59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657344130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1657344130
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2094226266
Short name T1084
Test name
Test status
Simulation time 111518146 ps
CPU time 0.77 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:26 PM PDT 24
Peak memory 203696 kb
Host smart-f36d5336-9965-445e-ba30-4b08811467e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094226266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2094226266
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4062841723
Short name T139
Test name
Test status
Simulation time 12431745639 ps
CPU time 16.3 seconds
Started Aug 12 05:35:18 PM PDT 24
Finished Aug 12 05:35:34 PM PDT 24
Peak memory 215236 kb
Host smart-95cb2f4f-d83f-4191-8ee3-a0b3a3565adf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062841723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.4062841723
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2263205207
Short name T138
Test name
Test status
Simulation time 188701860 ps
CPU time 11.39 seconds
Started Aug 12 05:35:14 PM PDT 24
Finished Aug 12 05:35:26 PM PDT 24
Peak memory 207008 kb
Host smart-757526ac-e1d8-4971-a16c-3a0f40f2dc65
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263205207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2263205207
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.93762817
Short name T94
Test name
Test status
Simulation time 22930744 ps
CPU time 0.98 seconds
Started Aug 12 05:35:01 PM PDT 24
Finished Aug 12 05:35:02 PM PDT 24
Peak memory 206732 kb
Host smart-963eedf5-5c27-4510-b3f0-78b924da33e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93762817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_
hw_reset.93762817
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1816744413
Short name T119
Test name
Test status
Simulation time 398581994 ps
CPU time 2.87 seconds
Started Aug 12 05:34:56 PM PDT 24
Finished Aug 12 05:34:59 PM PDT 24
Peak memory 217992 kb
Host smart-2ee1a26b-2c6e-4980-8e01-6f746c4cdab6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816744413 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1816744413
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2414059961
Short name T1107
Test name
Test status
Simulation time 215840130 ps
CPU time 1.91 seconds
Started Aug 12 05:35:06 PM PDT 24
Finished Aug 12 05:35:08 PM PDT 24
Peak memory 207004 kb
Host smart-48f5913e-98a0-495a-b29b-c63c2a08f694
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414059961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
414059961
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.394149530
Short name T1151
Test name
Test status
Simulation time 38727299 ps
CPU time 0.72 seconds
Started Aug 12 05:35:06 PM PDT 24
Finished Aug 12 05:35:07 PM PDT 24
Peak memory 203648 kb
Host smart-b92f1304-e03b-457b-ab7c-a12f0eb4866c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394149530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.394149530
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2190772071
Short name T135
Test name
Test status
Simulation time 280722505 ps
CPU time 1.67 seconds
Started Aug 12 05:35:17 PM PDT 24
Finished Aug 12 05:35:19 PM PDT 24
Peak memory 215268 kb
Host smart-6787381c-b7be-4854-a177-9aab92e4dd7d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190772071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2190772071
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1839671920
Short name T1150
Test name
Test status
Simulation time 19676307 ps
CPU time 0.66 seconds
Started Aug 12 05:35:08 PM PDT 24
Finished Aug 12 05:35:09 PM PDT 24
Peak memory 203920 kb
Host smart-773e271d-f5ca-4cd8-9af0-d1689a41d7ae
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839671920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1839671920
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1420850514
Short name T152
Test name
Test status
Simulation time 55036512 ps
CPU time 1.72 seconds
Started Aug 12 05:35:10 PM PDT 24
Finished Aug 12 05:35:12 PM PDT 24
Peak memory 215216 kb
Host smart-cebd036e-bd8a-423b-824c-b4a193025dfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420850514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1420850514
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.649465724
Short name T1141
Test name
Test status
Simulation time 408099387 ps
CPU time 6.29 seconds
Started Aug 12 05:35:24 PM PDT 24
Finished Aug 12 05:35:30 PM PDT 24
Peak memory 215372 kb
Host smart-ff80938f-2a9e-42e3-a8f2-08cc6a8ec1d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649465724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.649465724
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1259184331
Short name T1044
Test name
Test status
Simulation time 10380924 ps
CPU time 0.73 seconds
Started Aug 12 05:35:28 PM PDT 24
Finished Aug 12 05:35:29 PM PDT 24
Peak memory 204048 kb
Host smart-78773f37-61a3-4e34-8026-51e9c7e8fd66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259184331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1259184331
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1391596299
Short name T1147
Test name
Test status
Simulation time 41737256 ps
CPU time 0.68 seconds
Started Aug 12 05:35:33 PM PDT 24
Finished Aug 12 05:35:33 PM PDT 24
Peak memory 204056 kb
Host smart-d0efb84d-5618-49f5-af5c-59a95d021d97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391596299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1391596299
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3714048489
Short name T1108
Test name
Test status
Simulation time 66315700 ps
CPU time 0.74 seconds
Started Aug 12 05:35:49 PM PDT 24
Finished Aug 12 05:35:50 PM PDT 24
Peak memory 203732 kb
Host smart-440aaa42-1b75-4d75-a188-7e35940e8e46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714048489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3714048489
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4082865770
Short name T1068
Test name
Test status
Simulation time 58666779 ps
CPU time 0.7 seconds
Started Aug 12 05:35:28 PM PDT 24
Finished Aug 12 05:35:28 PM PDT 24
Peak memory 204072 kb
Host smart-305f821a-4e9d-4478-8115-b3fe1db21d9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082865770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4082865770
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.475168088
Short name T1046
Test name
Test status
Simulation time 11824665 ps
CPU time 0.74 seconds
Started Aug 12 05:35:29 PM PDT 24
Finished Aug 12 05:35:30 PM PDT 24
Peak memory 203768 kb
Host smart-57c125c1-bc44-4be8-a5a3-5360f12b6f31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475168088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.475168088
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3782967813
Short name T1066
Test name
Test status
Simulation time 78963604 ps
CPU time 0.75 seconds
Started Aug 12 05:35:25 PM PDT 24
Finished Aug 12 05:35:26 PM PDT 24
Peak memory 203728 kb
Host smart-2205c853-7e34-4051-ae88-f79115a40abb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782967813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3782967813
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.322225985
Short name T1101
Test name
Test status
Simulation time 31933920 ps
CPU time 0.67 seconds
Started Aug 12 05:35:42 PM PDT 24
Finished Aug 12 05:35:43 PM PDT 24
Peak memory 203724 kb
Host smart-094a8a55-5786-422d-b5d9-778b6fa0a051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322225985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.322225985
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1779196771
Short name T1053
Test name
Test status
Simulation time 19244906 ps
CPU time 0.75 seconds
Started Aug 12 05:35:32 PM PDT 24
Finished Aug 12 05:35:32 PM PDT 24
Peak memory 203808 kb
Host smart-7a1fd265-f00b-4332-b249-d8910e36de99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779196771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1779196771
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.996473238
Short name T1064
Test name
Test status
Simulation time 24173496 ps
CPU time 0.78 seconds
Started Aug 12 05:36:02 PM PDT 24
Finished Aug 12 05:36:03 PM PDT 24
Peak memory 203696 kb
Host smart-510172a8-6fd1-46aa-a1e4-f8a5a085519d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996473238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.996473238
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3298036627
Short name T1098
Test name
Test status
Simulation time 14969897 ps
CPU time 0.71 seconds
Started Aug 12 05:35:27 PM PDT 24
Finished Aug 12 05:35:28 PM PDT 24
Peak memory 203708 kb
Host smart-b5bbfa0e-6f06-4914-b532-f221cabbbe07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298036627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3298036627
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4111100529
Short name T134
Test name
Test status
Simulation time 719047260 ps
CPU time 15.05 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:41 PM PDT 24
Peak memory 215140 kb
Host smart-50db0e53-b736-4fbe-9545-0c812b9a341b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111100529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4111100529
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2355412692
Short name T1129
Test name
Test status
Simulation time 1222619027 ps
CPU time 13.43 seconds
Started Aug 12 05:35:01 PM PDT 24
Finished Aug 12 05:35:15 PM PDT 24
Peak memory 215124 kb
Host smart-ecbfd00a-6928-4aaf-8ffa-464fd80f468e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355412692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2355412692
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.165511054
Short name T96
Test name
Test status
Simulation time 81131862 ps
CPU time 1.36 seconds
Started Aug 12 05:35:04 PM PDT 24
Finished Aug 12 05:35:05 PM PDT 24
Peak memory 206960 kb
Host smart-50471dcc-7a6a-4262-b412-ef74415f27e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165511054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.165511054
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3405368121
Short name T1078
Test name
Test status
Simulation time 47364086 ps
CPU time 1.71 seconds
Started Aug 12 05:35:20 PM PDT 24
Finished Aug 12 05:35:22 PM PDT 24
Peak memory 216272 kb
Host smart-0d41d965-9439-495e-997b-9208f98adc80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405368121 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3405368121
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2079834582
Short name T1088
Test name
Test status
Simulation time 65185893 ps
CPU time 1.29 seconds
Started Aug 12 05:35:15 PM PDT 24
Finished Aug 12 05:35:17 PM PDT 24
Peak memory 207028 kb
Host smart-87782d34-bf5c-4d00-8d6e-c15d28b841f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079834582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
079834582
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3916582825
Short name T1094
Test name
Test status
Simulation time 14153624 ps
CPU time 0.73 seconds
Started Aug 12 05:34:52 PM PDT 24
Finished Aug 12 05:34:53 PM PDT 24
Peak memory 203708 kb
Host smart-4fd169d0-f8f6-4982-b874-c8b9a489f55c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916582825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
916582825
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1145919834
Short name T1085
Test name
Test status
Simulation time 61442678 ps
CPU time 2.22 seconds
Started Aug 12 05:35:08 PM PDT 24
Finished Aug 12 05:35:10 PM PDT 24
Peak memory 215312 kb
Host smart-a1612083-80a3-43a9-94a4-3ec8aa038ed4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145919834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1145919834
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.153444416
Short name T1047
Test name
Test status
Simulation time 99861950 ps
CPU time 0.67 seconds
Started Aug 12 05:34:52 PM PDT 24
Finished Aug 12 05:34:53 PM PDT 24
Peak memory 203552 kb
Host smart-79566e1d-9dc2-4d1a-8e5c-e9b73c6ad102
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153444416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.153444416
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2046241867
Short name T1095
Test name
Test status
Simulation time 236404372 ps
CPU time 3.85 seconds
Started Aug 12 05:34:54 PM PDT 24
Finished Aug 12 05:34:58 PM PDT 24
Peak memory 215952 kb
Host smart-e3645067-d220-4149-9056-9f74f9372a55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046241867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2046241867
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1541897331
Short name T1131
Test name
Test status
Simulation time 76466616 ps
CPU time 4.4 seconds
Started Aug 12 05:35:14 PM PDT 24
Finished Aug 12 05:35:18 PM PDT 24
Peak memory 215380 kb
Host smart-3d220871-3f3e-40bd-b7ae-e371266e1355
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541897331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
541897331
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4085000245
Short name T1106
Test name
Test status
Simulation time 9017583113 ps
CPU time 22.07 seconds
Started Aug 12 05:35:01 PM PDT 24
Finished Aug 12 05:35:23 PM PDT 24
Peak memory 215420 kb
Host smart-88a07f33-19bc-4428-b955-2235c5b7f04c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085000245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.4085000245
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.363523985
Short name T1061
Test name
Test status
Simulation time 14841493 ps
CPU time 0.74 seconds
Started Aug 12 05:35:18 PM PDT 24
Finished Aug 12 05:35:18 PM PDT 24
Peak memory 203756 kb
Host smart-bae9cc82-0dc6-4b2e-93d2-20b8dab37b3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363523985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.363523985
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4146227516
Short name T1089
Test name
Test status
Simulation time 14382284 ps
CPU time 0.76 seconds
Started Aug 12 05:35:17 PM PDT 24
Finished Aug 12 05:35:18 PM PDT 24
Peak memory 203748 kb
Host smart-3de75370-cb34-4965-adda-4e0c8f33196f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146227516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
4146227516
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2838959114
Short name T1082
Test name
Test status
Simulation time 52626170 ps
CPU time 0.73 seconds
Started Aug 12 05:35:37 PM PDT 24
Finished Aug 12 05:35:38 PM PDT 24
Peak memory 203740 kb
Host smart-14875e5e-ea3c-4b4c-bfde-7cd0bd78d125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838959114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2838959114
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4183450486
Short name T1057
Test name
Test status
Simulation time 72147288 ps
CPU time 0.76 seconds
Started Aug 12 05:35:25 PM PDT 24
Finished Aug 12 05:35:26 PM PDT 24
Peak memory 203740 kb
Host smart-33754c3f-4031-49b4-b520-05f905f3668e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183450486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4183450486
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2956619968
Short name T1100
Test name
Test status
Simulation time 83512587 ps
CPU time 0.76 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:27 PM PDT 24
Peak memory 203804 kb
Host smart-a4576b52-7b97-4d44-9e49-159801759164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956619968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2956619968
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.26979743
Short name T1074
Test name
Test status
Simulation time 12857570 ps
CPU time 0.7 seconds
Started Aug 12 05:35:33 PM PDT 24
Finished Aug 12 05:35:33 PM PDT 24
Peak memory 204044 kb
Host smart-5aed8be0-076e-4059-ab23-dd1f575c7dfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26979743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.26979743
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2181344039
Short name T1054
Test name
Test status
Simulation time 12241105 ps
CPU time 0.7 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:27 PM PDT 24
Peak memory 204052 kb
Host smart-9778541e-775d-4ace-83b6-3e5eea4ce38a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181344039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2181344039
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1187526960
Short name T1126
Test name
Test status
Simulation time 33488249 ps
CPU time 0.74 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:27 PM PDT 24
Peak memory 203672 kb
Host smart-9d6babc4-c2ad-45e3-95e0-2b4358a3696a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187526960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1187526960
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3318159189
Short name T1113
Test name
Test status
Simulation time 61044716 ps
CPU time 0.67 seconds
Started Aug 12 05:35:35 PM PDT 24
Finished Aug 12 05:35:35 PM PDT 24
Peak memory 203744 kb
Host smart-55d7f476-7188-4fa1-8666-a2c01ac57330
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318159189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3318159189
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1260917918
Short name T1115
Test name
Test status
Simulation time 14389509 ps
CPU time 0.74 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:26 PM PDT 24
Peak memory 203992 kb
Host smart-86f8afed-6c5a-4d5f-b723-49db9c17ba6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260917918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1260917918
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2505033121
Short name T1110
Test name
Test status
Simulation time 304037423 ps
CPU time 3.61 seconds
Started Aug 12 05:35:12 PM PDT 24
Finished Aug 12 05:35:16 PM PDT 24
Peak memory 218008 kb
Host smart-ea60fee1-dd76-46dc-9882-29e72593f9ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505033121 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2505033121
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1433974845
Short name T140
Test name
Test status
Simulation time 39856697 ps
CPU time 1.3 seconds
Started Aug 12 05:35:08 PM PDT 24
Finished Aug 12 05:35:10 PM PDT 24
Peak memory 207036 kb
Host smart-d27c02bd-8a8d-4b01-b95e-9c858d2a2803
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433974845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
433974845
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3985554888
Short name T1042
Test name
Test status
Simulation time 28531414 ps
CPU time 0.77 seconds
Started Aug 12 05:35:24 PM PDT 24
Finished Aug 12 05:35:25 PM PDT 24
Peak memory 203752 kb
Host smart-5faca764-5821-45c4-9fd0-c2d761201487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985554888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
985554888
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.547701638
Short name T1075
Test name
Test status
Simulation time 668393696 ps
CPU time 2.9 seconds
Started Aug 12 05:35:17 PM PDT 24
Finished Aug 12 05:35:20 PM PDT 24
Peak memory 215212 kb
Host smart-02c5e3f2-10e6-4dff-9c78-f7e973dd5c29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547701638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.547701638
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2223321643
Short name T106
Test name
Test status
Simulation time 67936295 ps
CPU time 1.82 seconds
Started Aug 12 05:35:23 PM PDT 24
Finished Aug 12 05:35:25 PM PDT 24
Peak memory 216444 kb
Host smart-401bbe92-c896-4976-abda-cb19b2d0dcdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223321643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
223321643
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3118503754
Short name T1136
Test name
Test status
Simulation time 361308378 ps
CPU time 7.73 seconds
Started Aug 12 05:34:51 PM PDT 24
Finished Aug 12 05:34:59 PM PDT 24
Peak memory 216040 kb
Host smart-ed578940-2f17-4f50-b81a-48265eb35f10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118503754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3118503754
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4015202790
Short name T124
Test name
Test status
Simulation time 54534825 ps
CPU time 1.65 seconds
Started Aug 12 05:35:46 PM PDT 24
Finished Aug 12 05:35:48 PM PDT 24
Peak memory 215380 kb
Host smart-d1170b50-f6f5-4ba9-ad24-897614a5ebf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015202790 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4015202790
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3690909048
Short name T130
Test name
Test status
Simulation time 125642651 ps
CPU time 2.2 seconds
Started Aug 12 05:35:20 PM PDT 24
Finished Aug 12 05:35:22 PM PDT 24
Peak memory 215216 kb
Host smart-bdcb2381-d53b-4dd8-9c29-7cced2422204
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690909048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
690909048
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2218336670
Short name T1038
Test name
Test status
Simulation time 23157962 ps
CPU time 0.72 seconds
Started Aug 12 05:35:01 PM PDT 24
Finished Aug 12 05:35:02 PM PDT 24
Peak memory 203748 kb
Host smart-16334113-e84f-41a5-b181-7b563c24ddd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218336670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
218336670
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.943459327
Short name T154
Test name
Test status
Simulation time 28229453 ps
CPU time 1.65 seconds
Started Aug 12 05:35:05 PM PDT 24
Finished Aug 12 05:35:07 PM PDT 24
Peak memory 215172 kb
Host smart-5a723e9f-116e-4069-be11-e3acd0859f3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943459327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.943459327
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3026279981
Short name T117
Test name
Test status
Simulation time 99451853 ps
CPU time 1.63 seconds
Started Aug 12 05:35:16 PM PDT 24
Finished Aug 12 05:35:18 PM PDT 24
Peak memory 215640 kb
Host smart-22168d5a-7dd8-40d3-ac3c-ff29557f6d95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026279981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
026279981
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2274599522
Short name T204
Test name
Test status
Simulation time 551645420 ps
CPU time 13.68 seconds
Started Aug 12 05:34:51 PM PDT 24
Finished Aug 12 05:35:10 PM PDT 24
Peak memory 215312 kb
Host smart-ada54a16-d027-487c-9027-a269c6adc9f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274599522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2274599522
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2705120289
Short name T1124
Test name
Test status
Simulation time 118502645 ps
CPU time 2.85 seconds
Started Aug 12 05:35:13 PM PDT 24
Finished Aug 12 05:35:16 PM PDT 24
Peak memory 217940 kb
Host smart-0414959a-1041-47a8-b4bf-334cf64faff3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705120289 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2705120289
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3480421052
Short name T137
Test name
Test status
Simulation time 562219715 ps
CPU time 1.91 seconds
Started Aug 12 05:35:21 PM PDT 24
Finished Aug 12 05:35:23 PM PDT 24
Peak memory 215064 kb
Host smart-9df6698c-eec7-4886-a34c-07d9606627c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480421052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
480421052
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.413164716
Short name T1051
Test name
Test status
Simulation time 54650207 ps
CPU time 0.72 seconds
Started Aug 12 05:35:11 PM PDT 24
Finished Aug 12 05:35:12 PM PDT 24
Peak memory 203768 kb
Host smart-adf8f355-49e8-475c-ab5f-37f92f8cdf30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413164716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.413164716
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4058477752
Short name T1140
Test name
Test status
Simulation time 92385412 ps
CPU time 1.6 seconds
Started Aug 12 05:35:29 PM PDT 24
Finished Aug 12 05:35:31 PM PDT 24
Peak memory 215112 kb
Host smart-934d216e-6869-4918-92d6-b73731115dbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058477752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4058477752
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.548782306
Short name T206
Test name
Test status
Simulation time 564472580 ps
CPU time 7.45 seconds
Started Aug 12 05:35:14 PM PDT 24
Finished Aug 12 05:35:26 PM PDT 24
Peak memory 215236 kb
Host smart-bc1a8bbc-1900-4405-b141-ad19856d0ada
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548782306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.548782306
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1796875008
Short name T1092
Test name
Test status
Simulation time 611242054 ps
CPU time 3.47 seconds
Started Aug 12 05:35:02 PM PDT 24
Finished Aug 12 05:35:06 PM PDT 24
Peak memory 216344 kb
Host smart-be94c561-cd0b-4463-be07-16e5d08ba6fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796875008 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1796875008
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3750584833
Short name T132
Test name
Test status
Simulation time 37777190 ps
CPU time 2.23 seconds
Started Aug 12 05:35:06 PM PDT 24
Finished Aug 12 05:35:08 PM PDT 24
Peak memory 215148 kb
Host smart-afe6b572-26ed-49e3-843c-bec5a9b6a6dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750584833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
750584833
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1533352476
Short name T1062
Test name
Test status
Simulation time 34283794 ps
CPU time 0.71 seconds
Started Aug 12 05:35:18 PM PDT 24
Finished Aug 12 05:35:19 PM PDT 24
Peak memory 203656 kb
Host smart-5392a45a-04df-4b57-87a4-97dc7e74c439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533352476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
533352476
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4028517418
Short name T1138
Test name
Test status
Simulation time 151894120 ps
CPU time 4.19 seconds
Started Aug 12 05:34:53 PM PDT 24
Finished Aug 12 05:34:57 PM PDT 24
Peak memory 215276 kb
Host smart-f763b20d-d24a-45c7-a264-4b057c4b06d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028517418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.4028517418
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.4054654545
Short name T1122
Test name
Test status
Simulation time 144346937 ps
CPU time 5.33 seconds
Started Aug 12 05:35:04 PM PDT 24
Finished Aug 12 05:35:09 PM PDT 24
Peak memory 215420 kb
Host smart-501cf9de-7ff4-4d3f-b07a-9d4cf14da518
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054654545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.4
054654545
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1499292003
Short name T202
Test name
Test status
Simulation time 741869170 ps
CPU time 11.75 seconds
Started Aug 12 05:35:05 PM PDT 24
Finished Aug 12 05:35:16 PM PDT 24
Peak memory 215232 kb
Host smart-cf71c517-d774-48ab-87c5-b1ef070ec959
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499292003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1499292003
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3795457816
Short name T1083
Test name
Test status
Simulation time 41569953 ps
CPU time 2.37 seconds
Started Aug 12 05:35:12 PM PDT 24
Finished Aug 12 05:35:15 PM PDT 24
Peak memory 216404 kb
Host smart-c362bcaa-19b8-4619-8062-cc673d6f7ce1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795457816 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3795457816
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.473433859
Short name T141
Test name
Test status
Simulation time 36578982 ps
CPU time 1.25 seconds
Started Aug 12 05:35:13 PM PDT 24
Finished Aug 12 05:35:15 PM PDT 24
Peak memory 215204 kb
Host smart-9d64f7bb-04c3-4090-b98b-4e76facfac55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473433859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.473433859
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3548954142
Short name T1123
Test name
Test status
Simulation time 38686321 ps
CPU time 0.77 seconds
Started Aug 12 05:35:24 PM PDT 24
Finished Aug 12 05:35:24 PM PDT 24
Peak memory 203736 kb
Host smart-6ae8ba97-e06f-473d-8655-9c5c79a33f1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548954142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
548954142
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.872085746
Short name T151
Test name
Test status
Simulation time 219600693 ps
CPU time 3.02 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:29 PM PDT 24
Peak memory 215312 kb
Host smart-9497abda-e08c-4d91-92ca-950ec34f9061
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872085746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.872085746
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.286968276
Short name T1119
Test name
Test status
Simulation time 53353775 ps
CPU time 2.94 seconds
Started Aug 12 05:35:14 PM PDT 24
Finished Aug 12 05:35:17 PM PDT 24
Peak memory 215412 kb
Host smart-a6f619dc-609d-4e81-b91f-c445b69a11a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286968276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.286968276
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3819702912
Short name T477
Test name
Test status
Simulation time 105768470 ps
CPU time 0.72 seconds
Started Aug 12 05:35:27 PM PDT 24
Finished Aug 12 05:35:28 PM PDT 24
Peak memory 205320 kb
Host smart-cd552b1f-cccc-48ae-b4d9-4959ced1cee7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819702912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
819702912
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.451716652
Short name T712
Test name
Test status
Simulation time 21049194 ps
CPU time 0.82 seconds
Started Aug 12 05:35:39 PM PDT 24
Finished Aug 12 05:35:40 PM PDT 24
Peak memory 206520 kb
Host smart-6737368c-fa31-43d8-8f7a-44979aa4b7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451716652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.451716652
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4229924000
Short name T788
Test name
Test status
Simulation time 9429181516 ps
CPU time 81.99 seconds
Started Aug 12 05:35:28 PM PDT 24
Finished Aug 12 05:36:50 PM PDT 24
Peak memory 265220 kb
Host smart-ed9d2026-ae52-406a-96b0-297e85c1bc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229924000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4229924000
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3599056131
Short name T724
Test name
Test status
Simulation time 33150032 ps
CPU time 0.79 seconds
Started Aug 12 05:35:49 PM PDT 24
Finished Aug 12 05:35:50 PM PDT 24
Peak memory 217032 kb
Host smart-565018fb-9e96-4112-880a-f537f2230034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599056131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3599056131
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.689765171
Short name T807
Test name
Test status
Simulation time 51745857397 ps
CPU time 202.81 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:38:49 PM PDT 24
Peak memory 249420 kb
Host smart-1cc3d63f-17b7-4570-bd70-b4d29ff96603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689765171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
689765171
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2499509464
Short name T183
Test name
Test status
Simulation time 4695587811 ps
CPU time 70.1 seconds
Started Aug 12 05:35:21 PM PDT 24
Finished Aug 12 05:36:31 PM PDT 24
Peak memory 253212 kb
Host smart-91ffe3ab-1792-4617-b6d4-979f08de7b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499509464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2499509464
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1119931483
Short name T237
Test name
Test status
Simulation time 3575315027 ps
CPU time 80.02 seconds
Started Aug 12 05:35:32 PM PDT 24
Finished Aug 12 05:36:52 PM PDT 24
Peak memory 250640 kb
Host smart-ceb667fc-20fb-45d9-b291-d18a21617806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119931483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1119931483
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2176027600
Short name T649
Test name
Test status
Simulation time 2258716006 ps
CPU time 19.8 seconds
Started Aug 12 05:35:38 PM PDT 24
Finished Aug 12 05:35:58 PM PDT 24
Peak memory 224788 kb
Host smart-d0934c50-20e3-4ffc-9848-c1959a9bba69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176027600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2176027600
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3750511447
Short name T453
Test name
Test status
Simulation time 145259326 ps
CPU time 4.7 seconds
Started Aug 12 05:35:40 PM PDT 24
Finished Aug 12 05:35:45 PM PDT 24
Peak memory 224720 kb
Host smart-689f8691-b09e-4a1a-940a-caf9d2c8ec65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750511447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3750511447
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3192296293
Short name T994
Test name
Test status
Simulation time 22756114755 ps
CPU time 16.58 seconds
Started Aug 12 05:35:24 PM PDT 24
Finished Aug 12 05:35:41 PM PDT 24
Peak memory 232992 kb
Host smart-092ed8cb-f212-4ec5-9495-e6f77e7967c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192296293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3192296293
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2501419971
Short name T549
Test name
Test status
Simulation time 516785439 ps
CPU time 6.95 seconds
Started Aug 12 05:35:45 PM PDT 24
Finished Aug 12 05:35:52 PM PDT 24
Peak memory 240880 kb
Host smart-afc76c4a-d42d-4c26-90ed-86c8adb3c45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501419971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2501419971
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3873599602
Short name T722
Test name
Test status
Simulation time 237094232 ps
CPU time 4.72 seconds
Started Aug 12 05:35:53 PM PDT 24
Finished Aug 12 05:36:03 PM PDT 24
Peak memory 222772 kb
Host smart-4e4047ec-eb7f-4e5d-a2ff-6d8ad22f006c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3873599602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3873599602
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3611291467
Short name T143
Test name
Test status
Simulation time 4864784058 ps
CPU time 25.23 seconds
Started Aug 12 05:35:33 PM PDT 24
Finished Aug 12 05:35:58 PM PDT 24
Peak memory 216724 kb
Host smart-1dc2949d-a41f-4681-8bb5-cb90a4b09ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611291467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3611291467
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2372477256
Short name T417
Test name
Test status
Simulation time 190279831 ps
CPU time 1.66 seconds
Started Aug 12 05:35:39 PM PDT 24
Finished Aug 12 05:35:41 PM PDT 24
Peak memory 207948 kb
Host smart-ec9e8595-d950-4600-8be2-f48478a55b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372477256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2372477256
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2975431000
Short name T380
Test name
Test status
Simulation time 108275077 ps
CPU time 1.32 seconds
Started Aug 12 05:35:38 PM PDT 24
Finished Aug 12 05:35:39 PM PDT 24
Peak memory 216316 kb
Host smart-e37e68e3-53c9-4370-b92f-2c93a5432b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975431000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2975431000
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3321703006
Short name T324
Test name
Test status
Simulation time 21710488 ps
CPU time 0.78 seconds
Started Aug 12 05:35:43 PM PDT 24
Finished Aug 12 05:35:44 PM PDT 24
Peak memory 206024 kb
Host smart-f36a397e-4d5d-4beb-ba73-5953c711d6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321703006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3321703006
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2463843720
Short name T291
Test name
Test status
Simulation time 2476694095 ps
CPU time 11.8 seconds
Started Aug 12 05:35:37 PM PDT 24
Finished Aug 12 05:35:49 PM PDT 24
Peak memory 224644 kb
Host smart-8dbdd6fd-b1a2-4e35-82cb-b6a75ea483e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463843720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2463843720
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3527104379
Short name T535
Test name
Test status
Simulation time 57617206 ps
CPU time 0.7 seconds
Started Aug 12 05:35:38 PM PDT 24
Finished Aug 12 05:35:39 PM PDT 24
Peak memory 205336 kb
Host smart-0a93295d-36e7-402c-bc35-24062aa32b20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527104379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
527104379
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3626042760
Short name T343
Test name
Test status
Simulation time 98856727 ps
CPU time 2.42 seconds
Started Aug 12 05:35:43 PM PDT 24
Finished Aug 12 05:35:46 PM PDT 24
Peak memory 232484 kb
Host smart-89a91c89-2381-423b-877e-efe3deda6917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626042760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3626042760
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2786324523
Short name T399
Test name
Test status
Simulation time 59438405 ps
CPU time 0.82 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:27 PM PDT 24
Peak memory 206460 kb
Host smart-4734d871-f6d5-4995-9c87-86a981453583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786324523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2786324523
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3881187825
Short name T50
Test name
Test status
Simulation time 29147450202 ps
CPU time 207.26 seconds
Started Aug 12 05:35:42 PM PDT 24
Finished Aug 12 05:39:09 PM PDT 24
Peak memory 253616 kb
Host smart-f3f1425b-a76f-49bf-9965-8542dae78e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881187825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3881187825
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.955057610
Short name T194
Test name
Test status
Simulation time 43548872407 ps
CPU time 351.46 seconds
Started Aug 12 05:35:39 PM PDT 24
Finished Aug 12 05:41:30 PM PDT 24
Peak memory 255324 kb
Host smart-94f8004c-2acb-4040-a10c-e5fc0a0561a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955057610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.955057610
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3114602593
Short name T943
Test name
Test status
Simulation time 22670893836 ps
CPU time 95.08 seconds
Started Aug 12 05:35:41 PM PDT 24
Finished Aug 12 05:37:16 PM PDT 24
Peak memory 251616 kb
Host smart-5612777c-891c-48ec-853b-56a2ae441936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114602593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3114602593
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.35918887
Short name T767
Test name
Test status
Simulation time 20528581430 ps
CPU time 17.44 seconds
Started Aug 12 05:35:50 PM PDT 24
Finished Aug 12 05:36:08 PM PDT 24
Peak memory 224788 kb
Host smart-8a070378-8ad3-4f46-a5fe-f3da6c7172f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35918887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.35918887
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2657302186
Short name T48
Test name
Test status
Simulation time 2905200581 ps
CPU time 37.12 seconds
Started Aug 12 05:35:40 PM PDT 24
Finished Aug 12 05:36:17 PM PDT 24
Peak memory 255588 kb
Host smart-3ec9517d-cb9a-45b3-8f89-6e90f1a99503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657302186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2657302186
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.410710847
Short name T1024
Test name
Test status
Simulation time 168028174 ps
CPU time 3.92 seconds
Started Aug 12 05:35:27 PM PDT 24
Finished Aug 12 05:35:31 PM PDT 24
Peak memory 232904 kb
Host smart-8a050e97-33c9-4d0d-841d-b099f75d4ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410710847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.410710847
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.413904188
Short name T578
Test name
Test status
Simulation time 6057224952 ps
CPU time 37.68 seconds
Started Aug 12 05:35:42 PM PDT 24
Finished Aug 12 05:36:19 PM PDT 24
Peak memory 234308 kb
Host smart-606ec410-16e4-4986-ac72-acb91656d35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413904188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.413904188
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.886136266
Short name T46
Test name
Test status
Simulation time 22428998 ps
CPU time 1 seconds
Started Aug 12 05:35:38 PM PDT 24
Finished Aug 12 05:35:39 PM PDT 24
Peak memory 216640 kb
Host smart-fd3ede8d-fbd4-426d-aceb-4169db2105b3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886136266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.886136266
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4064909639
Short name T787
Test name
Test status
Simulation time 3685952743 ps
CPU time 11.41 seconds
Started Aug 12 05:36:11 PM PDT 24
Finished Aug 12 05:36:32 PM PDT 24
Peak memory 224696 kb
Host smart-b55398e7-a1a2-4562-b421-475db8259892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064909639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4064909639
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3468584788
Short name T824
Test name
Test status
Simulation time 1265547359 ps
CPU time 2.98 seconds
Started Aug 12 05:35:35 PM PDT 24
Finished Aug 12 05:35:38 PM PDT 24
Peak memory 224664 kb
Host smart-48943db0-e174-4d42-be19-28cc0b00fc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468584788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3468584788
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3536219305
Short name T965
Test name
Test status
Simulation time 1610714789 ps
CPU time 5.63 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:32 PM PDT 24
Peak memory 219404 kb
Host smart-990b01ac-9dab-4f23-a97b-db5ba7326911
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3536219305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3536219305
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3858210481
Short name T78
Test name
Test status
Simulation time 350845294 ps
CPU time 1.21 seconds
Started Aug 12 05:35:40 PM PDT 24
Finished Aug 12 05:35:41 PM PDT 24
Peak memory 236908 kb
Host smart-749fa8b9-65eb-4112-b722-1df9fcff275d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858210481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3858210481
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.139017305
Short name T568
Test name
Test status
Simulation time 24383315639 ps
CPU time 103.57 seconds
Started Aug 12 05:35:49 PM PDT 24
Finished Aug 12 05:37:33 PM PDT 24
Peak memory 252336 kb
Host smart-6473f14b-f492-4e83-a964-c61ca2e39b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139017305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.139017305
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3642879284
Short name T550
Test name
Test status
Simulation time 719518028 ps
CPU time 3.07 seconds
Started Aug 12 05:35:37 PM PDT 24
Finished Aug 12 05:35:40 PM PDT 24
Peak memory 216444 kb
Host smart-0c41c92d-8ebf-44df-80ae-f3f8b65add25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642879284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3642879284
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.726376619
Short name T548
Test name
Test status
Simulation time 1097827610 ps
CPU time 4.17 seconds
Started Aug 12 05:35:43 PM PDT 24
Finished Aug 12 05:35:47 PM PDT 24
Peak memory 216296 kb
Host smart-673d000e-a430-469d-9185-ef1ea3ef8122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726376619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.726376619
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.632820239
Short name T495
Test name
Test status
Simulation time 786843449 ps
CPU time 0.83 seconds
Started Aug 12 05:35:35 PM PDT 24
Finished Aug 12 05:35:36 PM PDT 24
Peak memory 206012 kb
Host smart-741c3905-77c0-430a-b265-fa24907db1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632820239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.632820239
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2989081928
Short name T494
Test name
Test status
Simulation time 112467803 ps
CPU time 2.93 seconds
Started Aug 12 05:35:36 PM PDT 24
Finished Aug 12 05:35:39 PM PDT 24
Peak memory 232836 kb
Host smart-1a738f17-7697-47ff-8e9c-547b779da727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989081928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2989081928
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.675417410
Short name T825
Test name
Test status
Simulation time 13980071 ps
CPU time 0.74 seconds
Started Aug 12 05:35:57 PM PDT 24
Finished Aug 12 05:35:57 PM PDT 24
Peak memory 204648 kb
Host smart-860b693b-4392-491a-8736-ebabc5195127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675417410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.675417410
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.948758191
Short name T904
Test name
Test status
Simulation time 826241781 ps
CPU time 4.02 seconds
Started Aug 12 05:36:08 PM PDT 24
Finished Aug 12 05:36:22 PM PDT 24
Peak memory 232816 kb
Host smart-66ba8229-f37f-4e9c-b484-dd924aa6b64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948758191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.948758191
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2928689364
Short name T638
Test name
Test status
Simulation time 35172277 ps
CPU time 0.77 seconds
Started Aug 12 05:35:59 PM PDT 24
Finished Aug 12 05:35:59 PM PDT 24
Peak memory 206508 kb
Host smart-70d9cab2-b527-4842-a3c6-2d9212178b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928689364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2928689364
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1500883160
Short name T988
Test name
Test status
Simulation time 21367176469 ps
CPU time 42.42 seconds
Started Aug 12 05:36:01 PM PDT 24
Finished Aug 12 05:36:44 PM PDT 24
Peak memory 249376 kb
Host smart-62a10958-0967-46be-88b6-3fe2051a1039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500883160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1500883160
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.4276500826
Short name T897
Test name
Test status
Simulation time 52157765164 ps
CPU time 520.88 seconds
Started Aug 12 05:36:05 PM PDT 24
Finished Aug 12 05:44:46 PM PDT 24
Peak memory 272996 kb
Host smart-5c47d457-5b36-4b56-bd7b-128f0602717f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276500826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.4276500826
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1210472533
Short name T192
Test name
Test status
Simulation time 8066127108 ps
CPU time 22.18 seconds
Started Aug 12 05:36:00 PM PDT 24
Finished Aug 12 05:36:23 PM PDT 24
Peak memory 232912 kb
Host smart-5f9d4e5e-3788-445d-91e6-3a2af5b8f695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210472533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1210472533
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2899853208
Short name T303
Test name
Test status
Simulation time 92819247995 ps
CPU time 206.61 seconds
Started Aug 12 05:35:44 PM PDT 24
Finished Aug 12 05:39:11 PM PDT 24
Peak memory 265876 kb
Host smart-c3287d31-ff04-4705-86ae-c0dcec3819c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899853208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2899853208
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.441903254
Short name T330
Test name
Test status
Simulation time 3233854146 ps
CPU time 11.53 seconds
Started Aug 12 05:36:01 PM PDT 24
Finished Aug 12 05:36:13 PM PDT 24
Peak memory 232964 kb
Host smart-764c7b31-ba28-421f-a462-17efe201f6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441903254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.441903254
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2612321977
Short name T588
Test name
Test status
Simulation time 96329742 ps
CPU time 2.47 seconds
Started Aug 12 05:35:57 PM PDT 24
Finished Aug 12 05:35:59 PM PDT 24
Peak memory 232536 kb
Host smart-4d541d82-c503-4e8e-b8fa-b18921e7db67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612321977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2612321977
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1092358962
Short name T620
Test name
Test status
Simulation time 212513195 ps
CPU time 0.99 seconds
Started Aug 12 05:35:50 PM PDT 24
Finished Aug 12 05:35:51 PM PDT 24
Peak memory 217932 kb
Host smart-ac077ef4-8bb5-40c5-b42d-7026ab39e765
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092358962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1092358962
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.702565774
Short name T257
Test name
Test status
Simulation time 87165680 ps
CPU time 3.2 seconds
Started Aug 12 05:35:58 PM PDT 24
Finished Aug 12 05:36:01 PM PDT 24
Peak memory 232864 kb
Host smart-710e4f30-bc62-43c2-b429-d2156a67d3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702565774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.702565774
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1089419159
Short name T286
Test name
Test status
Simulation time 784054340 ps
CPU time 4.69 seconds
Started Aug 12 05:36:02 PM PDT 24
Finished Aug 12 05:36:06 PM PDT 24
Peak memory 232880 kb
Host smart-b2323f98-da36-42fa-aace-8f89f0dcc9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089419159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1089419159
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2525110254
Short name T394
Test name
Test status
Simulation time 4689559129 ps
CPU time 10.02 seconds
Started Aug 12 05:36:08 PM PDT 24
Finished Aug 12 05:36:18 PM PDT 24
Peak memory 220792 kb
Host smart-ae9f8f5a-5f17-4307-befe-f680c9f157fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2525110254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2525110254
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.472112332
Short name T463
Test name
Test status
Simulation time 188651481 ps
CPU time 1.11 seconds
Started Aug 12 05:36:00 PM PDT 24
Finished Aug 12 05:36:02 PM PDT 24
Peak memory 207028 kb
Host smart-e58adc08-23ef-488d-8d25-f7d80c0627f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472112332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.472112332
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3981839924
Short name T703
Test name
Test status
Simulation time 5660137792 ps
CPU time 15.58 seconds
Started Aug 12 05:36:12 PM PDT 24
Finished Aug 12 05:36:28 PM PDT 24
Peak memory 216572 kb
Host smart-e80916f8-eb44-4f9d-95d1-59030fb2d246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981839924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3981839924
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1074996455
Short name T834
Test name
Test status
Simulation time 14872411 ps
CPU time 0.79 seconds
Started Aug 12 05:36:06 PM PDT 24
Finished Aug 12 05:36:12 PM PDT 24
Peak memory 205580 kb
Host smart-7a9d1cae-6244-497e-86a7-303632ec59e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074996455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1074996455
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2154506815
Short name T467
Test name
Test status
Simulation time 39002679 ps
CPU time 1.09 seconds
Started Aug 12 05:36:06 PM PDT 24
Finished Aug 12 05:36:07 PM PDT 24
Peak memory 207904 kb
Host smart-6775353b-40f6-4688-b7ef-aff4c00fdc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154506815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2154506815
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1400463910
Short name T424
Test name
Test status
Simulation time 148083991 ps
CPU time 0.82 seconds
Started Aug 12 05:36:09 PM PDT 24
Finished Aug 12 05:36:10 PM PDT 24
Peak memory 206016 kb
Host smart-c1d1c2f6-d84b-45b1-9ceb-7d0453e219af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400463910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1400463910
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3448626269
Short name T412
Test name
Test status
Simulation time 1496380075 ps
CPU time 6.03 seconds
Started Aug 12 05:36:07 PM PDT 24
Finished Aug 12 05:36:13 PM PDT 24
Peak memory 224608 kb
Host smart-3a872927-2020-42c6-a2f9-d33f8a87a505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448626269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3448626269
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.790684523
Short name T369
Test name
Test status
Simulation time 14017451 ps
CPU time 0.78 seconds
Started Aug 12 05:35:57 PM PDT 24
Finished Aug 12 05:36:02 PM PDT 24
Peak memory 205296 kb
Host smart-c0ed89ed-0660-451b-98bd-f3b88fca31ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790684523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.790684523
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3565985111
Short name T818
Test name
Test status
Simulation time 55232176 ps
CPU time 2.45 seconds
Started Aug 12 05:35:58 PM PDT 24
Finished Aug 12 05:36:01 PM PDT 24
Peak memory 232536 kb
Host smart-74190c66-c3aa-491b-930b-f74f0aae7d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565985111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3565985111
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4236293379
Short name T619
Test name
Test status
Simulation time 30137184 ps
CPU time 0.78 seconds
Started Aug 12 05:36:19 PM PDT 24
Finished Aug 12 05:36:20 PM PDT 24
Peak memory 206400 kb
Host smart-d20a7f8a-0d36-4611-afda-d1965e91b439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236293379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4236293379
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2705402292
Short name T294
Test name
Test status
Simulation time 8531998350 ps
CPU time 28.17 seconds
Started Aug 12 05:36:00 PM PDT 24
Finished Aug 12 05:36:28 PM PDT 24
Peak memory 240572 kb
Host smart-46ea9d96-eb9e-474e-8eed-b7ea7d9592ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705402292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2705402292
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2555235595
Short name T527
Test name
Test status
Simulation time 7207078270 ps
CPU time 24.78 seconds
Started Aug 12 05:36:08 PM PDT 24
Finished Aug 12 05:36:33 PM PDT 24
Peak memory 241260 kb
Host smart-b9b8f620-3d59-4a1a-be44-cad9af437787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555235595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2555235595
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3337565646
Short name T842
Test name
Test status
Simulation time 222908337688 ps
CPU time 412.98 seconds
Started Aug 12 05:36:11 PM PDT 24
Finished Aug 12 05:43:04 PM PDT 24
Peak memory 256456 kb
Host smart-1fee6ecb-ca40-4e38-abdc-090b3c4a630f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337565646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3337565646
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1345542300
Short name T1028
Test name
Test status
Simulation time 189372226 ps
CPU time 5.21 seconds
Started Aug 12 05:36:00 PM PDT 24
Finished Aug 12 05:36:05 PM PDT 24
Peak memory 238076 kb
Host smart-0cf195e5-805c-4796-96ae-20f64bd30361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345542300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1345542300
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1688927953
Short name T208
Test name
Test status
Simulation time 85041751890 ps
CPU time 206.31 seconds
Started Aug 12 05:36:03 PM PDT 24
Finished Aug 12 05:39:29 PM PDT 24
Peak memory 253516 kb
Host smart-0e66f467-7edc-4a85-889e-8718c33cd6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688927953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1688927953
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1395703883
Short name T450
Test name
Test status
Simulation time 2353757322 ps
CPU time 18.5 seconds
Started Aug 12 05:35:55 PM PDT 24
Finished Aug 12 05:36:14 PM PDT 24
Peak memory 224672 kb
Host smart-d272c619-1e7f-4012-b569-08c3c2ad8d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395703883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1395703883
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1660578720
Short name T769
Test name
Test status
Simulation time 5927796471 ps
CPU time 61.86 seconds
Started Aug 12 05:36:06 PM PDT 24
Finished Aug 12 05:37:08 PM PDT 24
Peak memory 241132 kb
Host smart-0e74c9e9-0744-4117-acde-d40888640c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660578720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1660578720
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1945808596
Short name T896
Test name
Test status
Simulation time 18094795 ps
CPU time 1.02 seconds
Started Aug 12 05:35:53 PM PDT 24
Finished Aug 12 05:35:55 PM PDT 24
Peak memory 216672 kb
Host smart-efc98d9f-ba2e-44c6-bea3-6f5706f7f824
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945808596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1945808596
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1252965286
Short name T1007
Test name
Test status
Simulation time 88370474640 ps
CPU time 40.28 seconds
Started Aug 12 05:36:11 PM PDT 24
Finished Aug 12 05:36:51 PM PDT 24
Peak memory 232924 kb
Host smart-03375c37-f4ed-4ea1-8f18-d6b6ca2348e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252965286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1252965286
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3573849930
Short name T783
Test name
Test status
Simulation time 1148725094 ps
CPU time 3.71 seconds
Started Aug 12 05:36:02 PM PDT 24
Finished Aug 12 05:36:06 PM PDT 24
Peak memory 224700 kb
Host smart-77a7d2fa-acee-4117-b4b7-14d0fd339dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573849930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3573849930
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2439765781
Short name T41
Test name
Test status
Simulation time 1582475202 ps
CPU time 6.05 seconds
Started Aug 12 05:35:59 PM PDT 24
Finished Aug 12 05:36:05 PM PDT 24
Peak memory 223168 kb
Host smart-0ab0707c-7c7d-41e4-89d2-aee21cce111d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2439765781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2439765781
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.174364165
Short name T1011
Test name
Test status
Simulation time 191227217316 ps
CPU time 247.08 seconds
Started Aug 12 05:36:09 PM PDT 24
Finished Aug 12 05:40:17 PM PDT 24
Peak memory 284308 kb
Host smart-68688c2f-8094-4809-ad99-47f309ee8241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174364165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.174364165
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2133827009
Short name T806
Test name
Test status
Simulation time 16833331 ps
CPU time 0.69 seconds
Started Aug 12 05:36:18 PM PDT 24
Finished Aug 12 05:36:19 PM PDT 24
Peak memory 205644 kb
Host smart-7b6d9493-6dad-49ba-b636-75b154033d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133827009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2133827009
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2600428194
Short name T960
Test name
Test status
Simulation time 1680667895 ps
CPU time 3.12 seconds
Started Aug 12 05:35:41 PM PDT 24
Finished Aug 12 05:35:45 PM PDT 24
Peak memory 216360 kb
Host smart-1f9041a1-3809-4eda-8201-51afd1790cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600428194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2600428194
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.528697965
Short name T29
Test name
Test status
Simulation time 31185847 ps
CPU time 1.48 seconds
Started Aug 12 05:35:52 PM PDT 24
Finished Aug 12 05:35:54 PM PDT 24
Peak memory 216432 kb
Host smart-4cbc535c-3b0e-4591-856b-aa77de0b4d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528697965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.528697965
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2280148525
Short name T650
Test name
Test status
Simulation time 189146184 ps
CPU time 0.84 seconds
Started Aug 12 05:35:56 PM PDT 24
Finished Aug 12 05:35:57 PM PDT 24
Peak memory 206040 kb
Host smart-4f2a71ea-2a4a-47c6-bc67-1031df68ebb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280148525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2280148525
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1749549535
Short name T223
Test name
Test status
Simulation time 1730541554 ps
CPU time 5.24 seconds
Started Aug 12 05:36:30 PM PDT 24
Finished Aug 12 05:36:35 PM PDT 24
Peak memory 232860 kb
Host smart-937b2f9b-f2fd-4cf3-a8e9-d0df99124a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749549535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1749549535
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1564227160
Short name T404
Test name
Test status
Simulation time 15869852 ps
CPU time 0.77 seconds
Started Aug 12 05:36:30 PM PDT 24
Finished Aug 12 05:36:31 PM PDT 24
Peak memory 204708 kb
Host smart-ec439d4f-f5cb-406d-a91e-d9d995605098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564227160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1564227160
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3277195803
Short name T421
Test name
Test status
Simulation time 385989179 ps
CPU time 3.05 seconds
Started Aug 12 05:36:19 PM PDT 24
Finished Aug 12 05:36:22 PM PDT 24
Peak memory 228336 kb
Host smart-381e95ec-b171-4009-89fe-a2ad501f6169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277195803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3277195803
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.312375067
Short name T716
Test name
Test status
Simulation time 27457578 ps
CPU time 0.8 seconds
Started Aug 12 05:36:11 PM PDT 24
Finished Aug 12 05:36:11 PM PDT 24
Peak memory 206528 kb
Host smart-3d47d68d-e19d-4f3f-9928-b432734cad6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312375067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.312375067
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1269463
Short name T316
Test name
Test status
Simulation time 4499219419 ps
CPU time 21.33 seconds
Started Aug 12 05:36:09 PM PDT 24
Finished Aug 12 05:36:30 PM PDT 24
Peak memory 217920 kb
Host smart-41898058-611d-42b2-a69c-88ab4f30ec95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1269463
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3728946477
Short name T255
Test name
Test status
Simulation time 1444035496 ps
CPU time 37.86 seconds
Started Aug 12 05:36:02 PM PDT 24
Finished Aug 12 05:36:40 PM PDT 24
Peak memory 251072 kb
Host smart-7bd73058-7408-4871-b7d8-b6c424f836dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728946477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3728946477
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.659862598
Short name T529
Test name
Test status
Simulation time 881125392 ps
CPU time 4.14 seconds
Started Aug 12 05:36:14 PM PDT 24
Finished Aug 12 05:36:19 PM PDT 24
Peak memory 224692 kb
Host smart-5d707ce6-47cd-468d-be55-3e1ab5c8a381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659862598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.659862598
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3164826784
Short name T486
Test name
Test status
Simulation time 11575815537 ps
CPU time 79.95 seconds
Started Aug 12 05:35:59 PM PDT 24
Finished Aug 12 05:37:19 PM PDT 24
Peak memory 240944 kb
Host smart-b3847e09-5e82-48e1-a7f8-21788bbcd2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164826784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3164826784
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2346464002
Short name T142
Test name
Test status
Simulation time 1780761395 ps
CPU time 12.39 seconds
Started Aug 12 05:36:22 PM PDT 24
Finished Aug 12 05:36:35 PM PDT 24
Peak memory 224628 kb
Host smart-ebce69ba-f8fe-443c-bb37-b0711744d571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346464002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2346464002
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3145220259
Short name T835
Test name
Test status
Simulation time 997636425 ps
CPU time 11.9 seconds
Started Aug 12 05:36:33 PM PDT 24
Finished Aug 12 05:36:46 PM PDT 24
Peak memory 232904 kb
Host smart-0432ec11-ae08-4417-9f91-2ddd36381c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145220259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3145220259
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.4168107997
Short name T782
Test name
Test status
Simulation time 27765132 ps
CPU time 0.99 seconds
Started Aug 12 05:36:00 PM PDT 24
Finished Aug 12 05:36:01 PM PDT 24
Peak memory 217908 kb
Host smart-14ad275a-1cd5-4df8-a7d4-e2e0940c2f7a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168107997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.4168107997
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2942629776
Short name T679
Test name
Test status
Simulation time 748660733 ps
CPU time 6.26 seconds
Started Aug 12 05:36:00 PM PDT 24
Finished Aug 12 05:36:06 PM PDT 24
Peak memory 232864 kb
Host smart-7c153622-85e9-4350-801d-7a948fd2ad0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942629776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2942629776
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3883212390
Short name T275
Test name
Test status
Simulation time 107053075 ps
CPU time 3.29 seconds
Started Aug 12 05:36:15 PM PDT 24
Finished Aug 12 05:36:18 PM PDT 24
Peak memory 232812 kb
Host smart-ee0d36d3-6126-4f8a-8e9c-7691f1300a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883212390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3883212390
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3873834022
Short name T660
Test name
Test status
Simulation time 1193050739 ps
CPU time 14.68 seconds
Started Aug 12 05:36:32 PM PDT 24
Finished Aug 12 05:36:47 PM PDT 24
Peak memory 218848 kb
Host smart-4640c172-c717-40d8-8aa7-8a06da83704d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3873834022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3873834022
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3359350097
Short name T165
Test name
Test status
Simulation time 78965799 ps
CPU time 1.14 seconds
Started Aug 12 05:36:17 PM PDT 24
Finished Aug 12 05:36:18 PM PDT 24
Peak memory 206972 kb
Host smart-4001eac6-dce0-4375-9dea-c475bf1dd954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359350097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3359350097
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.382873057
Short name T547
Test name
Test status
Simulation time 1065381374 ps
CPU time 14.71 seconds
Started Aug 12 05:36:02 PM PDT 24
Finished Aug 12 05:36:17 PM PDT 24
Peak memory 216528 kb
Host smart-3b88019c-c4af-4ea6-ab5c-be6f2efb0402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382873057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.382873057
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.939553127
Short name T978
Test name
Test status
Simulation time 878830632 ps
CPU time 6.2 seconds
Started Aug 12 05:35:41 PM PDT 24
Finished Aug 12 05:35:48 PM PDT 24
Peak memory 216388 kb
Host smart-96dddf53-fd94-4d4c-bd3d-95727e1cbf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939553127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.939553127
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2351234578
Short name T673
Test name
Test status
Simulation time 94104606 ps
CPU time 1.23 seconds
Started Aug 12 05:36:09 PM PDT 24
Finished Aug 12 05:36:11 PM PDT 24
Peak memory 208176 kb
Host smart-18579fe5-dedc-4976-bdb8-0d337ad2ee37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351234578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2351234578
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1379142892
Short name T969
Test name
Test status
Simulation time 105780558 ps
CPU time 0.89 seconds
Started Aug 12 05:36:10 PM PDT 24
Finished Aug 12 05:36:11 PM PDT 24
Peak memory 205856 kb
Host smart-b860319b-8f9f-4662-84f6-f48a922a8331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379142892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1379142892
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1769391813
Short name T596
Test name
Test status
Simulation time 1182682320 ps
CPU time 10.24 seconds
Started Aug 12 05:36:26 PM PDT 24
Finished Aug 12 05:36:36 PM PDT 24
Peak memory 241080 kb
Host smart-06ed42c6-3510-4efb-a95e-d3e27138c1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769391813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1769391813
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3547259646
Short name T690
Test name
Test status
Simulation time 13165655 ps
CPU time 0.76 seconds
Started Aug 12 05:36:11 PM PDT 24
Finished Aug 12 05:36:12 PM PDT 24
Peak memory 205248 kb
Host smart-67c1586a-364f-42d4-8417-11c19c29586f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547259646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3547259646
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4028808946
Short name T12
Test name
Test status
Simulation time 266848732 ps
CPU time 3.85 seconds
Started Aug 12 05:36:12 PM PDT 24
Finished Aug 12 05:36:16 PM PDT 24
Peak memory 232872 kb
Host smart-4b07f6a4-ceff-4012-84f1-77d0aa491c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028808946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4028808946
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.899314599
Short name T1033
Test name
Test status
Simulation time 20450634 ps
CPU time 0.76 seconds
Started Aug 12 05:36:10 PM PDT 24
Finished Aug 12 05:36:11 PM PDT 24
Peak memory 205456 kb
Host smart-67782eb8-3521-4927-827d-e5012b86e640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899314599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.899314599
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.201359529
Short name T916
Test name
Test status
Simulation time 6058846193 ps
CPU time 61.18 seconds
Started Aug 12 05:36:05 PM PDT 24
Finished Aug 12 05:37:06 PM PDT 24
Peak memory 250488 kb
Host smart-39f6e3ae-e01a-47f2-b2e5-341f980c7d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201359529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.201359529
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2556800017
Short name T785
Test name
Test status
Simulation time 1255323956 ps
CPU time 37.12 seconds
Started Aug 12 05:36:06 PM PDT 24
Finished Aug 12 05:36:43 PM PDT 24
Peak memory 249356 kb
Host smart-a21893f9-1493-495e-b8a7-6f840ecfde51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556800017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2556800017
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3298062963
Short name T469
Test name
Test status
Simulation time 11527186977 ps
CPU time 106.45 seconds
Started Aug 12 05:36:09 PM PDT 24
Finished Aug 12 05:37:56 PM PDT 24
Peak memory 250460 kb
Host smart-f82e4f66-abfb-4385-a829-2973771490c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298062963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3298062963
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2759575898
Short name T332
Test name
Test status
Simulation time 1109372055 ps
CPU time 10.16 seconds
Started Aug 12 05:36:27 PM PDT 24
Finished Aug 12 05:36:37 PM PDT 24
Peak memory 224700 kb
Host smart-eade3317-b5ec-4e8f-b094-0bad22b99f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759575898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2759575898
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2503677902
Short name T401
Test name
Test status
Simulation time 5777899198 ps
CPU time 52.47 seconds
Started Aug 12 05:36:40 PM PDT 24
Finished Aug 12 05:37:32 PM PDT 24
Peak memory 249312 kb
Host smart-98b8553e-c78a-425d-a6d1-aed7d051f275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503677902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2503677902
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1492607676
Short name T821
Test name
Test status
Simulation time 473639498 ps
CPU time 5.73 seconds
Started Aug 12 05:36:04 PM PDT 24
Finished Aug 12 05:36:10 PM PDT 24
Peak memory 224652 kb
Host smart-14474234-0cdc-4182-be93-49b21c007ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492607676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1492607676
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3739744019
Short name T234
Test name
Test status
Simulation time 4555721288 ps
CPU time 14.98 seconds
Started Aug 12 05:36:07 PM PDT 24
Finished Aug 12 05:36:23 PM PDT 24
Peak memory 233112 kb
Host smart-1947582c-4f39-44b8-b988-2a275710cb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739744019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3739744019
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3602401665
Short name T84
Test name
Test status
Simulation time 138930795 ps
CPU time 1.08 seconds
Started Aug 12 05:36:21 PM PDT 24
Finished Aug 12 05:36:22 PM PDT 24
Peak memory 216692 kb
Host smart-0f214864-812c-4e01-b068-6bc1e4da898e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602401665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3602401665
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3811260293
Short name T5
Test name
Test status
Simulation time 103036208006 ps
CPU time 18.34 seconds
Started Aug 12 05:36:14 PM PDT 24
Finished Aug 12 05:36:33 PM PDT 24
Peak memory 235132 kb
Host smart-71c3b045-3400-481a-bbd9-3e1dd92c93c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811260293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3811260293
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3911079551
Short name T688
Test name
Test status
Simulation time 34855947 ps
CPU time 2.34 seconds
Started Aug 12 05:36:14 PM PDT 24
Finished Aug 12 05:36:16 PM PDT 24
Peak memory 232884 kb
Host smart-2e6202db-bb4a-4bfa-8de0-1a2dbfe16507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911079551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3911079551
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1833037349
Short name T999
Test name
Test status
Simulation time 7727993777 ps
CPU time 11.56 seconds
Started Aug 12 05:36:03 PM PDT 24
Finished Aug 12 05:36:15 PM PDT 24
Peak memory 222240 kb
Host smart-bc7be764-76b7-4661-87e1-ccff782a13bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1833037349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1833037349
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3548527995
Short name T797
Test name
Test status
Simulation time 11771144408 ps
CPU time 23.5 seconds
Started Aug 12 05:36:17 PM PDT 24
Finished Aug 12 05:36:41 PM PDT 24
Peak memory 216748 kb
Host smart-8ae30bde-ba27-4350-936a-e59a4480f42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548527995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3548527995
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.644799970
Short name T505
Test name
Test status
Simulation time 406506193 ps
CPU time 1.8 seconds
Started Aug 12 05:36:08 PM PDT 24
Finished Aug 12 05:36:09 PM PDT 24
Peak memory 216376 kb
Host smart-2626acf8-684e-4719-b84e-d6d291b62d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644799970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.644799970
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1431146579
Short name T951
Test name
Test status
Simulation time 140593383 ps
CPU time 1.03 seconds
Started Aug 12 05:36:10 PM PDT 24
Finished Aug 12 05:36:12 PM PDT 24
Peak memory 206964 kb
Host smart-322a5397-56ac-4d78-b8b3-5a5ec205c865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431146579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1431146579
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2871731832
Short name T87
Test name
Test status
Simulation time 315834642 ps
CPU time 6.14 seconds
Started Aug 12 05:36:29 PM PDT 24
Finished Aug 12 05:36:35 PM PDT 24
Peak memory 240908 kb
Host smart-8971554c-2424-4b57-9232-3857c1f3a34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871731832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2871731832
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2543092194
Short name T911
Test name
Test status
Simulation time 18207101 ps
CPU time 0.74 seconds
Started Aug 12 05:36:12 PM PDT 24
Finished Aug 12 05:36:13 PM PDT 24
Peak memory 204728 kb
Host smart-489d07cc-cf10-41fb-8b81-1d5653d6344f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543092194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2543092194
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3724094321
Short name T917
Test name
Test status
Simulation time 39584608 ps
CPU time 2.64 seconds
Started Aug 12 05:36:07 PM PDT 24
Finished Aug 12 05:36:10 PM PDT 24
Peak memory 232840 kb
Host smart-7bb2b15e-db56-480d-b8b8-bbf964a81fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724094321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3724094321
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.79864269
Short name T427
Test name
Test status
Simulation time 19468715 ps
CPU time 0.77 seconds
Started Aug 12 05:36:27 PM PDT 24
Finished Aug 12 05:36:28 PM PDT 24
Peak memory 206480 kb
Host smart-9a823649-3d43-4c5f-aedc-00408405d15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79864269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.79864269
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3274271079
Short name T1002
Test name
Test status
Simulation time 10144231839 ps
CPU time 22.78 seconds
Started Aug 12 05:36:18 PM PDT 24
Finished Aug 12 05:36:41 PM PDT 24
Peak memory 236844 kb
Host smart-ab4d538c-728f-4e74-add7-489569c4e954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274271079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3274271079
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.437661936
Short name T635
Test name
Test status
Simulation time 5270548189 ps
CPU time 73.14 seconds
Started Aug 12 05:36:07 PM PDT 24
Finished Aug 12 05:37:20 PM PDT 24
Peak memory 248704 kb
Host smart-01bcaa00-e8a2-495e-83b7-0e7333000d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437661936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.437661936
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1599379679
Short name T293
Test name
Test status
Simulation time 7127845380 ps
CPU time 88.33 seconds
Started Aug 12 05:36:02 PM PDT 24
Finished Aug 12 05:37:30 PM PDT 24
Peak memory 251660 kb
Host smart-9313819c-f77b-4a39-8c7d-6f00d6d2180f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599379679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1599379679
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3954463140
Short name T895
Test name
Test status
Simulation time 204263708 ps
CPU time 5.19 seconds
Started Aug 12 05:36:03 PM PDT 24
Finished Aug 12 05:36:08 PM PDT 24
Peak memory 224720 kb
Host smart-bf35ee7c-9c60-4df1-9227-4338d88fe74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954463140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3954463140
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1274201039
Short name T718
Test name
Test status
Simulation time 1042254691 ps
CPU time 11.17 seconds
Started Aug 12 05:36:19 PM PDT 24
Finished Aug 12 05:36:30 PM PDT 24
Peak memory 232872 kb
Host smart-80d6d9a4-126c-4720-9315-af764d3ef14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274201039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1274201039
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3062575346
Short name T273
Test name
Test status
Simulation time 1493891407 ps
CPU time 21.85 seconds
Started Aug 12 05:36:32 PM PDT 24
Finished Aug 12 05:36:54 PM PDT 24
Peak memory 224712 kb
Host smart-5dbe5999-1029-4dab-b756-75cdeb4f3f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062575346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3062575346
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1875612166
Short name T914
Test name
Test status
Simulation time 42974226 ps
CPU time 1.02 seconds
Started Aug 12 05:35:56 PM PDT 24
Finished Aug 12 05:35:57 PM PDT 24
Peak memory 216648 kb
Host smart-3926d53e-5da0-46df-abf4-dc9cd252438c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875612166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1875612166
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4186290619
Short name T726
Test name
Test status
Simulation time 742401102 ps
CPU time 4.33 seconds
Started Aug 12 05:36:10 PM PDT 24
Finished Aug 12 05:36:14 PM PDT 24
Peak memory 224676 kb
Host smart-c264d31e-4073-45ca-a360-9b711fee68b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186290619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4186290619
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.702541021
Short name T860
Test name
Test status
Simulation time 4069004898 ps
CPU time 12.92 seconds
Started Aug 12 05:36:18 PM PDT 24
Finished Aug 12 05:36:31 PM PDT 24
Peak memory 232960 kb
Host smart-a2962f24-650c-470f-b9ba-00ee0eadb875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702541021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.702541021
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.544110191
Short name T565
Test name
Test status
Simulation time 838517638 ps
CPU time 7.02 seconds
Started Aug 12 05:36:09 PM PDT 24
Finished Aug 12 05:36:16 PM PDT 24
Peak memory 222312 kb
Host smart-c494aa59-e283-4865-b76f-ff07ff8356c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=544110191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.544110191
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1493861920
Short name T885
Test name
Test status
Simulation time 33879600913 ps
CPU time 135.64 seconds
Started Aug 12 05:36:14 PM PDT 24
Finished Aug 12 05:38:30 PM PDT 24
Peak memory 249468 kb
Host smart-bff407bc-d449-4775-b5d7-091849719af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493861920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1493861920
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.279979258
Short name T799
Test name
Test status
Simulation time 18907702949 ps
CPU time 30.59 seconds
Started Aug 12 05:36:11 PM PDT 24
Finished Aug 12 05:36:41 PM PDT 24
Peak memory 216572 kb
Host smart-75e1916f-869b-4437-aa2f-7aa11402d574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279979258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.279979258
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1728629667
Short name T471
Test name
Test status
Simulation time 650329033 ps
CPU time 3.12 seconds
Started Aug 12 05:36:11 PM PDT 24
Finished Aug 12 05:36:14 PM PDT 24
Peak memory 216320 kb
Host smart-b4f79083-67dd-45e0-a5fd-8a12afc9dcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728629667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1728629667
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1563363707
Short name T561
Test name
Test status
Simulation time 48353727 ps
CPU time 1.05 seconds
Started Aug 12 05:36:09 PM PDT 24
Finished Aug 12 05:36:10 PM PDT 24
Peak memory 208044 kb
Host smart-eed291e2-4eb7-49eb-a140-eaee08f6b867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563363707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1563363707
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.681070621
Short name T631
Test name
Test status
Simulation time 34819669 ps
CPU time 0.83 seconds
Started Aug 12 05:36:34 PM PDT 24
Finished Aug 12 05:36:35 PM PDT 24
Peak memory 205976 kb
Host smart-f0c51c7d-da84-4dd5-95dd-6cafc36a082a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681070621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.681070621
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.4287337167
Short name T416
Test name
Test status
Simulation time 5640955422 ps
CPU time 10.31 seconds
Started Aug 12 05:36:32 PM PDT 24
Finished Aug 12 05:36:42 PM PDT 24
Peak memory 239732 kb
Host smart-003853d1-3d98-4481-85ba-a8f9fc912d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287337167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.4287337167
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1740752537
Short name T748
Test name
Test status
Simulation time 11289018 ps
CPU time 0.69 seconds
Started Aug 12 05:36:20 PM PDT 24
Finished Aug 12 05:36:21 PM PDT 24
Peak memory 205640 kb
Host smart-8eae9c2b-7609-46d1-8e8d-97b9c2b1b811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740752537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1740752537
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1522152865
Short name T630
Test name
Test status
Simulation time 2207776024 ps
CPU time 6.33 seconds
Started Aug 12 05:36:21 PM PDT 24
Finished Aug 12 05:36:27 PM PDT 24
Peak memory 224764 kb
Host smart-a70fc419-f0d8-4fbf-9a24-5a63be888702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522152865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1522152865
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.712940380
Short name T1037
Test name
Test status
Simulation time 158254370 ps
CPU time 0.79 seconds
Started Aug 12 05:35:58 PM PDT 24
Finished Aug 12 05:35:59 PM PDT 24
Peak memory 206508 kb
Host smart-266f9ee2-a8d2-4f5b-93dc-26e0357886f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712940380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.712940380
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3206660159
Short name T443
Test name
Test status
Simulation time 835031291 ps
CPU time 16.74 seconds
Started Aug 12 05:36:18 PM PDT 24
Finished Aug 12 05:36:35 PM PDT 24
Peak memory 239852 kb
Host smart-dcfcc2d8-2ff9-4414-82d7-06066383ca58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206660159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3206660159
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3352526553
Short name T217
Test name
Test status
Simulation time 35261930403 ps
CPU time 292.3 seconds
Started Aug 12 05:36:13 PM PDT 24
Finished Aug 12 05:41:05 PM PDT 24
Peak memory 255292 kb
Host smart-056d575b-fa9f-46ac-828b-042c74fd4a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352526553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3352526553
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1241317476
Short name T334
Test name
Test status
Simulation time 554049745 ps
CPU time 4.71 seconds
Started Aug 12 05:35:59 PM PDT 24
Finished Aug 12 05:36:03 PM PDT 24
Peak memory 224684 kb
Host smart-b622e03a-353b-42e4-993b-3fbfb8eb2898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241317476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1241317476
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2402903279
Short name T197
Test name
Test status
Simulation time 106785819969 ps
CPU time 111.81 seconds
Started Aug 12 05:36:15 PM PDT 24
Finished Aug 12 05:38:07 PM PDT 24
Peak memory 238512 kb
Host smart-5c86a7d3-dfbe-4517-b6d2-20b081a84b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402903279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2402903279
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1518210764
Short name T448
Test name
Test status
Simulation time 53893158 ps
CPU time 2.01 seconds
Started Aug 12 05:36:10 PM PDT 24
Finished Aug 12 05:36:12 PM PDT 24
Peak memory 223948 kb
Host smart-32583964-2938-42b8-bfa5-ae39df32490b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518210764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1518210764
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3407393971
Short name T243
Test name
Test status
Simulation time 5795829742 ps
CPU time 21.28 seconds
Started Aug 12 05:36:08 PM PDT 24
Finished Aug 12 05:36:29 PM PDT 24
Peak memory 240840 kb
Host smart-f94db856-cbc4-4be2-8089-7cccc24da563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407393971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3407393971
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3040873140
Short name T810
Test name
Test status
Simulation time 28402866 ps
CPU time 0.96 seconds
Started Aug 12 05:36:03 PM PDT 24
Finished Aug 12 05:36:04 PM PDT 24
Peak memory 217892 kb
Host smart-e9d3a6b6-5b06-4df4-96ad-54e7adeb100f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040873140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3040873140
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4213545452
Short name T974
Test name
Test status
Simulation time 539924200 ps
CPU time 7.01 seconds
Started Aug 12 05:36:29 PM PDT 24
Finished Aug 12 05:36:36 PM PDT 24
Peak memory 232924 kb
Host smart-20f45863-ccd8-461d-b3fa-16c4ef68ad90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213545452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.4213545452
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.195839515
Short name T866
Test name
Test status
Simulation time 8503797812 ps
CPU time 25.66 seconds
Started Aug 12 05:36:18 PM PDT 24
Finished Aug 12 05:36:44 PM PDT 24
Peak memory 241056 kb
Host smart-e4a4f5d6-3db8-4443-85cf-ace376473d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195839515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.195839515
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.520727195
Short name T953
Test name
Test status
Simulation time 1636370448 ps
CPU time 18.23 seconds
Started Aug 12 05:36:05 PM PDT 24
Finished Aug 12 05:36:24 PM PDT 24
Peak memory 222148 kb
Host smart-3461ee28-11f1-4c6c-9323-91d51afe9cec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=520727195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.520727195
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2122422396
Short name T894
Test name
Test status
Simulation time 4541535095 ps
CPU time 22.33 seconds
Started Aug 12 05:36:20 PM PDT 24
Finished Aug 12 05:36:43 PM PDT 24
Peak memory 233000 kb
Host smart-bd02ef53-a431-439e-b1be-13fdfbba3cdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122422396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2122422396
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.4054567972
Short name T675
Test name
Test status
Simulation time 1009035364 ps
CPU time 4.5 seconds
Started Aug 12 05:36:03 PM PDT 24
Finished Aug 12 05:36:08 PM PDT 24
Peak memory 216500 kb
Host smart-f639a175-b451-4ffa-8612-7d9191f07dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054567972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4054567972
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1310279210
Short name T586
Test name
Test status
Simulation time 1292651907 ps
CPU time 4.23 seconds
Started Aug 12 05:35:57 PM PDT 24
Finished Aug 12 05:36:01 PM PDT 24
Peak memory 216336 kb
Host smart-9ef2b413-c87c-40d5-8a47-ba242ae0ee11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310279210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1310279210
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3362893896
Short name T461
Test name
Test status
Simulation time 100495503 ps
CPU time 0.99 seconds
Started Aug 12 05:36:21 PM PDT 24
Finished Aug 12 05:36:22 PM PDT 24
Peak memory 207120 kb
Host smart-ca3fe044-887c-4483-8be9-8249d5d30ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362893896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3362893896
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.258405332
Short name T609
Test name
Test status
Simulation time 15542037 ps
CPU time 0.71 seconds
Started Aug 12 05:36:14 PM PDT 24
Finished Aug 12 05:36:15 PM PDT 24
Peak memory 206020 kb
Host smart-495e7c1f-c442-4917-be32-38bc269fcb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258405332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.258405332
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2780559863
Short name T614
Test name
Test status
Simulation time 7212598924 ps
CPU time 22.1 seconds
Started Aug 12 05:36:11 PM PDT 24
Finished Aug 12 05:36:34 PM PDT 24
Peak memory 224744 kb
Host smart-7c3a20c7-9a82-4e71-896f-a25a228b0ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780559863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2780559863
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2559270241
Short name T387
Test name
Test status
Simulation time 23752859 ps
CPU time 0.74 seconds
Started Aug 12 05:36:12 PM PDT 24
Finished Aug 12 05:36:13 PM PDT 24
Peak memory 205244 kb
Host smart-6ce66ed7-0605-4562-9805-14bcec64434c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559270241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2559270241
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1286662469
Short name T82
Test name
Test status
Simulation time 33106112 ps
CPU time 2.38 seconds
Started Aug 12 05:36:25 PM PDT 24
Finished Aug 12 05:36:28 PM PDT 24
Peak memory 232936 kb
Host smart-7f38f090-9a3f-4dc3-8386-ad6a3740c3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286662469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1286662469
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3115707854
Short name T552
Test name
Test status
Simulation time 83630750 ps
CPU time 0.74 seconds
Started Aug 12 05:36:31 PM PDT 24
Finished Aug 12 05:36:32 PM PDT 24
Peak memory 206840 kb
Host smart-51a195a5-8396-48e8-9feb-2d38d4a6d9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115707854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3115707854
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1114230392
Short name T196
Test name
Test status
Simulation time 18011984575 ps
CPU time 38.6 seconds
Started Aug 12 05:36:32 PM PDT 24
Finished Aug 12 05:37:11 PM PDT 24
Peak memory 251344 kb
Host smart-69adbe8d-6396-4b54-8287-e58674edfcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114230392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1114230392
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1539503444
Short name T466
Test name
Test status
Simulation time 21488100681 ps
CPU time 181.2 seconds
Started Aug 12 05:36:13 PM PDT 24
Finished Aug 12 05:39:14 PM PDT 24
Peak memory 256560 kb
Host smart-6efc31c6-7c07-44f6-b968-75d9cd73464a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539503444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1539503444
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.334712754
Short name T44
Test name
Test status
Simulation time 58520176844 ps
CPU time 195.5 seconds
Started Aug 12 05:36:19 PM PDT 24
Finished Aug 12 05:39:35 PM PDT 24
Peak memory 257632 kb
Host smart-0d3ff08c-121b-499c-bf93-54091991cb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334712754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.334712754
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.4133041324
Short name T587
Test name
Test status
Simulation time 1234619991 ps
CPU time 17.45 seconds
Started Aug 12 05:36:24 PM PDT 24
Finished Aug 12 05:36:41 PM PDT 24
Peak memory 233684 kb
Host smart-81474559-7f6d-4b06-a4f8-0f676add7889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133041324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4133041324
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.930429047
Short name T575
Test name
Test status
Simulation time 243270964 ps
CPU time 0.89 seconds
Started Aug 12 05:36:37 PM PDT 24
Finished Aug 12 05:36:38 PM PDT 24
Peak memory 215980 kb
Host smart-4b906b10-bd9f-4b99-b6bb-615918f96a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930429047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.930429047
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.954307693
Short name T593
Test name
Test status
Simulation time 160250050 ps
CPU time 2.99 seconds
Started Aug 12 05:36:17 PM PDT 24
Finished Aug 12 05:36:21 PM PDT 24
Peak memory 224860 kb
Host smart-20cd0a0b-a145-4fb7-8cb0-ca6c0aaa14cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954307693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.954307693
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3254437547
Short name T796
Test name
Test status
Simulation time 1850997586 ps
CPU time 26.19 seconds
Started Aug 12 05:36:41 PM PDT 24
Finished Aug 12 05:37:08 PM PDT 24
Peak memory 224656 kb
Host smart-27b7d21c-6967-4a23-b76f-2cb4325500f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254437547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3254437547
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.260418036
Short name T386
Test name
Test status
Simulation time 29378359 ps
CPU time 1.02 seconds
Started Aug 12 05:36:19 PM PDT 24
Finished Aug 12 05:36:20 PM PDT 24
Peak memory 216672 kb
Host smart-51ab58d5-9612-48f1-ac01-b791cfc8b185
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260418036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.260418036
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2501659014
Short name T744
Test name
Test status
Simulation time 2078669257 ps
CPU time 8.33 seconds
Started Aug 12 05:36:11 PM PDT 24
Finished Aug 12 05:36:20 PM PDT 24
Peak memory 232816 kb
Host smart-e4ccc9f2-b488-46be-b9e5-dd6b5d867818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501659014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2501659014
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.4166930465
Short name T382
Test name
Test status
Simulation time 14082717062 ps
CPU time 10.69 seconds
Started Aug 12 05:36:38 PM PDT 24
Finished Aug 12 05:36:49 PM PDT 24
Peak memory 232968 kb
Host smart-e277a36f-02e8-422c-b6b2-29e61e1eb2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166930465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.4166930465
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2998178588
Short name T646
Test name
Test status
Simulation time 1020940972 ps
CPU time 3.82 seconds
Started Aug 12 05:36:32 PM PDT 24
Finished Aug 12 05:36:36 PM PDT 24
Peak memory 220820 kb
Host smart-35a366b7-cc5d-4593-bee1-95c47c5fa9d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2998178588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2998178588
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3829298065
Short name T605
Test name
Test status
Simulation time 3320358341 ps
CPU time 30.24 seconds
Started Aug 12 05:36:28 PM PDT 24
Finished Aug 12 05:37:09 PM PDT 24
Peak memory 216548 kb
Host smart-bf8b2e48-5267-4d3e-9b2f-17fa5a2f291d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829298065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3829298065
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2885684301
Short name T752
Test name
Test status
Simulation time 30577504616 ps
CPU time 20.82 seconds
Started Aug 12 05:36:34 PM PDT 24
Finished Aug 12 05:37:00 PM PDT 24
Peak memory 216444 kb
Host smart-913f9583-f60b-415f-ba9b-615fd1894492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885684301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2885684301
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2695560407
Short name T376
Test name
Test status
Simulation time 51972247 ps
CPU time 0.91 seconds
Started Aug 12 05:36:31 PM PDT 24
Finished Aug 12 05:36:32 PM PDT 24
Peak memory 206724 kb
Host smart-ec798ad7-13b6-4032-8b07-90cefc51c1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695560407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2695560407
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.49930173
Short name T411
Test name
Test status
Simulation time 66172005 ps
CPU time 0.89 seconds
Started Aug 12 05:35:56 PM PDT 24
Finished Aug 12 05:35:57 PM PDT 24
Peak memory 205932 kb
Host smart-1698c918-624f-4f9e-a47f-97ae6212bd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49930173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.49930173
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3439954685
Short name T615
Test name
Test status
Simulation time 2466142520 ps
CPU time 11.01 seconds
Started Aug 12 05:36:04 PM PDT 24
Finished Aug 12 05:36:15 PM PDT 24
Peak memory 232888 kb
Host smart-d4f0d5ce-cb50-4238-b7e3-52aad0a3e22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439954685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3439954685
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.341528918
Short name T513
Test name
Test status
Simulation time 183396915 ps
CPU time 2.47 seconds
Started Aug 12 05:36:17 PM PDT 24
Finished Aug 12 05:36:20 PM PDT 24
Peak memory 232864 kb
Host smart-db88b5aa-0c8d-4a3d-9e6e-3375c3e872ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341528918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.341528918
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2313126465
Short name T335
Test name
Test status
Simulation time 64187634 ps
CPU time 0.78 seconds
Started Aug 12 05:36:21 PM PDT 24
Finished Aug 12 05:36:22 PM PDT 24
Peak memory 206408 kb
Host smart-e96d6018-f44d-49cc-beca-d4ac4b40dbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313126465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2313126465
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1144138413
Short name T63
Test name
Test status
Simulation time 48507674555 ps
CPU time 166.34 seconds
Started Aug 12 05:36:06 PM PDT 24
Finished Aug 12 05:38:52 PM PDT 24
Peak memory 251836 kb
Host smart-302f6595-49e0-4320-bfc6-1ed193ae4b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144138413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1144138413
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2930026778
Short name T68
Test name
Test status
Simulation time 8018594369 ps
CPU time 68.32 seconds
Started Aug 12 05:35:58 PM PDT 24
Finished Aug 12 05:37:06 PM PDT 24
Peak memory 241236 kb
Host smart-7918c14a-2e4b-4274-8148-a73889837e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930026778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2930026778
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.695113579
Short name T79
Test name
Test status
Simulation time 201452765 ps
CPU time 5.21 seconds
Started Aug 12 05:36:10 PM PDT 24
Finished Aug 12 05:36:15 PM PDT 24
Peak memory 232860 kb
Host smart-9d5081a8-e6a3-4a12-b32a-82974cdbf96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695113579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.695113579
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1947866612
Short name T1034
Test name
Test status
Simulation time 81489013659 ps
CPU time 141.88 seconds
Started Aug 12 05:36:00 PM PDT 24
Finished Aug 12 05:38:22 PM PDT 24
Peak memory 249344 kb
Host smart-b27f295d-b9dd-4879-b3dc-adf55ed7a361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947866612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1947866612
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1362156347
Short name T487
Test name
Test status
Simulation time 242708146 ps
CPU time 5.32 seconds
Started Aug 12 05:36:14 PM PDT 24
Finished Aug 12 05:36:19 PM PDT 24
Peak memory 220052 kb
Host smart-2cad19df-1f32-4683-bfc2-54ca1f9fe34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362156347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1362156347
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1288590707
Short name T559
Test name
Test status
Simulation time 17763230350 ps
CPU time 91.24 seconds
Started Aug 12 05:36:21 PM PDT 24
Finished Aug 12 05:37:52 PM PDT 24
Peak memory 233004 kb
Host smart-a0f993bc-633b-4c3d-b133-6a44d9eb2120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288590707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1288590707
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.800717381
Short name T478
Test name
Test status
Simulation time 55901480 ps
CPU time 1 seconds
Started Aug 12 05:36:36 PM PDT 24
Finished Aug 12 05:36:38 PM PDT 24
Peak memory 218020 kb
Host smart-51f4e459-2e8f-4fff-a01a-f6c6ce386b42
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800717381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.800717381
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1115311794
Short name T80
Test name
Test status
Simulation time 2017867806 ps
CPU time 7.18 seconds
Started Aug 12 05:36:02 PM PDT 24
Finished Aug 12 05:36:10 PM PDT 24
Peak memory 232932 kb
Host smart-ee4e1626-7a29-4677-92b1-bcbe971b9cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115311794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1115311794
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.767239669
Short name T739
Test name
Test status
Simulation time 8868869668 ps
CPU time 17.84 seconds
Started Aug 12 05:36:25 PM PDT 24
Finished Aug 12 05:36:43 PM PDT 24
Peak memory 238000 kb
Host smart-48bb9aa9-73fe-4b0b-87d6-af78a38bc12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767239669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.767239669
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1206978793
Short name T52
Test name
Test status
Simulation time 456514238 ps
CPU time 5.34 seconds
Started Aug 12 05:36:12 PM PDT 24
Finished Aug 12 05:36:18 PM PDT 24
Peak memory 223096 kb
Host smart-bb4d7aec-0472-4890-af42-99e539b1d687
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1206978793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1206978793
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3730156675
Short name T479
Test name
Test status
Simulation time 2083356450 ps
CPU time 24.36 seconds
Started Aug 12 05:36:07 PM PDT 24
Finished Aug 12 05:36:31 PM PDT 24
Peak memory 216388 kb
Host smart-9e102aca-bca1-4a3d-b080-e0d859cd5e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730156675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3730156675
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2645899359
Short name T367
Test name
Test status
Simulation time 71238167 ps
CPU time 1.1 seconds
Started Aug 12 05:36:08 PM PDT 24
Finished Aug 12 05:36:09 PM PDT 24
Peak memory 207092 kb
Host smart-fb126963-bf23-4386-9c81-4fedcdd8341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645899359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2645899359
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3431076708
Short name T766
Test name
Test status
Simulation time 12308863 ps
CPU time 0.75 seconds
Started Aug 12 05:36:33 PM PDT 24
Finished Aug 12 05:36:34 PM PDT 24
Peak memory 206036 kb
Host smart-c43a3f8c-040e-4d95-a288-800c8dcf1951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431076708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3431076708
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2431941104
Short name T62
Test name
Test status
Simulation time 140042611 ps
CPU time 0.95 seconds
Started Aug 12 05:36:14 PM PDT 24
Finished Aug 12 05:36:15 PM PDT 24
Peak memory 206056 kb
Host smart-2179c28e-769b-4396-be89-d4e5ac90e0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431941104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2431941104
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.394436109
Short name T880
Test name
Test status
Simulation time 228317925 ps
CPU time 2.6 seconds
Started Aug 12 05:36:23 PM PDT 24
Finished Aug 12 05:36:26 PM PDT 24
Peak memory 224668 kb
Host smart-d21e4005-1114-4568-8492-80cf6d2bd314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394436109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.394436109
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1345067796
Short name T617
Test name
Test status
Simulation time 13885984 ps
CPU time 0.7 seconds
Started Aug 12 05:36:14 PM PDT 24
Finished Aug 12 05:36:15 PM PDT 24
Peak memory 205292 kb
Host smart-06e07b6f-92bb-4f1f-99ec-dee00f7934e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345067796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1345067796
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4200819350
Short name T600
Test name
Test status
Simulation time 48184084 ps
CPU time 2.46 seconds
Started Aug 12 05:36:10 PM PDT 24
Finished Aug 12 05:36:12 PM PDT 24
Peak memory 224636 kb
Host smart-c67d1874-69f3-4bc2-9c14-27416e3cd123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200819350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4200819350
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1043858183
Short name T709
Test name
Test status
Simulation time 41301452 ps
CPU time 0.71 seconds
Started Aug 12 05:36:28 PM PDT 24
Finished Aug 12 05:36:29 PM PDT 24
Peak memory 205812 kb
Host smart-835a1d04-3d24-4388-a601-53e57ab3f4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043858183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1043858183
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1296832997
Short name T945
Test name
Test status
Simulation time 28880971803 ps
CPU time 66.4 seconds
Started Aug 12 05:36:29 PM PDT 24
Finished Aug 12 05:37:36 PM PDT 24
Peak memory 255584 kb
Host smart-859329be-92ff-4349-9c3e-7c46d608ead8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296832997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1296832997
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3476530025
Short name T656
Test name
Test status
Simulation time 4837223027 ps
CPU time 44.49 seconds
Started Aug 12 05:36:15 PM PDT 24
Finished Aug 12 05:36:59 PM PDT 24
Peak memory 249444 kb
Host smart-2b63a9aa-8b24-4e39-b5d4-6f8e6504bb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476530025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3476530025
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.4071194045
Short name T763
Test name
Test status
Simulation time 11677103652 ps
CPU time 71.61 seconds
Started Aug 12 05:36:43 PM PDT 24
Finished Aug 12 05:37:55 PM PDT 24
Peak memory 241200 kb
Host smart-e54d0fc6-f560-46e5-b016-06baa19e47f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071194045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.4071194045
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3320520218
Short name T348
Test name
Test status
Simulation time 5007147752 ps
CPU time 12.66 seconds
Started Aug 12 05:36:32 PM PDT 24
Finished Aug 12 05:36:44 PM PDT 24
Peak memory 224792 kb
Host smart-8004775c-0f61-4663-aec3-dea1c2683f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320520218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3320520218
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.698623057
Short name T211
Test name
Test status
Simulation time 5346482196 ps
CPU time 30.57 seconds
Started Aug 12 05:36:22 PM PDT 24
Finished Aug 12 05:36:53 PM PDT 24
Peak memory 241172 kb
Host smart-c8e2535b-5e2c-48e6-bcd3-0e7f01bc5ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698623057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.698623057
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2704524571
Short name T706
Test name
Test status
Simulation time 96589932 ps
CPU time 2.05 seconds
Started Aug 12 05:36:31 PM PDT 24
Finished Aug 12 05:36:33 PM PDT 24
Peak memory 224316 kb
Host smart-4d32a0f7-afea-45d1-89f9-b5bdeea72f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704524571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2704524571
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.280962084
Short name T277
Test name
Test status
Simulation time 1824842430 ps
CPU time 15.41 seconds
Started Aug 12 05:36:25 PM PDT 24
Finished Aug 12 05:36:40 PM PDT 24
Peak memory 224716 kb
Host smart-fb2fdb64-62c7-4974-987d-4060c6fcc0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280962084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.280962084
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1771696754
Short name T938
Test name
Test status
Simulation time 48225352 ps
CPU time 1.02 seconds
Started Aug 12 05:36:01 PM PDT 24
Finished Aug 12 05:36:02 PM PDT 24
Peak memory 216784 kb
Host smart-c88768cf-5507-4b12-943b-12419e7e3248
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771696754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1771696754
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4125729107
Short name T358
Test name
Test status
Simulation time 13168329471 ps
CPU time 35.27 seconds
Started Aug 12 05:36:38 PM PDT 24
Finished Aug 12 05:37:13 PM PDT 24
Peak memory 224792 kb
Host smart-88a6b7ef-783f-4c53-b62b-4ca3f934c174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125729107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4125729107
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2098193466
Short name T920
Test name
Test status
Simulation time 196198542 ps
CPU time 2.71 seconds
Started Aug 12 05:36:12 PM PDT 24
Finished Aug 12 05:36:15 PM PDT 24
Peak memory 224716 kb
Host smart-f5aba6bf-81ba-4289-a568-509ef3692727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098193466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2098193466
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3419445670
Short name T51
Test name
Test status
Simulation time 11481276156 ps
CPU time 7.14 seconds
Started Aug 12 05:36:08 PM PDT 24
Finished Aug 12 05:36:15 PM PDT 24
Peak memory 219100 kb
Host smart-21461126-df6a-4a98-a5f6-e26a6656ce13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3419445670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3419445670
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.81606043
Short name T664
Test name
Test status
Simulation time 45417189 ps
CPU time 0.97 seconds
Started Aug 12 05:36:27 PM PDT 24
Finished Aug 12 05:36:28 PM PDT 24
Peak memory 206840 kb
Host smart-5a871e2d-90a6-4099-aa53-f2684db5ce4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81606043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress
_all.81606043
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2259825240
Short name T345
Test name
Test status
Simulation time 29251653 ps
CPU time 0.78 seconds
Started Aug 12 05:36:03 PM PDT 24
Finished Aug 12 05:36:04 PM PDT 24
Peak memory 205668 kb
Host smart-62100904-a64a-4dc2-997e-f68bf50a23f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259825240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2259825240
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1788306636
Short name T558
Test name
Test status
Simulation time 32768123 ps
CPU time 0.69 seconds
Started Aug 12 05:36:28 PM PDT 24
Finished Aug 12 05:36:29 PM PDT 24
Peak memory 205628 kb
Host smart-cb385eaf-3929-41a5-be8d-958b8d4413d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788306636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1788306636
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.996563630
Short name T776
Test name
Test status
Simulation time 89997130 ps
CPU time 2.31 seconds
Started Aug 12 05:36:04 PM PDT 24
Finished Aug 12 05:36:06 PM PDT 24
Peak memory 216432 kb
Host smart-8afa9088-fa20-4ad6-87cc-b67410906472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996563630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.996563630
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1233387080
Short name T178
Test name
Test status
Simulation time 124204571 ps
CPU time 0.98 seconds
Started Aug 12 05:36:30 PM PDT 24
Finished Aug 12 05:36:31 PM PDT 24
Peak memory 206036 kb
Host smart-38a3b256-0779-4c8b-8fb5-f669cbffd2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233387080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1233387080
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2686195353
Short name T454
Test name
Test status
Simulation time 31469568518 ps
CPU time 6.97 seconds
Started Aug 12 05:36:13 PM PDT 24
Finished Aug 12 05:36:20 PM PDT 24
Peak memory 232960 kb
Host smart-5d4d23b6-29d5-491a-817b-2583d288dae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686195353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2686195353
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1005977772
Short name T342
Test name
Test status
Simulation time 48571771 ps
CPU time 0.72 seconds
Started Aug 12 05:36:35 PM PDT 24
Finished Aug 12 05:36:36 PM PDT 24
Peak memory 205244 kb
Host smart-279bd7d0-574f-42c7-a7ae-06eb3a22b22c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005977772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1005977772
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2951151228
Short name T853
Test name
Test status
Simulation time 355304523 ps
CPU time 5.65 seconds
Started Aug 12 05:36:21 PM PDT 24
Finished Aug 12 05:36:27 PM PDT 24
Peak memory 232900 kb
Host smart-10211135-2e10-40f5-a0d3-706b9878b3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951151228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2951151228
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1085666335
Short name T742
Test name
Test status
Simulation time 18724295 ps
CPU time 0.8 seconds
Started Aug 12 05:36:10 PM PDT 24
Finished Aug 12 05:36:11 PM PDT 24
Peak memory 206364 kb
Host smart-0e9dbf21-5542-42b1-9652-d4852c8c90fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085666335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1085666335
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.872357234
Short name T193
Test name
Test status
Simulation time 3282188683 ps
CPU time 65.91 seconds
Started Aug 12 05:36:31 PM PDT 24
Finished Aug 12 05:37:37 PM PDT 24
Peak memory 255732 kb
Host smart-afd653ab-ad11-4a74-ac85-2626ea1958d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872357234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.872357234
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.822114803
Short name T91
Test name
Test status
Simulation time 98736564386 ps
CPU time 267.56 seconds
Started Aug 12 05:36:13 PM PDT 24
Finished Aug 12 05:40:41 PM PDT 24
Peak memory 273804 kb
Host smart-49a67f78-33d1-4e98-9e1e-c3e0b3be64da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822114803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.822114803
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1648374851
Short name T434
Test name
Test status
Simulation time 2247180259 ps
CPU time 10.05 seconds
Started Aug 12 05:36:36 PM PDT 24
Finished Aug 12 05:36:47 PM PDT 24
Peak memory 233000 kb
Host smart-ad041be9-7c1a-47ff-b911-f9a63397cda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648374851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1648374851
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1322740672
Short name T447
Test name
Test status
Simulation time 37504072 ps
CPU time 0.8 seconds
Started Aug 12 05:36:21 PM PDT 24
Finished Aug 12 05:36:22 PM PDT 24
Peak memory 215920 kb
Host smart-3c6ba854-ef52-4cd7-8c3a-8a4d60c38db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322740672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1322740672
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2265321539
Short name T592
Test name
Test status
Simulation time 2546614023 ps
CPU time 6.35 seconds
Started Aug 12 05:36:30 PM PDT 24
Finished Aug 12 05:36:37 PM PDT 24
Peak memory 233008 kb
Host smart-3a11d07f-f4b4-4e2d-b7c3-10fc9f30cbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265321539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2265321539
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3476626186
Short name T756
Test name
Test status
Simulation time 6650119529 ps
CPU time 29.02 seconds
Started Aug 12 05:36:10 PM PDT 24
Finished Aug 12 05:36:39 PM PDT 24
Peak memory 238100 kb
Host smart-209170fb-69ff-4d5e-a311-7667152b35b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476626186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3476626186
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2796171447
Short name T947
Test name
Test status
Simulation time 85091896 ps
CPU time 1.05 seconds
Started Aug 12 05:36:10 PM PDT 24
Finished Aug 12 05:36:11 PM PDT 24
Peak memory 216672 kb
Host smart-1546716a-3bff-471f-9d1f-a95d6b00a7f5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796171447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2796171447
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1863936056
Short name T944
Test name
Test status
Simulation time 1025293380 ps
CPU time 4.79 seconds
Started Aug 12 05:36:33 PM PDT 24
Finished Aug 12 05:36:38 PM PDT 24
Peak memory 224584 kb
Host smart-71d0ab2d-70ff-45eb-831a-91a259dbf9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863936056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1863936056
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1965938286
Short name T292
Test name
Test status
Simulation time 7088294109 ps
CPU time 17.74 seconds
Started Aug 12 05:36:18 PM PDT 24
Finished Aug 12 05:36:36 PM PDT 24
Peak memory 232928 kb
Host smart-4fe4300e-4cfd-465f-a470-2a0be2d5ad15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965938286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1965938286
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.251044331
Short name T518
Test name
Test status
Simulation time 3700800732 ps
CPU time 9.73 seconds
Started Aug 12 05:36:23 PM PDT 24
Finished Aug 12 05:36:33 PM PDT 24
Peak memory 222788 kb
Host smart-8edc58b1-2926-4d2c-a61f-bcf3173a7d55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=251044331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.251044331
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.4017885605
Short name T19
Test name
Test status
Simulation time 78487967 ps
CPU time 1.32 seconds
Started Aug 12 05:36:43 PM PDT 24
Finished Aug 12 05:36:44 PM PDT 24
Peak memory 207072 kb
Host smart-fc5c5165-da3f-4ccb-98ab-6b63420f6516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017885605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.4017885605
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.4280123961
Short name T861
Test name
Test status
Simulation time 2574454649 ps
CPU time 23.33 seconds
Started Aug 12 05:36:28 PM PDT 24
Finished Aug 12 05:36:51 PM PDT 24
Peak memory 216540 kb
Host smart-5248fba7-af45-4d20-b946-b3b78f1a6058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280123961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.4280123961
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2276145199
Short name T879
Test name
Test status
Simulation time 6903844962 ps
CPU time 8.59 seconds
Started Aug 12 05:36:36 PM PDT 24
Finished Aug 12 05:36:45 PM PDT 24
Peak memory 216364 kb
Host smart-7bb7f38e-7844-4331-aae5-45f67d4336cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276145199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2276145199
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.667335473
Short name T642
Test name
Test status
Simulation time 102833334 ps
CPU time 1.52 seconds
Started Aug 12 05:36:33 PM PDT 24
Finished Aug 12 05:36:35 PM PDT 24
Peak memory 216404 kb
Host smart-b820fcaf-c6c0-46f8-8007-3992470a9b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667335473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.667335473
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3490467073
Short name T349
Test name
Test status
Simulation time 59159332 ps
CPU time 0.71 seconds
Started Aug 12 05:36:23 PM PDT 24
Finished Aug 12 05:36:24 PM PDT 24
Peak memory 206052 kb
Host smart-c090c77e-2249-462a-a053-e4fab9397cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490467073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3490467073
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.162735632
Short name T438
Test name
Test status
Simulation time 5141531162 ps
CPU time 9.18 seconds
Started Aug 12 05:36:34 PM PDT 24
Finished Aug 12 05:36:44 PM PDT 24
Peak memory 232988 kb
Host smart-45083b9e-0f4d-47d1-b13f-e384aede7b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162735632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.162735632
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1790704014
Short name T736
Test name
Test status
Simulation time 12954925 ps
CPU time 0.72 seconds
Started Aug 12 05:35:50 PM PDT 24
Finished Aug 12 05:35:51 PM PDT 24
Peak memory 205296 kb
Host smart-f6175142-07f8-483a-8045-ae064a9ac757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790704014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
790704014
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.712502175
Short name T618
Test name
Test status
Simulation time 131064944 ps
CPU time 2.58 seconds
Started Aug 12 05:35:21 PM PDT 24
Finished Aug 12 05:35:24 PM PDT 24
Peak memory 224724 kb
Host smart-9c0da1a3-06a6-44fe-8db5-cc17c33142b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712502175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.712502175
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1482616175
Short name T929
Test name
Test status
Simulation time 17807893 ps
CPU time 0.84 seconds
Started Aug 12 05:35:37 PM PDT 24
Finished Aug 12 05:35:38 PM PDT 24
Peak memory 206524 kb
Host smart-4e0f1e87-c2ab-4a79-8269-0283481420d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482616175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1482616175
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.171569691
Short name T793
Test name
Test status
Simulation time 12161704054 ps
CPU time 100.5 seconds
Started Aug 12 05:35:29 PM PDT 24
Finished Aug 12 05:37:09 PM PDT 24
Peak memory 256228 kb
Host smart-ec54ea42-5ba2-4478-9d55-5dfd3358d3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171569691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.171569691
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3426107543
Short name T627
Test name
Test status
Simulation time 19473753640 ps
CPU time 71.37 seconds
Started Aug 12 05:35:49 PM PDT 24
Finished Aug 12 05:37:00 PM PDT 24
Peak memory 254420 kb
Host smart-143c78c6-73ee-4488-b609-28c130f1dab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426107543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3426107543
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2134920803
Short name T689
Test name
Test status
Simulation time 8039594013 ps
CPU time 77.04 seconds
Started Aug 12 05:35:42 PM PDT 24
Finished Aug 12 05:37:00 PM PDT 24
Peak memory 233068 kb
Host smart-efef1cc0-f4d2-4fc8-9ca1-985168a92ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134920803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2134920803
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.568508245
Short name T857
Test name
Test status
Simulation time 5318107548 ps
CPU time 63.1 seconds
Started Aug 12 05:35:41 PM PDT 24
Finished Aug 12 05:36:44 PM PDT 24
Peak memory 237896 kb
Host smart-bb75899f-e342-441d-b08a-e81f358d3900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568508245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.568508245
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.440067545
Short name T261
Test name
Test status
Simulation time 54110397483 ps
CPU time 130.74 seconds
Started Aug 12 05:35:47 PM PDT 24
Finished Aug 12 05:37:58 PM PDT 24
Peak memory 255248 kb
Host smart-1931364b-940d-4d23-92d2-9515e82b3544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440067545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
440067545
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.574596375
Short name T915
Test name
Test status
Simulation time 723368198 ps
CPU time 4.74 seconds
Started Aug 12 05:35:32 PM PDT 24
Finished Aug 12 05:35:37 PM PDT 24
Peak memory 224668 kb
Host smart-fe4595b0-27be-408e-b289-e0c4deae8731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574596375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.574596375
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2848377611
Short name T942
Test name
Test status
Simulation time 12998045725 ps
CPU time 8.91 seconds
Started Aug 12 05:35:23 PM PDT 24
Finished Aug 12 05:35:32 PM PDT 24
Peak memory 232952 kb
Host smart-e54a2327-83c3-4954-8936-bba2c44306b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848377611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2848377611
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.700198770
Short name T497
Test name
Test status
Simulation time 53903799 ps
CPU time 1.05 seconds
Started Aug 12 05:35:34 PM PDT 24
Finished Aug 12 05:35:35 PM PDT 24
Peak memory 217912 kb
Host smart-8d695e07-6cb5-4e38-8d13-6d0ec75fd923
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700198770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.700198770
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.123993203
Short name T1013
Test name
Test status
Simulation time 507271700 ps
CPU time 3.69 seconds
Started Aug 12 05:35:57 PM PDT 24
Finished Aug 12 05:36:01 PM PDT 24
Peak memory 232752 kb
Host smart-1c6a1ecd-9817-4f92-9cf4-344db413c74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123993203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
123993203
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3516511075
Short name T621
Test name
Test status
Simulation time 8858851870 ps
CPU time 10.89 seconds
Started Aug 12 05:35:31 PM PDT 24
Finished Aug 12 05:35:42 PM PDT 24
Peak memory 240592 kb
Host smart-80eb3e8e-2c5f-4c4c-bd7a-cf9903795459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516511075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3516511075
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.227762567
Short name T156
Test name
Test status
Simulation time 904900632 ps
CPU time 3.25 seconds
Started Aug 12 05:36:01 PM PDT 24
Finished Aug 12 05:36:05 PM PDT 24
Peak memory 222112 kb
Host smart-d4084ce4-ec42-4f03-aebc-7a7a6b166537
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=227762567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.227762567
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1311656535
Short name T77
Test name
Test status
Simulation time 84158825 ps
CPU time 1.18 seconds
Started Aug 12 05:35:48 PM PDT 24
Finished Aug 12 05:35:50 PM PDT 24
Peak memory 236952 kb
Host smart-2c1e7bee-1055-442d-8af0-10a4aa229ce6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311656535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1311656535
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2564505726
Short name T419
Test name
Test status
Simulation time 15572004339 ps
CPU time 171.29 seconds
Started Aug 12 05:35:43 PM PDT 24
Finished Aug 12 05:38:35 PM PDT 24
Peak memory 257612 kb
Host smart-2fe7f552-db5f-4b05-bec3-a2754279d96f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564505726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2564505726
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3876198854
Short name T393
Test name
Test status
Simulation time 15286366790 ps
CPU time 19.76 seconds
Started Aug 12 05:35:33 PM PDT 24
Finished Aug 12 05:35:53 PM PDT 24
Peak memory 216728 kb
Host smart-98e82c40-bf78-4e51-8330-557e2eb518d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876198854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3876198854
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2115222752
Short name T356
Test name
Test status
Simulation time 1138245896 ps
CPU time 5.7 seconds
Started Aug 12 05:35:39 PM PDT 24
Finished Aug 12 05:35:45 PM PDT 24
Peak memory 216376 kb
Host smart-1fd51cd6-1891-4b9b-bcb4-8f211413568f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115222752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2115222752
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3245094362
Short name T900
Test name
Test status
Simulation time 29077215 ps
CPU time 0.79 seconds
Started Aug 12 05:35:54 PM PDT 24
Finished Aug 12 05:35:54 PM PDT 24
Peak memory 206100 kb
Host smart-1a7cbee9-b953-42ac-a744-ad8970f9d04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245094362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3245094362
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1874862727
Short name T919
Test name
Test status
Simulation time 113100723 ps
CPU time 0.83 seconds
Started Aug 12 05:35:38 PM PDT 24
Finished Aug 12 05:35:39 PM PDT 24
Peak memory 206012 kb
Host smart-5cf8aa78-87e0-43b6-b525-5d2daf4d7b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874862727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1874862727
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2435043078
Short name T403
Test name
Test status
Simulation time 2451019081 ps
CPU time 7.45 seconds
Started Aug 12 05:35:38 PM PDT 24
Finished Aug 12 05:35:46 PM PDT 24
Peak memory 232976 kb
Host smart-91c96052-22c9-4299-9b50-8bdd71736d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435043078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2435043078
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2300376277
Short name T339
Test name
Test status
Simulation time 77668165 ps
CPU time 0.71 seconds
Started Aug 12 05:36:22 PM PDT 24
Finished Aug 12 05:36:22 PM PDT 24
Peak memory 205264 kb
Host smart-60ce9bf2-741d-4bc4-aac6-7f4021893182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300376277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2300376277
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3993402281
Short name T64
Test name
Test status
Simulation time 5261129557 ps
CPU time 13.96 seconds
Started Aug 12 05:36:19 PM PDT 24
Finished Aug 12 05:36:33 PM PDT 24
Peak memory 224816 kb
Host smart-0b4bd23a-8c7f-4aca-8378-5cc416154b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993402281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3993402281
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.165231054
Short name T337
Test name
Test status
Simulation time 26376626 ps
CPU time 0.74 seconds
Started Aug 12 05:36:17 PM PDT 24
Finished Aug 12 05:36:18 PM PDT 24
Peak memory 205808 kb
Host smart-35adf0d2-589a-4924-be96-27e651af6be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165231054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.165231054
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2699609220
Short name T222
Test name
Test status
Simulation time 40495610867 ps
CPU time 165.07 seconds
Started Aug 12 05:36:15 PM PDT 24
Finished Aug 12 05:39:00 PM PDT 24
Peak memory 250392 kb
Host smart-8b47d57c-120a-4fe3-bad8-8f7138286236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699609220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2699609220
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.211440519
Short name T256
Test name
Test status
Simulation time 152273000201 ps
CPU time 153.44 seconds
Started Aug 12 05:36:16 PM PDT 24
Finished Aug 12 05:38:50 PM PDT 24
Peak memory 264648 kb
Host smart-b17ba815-7ab7-4950-838e-9dfda5992a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211440519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.211440519
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2546048214
Short name T209
Test name
Test status
Simulation time 6842629263 ps
CPU time 34.06 seconds
Started Aug 12 05:36:42 PM PDT 24
Finished Aug 12 05:37:16 PM PDT 24
Peak memory 222432 kb
Host smart-a5e29d72-aaac-4eb6-b417-1698986c561e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546048214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2546048214
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3697199066
Short name T366
Test name
Test status
Simulation time 603436791 ps
CPU time 5.53 seconds
Started Aug 12 05:36:35 PM PDT 24
Finished Aug 12 05:36:41 PM PDT 24
Peak memory 241084 kb
Host smart-bdee5ff3-ad9b-4f8b-9788-fb119e6e0c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697199066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3697199066
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1022794042
Short name T24
Test name
Test status
Simulation time 19466587437 ps
CPU time 34.08 seconds
Started Aug 12 05:36:31 PM PDT 24
Finished Aug 12 05:37:05 PM PDT 24
Peak memory 239964 kb
Host smart-910a3c4b-6a71-45fc-9d59-62c1b528dc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022794042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1022794042
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.458313693
Short name T643
Test name
Test status
Simulation time 102159673 ps
CPU time 2.12 seconds
Started Aug 12 05:36:46 PM PDT 24
Finished Aug 12 05:36:48 PM PDT 24
Peak memory 224076 kb
Host smart-dd537baf-a441-46e9-bb4e-72b239032ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458313693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.458313693
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1330996658
Short name T39
Test name
Test status
Simulation time 839585478 ps
CPU time 6.4 seconds
Started Aug 12 05:36:30 PM PDT 24
Finished Aug 12 05:36:36 PM PDT 24
Peak memory 232888 kb
Host smart-cc08bd2f-2973-444b-8cec-09f7caf2986e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330996658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1330996658
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1207290514
Short name T771
Test name
Test status
Simulation time 12417908429 ps
CPU time 6.04 seconds
Started Aug 12 05:36:30 PM PDT 24
Finished Aug 12 05:36:37 PM PDT 24
Peak memory 224724 kb
Host smart-cd94a245-31d0-4125-85ae-a69d06aa1b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207290514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1207290514
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1920592692
Short name T1020
Test name
Test status
Simulation time 1846184976 ps
CPU time 16.29 seconds
Started Aug 12 05:36:18 PM PDT 24
Finished Aug 12 05:36:34 PM PDT 24
Peak memory 222752 kb
Host smart-dbc22328-9ce7-4b0e-b2f4-c23f44ed8f73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1920592692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1920592692
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.4206399303
Short name T300
Test name
Test status
Simulation time 46143824245 ps
CPU time 478.56 seconds
Started Aug 12 05:36:14 PM PDT 24
Finished Aug 12 05:44:13 PM PDT 24
Peak memory 282012 kb
Host smart-59c1bbb1-1e38-46a4-8ea4-17dfd20562f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206399303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.4206399303
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1919759499
Short name T747
Test name
Test status
Simulation time 7444722959 ps
CPU time 26.83 seconds
Started Aug 12 05:36:22 PM PDT 24
Finished Aug 12 05:36:49 PM PDT 24
Peak memory 216496 kb
Host smart-166e9015-e671-494b-85ce-58cd1e5ff87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919759499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1919759499
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3504161339
Short name T333
Test name
Test status
Simulation time 591678080 ps
CPU time 3.36 seconds
Started Aug 12 05:36:33 PM PDT 24
Finished Aug 12 05:36:37 PM PDT 24
Peak memory 216340 kb
Host smart-a46e47b1-330d-4cd4-8460-e3d94ee08d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504161339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3504161339
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2925523072
Short name T912
Test name
Test status
Simulation time 58491372 ps
CPU time 1.3 seconds
Started Aug 12 05:36:52 PM PDT 24
Finished Aug 12 05:36:54 PM PDT 24
Peak memory 216404 kb
Host smart-21b8d6c5-a5c3-4e44-b36a-444a3a2ce95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925523072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2925523072
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3128804641
Short name T531
Test name
Test status
Simulation time 285146360 ps
CPU time 0.93 seconds
Started Aug 12 05:36:11 PM PDT 24
Finished Aug 12 05:36:12 PM PDT 24
Peak memory 206036 kb
Host smart-411a9781-2c5a-4aa5-b72d-5a9ab7d0bd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128804641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3128804641
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3660274274
Short name T442
Test name
Test status
Simulation time 5498257052 ps
CPU time 9.18 seconds
Started Aug 12 05:36:44 PM PDT 24
Finished Aug 12 05:36:53 PM PDT 24
Peak memory 224736 kb
Host smart-45e019fd-f03c-49c4-bf91-5d350b25c324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660274274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3660274274
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.383919236
Short name T961
Test name
Test status
Simulation time 45003143 ps
CPU time 0.75 seconds
Started Aug 12 05:36:23 PM PDT 24
Finished Aug 12 05:36:24 PM PDT 24
Peak memory 205628 kb
Host smart-0cd996ce-89b8-486b-8c1f-519281b237eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383919236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.383919236
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3018546709
Short name T887
Test name
Test status
Simulation time 170075137 ps
CPU time 2.39 seconds
Started Aug 12 05:36:24 PM PDT 24
Finished Aug 12 05:36:27 PM PDT 24
Peak memory 224484 kb
Host smart-23dfb8d2-09e3-495a-abdd-75274fce1937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018546709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3018546709
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3825707029
Short name T482
Test name
Test status
Simulation time 22685509 ps
CPU time 0.75 seconds
Started Aug 12 05:36:21 PM PDT 24
Finished Aug 12 05:36:21 PM PDT 24
Peak memory 206492 kb
Host smart-28193ae8-53d9-4876-84c1-9af7d1c8edfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825707029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3825707029
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2540247712
Short name T60
Test name
Test status
Simulation time 6968044792 ps
CPU time 96.19 seconds
Started Aug 12 05:36:41 PM PDT 24
Finished Aug 12 05:38:18 PM PDT 24
Peak memory 265516 kb
Host smart-c80da56a-2896-4f9a-924f-d1e61e6ded7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540247712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2540247712
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.142617746
Short name T672
Test name
Test status
Simulation time 6618701706 ps
CPU time 65.74 seconds
Started Aug 12 05:36:21 PM PDT 24
Finished Aug 12 05:37:27 PM PDT 24
Peak memory 250464 kb
Host smart-579ea472-4cc8-453f-9780-9d195b1d9cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142617746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.142617746
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.253339045
Short name T26
Test name
Test status
Simulation time 24426465825 ps
CPU time 235.68 seconds
Started Aug 12 05:36:18 PM PDT 24
Finished Aug 12 05:40:14 PM PDT 24
Peak memory 251896 kb
Host smart-a6df65f5-fea4-44ba-922d-e008d33525aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253339045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.253339045
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.4141441251
Short name T808
Test name
Test status
Simulation time 26418795299 ps
CPU time 124.61 seconds
Started Aug 12 05:36:28 PM PDT 24
Finished Aug 12 05:38:33 PM PDT 24
Peak memory 249396 kb
Host smart-265b9917-2658-43a0-8bca-35a3fa6f0722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141441251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.4141441251
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2189592697
Short name T731
Test name
Test status
Simulation time 822047873 ps
CPU time 5.74 seconds
Started Aug 12 05:36:20 PM PDT 24
Finished Aug 12 05:36:26 PM PDT 24
Peak memory 224504 kb
Host smart-9914ca8f-8eff-428b-8980-953d4e6984ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189592697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2189592697
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2103907704
Short name T670
Test name
Test status
Simulation time 2204941132 ps
CPU time 23.96 seconds
Started Aug 12 05:36:33 PM PDT 24
Finished Aug 12 05:36:58 PM PDT 24
Peak memory 234532 kb
Host smart-17ba08c4-3126-4975-961d-4c3a434bfa48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103907704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2103907704
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1008709186
Short name T981
Test name
Test status
Simulation time 335644313 ps
CPU time 2.29 seconds
Started Aug 12 05:36:19 PM PDT 24
Finished Aug 12 05:36:22 PM PDT 24
Peak memory 232864 kb
Host smart-a670fbd8-cc46-48c0-b354-6bb39f435dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008709186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1008709186
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1457436737
Short name T946
Test name
Test status
Simulation time 320484695 ps
CPU time 4.46 seconds
Started Aug 12 05:36:15 PM PDT 24
Finished Aug 12 05:36:19 PM PDT 24
Peak memory 232888 kb
Host smart-fbbdf35f-1e23-472d-975c-cb43e2fdfb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457436737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1457436737
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2947244300
Short name T432
Test name
Test status
Simulation time 235933738 ps
CPU time 4.22 seconds
Started Aug 12 05:36:39 PM PDT 24
Finished Aug 12 05:36:44 PM PDT 24
Peak memory 219600 kb
Host smart-4de59a5a-1fba-421d-9fa6-303c17bff5ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2947244300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2947244300
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.828285818
Short name T169
Test name
Test status
Simulation time 346736918187 ps
CPU time 659.57 seconds
Started Aug 12 05:36:27 PM PDT 24
Finished Aug 12 05:47:26 PM PDT 24
Peak memory 265820 kb
Host smart-e9ac4d36-8760-4685-8757-bff3cbbffbd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828285818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.828285818
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1109202755
Short name T61
Test name
Test status
Simulation time 2088424815 ps
CPU time 12.02 seconds
Started Aug 12 05:36:33 PM PDT 24
Finished Aug 12 05:36:45 PM PDT 24
Peak memory 216448 kb
Host smart-023ccf91-ef44-494d-9a25-ca300e37e3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109202755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1109202755
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.4084460186
Short name T571
Test name
Test status
Simulation time 10916773609 ps
CPU time 6.21 seconds
Started Aug 12 05:36:37 PM PDT 24
Finished Aug 12 05:36:44 PM PDT 24
Peak memory 216432 kb
Host smart-ee811450-6ea2-4b1b-ad08-61628ac7de87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084460186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.4084460186
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2327256000
Short name T594
Test name
Test status
Simulation time 17660368 ps
CPU time 0.75 seconds
Started Aug 12 05:36:10 PM PDT 24
Finished Aug 12 05:36:11 PM PDT 24
Peak memory 206044 kb
Host smart-7cb06c10-b71c-467a-ab33-9ce3f22ea06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327256000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2327256000
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3355990238
Short name T541
Test name
Test status
Simulation time 172159375 ps
CPU time 0.85 seconds
Started Aug 12 05:36:16 PM PDT 24
Finished Aug 12 05:36:17 PM PDT 24
Peak memory 206040 kb
Host smart-45d6b1a1-e455-48d3-8e29-6a9ab7b81474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355990238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3355990238
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1927772626
Short name T686
Test name
Test status
Simulation time 2703590589 ps
CPU time 4.85 seconds
Started Aug 12 05:36:24 PM PDT 24
Finished Aug 12 05:36:29 PM PDT 24
Peak memory 224628 kb
Host smart-5f94bc96-fdf2-4ace-b58f-e309ab27111b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927772626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1927772626
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2778505219
Short name T966
Test name
Test status
Simulation time 13874749 ps
CPU time 0.71 seconds
Started Aug 12 05:36:38 PM PDT 24
Finished Aug 12 05:36:39 PM PDT 24
Peak memory 204748 kb
Host smart-8c6e7bdb-2daf-4eab-9c25-675e563d42a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778505219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2778505219
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.595490256
Short name T15
Test name
Test status
Simulation time 847909208 ps
CPU time 3.94 seconds
Started Aug 12 05:36:35 PM PDT 24
Finished Aug 12 05:36:40 PM PDT 24
Peak memory 232804 kb
Host smart-d11c1b15-ce72-429b-be15-eb313209494f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595490256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.595490256
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2897412921
Short name T784
Test name
Test status
Simulation time 40635550 ps
CPU time 0.75 seconds
Started Aug 12 05:36:24 PM PDT 24
Finished Aug 12 05:36:25 PM PDT 24
Peak memory 205468 kb
Host smart-5cf3028b-8366-40a7-9187-ead704d4b22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897412921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2897412921
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3279317995
Short name T225
Test name
Test status
Simulation time 40907872033 ps
CPU time 210.4 seconds
Started Aug 12 05:36:41 PM PDT 24
Finished Aug 12 05:40:12 PM PDT 24
Peak memory 271252 kb
Host smart-edabacb6-bf12-47a6-a636-8f95b864d5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279317995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3279317995
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1410981739
Short name T1008
Test name
Test status
Simulation time 14835466628 ps
CPU time 90.53 seconds
Started Aug 12 05:36:45 PM PDT 24
Finished Aug 12 05:38:15 PM PDT 24
Peak memory 268420 kb
Host smart-333ea393-d1b4-43fd-86cb-de207dd13e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410981739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1410981739
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1673401109
Short name T927
Test name
Test status
Simulation time 137737401 ps
CPU time 4.17 seconds
Started Aug 12 05:36:27 PM PDT 24
Finished Aug 12 05:36:32 PM PDT 24
Peak memory 234320 kb
Host smart-739d57ad-9d8f-4ed3-a5ff-73ec35ffadf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673401109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1673401109
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3287625096
Short name T657
Test name
Test status
Simulation time 75491356843 ps
CPU time 516.17 seconds
Started Aug 12 05:36:27 PM PDT 24
Finished Aug 12 05:45:04 PM PDT 24
Peak memory 255448 kb
Host smart-4449c142-8b3b-4d26-b209-bd1b5a9888ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287625096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3287625096
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.573240604
Short name T265
Test name
Test status
Simulation time 2017608718 ps
CPU time 18.06 seconds
Started Aug 12 05:36:29 PM PDT 24
Finished Aug 12 05:36:48 PM PDT 24
Peak memory 232928 kb
Host smart-6ff40ba4-68ef-44b5-be5f-860cdc597253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573240604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.573240604
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3879954578
Short name T705
Test name
Test status
Simulation time 43735594498 ps
CPU time 54.19 seconds
Started Aug 12 05:36:27 PM PDT 24
Finished Aug 12 05:37:22 PM PDT 24
Peak memory 232964 kb
Host smart-fe0e7551-b61b-4212-86cb-9f752866f4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879954578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3879954578
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4065093179
Short name T296
Test name
Test status
Simulation time 30015949710 ps
CPU time 23.39 seconds
Started Aug 12 05:36:22 PM PDT 24
Finished Aug 12 05:36:46 PM PDT 24
Peak memory 224716 kb
Host smart-1933c52c-9b8a-4ae0-b51d-11089b53b711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065093179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4065093179
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1726606248
Short name T1010
Test name
Test status
Simulation time 763437626 ps
CPU time 2.45 seconds
Started Aug 12 05:36:15 PM PDT 24
Finished Aug 12 05:36:18 PM PDT 24
Peak memory 224024 kb
Host smart-c7ba9c66-10df-4def-a5c6-090a562d1cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726606248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1726606248
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1060409130
Short name T764
Test name
Test status
Simulation time 137383589 ps
CPU time 3.75 seconds
Started Aug 12 05:36:38 PM PDT 24
Finished Aug 12 05:36:42 PM PDT 24
Peak memory 222716 kb
Host smart-a2d78819-67f2-4e55-97c7-68a96419e76e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1060409130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1060409130
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2304423038
Short name T955
Test name
Test status
Simulation time 271815977257 ps
CPU time 559.41 seconds
Started Aug 12 05:36:23 PM PDT 24
Finished Aug 12 05:45:42 PM PDT 24
Peak memory 272472 kb
Host smart-8fcd27f7-9393-4945-856e-8caa3f702d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304423038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2304423038
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.124121023
Short name T383
Test name
Test status
Simulation time 466443071 ps
CPU time 6.31 seconds
Started Aug 12 05:36:16 PM PDT 24
Finished Aug 12 05:36:23 PM PDT 24
Peak memory 216508 kb
Host smart-dcc16a27-1511-4d35-9741-915d313c5805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124121023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.124121023
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2973824898
Short name T472
Test name
Test status
Simulation time 775272472 ps
CPU time 6.05 seconds
Started Aug 12 05:36:17 PM PDT 24
Finished Aug 12 05:36:23 PM PDT 24
Peak memory 216360 kb
Host smart-550c4b48-ed67-4c1d-84d1-4e67b1614383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973824898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2973824898
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.658142598
Short name T993
Test name
Test status
Simulation time 101293103 ps
CPU time 2.38 seconds
Started Aug 12 05:36:19 PM PDT 24
Finished Aug 12 05:36:21 PM PDT 24
Peak memory 216356 kb
Host smart-96321c33-0a09-4e9b-9868-580f354365eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658142598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.658142598
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3609386289
Short name T822
Test name
Test status
Simulation time 868634678 ps
CPU time 0.95 seconds
Started Aug 12 05:36:43 PM PDT 24
Finished Aug 12 05:36:44 PM PDT 24
Peak memory 206444 kb
Host smart-c24777ff-18d0-4059-aae3-445508ba67ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609386289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3609386289
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.4273027434
Short name T226
Test name
Test status
Simulation time 233481189 ps
CPU time 3.16 seconds
Started Aug 12 05:36:34 PM PDT 24
Finished Aug 12 05:36:38 PM PDT 24
Peak memory 224616 kb
Host smart-90c55a85-fb85-4658-b974-d64857f86768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273027434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.4273027434
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1742864763
Short name T397
Test name
Test status
Simulation time 34016639 ps
CPU time 0.69 seconds
Started Aug 12 05:36:32 PM PDT 24
Finished Aug 12 05:36:33 PM PDT 24
Peak memory 205612 kb
Host smart-120bd9f2-6e4d-4607-a47a-e037e23368b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742864763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1742864763
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3608266671
Short name T551
Test name
Test status
Simulation time 21014452 ps
CPU time 0.77 seconds
Started Aug 12 05:36:20 PM PDT 24
Finished Aug 12 05:36:21 PM PDT 24
Peak memory 206432 kb
Host smart-02e651f8-cee6-49f4-acc9-540031230d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608266671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3608266671
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.637228162
Short name T666
Test name
Test status
Simulation time 28711093783 ps
CPU time 219.28 seconds
Started Aug 12 05:36:34 PM PDT 24
Finished Aug 12 05:40:13 PM PDT 24
Peak memory 267336 kb
Host smart-162f3ede-6f30-40d5-a1fd-a965c56ba0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637228162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.637228162
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1537188371
Short name T377
Test name
Test status
Simulation time 13130935996 ps
CPU time 156.96 seconds
Started Aug 12 05:36:45 PM PDT 24
Finished Aug 12 05:39:22 PM PDT 24
Peak memory 262180 kb
Host smart-3bee6ee9-8580-47a7-a6b6-05e497d73256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537188371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1537188371
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2124010975
Short name T144
Test name
Test status
Simulation time 665136821 ps
CPU time 3.16 seconds
Started Aug 12 05:36:16 PM PDT 24
Finished Aug 12 05:36:20 PM PDT 24
Peak memory 224720 kb
Host smart-3e791a42-0d6e-45c9-96f3-a9be67bf6512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124010975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2124010975
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1825158418
Short name T173
Test name
Test status
Simulation time 1972395214 ps
CPU time 3.45 seconds
Started Aug 12 05:36:39 PM PDT 24
Finished Aug 12 05:36:42 PM PDT 24
Peak memory 232896 kb
Host smart-9784d66e-4a4b-4537-9d63-2cbf64ee2b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825158418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1825158418
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3109405156
Short name T581
Test name
Test status
Simulation time 48249566 ps
CPU time 2.43 seconds
Started Aug 12 05:36:45 PM PDT 24
Finished Aug 12 05:36:48 PM PDT 24
Peak memory 232544 kb
Host smart-122b9662-2d0e-420a-92cf-d14131a7807f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109405156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3109405156
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3934626997
Short name T468
Test name
Test status
Simulation time 2466372232 ps
CPU time 9.38 seconds
Started Aug 12 05:36:18 PM PDT 24
Finished Aug 12 05:36:27 PM PDT 24
Peak memory 232984 kb
Host smart-67a7acb6-bf99-4b99-b4fc-375f4ed092df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934626997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3934626997
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2383807022
Short name T692
Test name
Test status
Simulation time 1947807945 ps
CPU time 5.01 seconds
Started Aug 12 05:36:20 PM PDT 24
Finished Aug 12 05:36:25 PM PDT 24
Peak memory 232956 kb
Host smart-daedd19a-f34f-40c2-b562-674a2a69c8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383807022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2383807022
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2051957855
Short name T389
Test name
Test status
Simulation time 666075386 ps
CPU time 5.69 seconds
Started Aug 12 05:36:33 PM PDT 24
Finished Aug 12 05:36:39 PM PDT 24
Peak memory 221924 kb
Host smart-bb6b3b8c-7076-4a3d-a2aa-bdb0df8a0173
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2051957855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2051957855
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3907787751
Short name T750
Test name
Test status
Simulation time 32594271704 ps
CPU time 314.81 seconds
Started Aug 12 05:36:19 PM PDT 24
Finished Aug 12 05:41:34 PM PDT 24
Peak memory 268272 kb
Host smart-545e9f60-0d89-4c3b-9a49-dd9b011028eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907787751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3907787751
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3039881729
Short name T1029
Test name
Test status
Simulation time 8631931451 ps
CPU time 9.56 seconds
Started Aug 12 05:36:37 PM PDT 24
Finished Aug 12 05:36:47 PM PDT 24
Peak memory 216492 kb
Host smart-ae6e8110-a062-4fe3-bb4e-4eaea0dac568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039881729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3039881729
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.144906085
Short name T355
Test name
Test status
Simulation time 2299331158 ps
CPU time 2.09 seconds
Started Aug 12 05:36:43 PM PDT 24
Finished Aug 12 05:36:45 PM PDT 24
Peak memory 207164 kb
Host smart-3d4a3ee5-9983-4bab-b679-76138b035c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144906085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.144906085
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2981627366
Short name T655
Test name
Test status
Simulation time 14542810 ps
CPU time 0.93 seconds
Started Aug 12 05:36:31 PM PDT 24
Finished Aug 12 05:36:32 PM PDT 24
Peak memory 207076 kb
Host smart-692ee48b-d7bd-4c10-b579-02ab05aab549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981627366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2981627366
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3446869134
Short name T402
Test name
Test status
Simulation time 83508201 ps
CPU time 0.93 seconds
Started Aug 12 05:36:43 PM PDT 24
Finished Aug 12 05:36:44 PM PDT 24
Peak memory 205916 kb
Host smart-ec39562b-ff4b-41a2-9bb8-8a9659ba2c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446869134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3446869134
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.599622594
Short name T36
Test name
Test status
Simulation time 1418574614 ps
CPU time 6.39 seconds
Started Aug 12 05:36:34 PM PDT 24
Finished Aug 12 05:36:41 PM PDT 24
Peak memory 224588 kb
Host smart-06760bd9-5bf1-48fa-8168-3f00f85f9441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599622594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.599622594
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1287194387
Short name T452
Test name
Test status
Simulation time 44751988 ps
CPU time 0.71 seconds
Started Aug 12 05:36:43 PM PDT 24
Finished Aug 12 05:36:44 PM PDT 24
Peak memory 204748 kb
Host smart-66f1d45d-af6a-41ea-ae4f-4fde1ae9cc0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287194387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1287194387
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3915960961
Short name T701
Test name
Test status
Simulation time 150351598 ps
CPU time 2.2 seconds
Started Aug 12 05:36:39 PM PDT 24
Finished Aug 12 05:36:46 PM PDT 24
Peak memory 232872 kb
Host smart-6dc20adb-7352-4d58-b8b1-64a1a53252e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915960961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3915960961
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1486797256
Short name T772
Test name
Test status
Simulation time 14163723 ps
CPU time 0.77 seconds
Started Aug 12 05:36:40 PM PDT 24
Finished Aug 12 05:36:41 PM PDT 24
Peak memory 205760 kb
Host smart-4ad1cffb-0157-4491-97c5-56411cedf9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486797256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1486797256
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1589830136
Short name T490
Test name
Test status
Simulation time 4950126342 ps
CPU time 27.19 seconds
Started Aug 12 05:36:49 PM PDT 24
Finished Aug 12 05:37:16 PM PDT 24
Peak memory 232984 kb
Host smart-c106e404-b97a-4d8c-898f-675e482c568c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589830136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1589830136
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.111576464
Short name T740
Test name
Test status
Simulation time 3160422138 ps
CPU time 80.93 seconds
Started Aug 12 05:36:24 PM PDT 24
Finished Aug 12 05:37:45 PM PDT 24
Peak memory 249692 kb
Host smart-775527e6-de10-4159-be87-72492c9dec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111576464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.111576464
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3092709297
Short name T499
Test name
Test status
Simulation time 10945811163 ps
CPU time 82.01 seconds
Started Aug 12 05:36:42 PM PDT 24
Finished Aug 12 05:38:09 PM PDT 24
Peak memory 241624 kb
Host smart-b128701e-df00-410c-b094-df8ec2e3e4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092709297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3092709297
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3350346249
Short name T440
Test name
Test status
Simulation time 5386529739 ps
CPU time 21.77 seconds
Started Aug 12 05:36:35 PM PDT 24
Finished Aug 12 05:36:57 PM PDT 24
Peak memory 232992 kb
Host smart-7eed992f-2421-444a-b339-73d8fbe181d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350346249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3350346249
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3998965688
Short name T987
Test name
Test status
Simulation time 8735018815 ps
CPU time 99.86 seconds
Started Aug 12 05:36:33 PM PDT 24
Finished Aug 12 05:38:13 PM PDT 24
Peak memory 265728 kb
Host smart-f09a1364-24b3-4813-944a-f6c0c8998af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998965688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3998965688
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3512109288
Short name T219
Test name
Test status
Simulation time 4394121100 ps
CPU time 9.58 seconds
Started Aug 12 05:36:38 PM PDT 24
Finished Aug 12 05:36:48 PM PDT 24
Peak memory 232984 kb
Host smart-73e8f8bd-ca6c-4513-93b2-fceb68bb3df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512109288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3512109288
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1799472899
Short name T521
Test name
Test status
Simulation time 30449975 ps
CPU time 2.23 seconds
Started Aug 12 05:36:35 PM PDT 24
Finished Aug 12 05:36:38 PM PDT 24
Peak memory 223996 kb
Host smart-0347a102-aead-491e-9308-84b9ad3019c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799472899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1799472899
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2210835365
Short name T247
Test name
Test status
Simulation time 4441037418 ps
CPU time 8.17 seconds
Started Aug 12 05:36:21 PM PDT 24
Finished Aug 12 05:36:29 PM PDT 24
Peak memory 224700 kb
Host smart-7acb2adf-2e83-4443-ac16-45c8cde5ab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210835365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2210835365
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.387557121
Short name T889
Test name
Test status
Simulation time 6282029900 ps
CPU time 9.67 seconds
Started Aug 12 05:36:14 PM PDT 24
Finished Aug 12 05:36:24 PM PDT 24
Peak memory 224780 kb
Host smart-af03d14c-49be-4d43-9f20-03d184cd15cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387557121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.387557121
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2064070369
Short name T937
Test name
Test status
Simulation time 113978602 ps
CPU time 3.98 seconds
Started Aug 12 05:36:45 PM PDT 24
Finished Aug 12 05:36:49 PM PDT 24
Peak memory 222428 kb
Host smart-e115e8e3-d382-49d0-b41e-014414a4e10b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2064070369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2064070369
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1018566897
Short name T167
Test name
Test status
Simulation time 245493956 ps
CPU time 1.03 seconds
Started Aug 12 05:36:44 PM PDT 24
Finished Aug 12 05:36:45 PM PDT 24
Peak memory 215940 kb
Host smart-5b516f24-eb89-4fce-ae88-1786fea98ba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018566897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1018566897
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.428240637
Short name T669
Test name
Test status
Simulation time 1350560908 ps
CPU time 6.66 seconds
Started Aug 12 05:36:41 PM PDT 24
Finished Aug 12 05:36:48 PM PDT 24
Peak memory 216720 kb
Host smart-90e417cb-4f67-4488-abdc-4072b44984fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428240637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.428240637
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4248079466
Short name T936
Test name
Test status
Simulation time 614475494 ps
CPU time 2.9 seconds
Started Aug 12 05:36:46 PM PDT 24
Finished Aug 12 05:36:49 PM PDT 24
Peak memory 216376 kb
Host smart-31ef77d9-f605-47bf-aef6-c1cccb1bcb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248079466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4248079466
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1717480921
Short name T368
Test name
Test status
Simulation time 134203755 ps
CPU time 1.79 seconds
Started Aug 12 05:36:42 PM PDT 24
Finished Aug 12 05:36:45 PM PDT 24
Peak memory 216384 kb
Host smart-278a8afa-77a1-48d4-9fad-5fbc532a6b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717480921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1717480921
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3846468318
Short name T995
Test name
Test status
Simulation time 32166847 ps
CPU time 0.77 seconds
Started Aug 12 05:36:23 PM PDT 24
Finished Aug 12 05:36:24 PM PDT 24
Peak memory 206040 kb
Host smart-795ab3b9-cedd-457e-8f6c-1f93fe99da64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846468318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3846468318
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3824365002
Short name T832
Test name
Test status
Simulation time 17702134143 ps
CPU time 21.47 seconds
Started Aug 12 05:36:42 PM PDT 24
Finished Aug 12 05:37:04 PM PDT 24
Peak memory 249220 kb
Host smart-c0601c52-b95a-4d9f-8861-8322f622b184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824365002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3824365002
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3139035453
Short name T385
Test name
Test status
Simulation time 33462143 ps
CPU time 0.76 seconds
Started Aug 12 05:36:37 PM PDT 24
Finished Aug 12 05:36:38 PM PDT 24
Peak memory 205320 kb
Host smart-f5f04f0d-fd47-417d-8a77-1c19edd97b91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139035453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3139035453
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.676510845
Short name T970
Test name
Test status
Simulation time 743755699 ps
CPU time 5.31 seconds
Started Aug 12 05:36:39 PM PDT 24
Finished Aug 12 05:36:45 PM PDT 24
Peak memory 232924 kb
Host smart-890d42ab-b710-4626-9319-d2b18bff9dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676510845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.676510845
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2761079552
Short name T346
Test name
Test status
Simulation time 18447687 ps
CPU time 0.74 seconds
Started Aug 12 05:36:39 PM PDT 24
Finished Aug 12 05:36:40 PM PDT 24
Peak memory 205492 kb
Host smart-2319e325-a571-41de-a5a1-e6e8441e76ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761079552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2761079552
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1657477401
Short name T259
Test name
Test status
Simulation time 44842267432 ps
CPU time 91.02 seconds
Started Aug 12 05:36:56 PM PDT 24
Finished Aug 12 05:38:27 PM PDT 24
Peak memory 250128 kb
Host smart-f1c4f10a-af80-496d-91a5-e724b94e2dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657477401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1657477401
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2885302869
Short name T751
Test name
Test status
Simulation time 5438428141 ps
CPU time 76.79 seconds
Started Aug 12 05:36:43 PM PDT 24
Finished Aug 12 05:38:00 PM PDT 24
Peak memory 257308 kb
Host smart-2f15303d-aeff-447b-b01a-b70a8a402d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885302869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2885302869
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2453736772
Short name T589
Test name
Test status
Simulation time 81266050 ps
CPU time 0.83 seconds
Started Aug 12 05:36:40 PM PDT 24
Finished Aug 12 05:36:42 PM PDT 24
Peak memory 217444 kb
Host smart-a67105e6-e6da-4676-be05-2242d1e467a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453736772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2453736772
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4111968868
Short name T186
Test name
Test status
Simulation time 3747282750 ps
CPU time 34.45 seconds
Started Aug 12 05:37:03 PM PDT 24
Finished Aug 12 05:37:38 PM PDT 24
Peak memory 237264 kb
Host smart-be2182b6-79c3-4910-a96a-cfdfbe1c36fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111968868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4111968868
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3783192837
Short name T791
Test name
Test status
Simulation time 589609496 ps
CPU time 9.75 seconds
Started Aug 12 05:36:22 PM PDT 24
Finished Aug 12 05:36:32 PM PDT 24
Peak memory 235344 kb
Host smart-6f3d8d72-7377-4b28-9feb-8a729ac1a84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783192837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3783192837
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1400984091
Short name T290
Test name
Test status
Simulation time 73766592 ps
CPU time 2.62 seconds
Started Aug 12 05:36:44 PM PDT 24
Finished Aug 12 05:36:47 PM PDT 24
Peak memory 232904 kb
Host smart-a3070b53-fa04-4074-98c5-9c7f7ccf9575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400984091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1400984091
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1278598091
Short name T480
Test name
Test status
Simulation time 8779567412 ps
CPU time 18.83 seconds
Started Aug 12 05:36:31 PM PDT 24
Finished Aug 12 05:36:50 PM PDT 24
Peak memory 235460 kb
Host smart-e1ca0309-90a2-491a-9d49-20fff6a1e762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278598091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1278598091
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1653292345
Short name T54
Test name
Test status
Simulation time 1411838961 ps
CPU time 5.5 seconds
Started Aug 12 05:36:45 PM PDT 24
Finished Aug 12 05:36:51 PM PDT 24
Peak memory 224640 kb
Host smart-4aafa056-36d4-45cc-ae77-fdde42d32bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653292345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1653292345
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.887526585
Short name T858
Test name
Test status
Simulation time 5388869523 ps
CPU time 10.43 seconds
Started Aug 12 05:36:45 PM PDT 24
Finished Aug 12 05:36:56 PM PDT 24
Peak memory 232960 kb
Host smart-3fb56687-c50e-471d-aef1-bbff74902639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887526585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.887526585
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4018424682
Short name T854
Test name
Test status
Simulation time 2188189237 ps
CPU time 10.15 seconds
Started Aug 12 05:36:46 PM PDT 24
Finished Aug 12 05:36:56 PM PDT 24
Peak memory 220716 kb
Host smart-ab5bfe85-31c6-47da-a161-370ab02194ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4018424682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4018424682
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.4122096704
Short name T45
Test name
Test status
Simulation time 67533096775 ps
CPU time 748.67 seconds
Started Aug 12 05:36:31 PM PDT 24
Finished Aug 12 05:49:00 PM PDT 24
Peak memory 290320 kb
Host smart-b3b212bc-dc67-493d-8ce3-7773b7654b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122096704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.4122096704
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2147360345
Short name T836
Test name
Test status
Simulation time 2739132673 ps
CPU time 28.53 seconds
Started Aug 12 05:36:36 PM PDT 24
Finished Aug 12 05:37:04 PM PDT 24
Peak memory 216412 kb
Host smart-98bdc0ad-91bb-4e1b-8693-ad666ae6343c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147360345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2147360345
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2920746131
Short name T553
Test name
Test status
Simulation time 1255274623 ps
CPU time 4.84 seconds
Started Aug 12 05:36:24 PM PDT 24
Finished Aug 12 05:36:29 PM PDT 24
Peak memory 216340 kb
Host smart-0a2f36bd-f86e-4bfa-95a6-adc5e41036bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920746131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2920746131
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3120744912
Short name T1035
Test name
Test status
Simulation time 52414821 ps
CPU time 1.08 seconds
Started Aug 12 05:36:46 PM PDT 24
Finished Aug 12 05:36:47 PM PDT 24
Peak memory 208236 kb
Host smart-e01b533b-f864-473c-88c3-2921f7437d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120744912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3120744912
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.645663618
Short name T347
Test name
Test status
Simulation time 25107443 ps
CPU time 0.78 seconds
Started Aug 12 05:36:23 PM PDT 24
Finished Aug 12 05:36:24 PM PDT 24
Peak memory 205984 kb
Host smart-e5b1f34c-082c-4b19-9738-7e92b502b8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645663618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.645663618
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2974895134
Short name T398
Test name
Test status
Simulation time 392241890 ps
CPU time 6.23 seconds
Started Aug 12 05:36:33 PM PDT 24
Finished Aug 12 05:36:39 PM PDT 24
Peak memory 239496 kb
Host smart-9a52f4c3-fb5d-4be3-aeac-1d8f55765902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974895134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2974895134
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2512012098
Short name T433
Test name
Test status
Simulation time 12116574 ps
CPU time 0.74 seconds
Started Aug 12 05:36:29 PM PDT 24
Finished Aug 12 05:36:30 PM PDT 24
Peak memory 205292 kb
Host smart-b7865b10-3dd4-432f-865c-11cf811f1650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512012098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2512012098
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.62931065
Short name T695
Test name
Test status
Simulation time 2954153380 ps
CPU time 7.15 seconds
Started Aug 12 05:36:39 PM PDT 24
Finished Aug 12 05:36:46 PM PDT 24
Peak memory 232872 kb
Host smart-d38dd056-3956-480c-8915-c66eb4410a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62931065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.62931065
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.284837622
Short name T328
Test name
Test status
Simulation time 30151458 ps
CPU time 0.76 seconds
Started Aug 12 05:36:47 PM PDT 24
Finished Aug 12 05:36:48 PM PDT 24
Peak memory 205472 kb
Host smart-310ffbcb-17c6-41a9-83ec-3fc540ccd62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284837622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.284837622
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2751008073
Short name T707
Test name
Test status
Simulation time 2176053193 ps
CPU time 29.79 seconds
Started Aug 12 05:36:34 PM PDT 24
Finished Aug 12 05:37:04 PM PDT 24
Peak memory 249020 kb
Host smart-53dc8666-e6cd-4d94-930e-9417d62b1ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751008073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2751008073
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2038610789
Short name T805
Test name
Test status
Simulation time 9946313027 ps
CPU time 90.14 seconds
Started Aug 12 05:36:36 PM PDT 24
Finished Aug 12 05:38:07 PM PDT 24
Peak memory 239428 kb
Host smart-cc5539b1-4999-45a2-a111-59c64a2b0ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038610789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2038610789
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.321848349
Short name T146
Test name
Test status
Simulation time 131466397 ps
CPU time 3.05 seconds
Started Aug 12 05:36:58 PM PDT 24
Finished Aug 12 05:37:01 PM PDT 24
Peak memory 224724 kb
Host smart-0ca9df4b-3180-4ae2-8df2-5418cd409a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321848349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.321848349
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3759020564
Short name T971
Test name
Test status
Simulation time 44724184840 ps
CPU time 166.99 seconds
Started Aug 12 05:36:33 PM PDT 24
Finished Aug 12 05:39:21 PM PDT 24
Peak memory 249384 kb
Host smart-d679cfc2-5e22-47b9-9030-ef15ebb0ea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759020564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3759020564
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.925998804
Short name T779
Test name
Test status
Simulation time 4234717255 ps
CPU time 19.33 seconds
Started Aug 12 05:36:29 PM PDT 24
Finished Aug 12 05:36:48 PM PDT 24
Peak memory 224708 kb
Host smart-cb49e8fa-a894-4eb4-8021-6fbb16724f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925998804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.925998804
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2594125516
Short name T267
Test name
Test status
Simulation time 993256829 ps
CPU time 6.09 seconds
Started Aug 12 05:36:40 PM PDT 24
Finished Aug 12 05:36:47 PM PDT 24
Peak memory 224600 kb
Host smart-2dc0dfc6-ed06-4ee6-a374-4ce5729156b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594125516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2594125516
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.47451889
Short name T826
Test name
Test status
Simulation time 3422581751 ps
CPU time 11.07 seconds
Started Aug 12 05:36:39 PM PDT 24
Finished Aug 12 05:36:50 PM PDT 24
Peak memory 232968 kb
Host smart-3088e496-a7b8-45af-8a4c-1ef6dcfa9b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47451889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.47451889
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.507976763
Short name T905
Test name
Test status
Simulation time 222934971 ps
CPU time 2.57 seconds
Started Aug 12 05:36:34 PM PDT 24
Finished Aug 12 05:36:37 PM PDT 24
Peak memory 224656 kb
Host smart-4b3a4084-497e-45e2-a4d9-ded4fff327de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507976763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.507976763
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3703296093
Short name T708
Test name
Test status
Simulation time 7861361191 ps
CPU time 15.81 seconds
Started Aug 12 05:36:49 PM PDT 24
Finished Aug 12 05:37:05 PM PDT 24
Peak memory 222288 kb
Host smart-9b088e28-5afc-4418-a74e-381e29506a20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3703296093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3703296093
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2683435666
Short name T32
Test name
Test status
Simulation time 27630560702 ps
CPU time 88.37 seconds
Started Aug 12 05:36:47 PM PDT 24
Finished Aug 12 05:38:15 PM PDT 24
Peak memory 270200 kb
Host smart-79256afa-aabc-4757-9351-8c7b49618d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683435666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2683435666
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3748186514
Short name T901
Test name
Test status
Simulation time 3108430537 ps
CPU time 26.92 seconds
Started Aug 12 05:36:40 PM PDT 24
Finished Aug 12 05:37:08 PM PDT 24
Peak memory 216544 kb
Host smart-ab718e2c-30f7-4ffc-932b-f726b4149564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748186514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3748186514
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1103869884
Short name T436
Test name
Test status
Simulation time 855274438 ps
CPU time 5.22 seconds
Started Aug 12 05:36:48 PM PDT 24
Finished Aug 12 05:36:53 PM PDT 24
Peak memory 216308 kb
Host smart-f2de94c9-13da-44ad-8b9c-ac3a68515c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103869884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1103869884
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3099750304
Short name T632
Test name
Test status
Simulation time 469122158 ps
CPU time 1.01 seconds
Started Aug 12 05:36:34 PM PDT 24
Finished Aug 12 05:36:35 PM PDT 24
Peak memory 207988 kb
Host smart-5c7dad19-68f1-4828-9611-3a92fca10d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099750304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3099750304
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4245912279
Short name T496
Test name
Test status
Simulation time 68647783 ps
CPU time 0.83 seconds
Started Aug 12 05:36:35 PM PDT 24
Finished Aug 12 05:36:36 PM PDT 24
Peak memory 205932 kb
Host smart-319bceb8-d02a-48bc-a533-14f4c36dd8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245912279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4245912279
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1751967624
Short name T882
Test name
Test status
Simulation time 12196193296 ps
CPU time 15.05 seconds
Started Aug 12 05:37:00 PM PDT 24
Finished Aug 12 05:37:15 PM PDT 24
Peak memory 241132 kb
Host smart-f56d523e-ed1a-452a-9607-390c67260de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751967624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1751967624
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1338405007
Short name T844
Test name
Test status
Simulation time 11754677 ps
CPU time 0.75 seconds
Started Aug 12 05:36:34 PM PDT 24
Finished Aug 12 05:36:35 PM PDT 24
Peak memory 205308 kb
Host smart-cc790bf4-4850-4a8d-b6c8-fc8ca61977aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338405007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1338405007
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1610472736
Short name T591
Test name
Test status
Simulation time 692137007 ps
CPU time 4.17 seconds
Started Aug 12 05:37:03 PM PDT 24
Finished Aug 12 05:37:07 PM PDT 24
Peak memory 232800 kb
Host smart-1429606b-5c67-4119-995c-154987b88973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610472736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1610472736
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3849703492
Short name T176
Test name
Test status
Simulation time 27922410 ps
CPU time 0.77 seconds
Started Aug 12 05:36:53 PM PDT 24
Finished Aug 12 05:36:54 PM PDT 24
Peak memory 206496 kb
Host smart-ac533ee0-9a76-4392-a8f1-db6da316cd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849703492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3849703492
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1638810898
Short name T370
Test name
Test status
Simulation time 2749858528 ps
CPU time 10.71 seconds
Started Aug 12 05:36:56 PM PDT 24
Finished Aug 12 05:37:06 PM PDT 24
Peak memory 232924 kb
Host smart-23782a42-b784-49e5-8a0a-85cf7801277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638810898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1638810898
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3081744060
Short name T31
Test name
Test status
Simulation time 745256568 ps
CPU time 19.14 seconds
Started Aug 12 05:36:35 PM PDT 24
Finished Aug 12 05:36:55 PM PDT 24
Peak memory 249396 kb
Host smart-b36774b9-1aaf-41b6-bc5d-111e46fea4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081744060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3081744060
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.910064681
Short name T623
Test name
Test status
Simulation time 6000315514 ps
CPU time 28.91 seconds
Started Aug 12 05:36:30 PM PDT 24
Finished Aug 12 05:36:59 PM PDT 24
Peak memory 249460 kb
Host smart-2ae41548-487a-4507-93ce-685fdef91dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910064681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.910064681
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1107169776
Short name T871
Test name
Test status
Simulation time 35519506 ps
CPU time 2.81 seconds
Started Aug 12 05:36:55 PM PDT 24
Finished Aug 12 05:36:58 PM PDT 24
Peak memory 232852 kb
Host smart-c97d0ca2-2937-4251-94ec-13c4323d9156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107169776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1107169776
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1235447427
Short name T396
Test name
Test status
Simulation time 1758731895 ps
CPU time 11.1 seconds
Started Aug 12 05:36:42 PM PDT 24
Finished Aug 12 05:36:54 PM PDT 24
Peak memory 224632 kb
Host smart-f4065dd1-9201-4149-b96b-b1f653ffe01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235447427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1235447427
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2085361907
Short name T680
Test name
Test status
Simulation time 298792272 ps
CPU time 3.5 seconds
Started Aug 12 05:36:48 PM PDT 24
Finished Aug 12 05:36:51 PM PDT 24
Peak memory 232900 kb
Host smart-03e9af5d-4071-461f-b89b-a20656246b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085361907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2085361907
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1593426293
Short name T1031
Test name
Test status
Simulation time 38618738691 ps
CPU time 63.78 seconds
Started Aug 12 05:37:06 PM PDT 24
Finished Aug 12 05:38:10 PM PDT 24
Peak memory 232912 kb
Host smart-088b45d0-8dc8-4af5-8ad2-967b50e8b0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593426293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1593426293
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1874182640
Short name T566
Test name
Test status
Simulation time 1514721460 ps
CPU time 6.22 seconds
Started Aug 12 05:36:52 PM PDT 24
Finished Aug 12 05:36:59 PM PDT 24
Peak memory 232856 kb
Host smart-dfa426f4-83cc-40f7-8ec7-d80d4f8b439a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874182640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1874182640
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3884297687
Short name T778
Test name
Test status
Simulation time 5800751585 ps
CPU time 15.88 seconds
Started Aug 12 05:36:40 PM PDT 24
Finished Aug 12 05:36:57 PM PDT 24
Peak memory 224736 kb
Host smart-963aa2e4-1463-45bc-b676-2deb137a7c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884297687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3884297687
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.668096223
Short name T684
Test name
Test status
Simulation time 697283436 ps
CPU time 6.98 seconds
Started Aug 12 05:36:37 PM PDT 24
Finished Aug 12 05:36:45 PM PDT 24
Peak memory 220160 kb
Host smart-6a345810-3920-4522-959e-b66e0278311e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=668096223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.668096223
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1671141251
Short name T838
Test name
Test status
Simulation time 58891771865 ps
CPU time 127.88 seconds
Started Aug 12 05:36:38 PM PDT 24
Finished Aug 12 05:38:46 PM PDT 24
Peak memory 267076 kb
Host smart-73f8913c-09d6-40e6-a79e-d2807142d6c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671141251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1671141251
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.908514138
Short name T327
Test name
Test status
Simulation time 42286876 ps
CPU time 0.71 seconds
Started Aug 12 05:36:58 PM PDT 24
Finished Aug 12 05:36:59 PM PDT 24
Peak memory 205648 kb
Host smart-1cdf6e46-f8fb-4784-b2a1-13abca1a616c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908514138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.908514138
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2151519116
Short name T537
Test name
Test status
Simulation time 28658642 ps
CPU time 0.72 seconds
Started Aug 12 05:36:55 PM PDT 24
Finished Aug 12 05:36:56 PM PDT 24
Peak memory 205584 kb
Host smart-17471ec5-db56-4756-a24f-4732eea1b5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151519116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2151519116
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2781473221
Short name T372
Test name
Test status
Simulation time 70105286 ps
CPU time 0.99 seconds
Started Aug 12 05:37:03 PM PDT 24
Finished Aug 12 05:37:04 PM PDT 24
Peak memory 208068 kb
Host smart-e527e7c9-5703-4448-a958-6d0e81bcf255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781473221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2781473221
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.315975565
Short name T408
Test name
Test status
Simulation time 23723645 ps
CPU time 0.77 seconds
Started Aug 12 05:36:38 PM PDT 24
Finished Aug 12 05:36:39 PM PDT 24
Peak memory 206028 kb
Host smart-a956a28a-9e2d-4e3d-9139-2cca6887c26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315975565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.315975565
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2521087254
Short name T260
Test name
Test status
Simulation time 2274925563 ps
CPU time 9.7 seconds
Started Aug 12 05:36:34 PM PDT 24
Finished Aug 12 05:36:44 PM PDT 24
Peak memory 232896 kb
Host smart-6a3e6a92-fb86-4d5e-b7c6-3a05b3e70c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521087254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2521087254
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2049957525
Short name T855
Test name
Test status
Simulation time 17324219 ps
CPU time 0.73 seconds
Started Aug 12 05:36:42 PM PDT 24
Finished Aug 12 05:36:43 PM PDT 24
Peak memory 204640 kb
Host smart-926160fa-09d7-4ce3-862a-71aec40187f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049957525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2049957525
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2305971582
Short name T727
Test name
Test status
Simulation time 51923780 ps
CPU time 2.64 seconds
Started Aug 12 05:36:42 PM PDT 24
Finished Aug 12 05:36:45 PM PDT 24
Peak memory 232880 kb
Host smart-3f99d028-e69b-44ab-80c1-948883433cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305971582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2305971582
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.407304056
Short name T429
Test name
Test status
Simulation time 51235404 ps
CPU time 0.74 seconds
Started Aug 12 05:36:56 PM PDT 24
Finished Aug 12 05:36:57 PM PDT 24
Peak memory 205448 kb
Host smart-78071fd1-495c-4630-9d9d-cdf9cbad5f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407304056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.407304056
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1272745699
Short name T297
Test name
Test status
Simulation time 304474072764 ps
CPU time 494.66 seconds
Started Aug 12 05:36:56 PM PDT 24
Finished Aug 12 05:45:11 PM PDT 24
Peak memory 265760 kb
Host smart-fda89b7d-1f61-43e6-9f8b-396ea43a3a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272745699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1272745699
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4230086302
Short name T431
Test name
Test status
Simulation time 2574097093 ps
CPU time 13.27 seconds
Started Aug 12 05:36:57 PM PDT 24
Finished Aug 12 05:37:11 PM PDT 24
Peak memory 224876 kb
Host smart-68a83276-9c91-435e-aea6-be69106a89f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230086302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4230086302
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1770672991
Short name T40
Test name
Test status
Simulation time 8419955638 ps
CPU time 93.37 seconds
Started Aug 12 05:36:57 PM PDT 24
Finished Aug 12 05:38:31 PM PDT 24
Peak memory 235192 kb
Host smart-b8f305d0-adf8-491e-a057-154de881851c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770672991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1770672991
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2007703049
Short name T907
Test name
Test status
Simulation time 172685277 ps
CPU time 5.27 seconds
Started Aug 12 05:36:43 PM PDT 24
Finished Aug 12 05:36:48 PM PDT 24
Peak memory 224708 kb
Host smart-a42fa096-cfa1-4c2a-813b-0be17dca38be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007703049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2007703049
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.743669685
Short name T839
Test name
Test status
Simulation time 36284563646 ps
CPU time 42.69 seconds
Started Aug 12 05:36:35 PM PDT 24
Finished Aug 12 05:37:18 PM PDT 24
Peak memory 250356 kb
Host smart-f00b00a5-1d48-4c76-b580-15fd1f5ebd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743669685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.743669685
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2351645532
Short name T583
Test name
Test status
Simulation time 216712398 ps
CPU time 4.3 seconds
Started Aug 12 05:36:33 PM PDT 24
Finished Aug 12 05:36:38 PM PDT 24
Peak memory 224644 kb
Host smart-9723a152-d7cf-456e-959b-cc980f1c9e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351645532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2351645532
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3928516992
Short name T634
Test name
Test status
Simulation time 220255359 ps
CPU time 7.63 seconds
Started Aug 12 05:36:30 PM PDT 24
Finished Aug 12 05:36:37 PM PDT 24
Peak memory 238836 kb
Host smart-b00e3a5d-31ab-4bbe-b8f5-752e1d518830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928516992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3928516992
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2271358660
Short name T391
Test name
Test status
Simulation time 2207659814 ps
CPU time 5.96 seconds
Started Aug 12 05:36:42 PM PDT 24
Finished Aug 12 05:36:49 PM PDT 24
Peak memory 224748 kb
Host smart-adbff311-c422-4731-a91d-9e711f20b53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271358660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2271358660
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3355649414
Short name T289
Test name
Test status
Simulation time 27632404258 ps
CPU time 10.26 seconds
Started Aug 12 05:36:53 PM PDT 24
Finished Aug 12 05:37:04 PM PDT 24
Peak memory 232864 kb
Host smart-a5e2f315-b117-4a33-9d47-160e7026dcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355649414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3355649414
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.66612516
Short name T451
Test name
Test status
Simulation time 122210219 ps
CPU time 4.25 seconds
Started Aug 12 05:37:07 PM PDT 24
Finished Aug 12 05:37:12 PM PDT 24
Peak memory 221640 kb
Host smart-d6acafd6-0435-4301-81e2-c3aaf33d57f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=66612516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direc
t.66612516
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.374165988
Short name T519
Test name
Test status
Simulation time 51847984 ps
CPU time 1.01 seconds
Started Aug 12 05:36:37 PM PDT 24
Finished Aug 12 05:36:38 PM PDT 24
Peak memory 207572 kb
Host smart-bac6c246-4756-45d2-89d1-7dbd7003115e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374165988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.374165988
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3237573698
Short name T405
Test name
Test status
Simulation time 1746532713 ps
CPU time 21.14 seconds
Started Aug 12 05:36:45 PM PDT 24
Finished Aug 12 05:37:06 PM PDT 24
Peak memory 216508 kb
Host smart-62cb4c21-3975-43e9-9f91-7004623f610c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237573698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3237573698
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2257792430
Short name T852
Test name
Test status
Simulation time 48198027076 ps
CPU time 10.47 seconds
Started Aug 12 05:37:06 PM PDT 24
Finished Aug 12 05:37:16 PM PDT 24
Peak memory 216424 kb
Host smart-e676a928-71d2-4adb-83d3-42ced810b084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257792430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2257792430
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2023587987
Short name T415
Test name
Test status
Simulation time 805154985 ps
CPU time 3.02 seconds
Started Aug 12 05:36:50 PM PDT 24
Finished Aug 12 05:36:54 PM PDT 24
Peak memory 216440 kb
Host smart-6aacfc0a-033f-416e-b98b-a14fdf43f5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023587987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2023587987
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2115120744
Short name T556
Test name
Test status
Simulation time 143797167 ps
CPU time 0.77 seconds
Started Aug 12 05:36:43 PM PDT 24
Finished Aug 12 05:36:44 PM PDT 24
Peak memory 206056 kb
Host smart-bcd3f69a-d93e-4c2f-9bbb-d0881deb4525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115120744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2115120744
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3808687697
Short name T922
Test name
Test status
Simulation time 16629109813 ps
CPU time 14.21 seconds
Started Aug 12 05:36:40 PM PDT 24
Finished Aug 12 05:36:54 PM PDT 24
Peak memory 232968 kb
Host smart-659a2168-c2ad-4b92-a97b-9d0979da4852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808687697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3808687697
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2973610612
Short name T437
Test name
Test status
Simulation time 15478202 ps
CPU time 0.76 seconds
Started Aug 12 05:36:41 PM PDT 24
Finished Aug 12 05:36:42 PM PDT 24
Peak memory 204708 kb
Host smart-1ebd66f6-1b51-4dce-848a-ebf298d10b16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973610612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2973610612
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3753892640
Short name T843
Test name
Test status
Simulation time 103876529 ps
CPU time 2.42 seconds
Started Aug 12 05:36:39 PM PDT 24
Finished Aug 12 05:36:42 PM PDT 24
Peak memory 224632 kb
Host smart-1b130d05-85d8-4afd-870c-bd708de471ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753892640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3753892640
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3443893035
Short name T732
Test name
Test status
Simulation time 16391402 ps
CPU time 0.74 seconds
Started Aug 12 05:36:31 PM PDT 24
Finished Aug 12 05:36:32 PM PDT 24
Peak memory 205428 kb
Host smart-8afcddc0-35bf-4f29-a894-4dd7cc8ae621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443893035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3443893035
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1173950025
Short name T928
Test name
Test status
Simulation time 19772268535 ps
CPU time 75.94 seconds
Started Aug 12 05:36:57 PM PDT 24
Finished Aug 12 05:38:13 PM PDT 24
Peak memory 257636 kb
Host smart-7e9662fd-fba3-4574-a6cf-717978b43323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173950025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1173950025
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2866236522
Short name T148
Test name
Test status
Simulation time 1942155127 ps
CPU time 29.75 seconds
Started Aug 12 05:36:36 PM PDT 24
Finished Aug 12 05:37:06 PM PDT 24
Peak memory 249316 kb
Host smart-fdcb88dc-a4ac-4df8-9827-4e984af5fb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866236522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2866236522
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1036766128
Short name T878
Test name
Test status
Simulation time 1350099695 ps
CPU time 15.68 seconds
Started Aug 12 05:37:00 PM PDT 24
Finished Aug 12 05:37:15 PM PDT 24
Peak memory 230404 kb
Host smart-c39ae79b-b8a3-48a9-b9ce-29d70abb6fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036766128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1036766128
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.786126374
Short name T683
Test name
Test status
Simulation time 11228951724 ps
CPU time 24.7 seconds
Started Aug 12 05:36:41 PM PDT 24
Finished Aug 12 05:37:06 PM PDT 24
Peak memory 224712 kb
Host smart-15a442f4-bab4-4eed-a52b-00c1c04e474d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786126374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.786126374
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.430139719
Short name T280
Test name
Test status
Simulation time 3059108003 ps
CPU time 4.03 seconds
Started Aug 12 05:36:57 PM PDT 24
Finished Aug 12 05:37:01 PM PDT 24
Peak memory 224736 kb
Host smart-c383e3f9-f892-40ed-9049-20a80309539e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430139719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.430139719
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1636713267
Short name T251
Test name
Test status
Simulation time 1890945828 ps
CPU time 8.3 seconds
Started Aug 12 05:36:39 PM PDT 24
Finished Aug 12 05:36:47 PM PDT 24
Peak memory 232904 kb
Host smart-dbef467b-fb42-43a5-bdc6-68ee11997594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636713267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1636713267
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1514123260
Short name T713
Test name
Test status
Simulation time 6192874008 ps
CPU time 15.8 seconds
Started Aug 12 05:36:53 PM PDT 24
Finished Aug 12 05:37:09 PM PDT 24
Peak memory 222704 kb
Host smart-bf912785-3861-4f96-b9ed-ded55bedac6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1514123260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1514123260
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.568258635
Short name T319
Test name
Test status
Simulation time 240506144045 ps
CPU time 194.46 seconds
Started Aug 12 05:36:32 PM PDT 24
Finished Aug 12 05:39:47 PM PDT 24
Peak memory 264260 kb
Host smart-2050e5c9-e3f4-43c2-9b5e-ad133bdc40b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568258635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.568258635
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1295431545
Short name T321
Test name
Test status
Simulation time 1858629164 ps
CPU time 18.83 seconds
Started Aug 12 05:36:36 PM PDT 24
Finished Aug 12 05:36:55 PM PDT 24
Peak memory 216616 kb
Host smart-13378aee-0019-4f06-8208-5ed6527411de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295431545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1295431545
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4076512924
Short name T323
Test name
Test status
Simulation time 5798825943 ps
CPU time 6.13 seconds
Started Aug 12 05:36:49 PM PDT 24
Finished Aug 12 05:36:55 PM PDT 24
Peak memory 216452 kb
Host smart-0cb752cf-c91f-4d8f-9c5e-141ff9ef3292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076512924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4076512924
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2989425065
Short name T762
Test name
Test status
Simulation time 140872671 ps
CPU time 1.24 seconds
Started Aug 12 05:36:54 PM PDT 24
Finished Aug 12 05:37:00 PM PDT 24
Peak memory 208188 kb
Host smart-b0588c7a-8451-4607-bdd1-64fda095b7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989425065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2989425065
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.549492704
Short name T633
Test name
Test status
Simulation time 95665644 ps
CPU time 0.93 seconds
Started Aug 12 05:36:37 PM PDT 24
Finished Aug 12 05:36:38 PM PDT 24
Peak memory 206012 kb
Host smart-5e300d3b-1a99-4753-8696-c0fc15c58958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549492704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.549492704
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1798416187
Short name T682
Test name
Test status
Simulation time 2629143801 ps
CPU time 4.65 seconds
Started Aug 12 05:36:34 PM PDT 24
Finished Aug 12 05:36:39 PM PDT 24
Peak memory 224724 kb
Host smart-22d43957-65af-4f46-8943-92f8bfd83aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798416187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1798416187
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3732977901
Short name T351
Test name
Test status
Simulation time 19427461 ps
CPU time 0.68 seconds
Started Aug 12 05:35:35 PM PDT 24
Finished Aug 12 05:35:36 PM PDT 24
Peak memory 204728 kb
Host smart-18b39347-4060-4eaf-b4ee-d030712480df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732977901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
732977901
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.321663467
Short name T685
Test name
Test status
Simulation time 2205128217 ps
CPU time 19.88 seconds
Started Aug 12 05:35:32 PM PDT 24
Finished Aug 12 05:35:52 PM PDT 24
Peak memory 232916 kb
Host smart-9377104a-b65d-4f76-bc7f-c2f4bc8efa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321663467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.321663467
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3978576328
Short name T481
Test name
Test status
Simulation time 26434785 ps
CPU time 0.81 seconds
Started Aug 12 05:35:33 PM PDT 24
Finished Aug 12 05:35:34 PM PDT 24
Peak memory 206520 kb
Host smart-e04614ab-3894-4fcd-b22d-242b2d14e9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978576328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3978576328
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.4021786645
Short name T304
Test name
Test status
Simulation time 600658437905 ps
CPU time 403.48 seconds
Started Aug 12 05:35:38 PM PDT 24
Finished Aug 12 05:42:22 PM PDT 24
Peak memory 266956 kb
Host smart-bd089a06-8728-458e-893b-4bd7c9491679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021786645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.4021786645
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1517674039
Short name T610
Test name
Test status
Simulation time 59615764826 ps
CPU time 581.8 seconds
Started Aug 12 05:36:00 PM PDT 24
Finished Aug 12 05:45:42 PM PDT 24
Peak memory 265200 kb
Host smart-25890af8-5840-4b1f-bb15-30ee24f9d75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517674039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1517674039
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1388687415
Short name T570
Test name
Test status
Simulation time 441506750 ps
CPU time 9.78 seconds
Started Aug 12 05:35:46 PM PDT 24
Finished Aug 12 05:35:56 PM PDT 24
Peak memory 230004 kb
Host smart-4a2db6d4-e079-490a-a91e-8eb318e649cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388687415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1388687415
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3862510410
Short name T264
Test name
Test status
Simulation time 1156717811 ps
CPU time 7.39 seconds
Started Aug 12 05:35:48 PM PDT 24
Finished Aug 12 05:35:56 PM PDT 24
Peak memory 232904 kb
Host smart-5fe0e30a-20b1-4dc4-808b-4d6f4b2c573a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862510410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3862510410
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3160215977
Short name T574
Test name
Test status
Simulation time 31092304 ps
CPU time 2.39 seconds
Started Aug 12 05:35:38 PM PDT 24
Finished Aug 12 05:35:40 PM PDT 24
Peak memory 232512 kb
Host smart-6f5e4470-df4d-4a0b-8d6f-9892998fe3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160215977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3160215977
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3204968140
Short name T768
Test name
Test status
Simulation time 107864745 ps
CPU time 1.1 seconds
Started Aug 12 05:36:10 PM PDT 24
Finished Aug 12 05:36:11 PM PDT 24
Peak memory 216640 kb
Host smart-6923b444-5043-41e7-9593-aee6dd29ad96
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204968140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3204968140
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3651751277
Short name T862
Test name
Test status
Simulation time 10893682549 ps
CPU time 16.81 seconds
Started Aug 12 05:35:43 PM PDT 24
Finished Aug 12 05:36:00 PM PDT 24
Peak memory 224772 kb
Host smart-3e31c118-c33d-4b0d-8026-13035f5e21e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651751277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3651751277
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.344910469
Short name T10
Test name
Test status
Simulation time 399940021 ps
CPU time 3.68 seconds
Started Aug 12 05:35:41 PM PDT 24
Finished Aug 12 05:35:44 PM PDT 24
Peak memory 232916 kb
Host smart-80c04cf6-3058-4d2b-8e49-6126713f3d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344910469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.344910469
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.959356206
Short name T758
Test name
Test status
Simulation time 343656672 ps
CPU time 3.99 seconds
Started Aug 12 05:35:47 PM PDT 24
Finished Aug 12 05:35:51 PM PDT 24
Peak memory 222624 kb
Host smart-a263a327-a5e7-4649-8489-8672506f2134
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=959356206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.959356206
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3370624578
Short name T74
Test name
Test status
Simulation time 215191068 ps
CPU time 1.08 seconds
Started Aug 12 05:35:38 PM PDT 24
Finished Aug 12 05:35:39 PM PDT 24
Peak memory 235788 kb
Host smart-a74a582f-0aa3-4210-89f1-30469ddae2ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370624578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3370624578
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1479553234
Short name T980
Test name
Test status
Simulation time 14382646731 ps
CPU time 56.96 seconds
Started Aug 12 05:35:27 PM PDT 24
Finished Aug 12 05:36:24 PM PDT 24
Peak memory 239720 kb
Host smart-7d6a90a0-d697-4239-b5f2-0cbfe60dc5b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479553234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1479553234
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2647067144
Short name T809
Test name
Test status
Simulation time 25767060053 ps
CPU time 25.88 seconds
Started Aug 12 05:35:42 PM PDT 24
Finished Aug 12 05:36:08 PM PDT 24
Peak memory 216708 kb
Host smart-e3b44c83-0292-435d-8ca5-d143ba7bb431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647067144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2647067144
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2130555341
Short name T359
Test name
Test status
Simulation time 1110563593 ps
CPU time 2.66 seconds
Started Aug 12 05:35:46 PM PDT 24
Finished Aug 12 05:35:49 PM PDT 24
Peak memory 216292 kb
Host smart-2c9c1c5e-5bc0-4430-bc96-bae02297883d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130555341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2130555341
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.847026550
Short name T760
Test name
Test status
Simulation time 523250680 ps
CPU time 2.01 seconds
Started Aug 12 05:35:49 PM PDT 24
Finished Aug 12 05:35:51 PM PDT 24
Peak memory 216384 kb
Host smart-757c682a-ef38-4029-9ae7-7c7fcb78c0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847026550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.847026550
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.611942911
Short name T329
Test name
Test status
Simulation time 146404223 ps
CPU time 0.94 seconds
Started Aug 12 05:35:36 PM PDT 24
Finished Aug 12 05:35:37 PM PDT 24
Peak memory 206012 kb
Host smart-bddbf83e-d66a-4b83-862d-f5dc0775b687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611942911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.611942911
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2721867875
Short name T530
Test name
Test status
Simulation time 142983281 ps
CPU time 3.33 seconds
Started Aug 12 05:35:36 PM PDT 24
Finished Aug 12 05:35:40 PM PDT 24
Peak memory 224668 kb
Host smart-82a19197-cdd0-4192-b366-e3911e8140cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721867875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2721867875
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2747952767
Short name T72
Test name
Test status
Simulation time 42214298 ps
CPU time 0.73 seconds
Started Aug 12 05:37:06 PM PDT 24
Finished Aug 12 05:37:07 PM PDT 24
Peak memory 205324 kb
Host smart-f64b4eaf-7fd5-49c2-879f-0e606da87bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747952767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2747952767
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2419033233
Short name T262
Test name
Test status
Simulation time 80309320 ps
CPU time 2.35 seconds
Started Aug 12 05:37:03 PM PDT 24
Finished Aug 12 05:37:05 PM PDT 24
Peak memory 232904 kb
Host smart-274aeedc-3294-4205-a6fb-f480a6ee14f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419033233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2419033233
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3764046118
Short name T940
Test name
Test status
Simulation time 16608346 ps
CPU time 0.74 seconds
Started Aug 12 05:36:36 PM PDT 24
Finished Aug 12 05:36:37 PM PDT 24
Peak memory 205820 kb
Host smart-38392323-c75a-47e6-aa65-1b94eae58dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764046118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3764046118
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.4243454878
Short name T53
Test name
Test status
Simulation time 44672959001 ps
CPU time 313.88 seconds
Started Aug 12 05:36:50 PM PDT 24
Finished Aug 12 05:42:04 PM PDT 24
Peak memory 264728 kb
Host smart-5ead1d01-3ad4-40cb-b862-49e59f1e02db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243454878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.4243454878
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.169716370
Short name T501
Test name
Test status
Simulation time 45439164955 ps
CPU time 158.19 seconds
Started Aug 12 05:36:57 PM PDT 24
Finished Aug 12 05:39:36 PM PDT 24
Peak memory 273300 kb
Host smart-ec680f28-111b-4067-b3e7-3d027b4d2709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169716370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.169716370
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2253665411
Short name T488
Test name
Test status
Simulation time 19021862710 ps
CPU time 61.71 seconds
Started Aug 12 05:36:56 PM PDT 24
Finished Aug 12 05:37:58 PM PDT 24
Peak memory 249348 kb
Host smart-bb972a05-577a-4528-9933-84c1a10a62ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253665411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2253665411
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4138032804
Short name T180
Test name
Test status
Simulation time 225399959 ps
CPU time 2.93 seconds
Started Aug 12 05:36:58 PM PDT 24
Finished Aug 12 05:37:01 PM PDT 24
Peak memory 224676 kb
Host smart-625a534a-5f07-4e66-8e6b-0d74407827bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138032804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4138032804
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1209251274
Short name T828
Test name
Test status
Simulation time 11095849124 ps
CPU time 47.21 seconds
Started Aug 12 05:36:44 PM PDT 24
Finished Aug 12 05:37:31 PM PDT 24
Peak memory 249484 kb
Host smart-fee6defc-351f-434a-9da5-aceddcef6bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209251274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1209251274
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3456650705
Short name T1006
Test name
Test status
Simulation time 708554004 ps
CPU time 9.68 seconds
Started Aug 12 05:36:54 PM PDT 24
Finished Aug 12 05:37:04 PM PDT 24
Peak memory 224728 kb
Host smart-0ce45857-4142-4e4a-9ad8-8ed5ba00e8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456650705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3456650705
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3081893718
Short name T874
Test name
Test status
Simulation time 4383983468 ps
CPU time 15.32 seconds
Started Aug 12 05:37:02 PM PDT 24
Finished Aug 12 05:37:18 PM PDT 24
Peak memory 232968 kb
Host smart-6e3c8c43-4949-40d4-b41e-945abafc70d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081893718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3081893718
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1188716543
Short name T662
Test name
Test status
Simulation time 250100182 ps
CPU time 4.89 seconds
Started Aug 12 05:36:53 PM PDT 24
Finished Aug 12 05:36:58 PM PDT 24
Peak memory 235684 kb
Host smart-cf6c9da2-33ca-498e-b32f-4b188e217709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188716543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1188716543
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3213636294
Short name T263
Test name
Test status
Simulation time 501836674 ps
CPU time 3.22 seconds
Started Aug 12 05:37:00 PM PDT 24
Finished Aug 12 05:37:04 PM PDT 24
Peak memory 223516 kb
Host smart-06869ec6-b949-4e37-bf9d-2710b6d16d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213636294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3213636294
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1194368108
Short name T1027
Test name
Test status
Simulation time 276189404 ps
CPU time 4.56 seconds
Started Aug 12 05:36:45 PM PDT 24
Finished Aug 12 05:36:50 PM PDT 24
Peak memory 222700 kb
Host smart-aaba79e4-5fff-49ac-9e74-e12e32f96d34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1194368108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1194368108
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.78973548
Short name T941
Test name
Test status
Simulation time 60340885674 ps
CPU time 278.43 seconds
Started Aug 12 05:36:39 PM PDT 24
Finished Aug 12 05:41:18 PM PDT 24
Peak memory 271064 kb
Host smart-8f227246-195c-4ccc-a3a0-68fb99641c90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78973548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress
_all.78973548
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2130895452
Short name T407
Test name
Test status
Simulation time 2563721809 ps
CPU time 7.01 seconds
Started Aug 12 05:36:46 PM PDT 24
Finished Aug 12 05:36:53 PM PDT 24
Peak memory 220324 kb
Host smart-cb5e587e-896a-4e2b-8a40-c94df01af804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130895452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2130895452
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.4141530338
Short name T743
Test name
Test status
Simulation time 18440377 ps
CPU time 0.7 seconds
Started Aug 12 05:36:58 PM PDT 24
Finished Aug 12 05:36:59 PM PDT 24
Peak memory 205572 kb
Host smart-ee1604c8-a5d3-4f8f-9653-91197317b8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141530338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.4141530338
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3224964802
Short name T648
Test name
Test status
Simulation time 69009763 ps
CPU time 1.73 seconds
Started Aug 12 05:36:37 PM PDT 24
Finished Aug 12 05:36:39 PM PDT 24
Peak memory 216344 kb
Host smart-f4f1e6b6-7205-4c63-ab5c-cd3cfd4910c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224964802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3224964802
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3334061309
Short name T65
Test name
Test status
Simulation time 383458438 ps
CPU time 0.98 seconds
Started Aug 12 05:36:38 PM PDT 24
Finished Aug 12 05:36:39 PM PDT 24
Peak memory 206380 kb
Host smart-c8c7d2ac-6b44-44d3-a4cd-5e8a23b1ebf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334061309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3334061309
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.217876982
Short name T624
Test name
Test status
Simulation time 714422052 ps
CPU time 7.69 seconds
Started Aug 12 05:36:47 PM PDT 24
Finished Aug 12 05:36:54 PM PDT 24
Peak memory 232952 kb
Host smart-60044487-a820-4431-85ba-c1a516e8b74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217876982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.217876982
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3083899599
Short name T595
Test name
Test status
Simulation time 38502349 ps
CPU time 0.69 seconds
Started Aug 12 05:36:57 PM PDT 24
Finished Aug 12 05:36:58 PM PDT 24
Peak memory 204648 kb
Host smart-11c78812-967e-4227-b9c2-6bf97f8a9b16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083899599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3083899599
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2376760035
Short name T827
Test name
Test status
Simulation time 579784510 ps
CPU time 3.97 seconds
Started Aug 12 05:36:55 PM PDT 24
Finished Aug 12 05:37:05 PM PDT 24
Peak memory 224684 kb
Host smart-cf42b42b-dc63-4f5c-92cd-2ddf8292a766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376760035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2376760035
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2207582445
Short name T734
Test name
Test status
Simulation time 35608116 ps
CPU time 0.76 seconds
Started Aug 12 05:36:49 PM PDT 24
Finished Aug 12 05:36:50 PM PDT 24
Peak memory 205476 kb
Host smart-3157613c-3915-4853-9cce-c0e670e31023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207582445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2207582445
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.929873865
Short name T841
Test name
Test status
Simulation time 4526679164 ps
CPU time 20.93 seconds
Started Aug 12 05:36:41 PM PDT 24
Finished Aug 12 05:37:02 PM PDT 24
Peak memory 248744 kb
Host smart-204b265b-cf89-4aad-8124-9643b4e4f718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929873865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.929873865
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1657746551
Short name T777
Test name
Test status
Simulation time 3311094075 ps
CPU time 55.73 seconds
Started Aug 12 05:36:54 PM PDT 24
Finished Aug 12 05:37:50 PM PDT 24
Peak memory 252448 kb
Host smart-b78c18cf-afd0-494f-b8a9-41e1c1cfa614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657746551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1657746551
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1560030793
Short name T741
Test name
Test status
Simulation time 1253635311 ps
CPU time 5.17 seconds
Started Aug 12 05:36:51 PM PDT 24
Finished Aug 12 05:36:56 PM PDT 24
Peak memory 232928 kb
Host smart-b5c6c4b5-5ff0-4fdb-b527-a525586f7acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560030793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1560030793
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3600430008
Short name T239
Test name
Test status
Simulation time 48816079981 ps
CPU time 112.78 seconds
Started Aug 12 05:36:58 PM PDT 24
Finished Aug 12 05:38:51 PM PDT 24
Peak memory 249384 kb
Host smart-cf2a6419-f775-45f8-9735-becdb0b8ddfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600430008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3600430008
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2960948954
Short name T179
Test name
Test status
Simulation time 1541952924 ps
CPU time 15.3 seconds
Started Aug 12 05:36:45 PM PDT 24
Finished Aug 12 05:37:00 PM PDT 24
Peak memory 224744 kb
Host smart-710c4741-a827-47c6-9cf0-da9a23a28bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960948954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2960948954
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2019603006
Short name T573
Test name
Test status
Simulation time 3356829934 ps
CPU time 36.27 seconds
Started Aug 12 05:36:43 PM PDT 24
Finished Aug 12 05:37:19 PM PDT 24
Peak memory 232932 kb
Host smart-b0657b46-50f6-4bad-a22d-50acf8f87e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019603006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2019603006
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.459850285
Short name T392
Test name
Test status
Simulation time 318019460 ps
CPU time 5.64 seconds
Started Aug 12 05:36:51 PM PDT 24
Finished Aug 12 05:36:57 PM PDT 24
Peak memory 232868 kb
Host smart-590f3fd0-af0a-4766-9d41-de08a862b915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459850285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.459850285
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3677331244
Short name T601
Test name
Test status
Simulation time 30029429665 ps
CPU time 24.23 seconds
Started Aug 12 05:36:42 PM PDT 24
Finished Aug 12 05:37:07 PM PDT 24
Peak memory 240204 kb
Host smart-2bb88060-e649-4e7d-b5f0-5cd799063d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677331244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3677331244
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1009646400
Short name T876
Test name
Test status
Simulation time 100422431 ps
CPU time 4.34 seconds
Started Aug 12 05:36:52 PM PDT 24
Finished Aug 12 05:36:56 PM PDT 24
Peak memory 223276 kb
Host smart-9332facc-dd4e-4c7d-9350-117d8636c3b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1009646400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1009646400
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1105197254
Short name T301
Test name
Test status
Simulation time 85072778169 ps
CPU time 877.89 seconds
Started Aug 12 05:36:40 PM PDT 24
Finished Aug 12 05:51:19 PM PDT 24
Peak memory 283076 kb
Host smart-f6076dce-2d55-4386-a3db-ea14b5b6f236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105197254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1105197254
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2963917668
Short name T790
Test name
Test status
Simulation time 8204032257 ps
CPU time 37.04 seconds
Started Aug 12 05:36:41 PM PDT 24
Finished Aug 12 05:37:19 PM PDT 24
Peak memory 216440 kb
Host smart-3df83cdc-d4be-46fd-b5aa-66ca5868dd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963917668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2963917668
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1724963570
Short name T647
Test name
Test status
Simulation time 8189760088 ps
CPU time 8.15 seconds
Started Aug 12 05:36:40 PM PDT 24
Finished Aug 12 05:36:49 PM PDT 24
Peak memory 216436 kb
Host smart-00213b65-4305-4811-b058-37f6d95498d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724963570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1724963570
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1017480708
Short name T661
Test name
Test status
Simulation time 168373657 ps
CPU time 1.99 seconds
Started Aug 12 05:36:56 PM PDT 24
Finished Aug 12 05:36:58 PM PDT 24
Peak memory 216400 kb
Host smart-631b170c-2c9f-4688-b10f-c924c6f0ec86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017480708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1017480708
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.244477918
Short name T534
Test name
Test status
Simulation time 269559303 ps
CPU time 0.88 seconds
Started Aug 12 05:36:40 PM PDT 24
Finished Aug 12 05:36:42 PM PDT 24
Peak memory 206056 kb
Host smart-6dddcb88-3958-4847-930c-89200811b3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244477918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.244477918
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1787723275
Short name T746
Test name
Test status
Simulation time 936429370 ps
CPU time 4.3 seconds
Started Aug 12 05:37:07 PM PDT 24
Finished Aug 12 05:37:11 PM PDT 24
Peak memory 232864 kb
Host smart-bcf631bd-0ba0-4cbc-8aee-9f60440c9132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787723275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1787723275
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3127583877
Short name T493
Test name
Test status
Simulation time 185924061 ps
CPU time 0.7 seconds
Started Aug 12 05:36:39 PM PDT 24
Finished Aug 12 05:36:40 PM PDT 24
Peak memory 204756 kb
Host smart-9a94de6b-b5da-4308-9705-9ed215d20204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127583877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3127583877
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.394624667
Short name T458
Test name
Test status
Simulation time 872198443 ps
CPU time 4.33 seconds
Started Aug 12 05:36:48 PM PDT 24
Finished Aug 12 05:36:53 PM PDT 24
Peak memory 232884 kb
Host smart-2515fe4d-4775-4e70-90b1-e97ed1c9635e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394624667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.394624667
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3391553978
Short name T636
Test name
Test status
Simulation time 15344326 ps
CPU time 0.83 seconds
Started Aug 12 05:36:42 PM PDT 24
Finished Aug 12 05:36:43 PM PDT 24
Peak memory 206684 kb
Host smart-5be54b4b-a708-4168-903d-678564cdafa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391553978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3391553978
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1562967683
Short name T976
Test name
Test status
Simulation time 144130858715 ps
CPU time 132.96 seconds
Started Aug 12 05:36:41 PM PDT 24
Finished Aug 12 05:38:54 PM PDT 24
Peak memory 249312 kb
Host smart-26c7e96b-bedd-46ad-8b38-ca3a7f532635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562967683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1562967683
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2840546657
Short name T235
Test name
Test status
Simulation time 30280863668 ps
CPU time 71.38 seconds
Started Aug 12 05:37:03 PM PDT 24
Finished Aug 12 05:38:15 PM PDT 24
Peak memory 249328 kb
Host smart-ce295e03-ba41-41ff-850d-d627a3d465b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840546657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2840546657
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1207468106
Short name T302
Test name
Test status
Simulation time 42979353886 ps
CPU time 503.94 seconds
Started Aug 12 05:36:57 PM PDT 24
Finished Aug 12 05:45:21 PM PDT 24
Peak memory 268936 kb
Host smart-75654a6e-dd21-49a2-8e98-e9424715df0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207468106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1207468106
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2383314633
Short name T462
Test name
Test status
Simulation time 548203735 ps
CPU time 5.43 seconds
Started Aug 12 05:36:44 PM PDT 24
Finished Aug 12 05:36:50 PM PDT 24
Peak memory 224676 kb
Host smart-4ff26fa0-d64a-4517-ba3c-ee204239490f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383314633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2383314633
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.4021271215
Short name T977
Test name
Test status
Simulation time 12185936227 ps
CPU time 79.15 seconds
Started Aug 12 05:36:46 PM PDT 24
Finished Aug 12 05:38:06 PM PDT 24
Peak memory 251232 kb
Host smart-0bbec04a-f756-458d-b3fb-ea74f81fd8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021271215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.4021271215
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1922715653
Short name T426
Test name
Test status
Simulation time 2907438896 ps
CPU time 6.86 seconds
Started Aug 12 05:36:50 PM PDT 24
Finished Aug 12 05:36:57 PM PDT 24
Peak memory 224712 kb
Host smart-b69c455b-8c30-4330-9d07-a08b918674be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922715653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1922715653
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3676080119
Short name T498
Test name
Test status
Simulation time 268485162 ps
CPU time 5.58 seconds
Started Aug 12 05:36:52 PM PDT 24
Finished Aug 12 05:36:58 PM PDT 24
Peak memory 232868 kb
Host smart-3e7d400d-d917-46ff-9468-43ed7107792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676080119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3676080119
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.587558324
Short name T49
Test name
Test status
Simulation time 932080609 ps
CPU time 7.99 seconds
Started Aug 12 05:36:54 PM PDT 24
Finished Aug 12 05:37:02 PM PDT 24
Peak memory 224688 kb
Host smart-d5175cad-8223-458c-9e44-24c54a82385e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587558324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.587558324
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3614054044
Short name T869
Test name
Test status
Simulation time 1426804851 ps
CPU time 2.66 seconds
Started Aug 12 05:36:50 PM PDT 24
Finished Aug 12 05:36:53 PM PDT 24
Peak memory 224652 kb
Host smart-8c1f6273-f7e2-4bda-883d-89edb9ac31ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614054044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3614054044
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2543186216
Short name T802
Test name
Test status
Simulation time 472325838 ps
CPU time 8.39 seconds
Started Aug 12 05:36:45 PM PDT 24
Finished Aug 12 05:36:54 PM PDT 24
Peak memory 220304 kb
Host smart-26537d18-a38f-433b-b075-7cd7868685cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2543186216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2543186216
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1681730796
Short name T504
Test name
Test status
Simulation time 80470324 ps
CPU time 0.74 seconds
Started Aug 12 05:37:02 PM PDT 24
Finished Aug 12 05:37:03 PM PDT 24
Peak memory 205644 kb
Host smart-82a35f63-6092-4f5c-83d9-a4ae4262b779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681730796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1681730796
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.126806429
Short name T590
Test name
Test status
Simulation time 1146179662 ps
CPU time 8.11 seconds
Started Aug 12 05:36:45 PM PDT 24
Finished Aug 12 05:36:54 PM PDT 24
Peak memory 216372 kb
Host smart-93d7337f-d4ba-4d1b-b8b4-d72acdde502d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126806429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.126806429
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3447795986
Short name T555
Test name
Test status
Simulation time 37839062 ps
CPU time 0.85 seconds
Started Aug 12 05:36:42 PM PDT 24
Finished Aug 12 05:36:43 PM PDT 24
Peak memory 207144 kb
Host smart-563bfeeb-1f83-46c6-926d-5a61fd0609bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447795986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3447795986
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3008924607
Short name T737
Test name
Test status
Simulation time 32303234 ps
CPU time 0.73 seconds
Started Aug 12 05:36:52 PM PDT 24
Finished Aug 12 05:36:53 PM PDT 24
Peak memory 206000 kb
Host smart-89fe4bca-aaae-4210-acc6-7ba9cb56bf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008924607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3008924607
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3108953420
Short name T582
Test name
Test status
Simulation time 2195634946 ps
CPU time 12.71 seconds
Started Aug 12 05:36:41 PM PDT 24
Finished Aug 12 05:36:54 PM PDT 24
Peak memory 233000 kb
Host smart-1057829c-7d32-4289-b016-9ac3bfb24e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108953420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3108953420
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3289031920
Short name T512
Test name
Test status
Simulation time 38690538 ps
CPU time 0.7 seconds
Started Aug 12 05:37:12 PM PDT 24
Finished Aug 12 05:37:13 PM PDT 24
Peak memory 204760 kb
Host smart-a1076c22-4cec-452b-a6ec-6a5f82148f68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289031920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3289031920
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1078958167
Short name T363
Test name
Test status
Simulation time 277004923 ps
CPU time 5.26 seconds
Started Aug 12 05:37:21 PM PDT 24
Finished Aug 12 05:37:26 PM PDT 24
Peak memory 224692 kb
Host smart-2ebe5d2d-a80d-4de3-bcb5-91616b9f7989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078958167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1078958167
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2113304854
Short name T663
Test name
Test status
Simulation time 70529290 ps
CPU time 0.78 seconds
Started Aug 12 05:36:52 PM PDT 24
Finished Aug 12 05:36:53 PM PDT 24
Peak memory 206516 kb
Host smart-f317cd3c-70df-40fb-be30-e65b8b62b476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113304854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2113304854
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1867781302
Short name T220
Test name
Test status
Simulation time 1263068604 ps
CPU time 11.27 seconds
Started Aug 12 05:36:58 PM PDT 24
Finished Aug 12 05:37:09 PM PDT 24
Peak memory 224684 kb
Host smart-c6f35760-c529-430a-9b10-c5192f59f8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867781302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1867781302
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.748698981
Short name T465
Test name
Test status
Simulation time 25192628029 ps
CPU time 68.97 seconds
Started Aug 12 05:36:42 PM PDT 24
Finished Aug 12 05:37:51 PM PDT 24
Peak memory 249748 kb
Host smart-cb9a174f-b349-493b-b5fd-084a69b3b6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748698981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.748698981
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3224749488
Short name T508
Test name
Test status
Simulation time 2009034894 ps
CPU time 41.67 seconds
Started Aug 12 05:36:58 PM PDT 24
Finished Aug 12 05:37:40 PM PDT 24
Peak memory 249708 kb
Host smart-399dd9b7-bd5b-4b08-af44-9f598ead263d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224749488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3224749488
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3324627782
Short name T579
Test name
Test status
Simulation time 494549565 ps
CPU time 6.06 seconds
Started Aug 12 05:36:58 PM PDT 24
Finished Aug 12 05:37:04 PM PDT 24
Peak memory 232928 kb
Host smart-0d019b82-1ce8-4cf9-88ec-09a9a3c0b2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324627782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3324627782
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3993928643
Short name T271
Test name
Test status
Simulation time 91808677748 ps
CPU time 64.36 seconds
Started Aug 12 05:36:47 PM PDT 24
Finished Aug 12 05:37:52 PM PDT 24
Peak memory 249380 kb
Host smart-d8879e71-7496-4eff-b9eb-893d57061a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993928643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3993928643
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2096105971
Short name T538
Test name
Test status
Simulation time 24784434626 ps
CPU time 14.53 seconds
Started Aug 12 05:36:42 PM PDT 24
Finished Aug 12 05:36:57 PM PDT 24
Peak memory 224752 kb
Host smart-ba64502e-9e05-468c-9116-379eaba6f877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096105971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2096105971
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1345608293
Short name T483
Test name
Test status
Simulation time 1798949737 ps
CPU time 12.64 seconds
Started Aug 12 05:36:58 PM PDT 24
Finished Aug 12 05:37:11 PM PDT 24
Peak memory 232928 kb
Host smart-94e18563-ae57-4743-8b36-0a6068ab9080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345608293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1345608293
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3029512712
Short name T281
Test name
Test status
Simulation time 23753641023 ps
CPU time 17.64 seconds
Started Aug 12 05:36:57 PM PDT 24
Finished Aug 12 05:37:15 PM PDT 24
Peak memory 232912 kb
Host smart-624b34cf-9fa7-4575-bed7-98853ac0736d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029512712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3029512712
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.904846992
Short name T567
Test name
Test status
Simulation time 6687383220 ps
CPU time 8.71 seconds
Started Aug 12 05:37:10 PM PDT 24
Finished Aug 12 05:37:19 PM PDT 24
Peak memory 249264 kb
Host smart-3f02d47d-5fd7-40f9-a68d-6882547ea704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904846992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.904846992
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1078285919
Short name T474
Test name
Test status
Simulation time 315097408 ps
CPU time 3.61 seconds
Started Aug 12 05:37:11 PM PDT 24
Finished Aug 12 05:37:15 PM PDT 24
Peak memory 220360 kb
Host smart-fc44f3ca-815b-4f2f-ab19-88758b9ee786
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1078285919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1078285919
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2118927079
Short name T34
Test name
Test status
Simulation time 69069879 ps
CPU time 1.14 seconds
Started Aug 12 05:37:12 PM PDT 24
Finished Aug 12 05:37:13 PM PDT 24
Peak memory 207740 kb
Host smart-8468b4ab-2a16-4c8d-81bf-4de486647ad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118927079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2118927079
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2727646073
Short name T798
Test name
Test status
Simulation time 2833468091 ps
CPU time 16.07 seconds
Started Aug 12 05:36:51 PM PDT 24
Finished Aug 12 05:37:07 PM PDT 24
Peak memory 216572 kb
Host smart-31a1d0e7-5174-49c7-b5e2-3ee10d7f4aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727646073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2727646073
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2404284305
Short name T913
Test name
Test status
Simulation time 20175055703 ps
CPU time 14.91 seconds
Started Aug 12 05:37:10 PM PDT 24
Finished Aug 12 05:37:25 PM PDT 24
Peak memory 216400 kb
Host smart-5bda29fe-4ea9-4cec-8dd3-1d61d518e664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404284305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2404284305
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1616225990
Short name T659
Test name
Test status
Simulation time 24712918 ps
CPU time 0.88 seconds
Started Aug 12 05:36:45 PM PDT 24
Finished Aug 12 05:36:46 PM PDT 24
Peak memory 206968 kb
Host smart-ff2bcb68-d9d7-4811-8633-b0ae5b83f130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616225990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1616225990
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3229768605
Short name T812
Test name
Test status
Simulation time 54654413 ps
CPU time 0.71 seconds
Started Aug 12 05:37:23 PM PDT 24
Finished Aug 12 05:37:24 PM PDT 24
Peak memory 206020 kb
Host smart-55b53795-64e3-4ca4-9cdd-cfc7da1f0fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229768605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3229768605
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2483032927
Short name T1000
Test name
Test status
Simulation time 3950668733 ps
CPU time 15.42 seconds
Started Aug 12 05:37:01 PM PDT 24
Finished Aug 12 05:37:17 PM PDT 24
Peak memory 224784 kb
Host smart-c09184b5-a3ae-4e5a-a516-601ea0087f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483032927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2483032927
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2774710033
Short name T476
Test name
Test status
Simulation time 19817830 ps
CPU time 0.71 seconds
Started Aug 12 05:37:05 PM PDT 24
Finished Aug 12 05:37:06 PM PDT 24
Peak memory 205268 kb
Host smart-33e3cbdf-41e1-4121-92a2-209e1db04fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774710033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2774710033
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1223457456
Short name T444
Test name
Test status
Simulation time 139796433 ps
CPU time 2.75 seconds
Started Aug 12 05:37:06 PM PDT 24
Finished Aug 12 05:37:09 PM PDT 24
Peak memory 224648 kb
Host smart-bb34f014-6888-4003-807a-4f35ce1935c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223457456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1223457456
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.761318492
Short name T934
Test name
Test status
Simulation time 192725409 ps
CPU time 0.75 seconds
Started Aug 12 05:36:49 PM PDT 24
Finished Aug 12 05:36:50 PM PDT 24
Peak memory 205472 kb
Host smart-d92261ce-12c0-434e-9770-b105597bcb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761318492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.761318492
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2635586091
Short name T309
Test name
Test status
Simulation time 3534764330 ps
CPU time 80.86 seconds
Started Aug 12 05:36:57 PM PDT 24
Finished Aug 12 05:38:18 PM PDT 24
Peak memory 255496 kb
Host smart-dc27914d-c45b-4859-a29a-811f79e148e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635586091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2635586091
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.972176371
Short name T616
Test name
Test status
Simulation time 3088340309 ps
CPU time 23.25 seconds
Started Aug 12 05:37:04 PM PDT 24
Finished Aug 12 05:37:28 PM PDT 24
Peak memory 217808 kb
Host smart-54b8a389-083f-4be4-bd30-236c64429717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972176371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.972176371
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3262624887
Short name T850
Test name
Test status
Simulation time 15421088692 ps
CPU time 98.33 seconds
Started Aug 12 05:36:59 PM PDT 24
Finished Aug 12 05:38:38 PM PDT 24
Peak memory 257616 kb
Host smart-b4a97e76-ccac-455c-949b-e084bf4bd611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262624887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3262624887
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3922842270
Short name T973
Test name
Test status
Simulation time 20820791362 ps
CPU time 26.03 seconds
Started Aug 12 05:36:57 PM PDT 24
Finished Aug 12 05:37:24 PM PDT 24
Peak memory 249304 kb
Host smart-fff327d0-0fc0-4ac8-ade4-69a1c1860f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922842270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3922842270
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.649675319
Short name T607
Test name
Test status
Simulation time 34091989517 ps
CPU time 72.2 seconds
Started Aug 12 05:37:08 PM PDT 24
Finished Aug 12 05:38:20 PM PDT 24
Peak memory 249348 kb
Host smart-d124bbe4-a45a-4d76-873b-89bda90b946c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649675319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.649675319
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1835250172
Short name T241
Test name
Test status
Simulation time 805081083 ps
CPU time 9.76 seconds
Started Aug 12 05:37:06 PM PDT 24
Finished Aug 12 05:37:15 PM PDT 24
Peak memory 232920 kb
Host smart-e1af5eec-0174-4de6-95a0-889de004f4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835250172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1835250172
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3882423238
Short name T520
Test name
Test status
Simulation time 5268561421 ps
CPU time 36.23 seconds
Started Aug 12 05:36:48 PM PDT 24
Finished Aug 12 05:37:24 PM PDT 24
Peak memory 240864 kb
Host smart-eaa00732-bb7b-4dd4-9dae-007b013f7cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882423238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3882423238
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4189984843
Short name T702
Test name
Test status
Simulation time 5502233836 ps
CPU time 18.51 seconds
Started Aug 12 05:36:42 PM PDT 24
Finished Aug 12 05:37:01 PM PDT 24
Peak memory 224756 kb
Host smart-9986f292-9310-4f8f-a4f0-00f85c6ccbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189984843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4189984843
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.4234155218
Short name T800
Test name
Test status
Simulation time 1669914678 ps
CPU time 3.75 seconds
Started Aug 12 05:37:09 PM PDT 24
Finished Aug 12 05:37:13 PM PDT 24
Peak memory 232912 kb
Host smart-568ac83f-1220-48c6-b92d-ff0737d5458a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234155218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4234155218
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2273541150
Short name T957
Test name
Test status
Simulation time 8014041700 ps
CPU time 20.19 seconds
Started Aug 12 05:37:01 PM PDT 24
Finished Aug 12 05:37:22 PM PDT 24
Peak memory 219252 kb
Host smart-07a5ddd7-b8da-416d-90e9-24f02c9c55af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2273541150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2273541150
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3697686994
Short name T986
Test name
Test status
Simulation time 247721190 ps
CPU time 1.14 seconds
Started Aug 12 05:37:13 PM PDT 24
Finished Aug 12 05:37:14 PM PDT 24
Peak memory 214992 kb
Host smart-ff422973-82b7-47a9-b827-2b381774711d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697686994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3697686994
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3608345179
Short name T554
Test name
Test status
Simulation time 4513985577 ps
CPU time 24.2 seconds
Started Aug 12 05:36:58 PM PDT 24
Finished Aug 12 05:37:22 PM PDT 24
Peak memory 216528 kb
Host smart-b250a49b-f91e-45dc-bd5b-bfd50f9a9723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608345179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3608345179
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3690010648
Short name T814
Test name
Test status
Simulation time 7089991425 ps
CPU time 4.44 seconds
Started Aug 12 05:37:06 PM PDT 24
Finished Aug 12 05:37:11 PM PDT 24
Peak memory 216616 kb
Host smart-ad84b319-5245-4a47-9e11-e6829b8eeb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690010648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3690010648
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.30676441
Short name T326
Test name
Test status
Simulation time 243939082 ps
CPU time 1.86 seconds
Started Aug 12 05:37:21 PM PDT 24
Finished Aug 12 05:37:24 PM PDT 24
Peak memory 216400 kb
Host smart-3c01f6c5-aca1-414b-af98-e18e7ab339b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30676441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.30676441
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4121190740
Short name T336
Test name
Test status
Simulation time 68920229 ps
CPU time 0.8 seconds
Started Aug 12 05:37:00 PM PDT 24
Finished Aug 12 05:37:01 PM PDT 24
Peak memory 206040 kb
Host smart-38cf3e3f-213c-4d91-ac2c-d9d7aefa8cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121190740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4121190740
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3508033808
Short name T381
Test name
Test status
Simulation time 508912132 ps
CPU time 3.6 seconds
Started Aug 12 05:36:56 PM PDT 24
Finished Aug 12 05:36:59 PM PDT 24
Peak memory 224644 kb
Host smart-ad4e5d14-4c14-40e2-80e2-dd67790763c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508033808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3508033808
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3575215773
Short name T863
Test name
Test status
Simulation time 18278329 ps
CPU time 0.71 seconds
Started Aug 12 05:36:55 PM PDT 24
Finished Aug 12 05:36:55 PM PDT 24
Peak memory 205304 kb
Host smart-c8d75e1b-034e-4081-b194-676cb63bfccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575215773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3575215773
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4202661301
Short name T449
Test name
Test status
Simulation time 2784863327 ps
CPU time 4.48 seconds
Started Aug 12 05:36:57 PM PDT 24
Finished Aug 12 05:37:02 PM PDT 24
Peak memory 232944 kb
Host smart-f2954e7d-d115-441c-bee9-eacd5a2f573e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202661301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4202661301
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2351746341
Short name T906
Test name
Test status
Simulation time 16734532 ps
CPU time 0.8 seconds
Started Aug 12 05:37:06 PM PDT 24
Finished Aug 12 05:37:07 PM PDT 24
Peak memory 206492 kb
Host smart-01acdbcf-c4c0-4f70-8487-112224daf5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351746341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2351746341
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.428987362
Short name T676
Test name
Test status
Simulation time 19216710783 ps
CPU time 43.22 seconds
Started Aug 12 05:37:12 PM PDT 24
Finished Aug 12 05:37:55 PM PDT 24
Peak memory 241128 kb
Host smart-e08b0e21-3f6f-40b0-8f23-99ca4e61ea76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428987362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.428987362
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.4182063160
Short name T30
Test name
Test status
Simulation time 9852044934 ps
CPU time 56.77 seconds
Started Aug 12 05:37:02 PM PDT 24
Finished Aug 12 05:37:59 PM PDT 24
Peak memory 217768 kb
Host smart-ffd57837-24cd-4c05-9860-33a97b67d912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182063160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.4182063160
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2928924594
Short name T848
Test name
Test status
Simulation time 3363453192 ps
CPU time 12.31 seconds
Started Aug 12 05:36:53 PM PDT 24
Finished Aug 12 05:37:06 PM PDT 24
Peak memory 235400 kb
Host smart-cb78f48c-627e-4a32-893b-a27e98256513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928924594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2928924594
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1473059372
Short name T414
Test name
Test status
Simulation time 38672220457 ps
CPU time 285.91 seconds
Started Aug 12 05:37:07 PM PDT 24
Finished Aug 12 05:41:53 PM PDT 24
Peak memory 252824 kb
Host smart-8e4ac628-1db6-49f8-802d-b0e8f7a867bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473059372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1473059372
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.331687645
Short name T711
Test name
Test status
Simulation time 1890452288 ps
CPU time 7.66 seconds
Started Aug 12 05:37:12 PM PDT 24
Finished Aug 12 05:37:19 PM PDT 24
Peak memory 232916 kb
Host smart-7689d5a9-cde3-4c7f-8cb7-8241c9e47e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331687645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.331687645
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1139441399
Short name T775
Test name
Test status
Simulation time 7870171900 ps
CPU time 89.67 seconds
Started Aug 12 05:36:59 PM PDT 24
Finished Aug 12 05:38:29 PM PDT 24
Peak memory 224732 kb
Host smart-2bc9c17b-aa3f-4c0d-b02e-cb4670d21026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139441399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1139441399
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3883243519
Short name T66
Test name
Test status
Simulation time 562249326 ps
CPU time 8.55 seconds
Started Aug 12 05:37:00 PM PDT 24
Finished Aug 12 05:37:08 PM PDT 24
Peak memory 224700 kb
Host smart-5ab7ed6e-3491-4f94-94c7-fe998d65b43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883243519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3883243519
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.4237172333
Short name T384
Test name
Test status
Simulation time 5800691804 ps
CPU time 6.91 seconds
Started Aug 12 05:37:32 PM PDT 24
Finished Aug 12 05:37:39 PM PDT 24
Peak memory 224760 kb
Host smart-aae4e676-c4f2-4705-b45b-8d4aa8c7bf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237172333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.4237172333
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1918998721
Short name T464
Test name
Test status
Simulation time 1431384148 ps
CPU time 8.86 seconds
Started Aug 12 05:37:16 PM PDT 24
Finished Aug 12 05:37:25 PM PDT 24
Peak memory 218916 kb
Host smart-f5af3bb6-c0c9-4bd7-8b47-91d672401e0e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1918998721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1918998721
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.537984461
Short name T177
Test name
Test status
Simulation time 1058404094 ps
CPU time 11.02 seconds
Started Aug 12 05:36:59 PM PDT 24
Finished Aug 12 05:37:10 PM PDT 24
Peak memory 216468 kb
Host smart-4861ef72-4d60-498b-ad51-9b608d6d5bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537984461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.537984461
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2482266365
Short name T418
Test name
Test status
Simulation time 411609080 ps
CPU time 1.78 seconds
Started Aug 12 05:37:07 PM PDT 24
Finished Aug 12 05:37:09 PM PDT 24
Peak memory 216076 kb
Host smart-b86dd5b0-1863-48b7-aaa7-d92983a006c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482266365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2482266365
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.449617174
Short name T754
Test name
Test status
Simulation time 93534525 ps
CPU time 1.22 seconds
Started Aug 12 05:37:22 PM PDT 24
Finished Aug 12 05:37:24 PM PDT 24
Peak memory 216440 kb
Host smart-21e0b6e9-e70a-469b-a754-5c9642bb36e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449617174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.449617174
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.843158060
Short name T820
Test name
Test status
Simulation time 16409723 ps
CPU time 0.7 seconds
Started Aug 12 05:36:54 PM PDT 24
Finished Aug 12 05:36:55 PM PDT 24
Peak memory 206024 kb
Host smart-110ce51e-1967-4952-b815-f32f2e77203f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843158060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.843158060
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4084165668
Short name T236
Test name
Test status
Simulation time 5167724176 ps
CPU time 19.51 seconds
Started Aug 12 05:36:59 PM PDT 24
Finished Aug 12 05:37:18 PM PDT 24
Peak memory 232928 kb
Host smart-769e87ae-145d-4148-8946-01bea68cba41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084165668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4084165668
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.303599567
Short name T435
Test name
Test status
Simulation time 32639201 ps
CPU time 0.71 seconds
Started Aug 12 05:37:01 PM PDT 24
Finished Aug 12 05:37:02 PM PDT 24
Peak memory 205608 kb
Host smart-c0314f06-1ed7-44ac-9de8-a9dbda11ca47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303599567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.303599567
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2242188957
Short name T410
Test name
Test status
Simulation time 402540971 ps
CPU time 3 seconds
Started Aug 12 05:36:56 PM PDT 24
Finished Aug 12 05:36:59 PM PDT 24
Peak memory 232796 kb
Host smart-19ff25a7-fd14-4847-ba77-69f80e229086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242188957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2242188957
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2039872556
Short name T972
Test name
Test status
Simulation time 87235112 ps
CPU time 0.81 seconds
Started Aug 12 05:37:06 PM PDT 24
Finished Aug 12 05:37:07 PM PDT 24
Peak memory 206812 kb
Host smart-225ed096-bf3b-4722-ae39-4c5b31308c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039872556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2039872556
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.872420903
Short name T721
Test name
Test status
Simulation time 13134349415 ps
CPU time 138.24 seconds
Started Aug 12 05:37:10 PM PDT 24
Finished Aug 12 05:39:28 PM PDT 24
Peak memory 250540 kb
Host smart-9a5e721d-5ecc-4659-874a-d724f98d5f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872420903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.872420903
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1385817498
Short name T720
Test name
Test status
Simulation time 499173267748 ps
CPU time 618.49 seconds
Started Aug 12 05:37:06 PM PDT 24
Finished Aug 12 05:47:25 PM PDT 24
Peak memory 267420 kb
Host smart-9454a4f1-eb5c-408e-b172-17fc517d0276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385817498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1385817498
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3060037910
Short name T524
Test name
Test status
Simulation time 30545459173 ps
CPU time 77.52 seconds
Started Aug 12 05:37:06 PM PDT 24
Finished Aug 12 05:38:24 PM PDT 24
Peak memory 249436 kb
Host smart-f1354204-72ed-47aa-9ab2-59e4049785d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060037910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3060037910
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2501087067
Short name T516
Test name
Test status
Simulation time 286757512 ps
CPU time 2.46 seconds
Started Aug 12 05:37:11 PM PDT 24
Finished Aug 12 05:37:14 PM PDT 24
Peak memory 224684 kb
Host smart-ae0e564d-8236-418f-9b68-0d9c2886d580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501087067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2501087067
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3762250593
Short name T528
Test name
Test status
Simulation time 27600197059 ps
CPU time 81.38 seconds
Started Aug 12 05:36:59 PM PDT 24
Finished Aug 12 05:38:21 PM PDT 24
Peak memory 252216 kb
Host smart-ff291ccf-75b2-4200-ac65-2b1f44da2524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762250593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3762250593
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.658315755
Short name T278
Test name
Test status
Simulation time 104217592 ps
CPU time 2.44 seconds
Started Aug 12 05:36:59 PM PDT 24
Finished Aug 12 05:37:01 PM PDT 24
Peak memory 232896 kb
Host smart-d1a4efa1-ec3d-4658-8dd0-413fc87a59b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658315755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.658315755
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2750091666
Short name T395
Test name
Test status
Simulation time 2829198712 ps
CPU time 11.62 seconds
Started Aug 12 05:37:13 PM PDT 24
Finished Aug 12 05:37:25 PM PDT 24
Peak memory 240800 kb
Host smart-417380bf-4e5d-48e0-aeb2-bbee06e95c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750091666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2750091666
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.736288018
Short name T11
Test name
Test status
Simulation time 504001319 ps
CPU time 2.56 seconds
Started Aug 12 05:36:52 PM PDT 24
Finished Aug 12 05:36:54 PM PDT 24
Peak memory 224668 kb
Host smart-d9853e8c-2e9a-4ac8-8a63-e8075c6fbb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736288018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.736288018
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.584373054
Short name T840
Test name
Test status
Simulation time 539258859 ps
CPU time 6.07 seconds
Started Aug 12 05:37:26 PM PDT 24
Finished Aug 12 05:37:33 PM PDT 24
Peak memory 232928 kb
Host smart-27da9d32-1215-4756-a870-67821dfe25b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584373054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.584373054
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.527635715
Short name T847
Test name
Test status
Simulation time 104202839 ps
CPU time 3.74 seconds
Started Aug 12 05:37:04 PM PDT 24
Finished Aug 12 05:37:08 PM PDT 24
Peak memory 224300 kb
Host smart-43b3efce-abea-4c58-b5f2-f78d4e71b8a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=527635715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.527635715
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2228931254
Short name T35
Test name
Test status
Simulation time 16953520855 ps
CPU time 197.57 seconds
Started Aug 12 05:37:20 PM PDT 24
Finished Aug 12 05:40:38 PM PDT 24
Peak memory 249472 kb
Host smart-1e0fe003-9550-4c72-beb4-437794c7b77b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228931254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2228931254
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3563912751
Short name T886
Test name
Test status
Simulation time 215638486 ps
CPU time 3.66 seconds
Started Aug 12 05:37:14 PM PDT 24
Finished Aug 12 05:37:18 PM PDT 24
Peak memory 218552 kb
Host smart-7105126a-7179-4d88-93cb-2365dbba58fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563912751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3563912751
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.4294216748
Short name T598
Test name
Test status
Simulation time 6192642454 ps
CPU time 11.72 seconds
Started Aug 12 05:36:58 PM PDT 24
Finished Aug 12 05:37:10 PM PDT 24
Peak memory 216440 kb
Host smart-ee74a0e8-725f-40d5-a0d8-078d46ebfb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294216748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.4294216748
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2078480361
Short name T745
Test name
Test status
Simulation time 25880520 ps
CPU time 1.32 seconds
Started Aug 12 05:37:00 PM PDT 24
Finished Aug 12 05:37:01 PM PDT 24
Peak memory 216472 kb
Host smart-33b04180-61a5-4e4a-8ea4-516c64557a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078480361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2078480361
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.511865285
Short name T6
Test name
Test status
Simulation time 27537250 ps
CPU time 0.76 seconds
Started Aug 12 05:37:13 PM PDT 24
Finished Aug 12 05:37:14 PM PDT 24
Peak memory 206044 kb
Host smart-92679b5a-1ce4-4355-bba6-2ddb5ef8ba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511865285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.511865285
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.410764554
Short name T996
Test name
Test status
Simulation time 15236382347 ps
CPU time 11.64 seconds
Started Aug 12 05:37:07 PM PDT 24
Finished Aug 12 05:37:19 PM PDT 24
Peak memory 224708 kb
Host smart-e38ff947-eb7f-4c2a-a675-6d795fff5060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410764554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.410764554
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.420793997
Short name T413
Test name
Test status
Simulation time 12149464 ps
CPU time 0.71 seconds
Started Aug 12 05:37:13 PM PDT 24
Finished Aug 12 05:37:14 PM PDT 24
Peak memory 205296 kb
Host smart-0a6ca297-f89e-4691-95f1-5bfa84bc4fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420793997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.420793997
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1680570259
Short name T865
Test name
Test status
Simulation time 304414756 ps
CPU time 2.39 seconds
Started Aug 12 05:37:12 PM PDT 24
Finished Aug 12 05:37:14 PM PDT 24
Peak memory 224804 kb
Host smart-9f79ba12-17a9-4d5f-a129-d6e6389d61d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680570259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1680570259
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.386194740
Short name T572
Test name
Test status
Simulation time 38395883 ps
CPU time 0.77 seconds
Started Aug 12 05:37:13 PM PDT 24
Finished Aug 12 05:37:14 PM PDT 24
Peak memory 205828 kb
Host smart-2e954f1e-cd15-40b7-a797-02b23967ef0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386194740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.386194740
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2869877539
Short name T284
Test name
Test status
Simulation time 116930534448 ps
CPU time 226.52 seconds
Started Aug 12 05:37:01 PM PDT 24
Finished Aug 12 05:40:48 PM PDT 24
Peak memory 254376 kb
Host smart-92c3c333-4116-4098-82d4-5530c3120a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869877539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2869877539
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2574473659
Short name T312
Test name
Test status
Simulation time 3705726829 ps
CPU time 57.42 seconds
Started Aug 12 05:37:05 PM PDT 24
Finished Aug 12 05:38:02 PM PDT 24
Peak memory 249368 kb
Host smart-95677087-4e0b-4829-8d83-0682df2aa0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574473659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2574473659
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3233385364
Short name T310
Test name
Test status
Simulation time 2141132535 ps
CPU time 25.89 seconds
Started Aug 12 05:36:58 PM PDT 24
Finished Aug 12 05:37:24 PM PDT 24
Peak memory 224692 kb
Host smart-a976dddc-0ee5-438a-8070-7f3ef74192b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233385364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3233385364
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.844077292
Short name T188
Test name
Test status
Simulation time 214242877 ps
CPU time 6.1 seconds
Started Aug 12 05:37:01 PM PDT 24
Finished Aug 12 05:37:07 PM PDT 24
Peak memory 224724 kb
Host smart-9a80a18f-1d94-49e4-a62d-d0dec5aadc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844077292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.844077292
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1971974797
Short name T514
Test name
Test status
Simulation time 3023393684 ps
CPU time 39.61 seconds
Started Aug 12 05:37:05 PM PDT 24
Finished Aug 12 05:37:45 PM PDT 24
Peak memory 238260 kb
Host smart-22405a61-537e-45f2-9463-09d709fccf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971974797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1971974797
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.31086146
Short name T246
Test name
Test status
Simulation time 808353150 ps
CPU time 3.72 seconds
Started Aug 12 05:37:22 PM PDT 24
Finished Aug 12 05:37:26 PM PDT 24
Peak memory 223528 kb
Host smart-475b06c7-34f3-4174-9f77-5ded606eb37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31086146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.31086146
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.413755215
Short name T729
Test name
Test status
Simulation time 92595070090 ps
CPU time 90.32 seconds
Started Aug 12 05:37:13 PM PDT 24
Finished Aug 12 05:38:43 PM PDT 24
Peak memory 240324 kb
Host smart-f671df46-319b-4433-b37a-f6087d4b1fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413755215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.413755215
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.311177531
Short name T629
Test name
Test status
Simulation time 30143495653 ps
CPU time 22.74 seconds
Started Aug 12 05:37:25 PM PDT 24
Finished Aug 12 05:37:47 PM PDT 24
Peak memory 232944 kb
Host smart-54e57135-2509-4ae5-966d-2827ff7e82ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311177531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.311177531
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2598980734
Short name T815
Test name
Test status
Simulation time 1988449552 ps
CPU time 4.44 seconds
Started Aug 12 05:37:10 PM PDT 24
Finished Aug 12 05:37:14 PM PDT 24
Peak memory 232900 kb
Host smart-60e6ef8a-084e-4fc2-872e-4b72757b5e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598980734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2598980734
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.4173900164
Short name T984
Test name
Test status
Simulation time 882185721 ps
CPU time 4.79 seconds
Started Aug 12 05:37:18 PM PDT 24
Finished Aug 12 05:37:23 PM PDT 24
Peak memory 219040 kb
Host smart-a0d69902-a233-4d06-a142-1c59c69ac2dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4173900164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.4173900164
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1985224518
Short name T21
Test name
Test status
Simulation time 4474938546 ps
CPU time 71.69 seconds
Started Aug 12 05:37:31 PM PDT 24
Finished Aug 12 05:38:43 PM PDT 24
Peak memory 256900 kb
Host smart-1870f9ff-26fc-4b08-8076-df9ca7ddc024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985224518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1985224518
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.451369340
Short name T37
Test name
Test status
Simulation time 23357876678 ps
CPU time 30.4 seconds
Started Aug 12 05:37:18 PM PDT 24
Finished Aug 12 05:37:49 PM PDT 24
Peak memory 216488 kb
Host smart-0d0aa4ee-d41f-42dd-b663-714360d3e8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451369340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.451369340
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.854056709
Short name T420
Test name
Test status
Simulation time 4371307949 ps
CPU time 14.28 seconds
Started Aug 12 05:37:11 PM PDT 24
Finished Aug 12 05:37:25 PM PDT 24
Peak memory 216432 kb
Host smart-1ef9669b-9594-4750-8537-67133fd7191b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854056709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.854056709
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2118505215
Short name T967
Test name
Test status
Simulation time 76271048 ps
CPU time 0.99 seconds
Started Aug 12 05:37:03 PM PDT 24
Finished Aug 12 05:37:04 PM PDT 24
Peak memory 207112 kb
Host smart-5bce1679-fdd0-4883-8d24-347108b7004a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118505215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2118505215
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1284901324
Short name T174
Test name
Test status
Simulation time 254841851 ps
CPU time 0.72 seconds
Started Aug 12 05:37:13 PM PDT 24
Finished Aug 12 05:37:14 PM PDT 24
Peak memory 206024 kb
Host smart-3d734e22-ae36-48a9-9c68-bbed9956defe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284901324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1284901324
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1036413075
Short name T564
Test name
Test status
Simulation time 1828507810 ps
CPU time 9.48 seconds
Started Aug 12 05:37:23 PM PDT 24
Finished Aug 12 05:37:33 PM PDT 24
Peak memory 232944 kb
Host smart-a176e160-7e5c-410f-b595-663586c27459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036413075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1036413075
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3224695064
Short name T795
Test name
Test status
Simulation time 34286085 ps
CPU time 0.71 seconds
Started Aug 12 05:37:03 PM PDT 24
Finished Aug 12 05:37:04 PM PDT 24
Peak memory 205320 kb
Host smart-d25ced0c-08bd-4d55-93b4-9ca18fb230df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224695064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3224695064
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1114809438
Short name T755
Test name
Test status
Simulation time 253830839 ps
CPU time 2.71 seconds
Started Aug 12 05:37:11 PM PDT 24
Finished Aug 12 05:37:14 PM PDT 24
Peak memory 232860 kb
Host smart-f2e727c7-2d8a-4759-86f5-836065c1880d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114809438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1114809438
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.306351997
Short name T931
Test name
Test status
Simulation time 17856076 ps
CPU time 0.82 seconds
Started Aug 12 05:37:27 PM PDT 24
Finished Aug 12 05:37:28 PM PDT 24
Peak memory 206792 kb
Host smart-e198bd83-b170-481a-8287-9014646be1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306351997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.306351997
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2269564739
Short name T238
Test name
Test status
Simulation time 2450287586 ps
CPU time 9.49 seconds
Started Aug 12 05:37:15 PM PDT 24
Finished Aug 12 05:37:25 PM PDT 24
Peak memory 237472 kb
Host smart-e89b3246-3b40-478b-8802-5a45098fd3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269564739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2269564739
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2121273934
Short name T985
Test name
Test status
Simulation time 1960451570 ps
CPU time 38.35 seconds
Started Aug 12 05:37:15 PM PDT 24
Finished Aug 12 05:37:54 PM PDT 24
Peak memory 254092 kb
Host smart-24872f63-b382-43c9-b080-7dfe250f160b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121273934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2121273934
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3450520120
Short name T445
Test name
Test status
Simulation time 5426002300 ps
CPU time 82.63 seconds
Started Aug 12 05:37:13 PM PDT 24
Finished Aug 12 05:38:36 PM PDT 24
Peak memory 256092 kb
Host smart-9778732c-0b79-4100-bbfa-964120f838ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450520120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3450520120
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2728111282
Short name T774
Test name
Test status
Simulation time 546411487 ps
CPU time 3.65 seconds
Started Aug 12 05:37:25 PM PDT 24
Finished Aug 12 05:37:29 PM PDT 24
Peak memory 232868 kb
Host smart-8feb73b8-bf0e-4e98-afee-85ad33947d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728111282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2728111282
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1869728967
Short name T677
Test name
Test status
Simulation time 8410263638 ps
CPU time 44.53 seconds
Started Aug 12 05:37:05 PM PDT 24
Finished Aug 12 05:37:50 PM PDT 24
Peak memory 249380 kb
Host smart-444fdb02-8cee-4efa-805b-15f07ee738a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869728967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1869728967
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.4010940498
Short name T249
Test name
Test status
Simulation time 1455250836 ps
CPU time 9.27 seconds
Started Aug 12 05:37:06 PM PDT 24
Finished Aug 12 05:37:16 PM PDT 24
Peak memory 224632 kb
Host smart-d1558058-2b7c-4ac3-b14c-8a8a797a89c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010940498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.4010940498
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3940181506
Short name T500
Test name
Test status
Simulation time 7093940447 ps
CPU time 76.31 seconds
Started Aug 12 05:37:05 PM PDT 24
Finished Aug 12 05:38:22 PM PDT 24
Peak memory 224748 kb
Host smart-b02c9e8b-4f92-4396-ad1f-25b1a95fd9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940181506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3940181506
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1596031091
Short name T926
Test name
Test status
Simulation time 32464546 ps
CPU time 2.04 seconds
Started Aug 12 05:37:12 PM PDT 24
Finished Aug 12 05:37:15 PM PDT 24
Peak memory 223292 kb
Host smart-6567a263-1032-4aa7-a504-d49cc1069a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596031091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1596031091
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2376348331
Short name T699
Test name
Test status
Simulation time 27494253111 ps
CPU time 7.02 seconds
Started Aug 12 05:37:27 PM PDT 24
Finished Aug 12 05:37:34 PM PDT 24
Peak memory 224684 kb
Host smart-cba794dd-a940-4c0f-b05a-7438b3345227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376348331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2376348331
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4049049420
Short name T523
Test name
Test status
Simulation time 648323137 ps
CPU time 7.92 seconds
Started Aug 12 05:37:35 PM PDT 24
Finished Aug 12 05:37:43 PM PDT 24
Peak memory 222536 kb
Host smart-19192246-24b5-4009-984f-a73b9800b8e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4049049420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4049049420
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2707666579
Short name T1016
Test name
Test status
Simulation time 5828041550 ps
CPU time 91.8 seconds
Started Aug 12 05:37:12 PM PDT 24
Finished Aug 12 05:38:44 PM PDT 24
Peak memory 248856 kb
Host smart-72386efb-e835-4726-a6ef-ed35d08d72ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707666579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2707666579
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1083410810
Short name T654
Test name
Test status
Simulation time 1783121392 ps
CPU time 9.85 seconds
Started Aug 12 05:37:06 PM PDT 24
Finished Aug 12 05:37:16 PM PDT 24
Peak memory 216440 kb
Host smart-d07969c3-5298-4c0b-b68f-d1f27bf5b010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083410810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1083410810
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.964071623
Short name T757
Test name
Test status
Simulation time 30035382276 ps
CPU time 10.53 seconds
Started Aug 12 05:37:05 PM PDT 24
Finished Aug 12 05:37:16 PM PDT 24
Peak memory 216448 kb
Host smart-9babcf66-f666-42b8-9008-4ad1abb7f042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964071623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.964071623
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4227293315
Short name T525
Test name
Test status
Simulation time 17190707 ps
CPU time 0.94 seconds
Started Aug 12 05:37:12 PM PDT 24
Finished Aug 12 05:37:13 PM PDT 24
Peak memory 206812 kb
Host smart-4667a037-be8d-423e-b590-572f1a1e8282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227293315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4227293315
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.933667949
Short name T761
Test name
Test status
Simulation time 55886494 ps
CPU time 0.84 seconds
Started Aug 12 05:37:12 PM PDT 24
Finished Aug 12 05:37:13 PM PDT 24
Peak memory 206020 kb
Host smart-bc145032-4f9b-4b5b-8f9d-4244130187e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933667949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.933667949
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2189409961
Short name T455
Test name
Test status
Simulation time 494433218 ps
CPU time 4.94 seconds
Started Aug 12 05:37:07 PM PDT 24
Finished Aug 12 05:37:12 PM PDT 24
Peak memory 224656 kb
Host smart-a44ba677-7800-444c-a0c6-d6789d69e26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189409961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2189409961
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3746595303
Short name T422
Test name
Test status
Simulation time 12935859 ps
CPU time 0.71 seconds
Started Aug 12 05:37:18 PM PDT 24
Finished Aug 12 05:37:19 PM PDT 24
Peak memory 205280 kb
Host smart-77d1a6e5-547d-42ba-8936-29b00708a350
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746595303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3746595303
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3121140728
Short name T968
Test name
Test status
Simulation time 625132649 ps
CPU time 7.7 seconds
Started Aug 12 05:37:06 PM PDT 24
Finished Aug 12 05:37:14 PM PDT 24
Peak memory 224636 kb
Host smart-6cb1a61e-2cd8-4b03-9097-823948c39288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121140728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3121140728
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2836636241
Short name T423
Test name
Test status
Simulation time 18580457 ps
CPU time 0.83 seconds
Started Aug 12 05:37:22 PM PDT 24
Finished Aug 12 05:37:23 PM PDT 24
Peak memory 205380 kb
Host smart-47bbcfaa-950a-41a7-95c1-3650e3df2018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836636241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2836636241
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2822283602
Short name T540
Test name
Test status
Simulation time 114538594404 ps
CPU time 111.32 seconds
Started Aug 12 05:37:19 PM PDT 24
Finished Aug 12 05:39:11 PM PDT 24
Peak memory 241176 kb
Host smart-c764c82e-5fbd-4efb-aa1b-02ed5c539030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822283602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2822283602
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.895706036
Short name T1018
Test name
Test status
Simulation time 212683877914 ps
CPU time 249.82 seconds
Started Aug 12 05:37:13 PM PDT 24
Finished Aug 12 05:41:23 PM PDT 24
Peak memory 273944 kb
Host smart-c15774e4-d388-4da5-869e-7876bca60d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895706036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.895706036
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.940684886
Short name T640
Test name
Test status
Simulation time 130245063039 ps
CPU time 260.57 seconds
Started Aug 12 05:37:05 PM PDT 24
Finished Aug 12 05:41:26 PM PDT 24
Peak memory 249420 kb
Host smart-87d14b52-007c-483f-bfc5-d845f7d821f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940684886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.940684886
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3994393609
Short name T1021
Test name
Test status
Simulation time 1039431947 ps
CPU time 10.64 seconds
Started Aug 12 05:37:19 PM PDT 24
Finished Aug 12 05:37:30 PM PDT 24
Peak memory 232928 kb
Host smart-a234de7c-5cf7-4245-9372-2e00de04346c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994393609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3994393609
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3930682238
Short name T954
Test name
Test status
Simulation time 85938805204 ps
CPU time 201.44 seconds
Started Aug 12 05:37:10 PM PDT 24
Finished Aug 12 05:40:31 PM PDT 24
Peak memory 249504 kb
Host smart-3c93375f-47aa-425c-aa2e-8fa105a3dbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930682238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3930682238
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3763605342
Short name T85
Test name
Test status
Simulation time 1526415101 ps
CPU time 9.12 seconds
Started Aug 12 05:37:09 PM PDT 24
Finished Aug 12 05:37:18 PM PDT 24
Peak memory 224640 kb
Host smart-378eb630-1786-4c91-a2c8-061b160fb8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763605342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3763605342
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3635786136
Short name T738
Test name
Test status
Simulation time 127515530666 ps
CPU time 61.09 seconds
Started Aug 12 05:37:14 PM PDT 24
Finished Aug 12 05:38:16 PM PDT 24
Peak memory 232984 kb
Host smart-96c5b397-ad3b-4402-8e37-aad07fae9b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635786136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3635786136
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.80736025
Short name T489
Test name
Test status
Simulation time 626526076 ps
CPU time 2.37 seconds
Started Aug 12 05:37:24 PM PDT 24
Finished Aug 12 05:37:31 PM PDT 24
Peak memory 224664 kb
Host smart-dceac184-bef8-4151-a59f-a4b525896810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80736025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.80736025
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1988117377
Short name T459
Test name
Test status
Simulation time 6357002420 ps
CPU time 18.54 seconds
Started Aug 12 05:37:14 PM PDT 24
Finished Aug 12 05:37:33 PM PDT 24
Peak memory 232920 kb
Host smart-48fe56a5-be2a-42b8-b56d-57cc843b92e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988117377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1988117377
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.596963072
Short name T460
Test name
Test status
Simulation time 500304419 ps
CPU time 5.88 seconds
Started Aug 12 05:37:05 PM PDT 24
Finished Aug 12 05:37:11 PM PDT 24
Peak memory 219804 kb
Host smart-418865bb-cb12-483f-8983-89ffa12f7588
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=596963072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.596963072
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1261605419
Short name T723
Test name
Test status
Simulation time 7131459378 ps
CPU time 34.66 seconds
Started Aug 12 05:37:11 PM PDT 24
Finished Aug 12 05:37:46 PM PDT 24
Peak memory 224772 kb
Host smart-81506bb1-ed34-4155-b5e9-b118e31da850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261605419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1261605419
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1249033344
Short name T318
Test name
Test status
Simulation time 9802696833 ps
CPU time 23.32 seconds
Started Aug 12 05:37:16 PM PDT 24
Finished Aug 12 05:37:39 PM PDT 24
Peak memory 216524 kb
Host smart-b7f9ba77-afc5-470d-a99f-8432860d7d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249033344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1249033344
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2101657744
Short name T641
Test name
Test status
Simulation time 874570030 ps
CPU time 5.41 seconds
Started Aug 12 05:37:11 PM PDT 24
Finished Aug 12 05:37:16 PM PDT 24
Peak memory 216348 kb
Host smart-08fd7556-fe09-463d-a2b5-70ad543ca9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101657744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2101657744
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1301790378
Short name T804
Test name
Test status
Simulation time 482353494 ps
CPU time 4.96 seconds
Started Aug 12 05:37:29 PM PDT 24
Finished Aug 12 05:37:34 PM PDT 24
Peak memory 216392 kb
Host smart-9ace332d-f5e4-4892-9ddc-6e5ba0f8ed6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301790378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1301790378
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2613017615
Short name T608
Test name
Test status
Simulation time 26138219 ps
CPU time 0.82 seconds
Started Aug 12 05:36:59 PM PDT 24
Finished Aug 12 05:37:00 PM PDT 24
Peak memory 206056 kb
Host smart-d456b64a-78ed-403c-a5e5-6f7b94b8ba21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613017615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2613017615
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1921854155
Short name T1009
Test name
Test status
Simulation time 1722692160 ps
CPU time 8.63 seconds
Started Aug 12 05:37:08 PM PDT 24
Finished Aug 12 05:37:16 PM PDT 24
Peak memory 232800 kb
Host smart-189371d1-4b34-4667-9742-fd08affe7cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921854155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1921854155
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.760520889
Short name T70
Test name
Test status
Simulation time 30057706 ps
CPU time 0.68 seconds
Started Aug 12 05:35:31 PM PDT 24
Finished Aug 12 05:35:32 PM PDT 24
Peak memory 205612 kb
Host smart-44717901-de19-449a-9537-8197d174c885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760520889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.760520889
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2928268376
Short name T603
Test name
Test status
Simulation time 1182981562 ps
CPU time 3.54 seconds
Started Aug 12 05:35:28 PM PDT 24
Finished Aug 12 05:35:32 PM PDT 24
Peak memory 224660 kb
Host smart-66c77a47-08fa-45ef-a11f-8e4a3cf70f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928268376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2928268376
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.96558353
Short name T1015
Test name
Test status
Simulation time 66293295 ps
CPU time 0.77 seconds
Started Aug 12 05:35:49 PM PDT 24
Finished Aug 12 05:35:50 PM PDT 24
Peak memory 206812 kb
Host smart-05dc5592-ba6f-4e3f-8cf3-62da741fc039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96558353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.96558353
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.932208907
Short name T213
Test name
Test status
Simulation time 15998115032 ps
CPU time 148.09 seconds
Started Aug 12 05:35:42 PM PDT 24
Finished Aug 12 05:38:11 PM PDT 24
Peak memory 249368 kb
Host smart-99de9e09-fd38-41e3-8f10-9c005e6b3b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932208907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.932208907
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2332850602
Short name T245
Test name
Test status
Simulation time 67669330094 ps
CPU time 289.27 seconds
Started Aug 12 05:35:41 PM PDT 24
Finished Aug 12 05:40:30 PM PDT 24
Peak memory 270148 kb
Host smart-25385ade-f9be-4e3a-8626-fdfc4fabdeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332850602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2332850602
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3307886671
Short name T311
Test name
Test status
Simulation time 4721096757 ps
CPU time 9.02 seconds
Started Aug 12 05:35:54 PM PDT 24
Finished Aug 12 05:36:03 PM PDT 24
Peak memory 217768 kb
Host smart-50fd18a2-fb14-48d2-b16d-971ae4f1d6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307886671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3307886671
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3165763609
Short name T526
Test name
Test status
Simulation time 2153413082 ps
CPU time 30.4 seconds
Started Aug 12 05:35:52 PM PDT 24
Finished Aug 12 05:36:23 PM PDT 24
Peak memory 241144 kb
Host smart-967a33ed-99ea-405a-bce7-755ea4384c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165763609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3165763609
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3444386382
Short name T639
Test name
Test status
Simulation time 50075356561 ps
CPU time 89.52 seconds
Started Aug 12 05:35:30 PM PDT 24
Finished Aug 12 05:37:00 PM PDT 24
Peak memory 251176 kb
Host smart-19dca913-eb06-4d23-b489-f610a4081e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444386382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3444386382
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1727438626
Short name T102
Test name
Test status
Simulation time 881141324 ps
CPU time 5.42 seconds
Started Aug 12 05:35:31 PM PDT 24
Finished Aug 12 05:35:37 PM PDT 24
Peak memory 224684 kb
Host smart-77e02440-b17f-48fd-9493-258b7845bd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727438626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1727438626
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3588903729
Short name T274
Test name
Test status
Simulation time 9840932248 ps
CPU time 73.74 seconds
Started Aug 12 05:35:44 PM PDT 24
Finished Aug 12 05:36:58 PM PDT 24
Peak memory 237764 kb
Host smart-f6c6b93b-5bb8-4603-97f3-56e75c060487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588903729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3588903729
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1499044829
Short name T47
Test name
Test status
Simulation time 14987839 ps
CPU time 0.95 seconds
Started Aug 12 05:35:38 PM PDT 24
Finished Aug 12 05:35:39 PM PDT 24
Peak memory 217916 kb
Host smart-62bab2e5-b59f-4e05-b3d8-13a3454d4ecd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499044829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1499044829
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3568009017
Short name T228
Test name
Test status
Simulation time 323377976 ps
CPU time 5.01 seconds
Started Aug 12 05:35:50 PM PDT 24
Finished Aug 12 05:35:55 PM PDT 24
Peak memory 240872 kb
Host smart-f95cc655-4560-4c91-92c7-34ae170c28df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568009017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3568009017
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.283896800
Short name T819
Test name
Test status
Simulation time 3317703443 ps
CPU time 9.91 seconds
Started Aug 12 05:35:40 PM PDT 24
Finished Aug 12 05:35:50 PM PDT 24
Peak memory 232884 kb
Host smart-2e00c89e-1763-4680-9671-97e9b99754be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283896800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.283896800
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2735727459
Short name T875
Test name
Test status
Simulation time 792185425 ps
CPU time 4.91 seconds
Started Aug 12 05:35:53 PM PDT 24
Finished Aug 12 05:35:58 PM PDT 24
Peak memory 219816 kb
Host smart-754d6910-89d8-4484-bed6-f347563f691a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2735727459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2735727459
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2313660389
Short name T75
Test name
Test status
Simulation time 168364940 ps
CPU time 1.11 seconds
Started Aug 12 05:35:45 PM PDT 24
Finished Aug 12 05:35:46 PM PDT 24
Peak memory 236172 kb
Host smart-2d26a2d2-8687-4df1-977e-edb04560f499
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313660389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2313660389
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2237470899
Short name T651
Test name
Test status
Simulation time 4227806518 ps
CPU time 14.09 seconds
Started Aug 12 05:36:01 PM PDT 24
Finished Aug 12 05:36:15 PM PDT 24
Peak memory 216464 kb
Host smart-a8283111-9e49-40ef-b233-0ebeac21d030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237470899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2237470899
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2218426500
Short name T849
Test name
Test status
Simulation time 5585277010 ps
CPU time 11.14 seconds
Started Aug 12 05:35:50 PM PDT 24
Finished Aug 12 05:36:01 PM PDT 24
Peak memory 216452 kb
Host smart-58f87c7f-7d0d-47e5-b273-a89f27588fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218426500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2218426500
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2044037772
Short name T989
Test name
Test status
Simulation time 67005283 ps
CPU time 1.7 seconds
Started Aug 12 05:35:37 PM PDT 24
Finished Aug 12 05:35:39 PM PDT 24
Peak memory 216452 kb
Host smart-db688774-a9a5-4c00-9065-1360dc2d793f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044037772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2044037772
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3340143361
Short name T1003
Test name
Test status
Simulation time 75855782 ps
CPU time 0.89 seconds
Started Aug 12 05:35:27 PM PDT 24
Finished Aug 12 05:35:28 PM PDT 24
Peak memory 206044 kb
Host smart-fb4606c4-8491-461c-8382-766736ab10a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340143361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3340143361
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1463415340
Short name T86
Test name
Test status
Simulation time 6742252530 ps
CPU time 7.75 seconds
Started Aug 12 05:36:00 PM PDT 24
Finished Aug 12 05:36:08 PM PDT 24
Peak memory 232952 kb
Host smart-aa9d5648-c972-4a9c-9ee3-dbfaccc207db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463415340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1463415340
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2371152217
Short name T390
Test name
Test status
Simulation time 23770535 ps
CPU time 0.73 seconds
Started Aug 12 05:37:10 PM PDT 24
Finished Aug 12 05:37:11 PM PDT 24
Peak memory 204716 kb
Host smart-4202aebd-7ef9-4ee6-8dff-3cc470fbb657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371152217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2371152217
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3139825362
Short name T214
Test name
Test status
Simulation time 81799337 ps
CPU time 2.37 seconds
Started Aug 12 05:37:27 PM PDT 24
Finished Aug 12 05:37:30 PM PDT 24
Peak memory 232880 kb
Host smart-7e8ce748-339f-4214-a003-a03e308193a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139825362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3139825362
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.816603919
Short name T69
Test name
Test status
Simulation time 25561057 ps
CPU time 0.73 seconds
Started Aug 12 05:37:09 PM PDT 24
Finished Aug 12 05:37:10 PM PDT 24
Peak memory 205796 kb
Host smart-6d75b5d6-8ec0-46e1-b550-c873d9777ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816603919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.816603919
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1013350150
Short name T306
Test name
Test status
Simulation time 7344013976 ps
CPU time 50.94 seconds
Started Aug 12 05:37:10 PM PDT 24
Finished Aug 12 05:38:01 PM PDT 24
Peak memory 224776 kb
Host smart-3d9024a6-f431-4a32-a5d2-75e151b3fd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013350150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1013350150
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2316487955
Short name T691
Test name
Test status
Simulation time 3764360774 ps
CPU time 44 seconds
Started Aug 12 05:37:16 PM PDT 24
Finished Aug 12 05:38:00 PM PDT 24
Peak memory 232992 kb
Host smart-aad0822f-0954-4c22-b04e-3825fa4205bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316487955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2316487955
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2881013948
Short name T959
Test name
Test status
Simulation time 177875096637 ps
CPU time 340.88 seconds
Started Aug 12 05:37:11 PM PDT 24
Finished Aug 12 05:42:52 PM PDT 24
Peak memory 257620 kb
Host smart-62029620-3f53-45ce-8899-199172d4cd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881013948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2881013948
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4214200846
Short name T364
Test name
Test status
Simulation time 853390095 ps
CPU time 4.65 seconds
Started Aug 12 05:37:08 PM PDT 24
Finished Aug 12 05:37:13 PM PDT 24
Peak memory 224712 kb
Host smart-53ac3981-6bda-4078-9d06-f845acc62857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214200846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4214200846
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2366652846
Short name T224
Test name
Test status
Simulation time 22391604926 ps
CPU time 182.02 seconds
Started Aug 12 05:37:13 PM PDT 24
Finished Aug 12 05:40:16 PM PDT 24
Peak memory 249696 kb
Host smart-844cfcea-6063-4678-9247-b7718ed9f67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366652846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2366652846
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1046060082
Short name T710
Test name
Test status
Simulation time 2944683927 ps
CPU time 11.37 seconds
Started Aug 12 05:37:13 PM PDT 24
Finished Aug 12 05:37:25 PM PDT 24
Peak memory 224904 kb
Host smart-328eeb65-377e-433d-a370-e8c0918b5169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046060082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1046060082
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3188208998
Short name T759
Test name
Test status
Simulation time 520645432 ps
CPU time 3.98 seconds
Started Aug 12 05:37:25 PM PDT 24
Finished Aug 12 05:37:29 PM PDT 24
Peak memory 241108 kb
Host smart-5ad7362a-c041-40cc-ac6a-457689838f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188208998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3188208998
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4100269728
Short name T883
Test name
Test status
Simulation time 620709264 ps
CPU time 2.64 seconds
Started Aug 12 05:37:27 PM PDT 24
Finished Aug 12 05:37:29 PM PDT 24
Peak memory 224636 kb
Host smart-a33eb52e-d376-455a-b216-dda54f2f0faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100269728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4100269728
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1360336896
Short name T147
Test name
Test status
Simulation time 3023235236 ps
CPU time 5.07 seconds
Started Aug 12 05:37:14 PM PDT 24
Finished Aug 12 05:37:20 PM PDT 24
Peak memory 220872 kb
Host smart-e43cd994-7e97-45c0-a426-cabd7896d277
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1360336896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1360336896
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4129817886
Short name T733
Test name
Test status
Simulation time 690348212 ps
CPU time 6.17 seconds
Started Aug 12 05:37:17 PM PDT 24
Finished Aug 12 05:37:23 PM PDT 24
Peak memory 216524 kb
Host smart-8666a7a2-00a1-4c41-85f8-f73fa0c2c140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129817886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4129817886
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.782770384
Short name T99
Test name
Test status
Simulation time 5746857603 ps
CPU time 9.53 seconds
Started Aug 12 05:37:11 PM PDT 24
Finished Aug 12 05:37:20 PM PDT 24
Peak memory 216460 kb
Host smart-db971863-0a80-4cad-8824-09e6ce37aaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782770384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.782770384
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1081530949
Short name T873
Test name
Test status
Simulation time 68214970 ps
CPU time 1.26 seconds
Started Aug 12 05:37:24 PM PDT 24
Finished Aug 12 05:37:25 PM PDT 24
Peak memory 208032 kb
Host smart-0dba5933-c3b0-4eb4-b978-1757b5829081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081530949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1081530949
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3066465425
Short name T2
Test name
Test status
Simulation time 24014789 ps
CPU time 0.75 seconds
Started Aug 12 05:37:24 PM PDT 24
Finished Aug 12 05:37:25 PM PDT 24
Peak memory 206012 kb
Host smart-899d94b7-292f-49b9-a5c6-10fde6e8749f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066465425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3066465425
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1205191305
Short name T622
Test name
Test status
Simulation time 18611289361 ps
CPU time 16.01 seconds
Started Aug 12 05:37:20 PM PDT 24
Finished Aug 12 05:37:36 PM PDT 24
Peak memory 240872 kb
Host smart-aef452f8-67c6-427d-8422-a5d9cc5184d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205191305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1205191305
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.842204251
Short name T542
Test name
Test status
Simulation time 31415513 ps
CPU time 0.74 seconds
Started Aug 12 05:37:04 PM PDT 24
Finished Aug 12 05:37:05 PM PDT 24
Peak memory 205280 kb
Host smart-ab554abe-e354-4cae-8160-156e25835113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842204251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.842204251
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3649999844
Short name T4
Test name
Test status
Simulation time 1282564087 ps
CPU time 7.24 seconds
Started Aug 12 05:37:12 PM PDT 24
Finished Aug 12 05:37:20 PM PDT 24
Peak memory 224660 kb
Host smart-23055ff9-c4a5-49ab-81c3-1ea3946413a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649999844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3649999844
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.214182695
Short name T1005
Test name
Test status
Simulation time 33414886 ps
CPU time 0.73 seconds
Started Aug 12 05:37:23 PM PDT 24
Finished Aug 12 05:37:24 PM PDT 24
Peak memory 205460 kb
Host smart-85141910-0c85-4ffc-ad43-cc5c5ebeceeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214182695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.214182695
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2554838829
Short name T1012
Test name
Test status
Simulation time 4769704787 ps
CPU time 20.15 seconds
Started Aug 12 05:37:28 PM PDT 24
Finished Aug 12 05:37:49 PM PDT 24
Peak memory 232948 kb
Host smart-9693347e-f496-4a2d-a1a8-2b7c410943fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554838829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2554838829
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3056172440
Short name T979
Test name
Test status
Simulation time 19948392168 ps
CPU time 121.91 seconds
Started Aug 12 05:37:09 PM PDT 24
Finished Aug 12 05:39:11 PM PDT 24
Peak memory 252172 kb
Host smart-17ad7607-9eed-4113-b242-5e2e27c49097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056172440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3056172440
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1983767233
Short name T975
Test name
Test status
Simulation time 7198056287 ps
CPU time 100.77 seconds
Started Aug 12 05:37:14 PM PDT 24
Finished Aug 12 05:38:55 PM PDT 24
Peak memory 249496 kb
Host smart-b338fce9-d262-4b81-af23-c24b43701817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983767233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1983767233
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2031823399
Short name T786
Test name
Test status
Simulation time 1819315930 ps
CPU time 8.99 seconds
Started Aug 12 05:37:08 PM PDT 24
Finished Aug 12 05:37:17 PM PDT 24
Peak memory 237648 kb
Host smart-4f6c9ae2-159d-4524-9cb4-db29702777cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031823399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2031823399
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1101587436
Short name T270
Test name
Test status
Simulation time 209417763260 ps
CPU time 378.74 seconds
Started Aug 12 05:37:23 PM PDT 24
Finished Aug 12 05:43:42 PM PDT 24
Peak memory 255956 kb
Host smart-1b909f51-cc3e-425f-ab25-f9a72821c63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101587436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1101587436
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3580392816
Short name T801
Test name
Test status
Simulation time 156107819 ps
CPU time 3.19 seconds
Started Aug 12 05:37:08 PM PDT 24
Finished Aug 12 05:37:11 PM PDT 24
Peak memory 224648 kb
Host smart-c0aeee27-8e90-4628-b17c-3dcbe6cc25ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580392816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3580392816
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3739125974
Short name T254
Test name
Test status
Simulation time 9092528203 ps
CPU time 88.84 seconds
Started Aug 12 05:37:20 PM PDT 24
Finished Aug 12 05:38:49 PM PDT 24
Peak memory 252720 kb
Host smart-ed595b28-9b69-4c8c-a96e-77cada0c2658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739125974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3739125974
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1677062477
Short name T924
Test name
Test status
Simulation time 4382187596 ps
CPU time 9.89 seconds
Started Aug 12 05:37:36 PM PDT 24
Finished Aug 12 05:37:46 PM PDT 24
Peak memory 240636 kb
Host smart-bd656592-d34b-4828-97d6-d70df3d385d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677062477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1677062477
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1302339932
Short name T253
Test name
Test status
Simulation time 1519468793 ps
CPU time 6.55 seconds
Started Aug 12 05:37:38 PM PDT 24
Finished Aug 12 05:37:44 PM PDT 24
Peak memory 232900 kb
Host smart-33643df9-0d7b-4b04-b0ab-e4e23eebd476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302339932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1302339932
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3099329346
Short name T864
Test name
Test status
Simulation time 3348389097 ps
CPU time 5.51 seconds
Started Aug 12 05:37:23 PM PDT 24
Finished Aug 12 05:37:29 PM PDT 24
Peak memory 220156 kb
Host smart-3a5a7e19-311e-49d0-a7bb-80b71bce953f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3099329346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3099329346
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3781713314
Short name T678
Test name
Test status
Simulation time 3108163724 ps
CPU time 16.74 seconds
Started Aug 12 05:37:12 PM PDT 24
Finished Aug 12 05:37:29 PM PDT 24
Peak memory 216560 kb
Host smart-bf41bc21-d5fd-4566-9aaa-1f8178d207a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781713314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3781713314
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3455670299
Short name T325
Test name
Test status
Simulation time 20164482915 ps
CPU time 9.05 seconds
Started Aug 12 05:37:14 PM PDT 24
Finished Aug 12 05:37:24 PM PDT 24
Peak memory 216408 kb
Host smart-e501a51e-4d2f-4208-8173-216d1cd67752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455670299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3455670299
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3436407426
Short name T991
Test name
Test status
Simulation time 97285977 ps
CPU time 2.71 seconds
Started Aug 12 05:37:16 PM PDT 24
Finished Aug 12 05:37:19 PM PDT 24
Peak memory 216480 kb
Host smart-d62dca92-292a-4093-b6c3-da3f1880c6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436407426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3436407426
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3599506495
Short name T963
Test name
Test status
Simulation time 87352350 ps
CPU time 0.74 seconds
Started Aug 12 05:37:10 PM PDT 24
Finished Aug 12 05:37:10 PM PDT 24
Peak memory 206168 kb
Host smart-d5367a18-b215-489d-90a1-e31dd928834b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599506495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3599506495
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3840582819
Short name T545
Test name
Test status
Simulation time 2586456104 ps
CPU time 19.46 seconds
Started Aug 12 05:37:10 PM PDT 24
Finished Aug 12 05:37:30 PM PDT 24
Peak memory 232928 kb
Host smart-fe693004-8815-4e45-88c1-bb58a3883705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840582819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3840582819
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1161637384
Short name T694
Test name
Test status
Simulation time 36212074 ps
CPU time 0.7 seconds
Started Aug 12 05:37:39 PM PDT 24
Finished Aug 12 05:37:40 PM PDT 24
Peak memory 205252 kb
Host smart-855f4399-f6b7-4c17-a6ed-4e80c91a7a29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161637384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1161637384
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4152806290
Short name T794
Test name
Test status
Simulation time 76195799 ps
CPU time 2.31 seconds
Started Aug 12 05:37:28 PM PDT 24
Finished Aug 12 05:37:30 PM PDT 24
Peak memory 232868 kb
Host smart-8e9ff4d6-6833-4594-90e6-93df7cbc5a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152806290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4152806290
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.4187319837
Short name T817
Test name
Test status
Simulation time 15949000 ps
CPU time 0.79 seconds
Started Aug 12 05:37:07 PM PDT 24
Finished Aug 12 05:37:08 PM PDT 24
Peak memory 206512 kb
Host smart-4c88a388-20fe-48f6-9f1f-ebf6fd231001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187319837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.4187319837
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2259341530
Short name T652
Test name
Test status
Simulation time 43618447 ps
CPU time 0.9 seconds
Started Aug 12 05:37:16 PM PDT 24
Finished Aug 12 05:37:17 PM PDT 24
Peak memory 216080 kb
Host smart-b06e0c9c-4fb5-4cb7-8b3a-08b36bb8ecec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259341530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2259341530
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2436975418
Short name T457
Test name
Test status
Simulation time 5773477045 ps
CPU time 51.12 seconds
Started Aug 12 05:37:15 PM PDT 24
Finished Aug 12 05:38:06 PM PDT 24
Peak memory 224788 kb
Host smart-bb30146e-5d37-44ee-826b-f758a83259bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436975418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2436975418
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2067360387
Short name T533
Test name
Test status
Simulation time 101199468 ps
CPU time 2.98 seconds
Started Aug 12 05:37:23 PM PDT 24
Finished Aug 12 05:37:26 PM PDT 24
Peak memory 224592 kb
Host smart-1040cf4d-6317-4964-94d7-28530258185e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067360387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2067360387
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3158713156
Short name T992
Test name
Test status
Simulation time 12291204391 ps
CPU time 13.75 seconds
Started Aug 12 05:37:15 PM PDT 24
Finished Aug 12 05:37:29 PM PDT 24
Peak memory 224768 kb
Host smart-0000a10e-cd49-4355-8740-0fdf4a6d185a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158713156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3158713156
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1456581160
Short name T1004
Test name
Test status
Simulation time 9554589163 ps
CPU time 19.66 seconds
Started Aug 12 05:37:11 PM PDT 24
Finished Aug 12 05:37:31 PM PDT 24
Peak memory 224720 kb
Host smart-5071a1f1-27b1-4544-bc7d-694fd30379d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456581160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1456581160
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4033741465
Short name T507
Test name
Test status
Simulation time 1021640729 ps
CPU time 7.99 seconds
Started Aug 12 05:37:13 PM PDT 24
Finished Aug 12 05:37:22 PM PDT 24
Peak memory 224716 kb
Host smart-b63a87bf-bd9d-45be-ab79-07f2e9cc60ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033741465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4033741465
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2521784928
Short name T667
Test name
Test status
Simulation time 636885822 ps
CPU time 3.2 seconds
Started Aug 12 05:37:14 PM PDT 24
Finished Aug 12 05:37:17 PM PDT 24
Peak memory 224656 kb
Host smart-2684badc-7152-442b-9dac-b3d6becf3e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521784928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2521784928
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2710892581
Short name T252
Test name
Test status
Simulation time 3157572192 ps
CPU time 7.22 seconds
Started Aug 12 05:37:12 PM PDT 24
Finished Aug 12 05:37:21 PM PDT 24
Peak memory 232996 kb
Host smart-6d7b94e7-591c-4f1e-8e2d-4b91bdef4c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710892581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2710892581
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1938727821
Short name T353
Test name
Test status
Simulation time 391684869 ps
CPU time 4.93 seconds
Started Aug 12 05:37:24 PM PDT 24
Finished Aug 12 05:37:29 PM PDT 24
Peak memory 218844 kb
Host smart-5300409e-f1bb-4f70-b44a-f1a7fdd4cf25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1938727821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1938727821
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1615387261
Short name T811
Test name
Test status
Simulation time 46198424855 ps
CPU time 271.6 seconds
Started Aug 12 05:37:15 PM PDT 24
Finished Aug 12 05:41:47 PM PDT 24
Peak memory 256244 kb
Host smart-3102af30-a20f-4809-87ad-7b5561a27c31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615387261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1615387261
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.926679882
Short name T446
Test name
Test status
Simulation time 17298768265 ps
CPU time 42.41 seconds
Started Aug 12 05:37:30 PM PDT 24
Finished Aug 12 05:38:12 PM PDT 24
Peak memory 216424 kb
Host smart-cfdc777c-5096-4386-8541-93754dc62cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926679882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.926679882
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.684904016
Short name T375
Test name
Test status
Simulation time 1729902986 ps
CPU time 4.2 seconds
Started Aug 12 05:37:16 PM PDT 24
Finished Aug 12 05:37:20 PM PDT 24
Peak memory 216424 kb
Host smart-b6925b9e-1877-46fa-95eb-6eb066312bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684904016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.684904016
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2185504190
Short name T899
Test name
Test status
Simulation time 175455913 ps
CPU time 7.88 seconds
Started Aug 12 05:37:18 PM PDT 24
Finished Aug 12 05:37:26 PM PDT 24
Peak memory 216472 kb
Host smart-31e5d106-bea9-470c-b8be-a192021a1408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185504190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2185504190
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.215990769
Short name T845
Test name
Test status
Simulation time 51498069 ps
CPU time 0.91 seconds
Started Aug 12 05:37:09 PM PDT 24
Finished Aug 12 05:37:10 PM PDT 24
Peak memory 206032 kb
Host smart-f61ff79b-fc71-4afd-b05c-c91cf8967bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215990769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.215990769
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2685499317
Short name T374
Test name
Test status
Simulation time 21399344346 ps
CPU time 16.28 seconds
Started Aug 12 05:37:20 PM PDT 24
Finished Aug 12 05:37:36 PM PDT 24
Peak memory 240608 kb
Host smart-37024f9b-5c18-4193-a2a3-345e9e7315a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685499317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2685499317
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.497847453
Short name T73
Test name
Test status
Simulation time 44327594 ps
CPU time 0.73 seconds
Started Aug 12 05:37:18 PM PDT 24
Finished Aug 12 05:37:19 PM PDT 24
Peak memory 204568 kb
Host smart-9442271c-7486-480a-ad7c-7272fd5ecc8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497847453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.497847453
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2922013972
Short name T268
Test name
Test status
Simulation time 178848430 ps
CPU time 2.25 seconds
Started Aug 12 05:37:21 PM PDT 24
Finished Aug 12 05:37:23 PM PDT 24
Peak memory 224632 kb
Host smart-8dffb276-aa31-49ec-9dd1-4f2dedbee113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922013972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2922013972
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2539560748
Short name T28
Test name
Test status
Simulation time 38287857 ps
CPU time 0.77 seconds
Started Aug 12 05:37:34 PM PDT 24
Finished Aug 12 05:37:35 PM PDT 24
Peak memory 206460 kb
Host smart-033b7a12-37c4-46c5-8d98-8a6072ba5cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539560748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2539560748
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.167850210
Short name T258
Test name
Test status
Simulation time 60350188505 ps
CPU time 123.98 seconds
Started Aug 12 05:37:40 PM PDT 24
Finished Aug 12 05:39:44 PM PDT 24
Peak memory 241160 kb
Host smart-1205a284-9a6e-4fd3-933a-6abed8d5a745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167850210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.167850210
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2059802960
Short name T298
Test name
Test status
Simulation time 21694181144 ps
CPU time 213.09 seconds
Started Aug 12 05:37:30 PM PDT 24
Finished Aug 12 05:41:03 PM PDT 24
Peak memory 249460 kb
Host smart-89b601e3-2c91-47bd-88f8-67b199a589d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059802960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2059802960
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1583036745
Short name T43
Test name
Test status
Simulation time 19374855688 ps
CPU time 169.54 seconds
Started Aug 12 05:37:12 PM PDT 24
Finished Aug 12 05:40:02 PM PDT 24
Peak memory 253776 kb
Host smart-aed615ca-e6fe-425e-9b96-6d7dc3acfa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583036745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1583036745
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.804836753
Short name T181
Test name
Test status
Simulation time 257520160 ps
CPU time 7.55 seconds
Started Aug 12 05:37:33 PM PDT 24
Finished Aug 12 05:37:41 PM PDT 24
Peak memory 224672 kb
Host smart-2f38b93f-65a2-4094-bbfc-e170bd7601dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804836753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.804836753
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.532283763
Short name T517
Test name
Test status
Simulation time 65965720584 ps
CPU time 292.28 seconds
Started Aug 12 05:37:13 PM PDT 24
Finished Aug 12 05:42:05 PM PDT 24
Peak memory 271008 kb
Host smart-dd8adb7c-03a0-4de6-83f5-68699437af2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532283763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.532283763
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2125187586
Short name T884
Test name
Test status
Simulation time 213425037 ps
CPU time 2.89 seconds
Started Aug 12 05:37:23 PM PDT 24
Finished Aug 12 05:37:26 PM PDT 24
Peak memory 224680 kb
Host smart-c4513d7b-2eb3-4c85-9a08-6ec4f70e0501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125187586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2125187586
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1240092352
Short name T831
Test name
Test status
Simulation time 1865676743 ps
CPU time 10.4 seconds
Started Aug 12 05:37:27 PM PDT 24
Finished Aug 12 05:37:38 PM PDT 24
Peak memory 224712 kb
Host smart-5e9a3c45-cb48-49d1-b869-4bcf49412210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240092352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1240092352
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2737133839
Short name T867
Test name
Test status
Simulation time 42170613246 ps
CPU time 9.9 seconds
Started Aug 12 05:37:41 PM PDT 24
Finished Aug 12 05:37:51 PM PDT 24
Peak memory 232904 kb
Host smart-e733145d-3a70-40ba-9cd5-954754d77c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737133839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2737133839
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2123141763
Short name T470
Test name
Test status
Simulation time 50964443698 ps
CPU time 36.65 seconds
Started Aug 12 05:37:32 PM PDT 24
Finished Aug 12 05:38:09 PM PDT 24
Peak memory 233844 kb
Host smart-7b243f59-602d-4ddc-9345-9bf3ddc7e2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123141763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2123141763
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1136678504
Short name T998
Test name
Test status
Simulation time 25713372546 ps
CPU time 13.94 seconds
Started Aug 12 05:37:17 PM PDT 24
Finished Aug 12 05:37:31 PM PDT 24
Peak memory 223456 kb
Host smart-a709176b-108f-4645-9de7-bddf9eb288df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1136678504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1136678504
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4242574123
Short name T170
Test name
Test status
Simulation time 92815382 ps
CPU time 0.96 seconds
Started Aug 12 05:37:15 PM PDT 24
Finished Aug 12 05:37:16 PM PDT 24
Peak memory 207492 kb
Host smart-9070efe3-ba49-4d6e-8834-38babf5d980d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242574123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4242574123
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.542544729
Short name T317
Test name
Test status
Simulation time 2403583465 ps
CPU time 8.3 seconds
Started Aug 12 05:37:21 PM PDT 24
Finished Aug 12 05:37:29 PM PDT 24
Peak memory 216620 kb
Host smart-1fd17429-a761-4b5f-ad2a-cd5db3f0bff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542544729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.542544729
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4088444148
Short name T1
Test name
Test status
Simulation time 15128117174 ps
CPU time 11.16 seconds
Started Aug 12 05:37:17 PM PDT 24
Finished Aug 12 05:37:29 PM PDT 24
Peak memory 216468 kb
Host smart-ca55042b-6537-4357-8fda-a14d12a4d7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088444148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4088444148
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1481624107
Short name T406
Test name
Test status
Simulation time 65816078 ps
CPU time 1.29 seconds
Started Aug 12 05:37:15 PM PDT 24
Finished Aug 12 05:37:17 PM PDT 24
Peak memory 208072 kb
Host smart-c789f374-fff0-4d9d-bfb1-17ff04ab9072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481624107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1481624107
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.185084957
Short name T780
Test name
Test status
Simulation time 27375468 ps
CPU time 0.75 seconds
Started Aug 12 05:37:22 PM PDT 24
Finished Aug 12 05:37:23 PM PDT 24
Peak memory 206016 kb
Host smart-cd5cbca5-4ef2-4b68-a293-a2febb78e35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185084957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.185084957
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.246194535
Short name T557
Test name
Test status
Simulation time 2290957325 ps
CPU time 10.13 seconds
Started Aug 12 05:37:48 PM PDT 24
Finished Aug 12 05:37:58 PM PDT 24
Peak memory 239628 kb
Host smart-b45e975e-ecf0-4b43-808f-9744cce43812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246194535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.246194535
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4269339827
Short name T892
Test name
Test status
Simulation time 142530792 ps
CPU time 0.69 seconds
Started Aug 12 05:37:30 PM PDT 24
Finished Aug 12 05:37:31 PM PDT 24
Peak memory 204704 kb
Host smart-90e002cf-4bf1-45af-9e70-2559ba4d5399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269339827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4269339827
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1333754616
Short name T693
Test name
Test status
Simulation time 3975292935 ps
CPU time 24.55 seconds
Started Aug 12 05:37:46 PM PDT 24
Finished Aug 12 05:38:11 PM PDT 24
Peak memory 240552 kb
Host smart-82b0cb3c-8325-46e6-b5ec-7dc3aea41a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333754616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1333754616
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1740551323
Short name T1019
Test name
Test status
Simulation time 45292847 ps
CPU time 0.76 seconds
Started Aug 12 05:37:18 PM PDT 24
Finished Aug 12 05:37:19 PM PDT 24
Peak memory 205660 kb
Host smart-85a83cc2-fdfe-4eb6-97b0-480d0ee7531a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740551323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1740551323
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3430537546
Short name T870
Test name
Test status
Simulation time 50305133 ps
CPU time 0.75 seconds
Started Aug 12 05:37:32 PM PDT 24
Finished Aug 12 05:37:33 PM PDT 24
Peak memory 215896 kb
Host smart-d2775d0b-a3ef-43cc-b9d7-43474e349980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430537546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3430537546
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.780046203
Short name T725
Test name
Test status
Simulation time 9437819687 ps
CPU time 70.68 seconds
Started Aug 12 05:37:26 PM PDT 24
Finished Aug 12 05:38:37 PM PDT 24
Peak memory 223300 kb
Host smart-80474e45-0391-4281-9c57-44958909fb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780046203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.780046203
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4076187125
Short name T233
Test name
Test status
Simulation time 7578829333 ps
CPU time 39.39 seconds
Started Aug 12 05:37:51 PM PDT 24
Finished Aug 12 05:38:31 PM PDT 24
Peak memory 240428 kb
Host smart-75f50551-9ea3-4849-bd0e-0c27f9eab0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076187125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4076187125
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2071461728
Short name T644
Test name
Test status
Simulation time 919424651 ps
CPU time 13.76 seconds
Started Aug 12 05:37:37 PM PDT 24
Finished Aug 12 05:37:50 PM PDT 24
Peak memory 233060 kb
Host smart-5b4f2acc-8d42-4345-83d8-1d8f3c85a44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071461728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2071461728
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3420025488
Short name T67
Test name
Test status
Simulation time 8718261348 ps
CPU time 14.32 seconds
Started Aug 12 05:37:28 PM PDT 24
Finished Aug 12 05:37:43 PM PDT 24
Peak memory 234048 kb
Host smart-d39c9e8d-4134-41c1-8167-38614b0947b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420025488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3420025488
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.926692769
Short name T373
Test name
Test status
Simulation time 59908692 ps
CPU time 2.44 seconds
Started Aug 12 05:37:30 PM PDT 24
Finished Aug 12 05:37:33 PM PDT 24
Peak memory 226880 kb
Host smart-d184349d-18b4-404b-9e14-055680f08c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926692769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.926692769
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3333844734
Short name T903
Test name
Test status
Simulation time 794447708 ps
CPU time 12.1 seconds
Started Aug 12 05:37:45 PM PDT 24
Finished Aug 12 05:37:57 PM PDT 24
Peak memory 232764 kb
Host smart-64fb8720-eaea-4a7c-b460-c6ae42ae04c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333844734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3333844734
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1720792500
Short name T990
Test name
Test status
Simulation time 672732625 ps
CPU time 6.45 seconds
Started Aug 12 05:37:29 PM PDT 24
Finished Aug 12 05:37:36 PM PDT 24
Peak memory 240988 kb
Host smart-0624cd91-79d8-42cf-a00f-da5975e5b5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720792500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1720792500
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1639852930
Short name T409
Test name
Test status
Simulation time 2033290141 ps
CPU time 10.92 seconds
Started Aug 12 05:37:25 PM PDT 24
Finished Aug 12 05:37:36 PM PDT 24
Peak memory 237124 kb
Host smart-57e74fea-0958-4023-ac7a-56c4f5b23f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639852930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1639852930
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2365677656
Short name T475
Test name
Test status
Simulation time 623698292 ps
CPU time 3.68 seconds
Started Aug 12 05:37:35 PM PDT 24
Finished Aug 12 05:37:39 PM PDT 24
Peak memory 219112 kb
Host smart-dea5dae1-e6c3-4008-9215-95bd2b13ad44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2365677656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2365677656
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1601714805
Short name T687
Test name
Test status
Simulation time 825782343 ps
CPU time 0.93 seconds
Started Aug 12 05:37:46 PM PDT 24
Finished Aug 12 05:37:47 PM PDT 24
Peak memory 207428 kb
Host smart-e0cd769f-61ae-45d8-9e1e-f2884f5d3ee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601714805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1601714805
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1016709021
Short name T430
Test name
Test status
Simulation time 6863277644 ps
CPU time 23.82 seconds
Started Aug 12 05:37:48 PM PDT 24
Finished Aug 12 05:38:12 PM PDT 24
Peak memory 216816 kb
Host smart-fdc45e0b-b4ee-4dca-b367-2d50603bf49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016709021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1016709021
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4166766381
Short name T714
Test name
Test status
Simulation time 5245955321 ps
CPU time 14.33 seconds
Started Aug 12 05:37:30 PM PDT 24
Finished Aug 12 05:37:45 PM PDT 24
Peak memory 216472 kb
Host smart-5e34092e-cd82-4ef9-9e93-c364c526e851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166766381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4166766381
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1463531327
Short name T511
Test name
Test status
Simulation time 35656235 ps
CPU time 0.73 seconds
Started Aug 12 05:37:18 PM PDT 24
Finished Aug 12 05:37:19 PM PDT 24
Peak memory 205572 kb
Host smart-10090d58-dfd3-4f7e-bcd9-45bc0df5308b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463531327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1463531327
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.964789375
Short name T361
Test name
Test status
Simulation time 26772488 ps
CPU time 0.79 seconds
Started Aug 12 05:37:35 PM PDT 24
Finished Aug 12 05:37:36 PM PDT 24
Peak memory 206028 kb
Host smart-03cad08e-ede0-4c27-8f15-d91abc33fc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964789375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.964789375
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3072293163
Short name T59
Test name
Test status
Simulation time 2340408750 ps
CPU time 8.96 seconds
Started Aug 12 05:37:37 PM PDT 24
Finished Aug 12 05:37:46 PM PDT 24
Peak memory 235220 kb
Host smart-72edf424-1c9b-421f-a1a3-a98d26413046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072293163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3072293163
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1956049294
Short name T71
Test name
Test status
Simulation time 16558533 ps
CPU time 0.74 seconds
Started Aug 12 05:37:51 PM PDT 24
Finished Aug 12 05:37:52 PM PDT 24
Peak memory 204760 kb
Host smart-779fd815-17c0-4569-a1be-e1e04bd53126
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956049294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1956049294
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2541605090
Short name T425
Test name
Test status
Simulation time 208898436 ps
CPU time 5.44 seconds
Started Aug 12 05:37:30 PM PDT 24
Finished Aug 12 05:37:35 PM PDT 24
Peak memory 224728 kb
Host smart-75bfdc04-9a38-4193-a0cf-22cb40709c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541605090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2541605090
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.4224914084
Short name T939
Test name
Test status
Simulation time 57678335 ps
CPU time 0.76 seconds
Started Aug 12 05:37:30 PM PDT 24
Finished Aug 12 05:37:31 PM PDT 24
Peak memory 205432 kb
Host smart-9dc09395-e0f9-4a5b-9164-8518fa7e6eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224914084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.4224914084
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.297698531
Short name T503
Test name
Test status
Simulation time 9418240554 ps
CPU time 23.8 seconds
Started Aug 12 05:37:41 PM PDT 24
Finished Aug 12 05:38:05 PM PDT 24
Peak memory 249356 kb
Host smart-c2e4f19d-d055-47b1-a724-12362625ff66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297698531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.297698531
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3423836310
Short name T509
Test name
Test status
Simulation time 3052925454 ps
CPU time 16.01 seconds
Started Aug 12 05:37:35 PM PDT 24
Finished Aug 12 05:37:51 PM PDT 24
Peak memory 218040 kb
Host smart-399228d6-2007-4492-9f8c-34431b9162bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423836310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3423836310
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.236469460
Short name T111
Test name
Test status
Simulation time 5404254668 ps
CPU time 81.96 seconds
Started Aug 12 05:37:50 PM PDT 24
Finished Aug 12 05:39:12 PM PDT 24
Peak memory 257616 kb
Host smart-737cdb34-9b79-4494-a62b-f968cac0b6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236469460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.236469460
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2689972823
Short name T1014
Test name
Test status
Simulation time 3014989985 ps
CPU time 8.08 seconds
Started Aug 12 05:37:31 PM PDT 24
Finished Aug 12 05:37:39 PM PDT 24
Peak memory 224756 kb
Host smart-4e6dea6f-f806-4fb3-82fb-0988fd4e161c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689972823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2689972823
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.292976961
Short name T833
Test name
Test status
Simulation time 423989498 ps
CPU time 0.93 seconds
Started Aug 12 05:37:20 PM PDT 24
Finished Aug 12 05:37:21 PM PDT 24
Peak memory 216092 kb
Host smart-14f5fdfc-d974-4836-b4cc-e113f8738719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292976961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.292976961
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.652966283
Short name T890
Test name
Test status
Simulation time 13162945234 ps
CPU time 28.12 seconds
Started Aug 12 05:37:29 PM PDT 24
Finished Aug 12 05:37:57 PM PDT 24
Peak memory 229580 kb
Host smart-d3042c2d-f520-4e89-b554-4aea2f5a61f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652966283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.652966283
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.170277077
Short name T13
Test name
Test status
Simulation time 16849148761 ps
CPU time 77.83 seconds
Started Aug 12 05:37:35 PM PDT 24
Finished Aug 12 05:38:53 PM PDT 24
Peak memory 241160 kb
Host smart-dbfea5fd-b03e-436d-a109-8477f2e6db54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170277077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.170277077
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.655408478
Short name T295
Test name
Test status
Simulation time 20475423202 ps
CPU time 12.53 seconds
Started Aug 12 05:37:33 PM PDT 24
Finished Aug 12 05:37:46 PM PDT 24
Peak memory 249356 kb
Host smart-d94e0495-0409-48a2-a203-3c5ac29ecb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655408478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.655408478
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2022324054
Short name T910
Test name
Test status
Simulation time 8933807042 ps
CPU time 20.08 seconds
Started Aug 12 05:37:34 PM PDT 24
Finished Aug 12 05:37:54 PM PDT 24
Peak memory 240232 kb
Host smart-0ac2bcea-4999-4766-9680-e2b90baab9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022324054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2022324054
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3228105353
Short name T1026
Test name
Test status
Simulation time 2324292118 ps
CPU time 6.08 seconds
Started Aug 12 05:37:38 PM PDT 24
Finished Aug 12 05:37:44 PM PDT 24
Peak memory 223208 kb
Host smart-56f5a971-ead9-4f18-8a01-ab7484e12066
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3228105353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3228105353
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2568821932
Short name T813
Test name
Test status
Simulation time 122192380182 ps
CPU time 274.06 seconds
Started Aug 12 05:37:54 PM PDT 24
Finished Aug 12 05:42:28 PM PDT 24
Peak memory 256696 kb
Host smart-ef1e0d8d-5f67-481c-856a-98028b84f303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568821932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2568821932
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4087615860
Short name T388
Test name
Test status
Simulation time 637795604 ps
CPU time 10.63 seconds
Started Aug 12 05:37:30 PM PDT 24
Finished Aug 12 05:37:41 PM PDT 24
Peak memory 219812 kb
Host smart-49a69235-283f-435a-b301-020b6428ac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087615860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4087615860
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.156546614
Short name T350
Test name
Test status
Simulation time 691601322 ps
CPU time 4.53 seconds
Started Aug 12 05:37:22 PM PDT 24
Finished Aug 12 05:37:26 PM PDT 24
Peak memory 216192 kb
Host smart-d6b4fd0c-6351-4882-99ff-515344383813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156546614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.156546614
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2396515104
Short name T881
Test name
Test status
Simulation time 569958000 ps
CPU time 4.28 seconds
Started Aug 12 05:37:27 PM PDT 24
Finished Aug 12 05:37:31 PM PDT 24
Peak memory 216412 kb
Host smart-9637dc5c-d0c1-4d6e-9725-9a4502a49619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396515104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2396515104
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3879465951
Short name T22
Test name
Test status
Simulation time 111815309 ps
CPU time 0.83 seconds
Started Aug 12 05:37:22 PM PDT 24
Finished Aug 12 05:37:23 PM PDT 24
Peak memory 206044 kb
Host smart-55ab7db5-e7fe-495e-a441-084d0f793c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879465951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3879465951
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.76963424
Short name T868
Test name
Test status
Simulation time 2102511071 ps
CPU time 5.5 seconds
Started Aug 12 05:37:29 PM PDT 24
Finished Aug 12 05:37:35 PM PDT 24
Peak memory 232888 kb
Host smart-c00d89b9-f433-4bd8-aadc-ad2f65ec2612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76963424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.76963424
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3680798389
Short name T171
Test name
Test status
Simulation time 23587477 ps
CPU time 0.73 seconds
Started Aug 12 05:37:33 PM PDT 24
Finished Aug 12 05:37:33 PM PDT 24
Peak memory 204652 kb
Host smart-a70bec93-a3fe-4120-999b-2170bc9402b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680798389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3680798389
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1330545995
Short name T441
Test name
Test status
Simulation time 1385404741 ps
CPU time 16.86 seconds
Started Aug 12 05:37:52 PM PDT 24
Finished Aug 12 05:38:10 PM PDT 24
Peak memory 224588 kb
Host smart-35334165-3e3b-4dd9-88ac-0231b6e79565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330545995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1330545995
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3470983869
Short name T962
Test name
Test status
Simulation time 64381926 ps
CPU time 0.77 seconds
Started Aug 12 05:37:23 PM PDT 24
Finished Aug 12 05:37:24 PM PDT 24
Peak memory 205816 kb
Host smart-2977d39f-757b-4095-8c0b-b5d6dd61897e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470983869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3470983869
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2374774001
Short name T1025
Test name
Test status
Simulation time 1554436286 ps
CPU time 31.43 seconds
Started Aug 12 05:37:32 PM PDT 24
Finished Aug 12 05:38:04 PM PDT 24
Peak memory 249216 kb
Host smart-b0f48e4f-d0d0-4d3b-a08a-933defecdd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374774001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2374774001
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.876755644
Short name T55
Test name
Test status
Simulation time 763383459 ps
CPU time 21.73 seconds
Started Aug 12 05:37:38 PM PDT 24
Finished Aug 12 05:38:00 PM PDT 24
Peak memory 246620 kb
Host smart-d7b176a7-e4d2-4d0f-8ea6-618a2f6f456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876755644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.876755644
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.5363639
Short name T248
Test name
Test status
Simulation time 4344704524 ps
CPU time 41.8 seconds
Started Aug 12 05:37:32 PM PDT 24
Finished Aug 12 05:38:14 PM PDT 24
Peak memory 253752 kb
Host smart-262e87cb-cc74-438b-8e88-2475de6bc462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5363639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.5363639
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.527860929
Short name T182
Test name
Test status
Simulation time 1733469656 ps
CPU time 20.67 seconds
Started Aug 12 05:37:51 PM PDT 24
Finished Aug 12 05:38:12 PM PDT 24
Peak memory 224700 kb
Host smart-fdbdb5cf-7bce-4405-9577-8d1c2126a352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527860929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.527860929
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2290740866
Short name T216
Test name
Test status
Simulation time 3688037519 ps
CPU time 45.53 seconds
Started Aug 12 05:37:30 PM PDT 24
Finished Aug 12 05:38:16 PM PDT 24
Peak memory 249584 kb
Host smart-232bbdf6-14d1-4b0a-8df9-62c89c129365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290740866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2290740866
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1946940664
Short name T287
Test name
Test status
Simulation time 210949470 ps
CPU time 5.07 seconds
Started Aug 12 05:37:27 PM PDT 24
Finished Aug 12 05:37:32 PM PDT 24
Peak memory 232824 kb
Host smart-07333d5c-9e51-4293-9443-a253ad9ac1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946940664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1946940664
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.513923968
Short name T859
Test name
Test status
Simulation time 801394925 ps
CPU time 8.39 seconds
Started Aug 12 05:37:39 PM PDT 24
Finished Aug 12 05:37:48 PM PDT 24
Peak memory 224684 kb
Host smart-9ccd905d-54cd-4e72-aac7-c6c11ce0047a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513923968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.513923968
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1446295782
Short name T473
Test name
Test status
Simulation time 80586321696 ps
CPU time 50.45 seconds
Started Aug 12 05:37:40 PM PDT 24
Finished Aug 12 05:38:30 PM PDT 24
Peak memory 232844 kb
Host smart-0310becb-7d24-4716-a7a3-5123abdbafed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446295782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1446295782
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2947143454
Short name T909
Test name
Test status
Simulation time 2763095664 ps
CPU time 7.23 seconds
Started Aug 12 05:37:30 PM PDT 24
Finished Aug 12 05:37:38 PM PDT 24
Peak memory 232976 kb
Host smart-a001a014-dcb5-4aea-a020-34465e3f30e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947143454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2947143454
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.568761489
Short name T161
Test name
Test status
Simulation time 228374938 ps
CPU time 3.67 seconds
Started Aug 12 05:37:29 PM PDT 24
Finished Aug 12 05:37:33 PM PDT 24
Peak memory 218832 kb
Host smart-00bc4128-fb18-4fc9-8c28-20427aca2494
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=568761489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.568761489
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3998470988
Short name T715
Test name
Test status
Simulation time 227166288 ps
CPU time 1.08 seconds
Started Aug 12 05:37:48 PM PDT 24
Finished Aug 12 05:38:00 PM PDT 24
Peak memory 217280 kb
Host smart-7ab01937-7d0f-446d-8eb1-c8a2056b3d7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998470988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3998470988
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4115448114
Short name T313
Test name
Test status
Simulation time 384420173 ps
CPU time 3.54 seconds
Started Aug 12 05:37:34 PM PDT 24
Finished Aug 12 05:37:38 PM PDT 24
Peak memory 216504 kb
Host smart-6811866b-e517-4fc1-8555-ffc68905d537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115448114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4115448114
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.95822402
Short name T958
Test name
Test status
Simulation time 13876600927 ps
CPU time 13.07 seconds
Started Aug 12 05:37:41 PM PDT 24
Finished Aug 12 05:37:54 PM PDT 24
Peak memory 217600 kb
Host smart-ecb734ee-080f-487b-beab-84e95fcd963f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95822402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.95822402
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2440874513
Short name T439
Test name
Test status
Simulation time 35897413 ps
CPU time 0.87 seconds
Started Aug 12 05:37:49 PM PDT 24
Finished Aug 12 05:37:50 PM PDT 24
Peak memory 207096 kb
Host smart-13bc78cf-d5c6-48a4-a955-f1aed68d58fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440874513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2440874513
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.751926122
Short name T956
Test name
Test status
Simulation time 156331285 ps
CPU time 1.14 seconds
Started Aug 12 05:37:31 PM PDT 24
Finished Aug 12 05:37:32 PM PDT 24
Peak memory 207192 kb
Host smart-629f59a9-aff4-495d-a892-8b36555c6207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751926122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.751926122
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.885683772
Short name T846
Test name
Test status
Simulation time 6922006185 ps
CPU time 11.85 seconds
Started Aug 12 05:37:26 PM PDT 24
Finished Aug 12 05:37:38 PM PDT 24
Peak memory 232956 kb
Host smart-3cc62e0e-e621-4524-8a60-1029bd35922b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885683772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.885683772
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2846921334
Short name T1023
Test name
Test status
Simulation time 11341700 ps
CPU time 0.72 seconds
Started Aug 12 05:37:36 PM PDT 24
Finished Aug 12 05:37:37 PM PDT 24
Peak memory 205284 kb
Host smart-9991f898-f811-485c-b382-8c6a28ec364c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846921334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2846921334
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2457098099
Short name T597
Test name
Test status
Simulation time 243442082 ps
CPU time 4.22 seconds
Started Aug 12 05:37:51 PM PDT 24
Finished Aug 12 05:37:55 PM PDT 24
Peak memory 232892 kb
Host smart-dc93ef43-57ca-4fed-b498-5d93736a366b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457098099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2457098099
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3316912265
Short name T935
Test name
Test status
Simulation time 24826847 ps
CPU time 0.72 seconds
Started Aug 12 05:37:34 PM PDT 24
Finished Aug 12 05:37:35 PM PDT 24
Peak memory 206528 kb
Host smart-71658f2e-ea8a-49ee-a19c-dfa9eee94c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316912265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3316912265
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2072311714
Short name T856
Test name
Test status
Simulation time 137275429728 ps
CPU time 196.45 seconds
Started Aug 12 05:37:42 PM PDT 24
Finished Aug 12 05:40:59 PM PDT 24
Peak memory 250460 kb
Host smart-2650b05a-011b-4f0e-adb1-51a94220e5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072311714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2072311714
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.803090110
Short name T637
Test name
Test status
Simulation time 21734763286 ps
CPU time 154.68 seconds
Started Aug 12 05:37:55 PM PDT 24
Finished Aug 12 05:40:30 PM PDT 24
Peak memory 250184 kb
Host smart-4f338d6b-f4c4-4825-99b8-ff9e8cd56666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803090110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.803090110
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2703166515
Short name T522
Test name
Test status
Simulation time 2398350688 ps
CPU time 31.66 seconds
Started Aug 12 05:37:54 PM PDT 24
Finished Aug 12 05:38:26 PM PDT 24
Peak memory 255080 kb
Host smart-d4b09f32-8665-4fbb-b3c7-a75beb027482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703166515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2703166515
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3434385605
Short name T191
Test name
Test status
Simulation time 520233103 ps
CPU time 11.34 seconds
Started Aug 12 05:37:45 PM PDT 24
Finished Aug 12 05:37:57 PM PDT 24
Peak memory 236184 kb
Host smart-7597f199-6b95-4d7c-9cf8-7ce8cd6e3bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434385605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3434385605
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1331358810
Short name T562
Test name
Test status
Simulation time 99098138825 ps
CPU time 223.89 seconds
Started Aug 12 05:37:32 PM PDT 24
Finished Aug 12 05:41:16 PM PDT 24
Peak memory 253588 kb
Host smart-6e13776a-999d-4aaa-ad96-e577f8a41a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331358810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1331358810
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2256688981
Short name T872
Test name
Test status
Simulation time 1315918605 ps
CPU time 8.17 seconds
Started Aug 12 05:37:39 PM PDT 24
Finished Aug 12 05:37:47 PM PDT 24
Peak memory 232936 kb
Host smart-19aa4d9f-1ccb-48c5-a78f-cbb883e0f54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256688981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2256688981
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.772886159
Short name T719
Test name
Test status
Simulation time 7652923017 ps
CPU time 18.11 seconds
Started Aug 12 05:37:56 PM PDT 24
Finished Aug 12 05:38:15 PM PDT 24
Peak memory 235072 kb
Host smart-bcc39fdf-579a-455f-81b6-845398f73ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772886159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.772886159
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1956504713
Short name T307
Test name
Test status
Simulation time 1458143522 ps
CPU time 8.86 seconds
Started Aug 12 05:37:57 PM PDT 24
Finished Aug 12 05:38:06 PM PDT 24
Peak memory 240924 kb
Host smart-08584fc9-c5db-4a22-9af6-249f39eed0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956504713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1956504713
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.696700475
Short name T266
Test name
Test status
Simulation time 11453011968 ps
CPU time 11.83 seconds
Started Aug 12 05:37:31 PM PDT 24
Finished Aug 12 05:37:48 PM PDT 24
Peak memory 232936 kb
Host smart-8fac720d-3c49-4bdb-a63c-aba54777cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696700475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.696700475
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1760581707
Short name T502
Test name
Test status
Simulation time 7988720307 ps
CPU time 5.9 seconds
Started Aug 12 05:37:49 PM PDT 24
Finished Aug 12 05:37:55 PM PDT 24
Peak memory 220416 kb
Host smart-7f80b614-7a39-453c-a09f-31745f43c686
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1760581707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1760581707
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.381832171
Short name T645
Test name
Test status
Simulation time 30826074341 ps
CPU time 143.04 seconds
Started Aug 12 05:37:35 PM PDT 24
Finished Aug 12 05:39:58 PM PDT 24
Peak memory 249400 kb
Host smart-72b053ec-9507-4bcc-ad1b-4117e39fe7de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381832171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.381832171
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4039089973
Short name T653
Test name
Test status
Simulation time 2803159995 ps
CPU time 25.59 seconds
Started Aug 12 05:37:54 PM PDT 24
Finished Aug 12 05:38:20 PM PDT 24
Peak memory 216460 kb
Host smart-d3a18917-90d6-4ee3-9bf0-83fec96dfd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039089973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4039089973
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.515264333
Short name T717
Test name
Test status
Simulation time 5558113662 ps
CPU time 8.41 seconds
Started Aug 12 05:37:32 PM PDT 24
Finished Aug 12 05:37:40 PM PDT 24
Peak memory 216400 kb
Host smart-2997e2eb-1f17-40ce-9036-f6d7cee70de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515264333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.515264333
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2581050218
Short name T56
Test name
Test status
Simulation time 111496368 ps
CPU time 1.41 seconds
Started Aug 12 05:37:32 PM PDT 24
Finished Aug 12 05:37:33 PM PDT 24
Peak memory 216428 kb
Host smart-c30a9e89-25d9-4351-9980-4cf2bfe99b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581050218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2581050218
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1751073641
Short name T485
Test name
Test status
Simulation time 202824198 ps
CPU time 0.87 seconds
Started Aug 12 05:37:43 PM PDT 24
Finished Aug 12 05:37:44 PM PDT 24
Peak memory 206028 kb
Host smart-641980c3-ff93-4fd6-b748-e0361210f71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751073641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1751073641
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1880978861
Short name T628
Test name
Test status
Simulation time 710760008 ps
CPU time 5.42 seconds
Started Aug 12 05:37:35 PM PDT 24
Finished Aug 12 05:37:40 PM PDT 24
Peak memory 232840 kb
Host smart-ffe289bf-a49d-4400-bfac-4ac144c61475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880978861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1880978861
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2288843322
Short name T576
Test name
Test status
Simulation time 26473326 ps
CPU time 0.71 seconds
Started Aug 12 05:37:30 PM PDT 24
Finished Aug 12 05:37:31 PM PDT 24
Peak memory 205224 kb
Host smart-d028a135-28f1-401d-968f-8f61341e64a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288843322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2288843322
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1049254363
Short name T1001
Test name
Test status
Simulation time 802771886 ps
CPU time 3.66 seconds
Started Aug 12 05:37:45 PM PDT 24
Finished Aug 12 05:37:49 PM PDT 24
Peak memory 224680 kb
Host smart-64f60661-c0db-40b1-9791-8b548b5c7781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049254363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1049254363
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2806612402
Short name T539
Test name
Test status
Simulation time 67884713 ps
CPU time 0.82 seconds
Started Aug 12 05:37:55 PM PDT 24
Finished Aug 12 05:37:56 PM PDT 24
Peak memory 206520 kb
Host smart-ddd09cdd-fec3-4f48-bb17-bff7fd6a81a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806612402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2806612402
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.412161697
Short name T668
Test name
Test status
Simulation time 55648083545 ps
CPU time 203.98 seconds
Started Aug 12 05:37:37 PM PDT 24
Finished Aug 12 05:41:01 PM PDT 24
Peak memory 266808 kb
Host smart-354aa837-e511-425e-ac8e-4789db197d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412161697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.412161697
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1055373365
Short name T81
Test name
Test status
Simulation time 30011549397 ps
CPU time 173.95 seconds
Started Aug 12 05:37:41 PM PDT 24
Finished Aug 12 05:40:35 PM PDT 24
Peak memory 249428 kb
Host smart-83740c85-17e6-4f0a-918d-773d2ee636a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055373365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1055373365
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3345960264
Short name T816
Test name
Test status
Simulation time 15604489880 ps
CPU time 47.26 seconds
Started Aug 12 05:37:49 PM PDT 24
Finished Aug 12 05:38:42 PM PDT 24
Peak memory 239288 kb
Host smart-fd975e09-84a7-4945-85c3-fbeca25fcf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345960264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3345960264
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2751265078
Short name T145
Test name
Test status
Simulation time 8370317595 ps
CPU time 24.8 seconds
Started Aug 12 05:37:35 PM PDT 24
Finished Aug 12 05:38:00 PM PDT 24
Peak memory 236948 kb
Host smart-d6eb914d-cac2-4eb3-9634-7c76af172674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751265078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2751265078
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3765256982
Short name T563
Test name
Test status
Simulation time 6930111069 ps
CPU time 39.91 seconds
Started Aug 12 05:37:35 PM PDT 24
Finished Aug 12 05:38:15 PM PDT 24
Peak memory 249288 kb
Host smart-417bf8e1-2242-417f-8958-38a4a93caed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765256982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3765256982
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3011969094
Short name T83
Test name
Test status
Simulation time 724356806 ps
CPU time 2.91 seconds
Started Aug 12 05:37:36 PM PDT 24
Finished Aug 12 05:37:44 PM PDT 24
Peak memory 224676 kb
Host smart-2e91c547-cc85-49bd-94c2-c80962cd509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011969094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3011969094
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.852393660
Short name T950
Test name
Test status
Simulation time 10646268244 ps
CPU time 40.37 seconds
Started Aug 12 05:37:35 PM PDT 24
Finished Aug 12 05:38:16 PM PDT 24
Peak memory 237424 kb
Host smart-ed85200e-97f1-4a34-8ede-eaeffc509ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852393660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.852393660
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.153893919
Short name T898
Test name
Test status
Simulation time 211942253 ps
CPU time 2.35 seconds
Started Aug 12 05:37:47 PM PDT 24
Finished Aug 12 05:37:49 PM PDT 24
Peak memory 223280 kb
Host smart-49d892ff-a886-44ea-b831-80b900903b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153893919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.153893919
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.882735969
Short name T378
Test name
Test status
Simulation time 329223141 ps
CPU time 3.37 seconds
Started Aug 12 05:37:34 PM PDT 24
Finished Aug 12 05:37:38 PM PDT 24
Peak memory 232892 kb
Host smart-138da61e-7ccc-4db0-8c2f-265c3762ef8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882735969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.882735969
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3199641191
Short name T100
Test name
Test status
Simulation time 1686224265 ps
CPU time 6.15 seconds
Started Aug 12 05:37:34 PM PDT 24
Finished Aug 12 05:37:40 PM PDT 24
Peak memory 219164 kb
Host smart-3c2471fa-481f-4e51-b25a-c5fa219f0119
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3199641191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3199641191
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2358859704
Short name T379
Test name
Test status
Simulation time 1064947245 ps
CPU time 1.14 seconds
Started Aug 12 05:37:45 PM PDT 24
Finished Aug 12 05:37:47 PM PDT 24
Peak memory 207204 kb
Host smart-0e3e28f4-fca9-4131-a9d1-78002fc8a6cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358859704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2358859704
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.250197968
Short name T948
Test name
Test status
Simulation time 1725213007 ps
CPU time 10.54 seconds
Started Aug 12 05:37:33 PM PDT 24
Finished Aug 12 05:37:44 PM PDT 24
Peak memory 216376 kb
Host smart-a2f48b41-6d72-4a82-b020-6221175cbed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250197968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.250197968
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.145798826
Short name T357
Test name
Test status
Simulation time 5575393528 ps
CPU time 15.26 seconds
Started Aug 12 05:37:50 PM PDT 24
Finished Aug 12 05:38:05 PM PDT 24
Peak memory 216496 kb
Host smart-352e4a85-4139-4597-9323-9ea38adc12d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145798826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.145798826
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.599035055
Short name T921
Test name
Test status
Simulation time 16357117 ps
CPU time 0.75 seconds
Started Aug 12 05:37:51 PM PDT 24
Finished Aug 12 05:37:52 PM PDT 24
Peak memory 206040 kb
Host smart-900a6eae-ca47-48df-a6a9-f181f2abf790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599035055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.599035055
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3350974632
Short name T671
Test name
Test status
Simulation time 34826521 ps
CPU time 0.7 seconds
Started Aug 12 05:37:38 PM PDT 24
Finished Aug 12 05:37:39 PM PDT 24
Peak memory 205496 kb
Host smart-167b4ac5-1380-4529-8f45-3c24237fc72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350974632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3350974632
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1306174337
Short name T560
Test name
Test status
Simulation time 682808761 ps
CPU time 6.35 seconds
Started Aug 12 05:37:34 PM PDT 24
Finished Aug 12 05:37:41 PM PDT 24
Peak memory 224724 kb
Host smart-0647b3e2-7114-41a6-9563-2359d2448569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306174337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1306174337
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.331773230
Short name T949
Test name
Test status
Simulation time 12876456 ps
CPU time 0.7 seconds
Started Aug 12 05:37:38 PM PDT 24
Finished Aug 12 05:37:39 PM PDT 24
Peak memory 204728 kb
Host smart-95b009d5-94da-47e0-a01b-79a031c3bd40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331773230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.331773230
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3352678484
Short name T340
Test name
Test status
Simulation time 1903574072 ps
CPU time 13.29 seconds
Started Aug 12 05:37:33 PM PDT 24
Finished Aug 12 05:37:46 PM PDT 24
Peak memory 224720 kb
Host smart-2fe6b251-9ef8-4f6a-940b-ad388cce1b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352678484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3352678484
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.817077852
Short name T172
Test name
Test status
Simulation time 87591765 ps
CPU time 0.82 seconds
Started Aug 12 05:37:57 PM PDT 24
Finished Aug 12 05:38:03 PM PDT 24
Peak memory 206496 kb
Host smart-f6543afc-7afa-4f64-a225-eb62ab2aa5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817077852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.817077852
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.221969323
Short name T221
Test name
Test status
Simulation time 166415826886 ps
CPU time 288.4 seconds
Started Aug 12 05:37:49 PM PDT 24
Finished Aug 12 05:42:38 PM PDT 24
Peak memory 265160 kb
Host smart-070aea82-5339-4450-a0fb-6464458a75e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221969323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.221969323
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1849987221
Short name T753
Test name
Test status
Simulation time 21072218606 ps
CPU time 29.04 seconds
Started Aug 12 05:37:35 PM PDT 24
Finished Aug 12 05:38:04 PM PDT 24
Peak memory 217892 kb
Host smart-2be8d297-8dbe-4a1e-a643-1263ea68dd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849987221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1849987221
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1671510938
Short name T735
Test name
Test status
Simulation time 21291065988 ps
CPU time 85.04 seconds
Started Aug 12 05:37:51 PM PDT 24
Finished Aug 12 05:39:16 PM PDT 24
Peak memory 255700 kb
Host smart-0107b5c6-12ad-4e1a-ac52-2980097a4064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671510938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1671510938
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1852901839
Short name T1036
Test name
Test status
Simulation time 622878126 ps
CPU time 10.6 seconds
Started Aug 12 05:37:42 PM PDT 24
Finished Aug 12 05:37:53 PM PDT 24
Peak memory 234912 kb
Host smart-b9239788-ef2d-4363-8a5d-e71037210e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852901839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1852901839
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2034105051
Short name T770
Test name
Test status
Simulation time 49355556151 ps
CPU time 110.72 seconds
Started Aug 12 05:37:53 PM PDT 24
Finished Aug 12 05:39:44 PM PDT 24
Peak memory 252048 kb
Host smart-2a64e1a1-4c05-42b4-bd16-02d3b1e2a9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034105051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2034105051
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.807510507
Short name T781
Test name
Test status
Simulation time 4652922319 ps
CPU time 10.94 seconds
Started Aug 12 05:37:46 PM PDT 24
Finished Aug 12 05:37:57 PM PDT 24
Peak memory 224732 kb
Host smart-b87768ca-668e-4e99-8318-52a066f6bb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807510507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.807510507
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.337832993
Short name T891
Test name
Test status
Simulation time 309027431 ps
CPU time 5.59 seconds
Started Aug 12 05:37:53 PM PDT 24
Finished Aug 12 05:37:59 PM PDT 24
Peak memory 224608 kb
Host smart-4fbf19fa-e79c-438f-9d57-8762a00d4f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337832993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.337832993
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3878954660
Short name T851
Test name
Test status
Simulation time 781405486 ps
CPU time 3.8 seconds
Started Aug 12 05:37:52 PM PDT 24
Finished Aug 12 05:37:57 PM PDT 24
Peak memory 232872 kb
Host smart-6b49c17a-9913-4374-8c8e-4a1798db6722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878954660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3878954660
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1858261486
Short name T227
Test name
Test status
Simulation time 3432039117 ps
CPU time 4.78 seconds
Started Aug 12 05:37:42 PM PDT 24
Finished Aug 12 05:37:47 PM PDT 24
Peak memory 232900 kb
Host smart-bf989b64-3f08-49eb-8180-e41deecc4ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858261486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1858261486
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2916021479
Short name T160
Test name
Test status
Simulation time 1256082426 ps
CPU time 9.19 seconds
Started Aug 12 05:37:31 PM PDT 24
Finished Aug 12 05:37:40 PM PDT 24
Peak memory 222216 kb
Host smart-20f21daf-cd8f-4cca-8195-117fe7c03e1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2916021479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2916021479
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2800361242
Short name T765
Test name
Test status
Simulation time 2700918258 ps
CPU time 35.56 seconds
Started Aug 12 05:37:38 PM PDT 24
Finished Aug 12 05:38:14 PM PDT 24
Peak memory 234516 kb
Host smart-8a5baf13-6252-4afc-ba58-dd3d16476d50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800361242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2800361242
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3606889018
Short name T696
Test name
Test status
Simulation time 2046375675 ps
CPU time 25.83 seconds
Started Aug 12 05:37:53 PM PDT 24
Finished Aug 12 05:38:19 PM PDT 24
Peak memory 216380 kb
Host smart-d29ef68c-1ec0-4df2-a4f8-5dee36d6a2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606889018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3606889018
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3986223852
Short name T331
Test name
Test status
Simulation time 918272209 ps
CPU time 5.15 seconds
Started Aug 12 05:37:33 PM PDT 24
Finished Aug 12 05:37:38 PM PDT 24
Peak memory 216292 kb
Host smart-3687e750-0c25-4fe5-bbee-4c050f136ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986223852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3986223852
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.84148176
Short name T877
Test name
Test status
Simulation time 87601831 ps
CPU time 1.36 seconds
Started Aug 12 05:37:35 PM PDT 24
Finished Aug 12 05:37:36 PM PDT 24
Peak memory 216424 kb
Host smart-f8719dfe-88f3-4ac6-b120-eac08e04b53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84148176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.84148176
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2555743958
Short name T98
Test name
Test status
Simulation time 457092754 ps
CPU time 0.97 seconds
Started Aug 12 05:38:02 PM PDT 24
Finished Aug 12 05:38:03 PM PDT 24
Peak memory 206952 kb
Host smart-8c7f8ca3-58b1-4377-b0f9-a8357b9cde28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555743958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2555743958
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3612445627
Short name T704
Test name
Test status
Simulation time 431540097 ps
CPU time 6.21 seconds
Started Aug 12 05:37:53 PM PDT 24
Finished Aug 12 05:37:59 PM PDT 24
Peak memory 224668 kb
Host smart-ade27d4a-1962-4a1f-8f05-59dc65a49bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612445627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3612445627
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2305351108
Short name T341
Test name
Test status
Simulation time 11844390 ps
CPU time 0.7 seconds
Started Aug 12 05:35:38 PM PDT 24
Finished Aug 12 05:35:38 PM PDT 24
Peak memory 204708 kb
Host smart-6e858f2e-9d2a-4d19-96da-b6a3ab8b9c89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305351108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
305351108
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2159631636
Short name T837
Test name
Test status
Simulation time 67732535 ps
CPU time 2.89 seconds
Started Aug 12 05:35:59 PM PDT 24
Finished Aug 12 05:36:02 PM PDT 24
Peak memory 232796 kb
Host smart-68ae9f65-8124-44d7-912c-9c786e8a218f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159631636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2159631636
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.922064489
Short name T829
Test name
Test status
Simulation time 26800213 ps
CPU time 0.76 seconds
Started Aug 12 05:35:43 PM PDT 24
Finished Aug 12 05:35:44 PM PDT 24
Peak memory 206512 kb
Host smart-4f26142d-e681-4ac0-9b4e-8f9023cf168a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922064489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.922064489
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1305775931
Short name T218
Test name
Test status
Simulation time 8814777335 ps
CPU time 108.42 seconds
Started Aug 12 05:35:23 PM PDT 24
Finished Aug 12 05:37:11 PM PDT 24
Peak memory 256480 kb
Host smart-9e012078-99d9-4d22-a35a-b3ce911b105a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305775931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1305775931
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.19240185
Short name T611
Test name
Test status
Simulation time 10048761166 ps
CPU time 39.15 seconds
Started Aug 12 05:35:48 PM PDT 24
Finished Aug 12 05:36:28 PM PDT 24
Peak memory 249388 kb
Host smart-0acb33cb-1006-4c88-9317-19989d23e30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19240185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.19240185
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.767119683
Short name T282
Test name
Test status
Simulation time 105009198070 ps
CPU time 250.58 seconds
Started Aug 12 05:35:46 PM PDT 24
Finished Aug 12 05:39:57 PM PDT 24
Peak memory 256432 kb
Host smart-39c58431-032d-4546-89ad-2fcb555a6a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767119683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
767119683
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.4110620363
Short name T187
Test name
Test status
Simulation time 376113804 ps
CPU time 4.02 seconds
Started Aug 12 05:35:42 PM PDT 24
Finished Aug 12 05:35:46 PM PDT 24
Peak memory 232876 kb
Host smart-e03063bd-4e47-4037-b8a9-6400d4a344a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110620363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.4110620363
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1477314483
Short name T983
Test name
Test status
Simulation time 85431078 ps
CPU time 3.19 seconds
Started Aug 12 05:35:50 PM PDT 24
Finished Aug 12 05:35:54 PM PDT 24
Peak memory 224624 kb
Host smart-ea0c6204-3797-4338-b3ab-940821588b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477314483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1477314483
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.4241290094
Short name T626
Test name
Test status
Simulation time 16967154363 ps
CPU time 39.12 seconds
Started Aug 12 05:35:58 PM PDT 24
Finished Aug 12 05:36:38 PM PDT 24
Peak memory 232984 kb
Host smart-eaedbe0d-586d-47e8-9646-e32673ab48c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241290094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4241290094
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1209512035
Short name T658
Test name
Test status
Simulation time 25393137 ps
CPU time 1 seconds
Started Aug 12 05:35:46 PM PDT 24
Finished Aug 12 05:35:48 PM PDT 24
Peak memory 217984 kb
Host smart-619b2172-74bd-42af-8d76-ddff1d7901c3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209512035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1209512035
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3191897060
Short name T681
Test name
Test status
Simulation time 22253067409 ps
CPU time 13.59 seconds
Started Aug 12 05:35:57 PM PDT 24
Finished Aug 12 05:36:11 PM PDT 24
Peak memory 224720 kb
Host smart-c07ffe14-fa4d-4c70-b312-0821bcae2b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191897060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3191897060
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2737942466
Short name T665
Test name
Test status
Simulation time 3665200898 ps
CPU time 12.12 seconds
Started Aug 12 05:35:53 PM PDT 24
Finished Aug 12 05:36:10 PM PDT 24
Peak memory 224748 kb
Host smart-b64811c2-5310-46aa-b80b-27b9d45a5f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737942466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2737942466
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3239196717
Short name T532
Test name
Test status
Simulation time 4158026238 ps
CPU time 5.45 seconds
Started Aug 12 05:35:54 PM PDT 24
Finished Aug 12 05:36:00 PM PDT 24
Peak memory 223108 kb
Host smart-e846cb9a-2c91-41c7-89ec-4958623a6ecb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3239196717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3239196717
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.400103605
Short name T674
Test name
Test status
Simulation time 39091041 ps
CPU time 0.96 seconds
Started Aug 12 05:35:46 PM PDT 24
Finished Aug 12 05:35:47 PM PDT 24
Peak memory 207412 kb
Host smart-75285789-7c42-4d24-af37-ed851f5cdaba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400103605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.400103605
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3489920531
Short name T585
Test name
Test status
Simulation time 2880825015 ps
CPU time 28.21 seconds
Started Aug 12 05:35:42 PM PDT 24
Finished Aug 12 05:36:10 PM PDT 24
Peak memory 216492 kb
Host smart-b596c743-3f5a-4ee1-9c3f-ab0a6d4558cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489920531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3489920531
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.384335215
Short name T362
Test name
Test status
Simulation time 1392125028 ps
CPU time 3.84 seconds
Started Aug 12 05:35:36 PM PDT 24
Finished Aug 12 05:35:40 PM PDT 24
Peak memory 216388 kb
Host smart-cfadfe20-4608-4be0-8978-4f71a8c40bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384335215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.384335215
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.227852260
Short name T352
Test name
Test status
Simulation time 27080320 ps
CPU time 0.68 seconds
Started Aug 12 05:35:26 PM PDT 24
Finished Aug 12 05:35:27 PM PDT 24
Peak memory 205544 kb
Host smart-f95037ac-1a19-4c40-9aa3-8ba099a58a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227852260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.227852260
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.89383354
Short name T322
Test name
Test status
Simulation time 132589418 ps
CPU time 0.7 seconds
Started Aug 12 05:35:51 PM PDT 24
Finished Aug 12 05:35:52 PM PDT 24
Peak memory 205568 kb
Host smart-4fa8820c-0969-4185-b175-4eb84a5cf332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89383354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.89383354
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.4066549088
Short name T285
Test name
Test status
Simulation time 1301288862 ps
CPU time 5.38 seconds
Started Aug 12 05:35:51 PM PDT 24
Finished Aug 12 05:35:56 PM PDT 24
Peak memory 224724 kb
Host smart-cc9de0e8-409b-44c7-9e7d-26996994e98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066549088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4066549088
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3676981531
Short name T1017
Test name
Test status
Simulation time 18709459 ps
CPU time 0.68 seconds
Started Aug 12 05:36:12 PM PDT 24
Finished Aug 12 05:36:13 PM PDT 24
Peak memory 204692 kb
Host smart-982e368b-2e45-49ab-aca6-80179f710a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676981531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
676981531
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1678666808
Short name T269
Test name
Test status
Simulation time 181026028 ps
CPU time 3.99 seconds
Started Aug 12 05:35:52 PM PDT 24
Finished Aug 12 05:35:56 PM PDT 24
Peak memory 232812 kb
Host smart-525e818a-cbd6-4a2d-9d82-bc0761132726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678666808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1678666808
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3277697060
Short name T599
Test name
Test status
Simulation time 282801947 ps
CPU time 0.85 seconds
Started Aug 12 05:35:51 PM PDT 24
Finished Aug 12 05:35:52 PM PDT 24
Peak memory 206504 kb
Host smart-b5d76969-c7eb-4148-ba39-9f957976799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277697060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3277697060
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.152657574
Short name T283
Test name
Test status
Simulation time 6958958864 ps
CPU time 92.32 seconds
Started Aug 12 05:35:57 PM PDT 24
Finished Aug 12 05:37:29 PM PDT 24
Peak memory 253220 kb
Host smart-d3a4046d-5adf-4848-b03f-bbaababd6770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152657574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.152657574
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2890563553
Short name T308
Test name
Test status
Simulation time 3705185362 ps
CPU time 85.95 seconds
Started Aug 12 05:35:59 PM PDT 24
Finished Aug 12 05:37:25 PM PDT 24
Peak memory 240252 kb
Host smart-e77c64ea-cee0-42e5-a524-172da32ac371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890563553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2890563553
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2337568968
Short name T314
Test name
Test status
Simulation time 59181953271 ps
CPU time 282.21 seconds
Started Aug 12 05:35:39 PM PDT 24
Finished Aug 12 05:40:22 PM PDT 24
Peak memory 255392 kb
Host smart-15c68315-a127-411c-851f-557dc943dfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337568968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2337568968
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.4283118297
Short name T698
Test name
Test status
Simulation time 9761636483 ps
CPU time 44.94 seconds
Started Aug 12 05:35:55 PM PDT 24
Finished Aug 12 05:36:40 PM PDT 24
Peak memory 255876 kb
Host smart-d1344a40-ab25-409c-bb11-b00f0ca31183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283118297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.4283118297
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2596726180
Short name T923
Test name
Test status
Simulation time 535957673 ps
CPU time 5.77 seconds
Started Aug 12 05:36:00 PM PDT 24
Finished Aug 12 05:36:06 PM PDT 24
Peak memory 232884 kb
Host smart-db383ac4-054c-428c-b77b-53e6a75411c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596726180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2596726180
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1209994345
Short name T964
Test name
Test status
Simulation time 30394560 ps
CPU time 2.36 seconds
Started Aug 12 05:35:48 PM PDT 24
Finished Aug 12 05:35:51 PM PDT 24
Peak memory 232376 kb
Host smart-4592a31f-d159-428a-ab18-604af487b6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209994345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1209994345
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2424695210
Short name T25
Test name
Test status
Simulation time 72617378 ps
CPU time 1.07 seconds
Started Aug 12 05:35:38 PM PDT 24
Finished Aug 12 05:35:40 PM PDT 24
Peak memory 216676 kb
Host smart-6bf6761c-cf26-4e39-a259-217028ebd62d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424695210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2424695210
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3734723499
Short name T584
Test name
Test status
Simulation time 2834363326 ps
CPU time 10.9 seconds
Started Aug 12 05:36:00 PM PDT 24
Finished Aug 12 05:36:11 PM PDT 24
Peak memory 224720 kb
Host smart-0dc4c903-b80d-4504-9070-e8c8198dc2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734723499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3734723499
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2891984405
Short name T491
Test name
Test status
Simulation time 94286954 ps
CPU time 2.14 seconds
Started Aug 12 05:35:49 PM PDT 24
Finished Aug 12 05:35:56 PM PDT 24
Peak memory 224552 kb
Host smart-6ff05188-f147-4d6e-89fd-c81c52b80024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891984405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2891984405
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3634434259
Short name T354
Test name
Test status
Simulation time 4993891684 ps
CPU time 15.29 seconds
Started Aug 12 05:35:42 PM PDT 24
Finished Aug 12 05:35:58 PM PDT 24
Peak memory 219556 kb
Host smart-db49a9e9-6bd1-48c8-932a-16f51506f3e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3634434259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3634434259
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.251823990
Short name T212
Test name
Test status
Simulation time 86216012713 ps
CPU time 204.35 seconds
Started Aug 12 05:35:59 PM PDT 24
Finished Aug 12 05:39:24 PM PDT 24
Peak memory 257580 kb
Host smart-d95dda30-6507-45dc-9b6c-0d7cbc8c5af7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251823990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.251823990
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2693614254
Short name T510
Test name
Test status
Simulation time 4106330503 ps
CPU time 11.03 seconds
Started Aug 12 05:35:35 PM PDT 24
Finished Aug 12 05:35:46 PM PDT 24
Peak memory 216592 kb
Host smart-89ef85fc-561a-4ebe-b44c-da9a735623f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693614254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2693614254
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3487753091
Short name T428
Test name
Test status
Simulation time 304562822 ps
CPU time 2.36 seconds
Started Aug 12 05:35:51 PM PDT 24
Finished Aug 12 05:35:58 PM PDT 24
Peak memory 216404 kb
Host smart-d801a970-7928-47fc-9214-429b1ada641c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487753091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3487753091
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.715299113
Short name T933
Test name
Test status
Simulation time 489197888 ps
CPU time 1.82 seconds
Started Aug 12 05:35:53 PM PDT 24
Finished Aug 12 05:35:55 PM PDT 24
Peak memory 216312 kb
Host smart-5b864d7e-edf3-4b81-8810-936b2e2692b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715299113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.715299113
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3176851809
Short name T730
Test name
Test status
Simulation time 90770496 ps
CPU time 0.92 seconds
Started Aug 12 05:35:53 PM PDT 24
Finished Aug 12 05:35:54 PM PDT 24
Peak memory 206008 kb
Host smart-e5fbcc18-7747-4b66-8375-a0cf9c1b5284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176851809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3176851809
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2303119262
Short name T14
Test name
Test status
Simulation time 1902531936 ps
CPU time 9.25 seconds
Started Aug 12 05:36:12 PM PDT 24
Finished Aug 12 05:36:21 PM PDT 24
Peak memory 241080 kb
Host smart-69e44f98-f762-464f-a2ce-8ead73b3ade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303119262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2303119262
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4127139290
Short name T830
Test name
Test status
Simulation time 42143475 ps
CPU time 0.72 seconds
Started Aug 12 05:35:54 PM PDT 24
Finished Aug 12 05:35:55 PM PDT 24
Peak memory 204568 kb
Host smart-e99b7313-f08c-4768-8baf-4b6dc49330fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127139290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
127139290
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3415468209
Short name T506
Test name
Test status
Simulation time 450248389 ps
CPU time 8.36 seconds
Started Aug 12 05:35:34 PM PDT 24
Finished Aug 12 05:35:43 PM PDT 24
Peak memory 224612 kb
Host smart-ba336ea0-389c-4d0f-870a-16ba849a9973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415468209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3415468209
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.728645004
Short name T612
Test name
Test status
Simulation time 77143286 ps
CPU time 0.76 seconds
Started Aug 12 05:35:42 PM PDT 24
Finished Aug 12 05:35:43 PM PDT 24
Peak memory 206508 kb
Host smart-29abf48f-022d-411c-aa9f-7e23fb1bba4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728645004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.728645004
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3137933165
Short name T492
Test name
Test status
Simulation time 64949566682 ps
CPU time 250.15 seconds
Started Aug 12 05:36:10 PM PDT 24
Finished Aug 12 05:40:21 PM PDT 24
Peak memory 251468 kb
Host smart-a2f9509e-c96e-4ee9-b429-5141af19604d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137933165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3137933165
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.372719251
Short name T315
Test name
Test status
Simulation time 67166256224 ps
CPU time 83.64 seconds
Started Aug 12 05:35:53 PM PDT 24
Finished Aug 12 05:37:17 PM PDT 24
Peak memory 240912 kb
Host smart-0e9551bd-13ee-4c26-9e48-854fb8a70648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372719251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.372719251
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3300658140
Short name T997
Test name
Test status
Simulation time 3227375019 ps
CPU time 44.79 seconds
Started Aug 12 05:35:58 PM PDT 24
Finished Aug 12 05:36:43 PM PDT 24
Peak memory 249448 kb
Host smart-6562e908-d66d-4140-a737-9fc8c56c9267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300658140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3300658140
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3571562349
Short name T158
Test name
Test status
Simulation time 257912527 ps
CPU time 2.92 seconds
Started Aug 12 05:36:01 PM PDT 24
Finished Aug 12 05:36:04 PM PDT 24
Peak memory 232884 kb
Host smart-1526fedd-9534-44ff-8cc4-5b854312ee81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571562349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3571562349
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2428072390
Short name T88
Test name
Test status
Simulation time 22570698511 ps
CPU time 176.96 seconds
Started Aug 12 05:35:59 PM PDT 24
Finished Aug 12 05:38:57 PM PDT 24
Peak memory 255856 kb
Host smart-f9be21f8-1a40-4692-8194-97f1d7943b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428072390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2428072390
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1802153361
Short name T918
Test name
Test status
Simulation time 1683765158 ps
CPU time 14.37 seconds
Started Aug 12 05:35:59 PM PDT 24
Finished Aug 12 05:36:13 PM PDT 24
Peak memory 224632 kb
Host smart-cabcc424-4acd-4ff0-bea9-037097b88805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802153361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1802153361
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3058256028
Short name T932
Test name
Test status
Simulation time 57404328769 ps
CPU time 91.39 seconds
Started Aug 12 05:36:02 PM PDT 24
Finished Aug 12 05:37:33 PM PDT 24
Peak memory 232988 kb
Host smart-22aed05f-98bc-4756-8ac0-f047352a7714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058256028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3058256028
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3009955224
Short name T604
Test name
Test status
Simulation time 24929072 ps
CPU time 1.05 seconds
Started Aug 12 05:35:48 PM PDT 24
Finished Aug 12 05:35:50 PM PDT 24
Peak memory 217808 kb
Host smart-248e9b18-d852-4ec2-be93-19e6873d3381
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009955224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3009955224
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1073603990
Short name T697
Test name
Test status
Simulation time 19384799629 ps
CPU time 15.1 seconds
Started Aug 12 05:35:37 PM PDT 24
Finished Aug 12 05:35:52 PM PDT 24
Peak memory 232948 kb
Host smart-3db57578-8ded-4233-912a-e094f49b493b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073603990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1073603990
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2141016051
Short name T792
Test name
Test status
Simulation time 31522155 ps
CPU time 2.03 seconds
Started Aug 12 05:35:56 PM PDT 24
Finished Aug 12 05:35:58 PM PDT 24
Peak memory 222872 kb
Host smart-6f6c1955-f74d-4862-9a58-e644cf20f0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141016051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2141016051
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.656703925
Short name T625
Test name
Test status
Simulation time 12767629626 ps
CPU time 15.44 seconds
Started Aug 12 05:35:58 PM PDT 24
Finished Aug 12 05:36:14 PM PDT 24
Peak memory 222736 kb
Host smart-8ec42550-7ef8-446e-afd2-66c00cc34ad9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=656703925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.656703925
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.278009537
Short name T908
Test name
Test status
Simulation time 24586100538 ps
CPU time 151.45 seconds
Started Aug 12 05:36:01 PM PDT 24
Finished Aug 12 05:38:32 PM PDT 24
Peak memory 256720 kb
Host smart-8890aef2-4b8a-4021-b683-e59a66768101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278009537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.278009537
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3134734340
Short name T543
Test name
Test status
Simulation time 5090476302 ps
CPU time 14.63 seconds
Started Aug 12 05:35:33 PM PDT 24
Finished Aug 12 05:35:48 PM PDT 24
Peak memory 216508 kb
Host smart-2894f53f-4a66-4108-beb8-d2b677f8cdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134734340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3134734340
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1406033296
Short name T175
Test name
Test status
Simulation time 17615424496 ps
CPU time 8.33 seconds
Started Aug 12 05:35:54 PM PDT 24
Finished Aug 12 05:36:03 PM PDT 24
Peak memory 217204 kb
Host smart-b7636abc-4427-465c-9ea1-5412923a90aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406033296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1406033296
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1440355524
Short name T344
Test name
Test status
Simulation time 338022588 ps
CPU time 2.48 seconds
Started Aug 12 05:35:43 PM PDT 24
Finished Aug 12 05:35:46 PM PDT 24
Peak memory 216484 kb
Host smart-7268947b-067d-449c-93fa-030a681c5276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440355524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1440355524
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1889637114
Short name T3
Test name
Test status
Simulation time 76929534 ps
CPU time 0.93 seconds
Started Aug 12 05:35:43 PM PDT 24
Finished Aug 12 05:35:44 PM PDT 24
Peak memory 206052 kb
Host smart-988b274d-4268-4fa6-a670-aafa48147041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889637114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1889637114
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1534616451
Short name T700
Test name
Test status
Simulation time 26841713145 ps
CPU time 14.91 seconds
Started Aug 12 05:35:57 PM PDT 24
Finished Aug 12 05:36:12 PM PDT 24
Peak memory 224736 kb
Host smart-ea0916ac-5437-483f-bc19-6af2a4f09c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534616451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1534616451
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1467781290
Short name T982
Test name
Test status
Simulation time 32924775 ps
CPU time 0.73 seconds
Started Aug 12 05:35:54 PM PDT 24
Finished Aug 12 05:35:55 PM PDT 24
Peak memory 204712 kb
Host smart-a02f7c14-7314-4018-aaaa-2a0080ef50d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467781290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
467781290
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.769789924
Short name T276
Test name
Test status
Simulation time 80793736 ps
CPU time 2.35 seconds
Started Aug 12 05:35:44 PM PDT 24
Finished Aug 12 05:35:46 PM PDT 24
Peak memory 224728 kb
Host smart-17e8ca33-b1d8-44dc-a5b1-e09e654327bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769789924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.769789924
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.233410606
Short name T546
Test name
Test status
Simulation time 16819519 ps
CPU time 0.81 seconds
Started Aug 12 05:35:43 PM PDT 24
Finished Aug 12 05:35:44 PM PDT 24
Peak memory 206456 kb
Host smart-bd834dae-71c3-48f0-97a7-74becee955fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233410606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.233410606
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.151801635
Short name T250
Test name
Test status
Simulation time 11951858637 ps
CPU time 79.84 seconds
Started Aug 12 05:36:04 PM PDT 24
Finished Aug 12 05:37:24 PM PDT 24
Peak memory 257324 kb
Host smart-fe0391c5-d1a7-42df-9fb0-d7842d8e7586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151801635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.151801635
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3919931119
Short name T229
Test name
Test status
Simulation time 586345450505 ps
CPU time 420.07 seconds
Started Aug 12 05:35:49 PM PDT 24
Finished Aug 12 05:42:50 PM PDT 24
Peak memory 249432 kb
Host smart-d58b963d-e0c2-4d43-8116-5e5f74834c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919931119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3919931119
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3935069183
Short name T902
Test name
Test status
Simulation time 36151835919 ps
CPU time 427.84 seconds
Started Aug 12 05:35:53 PM PDT 24
Finished Aug 12 05:43:01 PM PDT 24
Peak memory 257588 kb
Host smart-144f01ce-dea8-4ae9-9705-0a19ea502b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935069183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3935069183
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1979860661
Short name T185
Test name
Test status
Simulation time 4872451420 ps
CPU time 46.02 seconds
Started Aug 12 05:36:02 PM PDT 24
Finished Aug 12 05:36:48 PM PDT 24
Peak memory 241136 kb
Host smart-6c65050b-643a-4c03-89c8-89d742963630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979860661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1979860661
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.354839513
Short name T42
Test name
Test status
Simulation time 993619390 ps
CPU time 25.67 seconds
Started Aug 12 05:35:47 PM PDT 24
Finished Aug 12 05:36:13 PM PDT 24
Peak memory 253732 kb
Host smart-0b73bb9d-b8df-42c6-9e1b-de929e66344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354839513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
354839513
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4156193704
Short name T728
Test name
Test status
Simulation time 1827132739 ps
CPU time 10.7 seconds
Started Aug 12 05:36:00 PM PDT 24
Finished Aug 12 05:36:11 PM PDT 24
Peak memory 224580 kb
Host smart-6967712e-609d-46ed-bc76-9680edfd75cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156193704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4156193704
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.998892496
Short name T930
Test name
Test status
Simulation time 3378217889 ps
CPU time 40.28 seconds
Started Aug 12 05:35:59 PM PDT 24
Finished Aug 12 05:36:40 PM PDT 24
Peak memory 232904 kb
Host smart-bb055f11-f64b-46cc-b8a3-5b5b551c4831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998892496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.998892496
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1034102068
Short name T580
Test name
Test status
Simulation time 93731777 ps
CPU time 1.1 seconds
Started Aug 12 05:35:46 PM PDT 24
Finished Aug 12 05:35:47 PM PDT 24
Peak memory 216668 kb
Host smart-d2d0e44b-11b6-420d-9174-a62d4ae7243c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034102068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1034102068
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2621719531
Short name T749
Test name
Test status
Simulation time 2280022594 ps
CPU time 9 seconds
Started Aug 12 05:36:28 PM PDT 24
Finished Aug 12 05:36:37 PM PDT 24
Peak memory 232960 kb
Host smart-dc8219e1-e315-43ce-9022-2c597f239bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621719531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2621719531
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3607908990
Short name T232
Test name
Test status
Simulation time 1710922430 ps
CPU time 4.26 seconds
Started Aug 12 05:36:08 PM PDT 24
Finished Aug 12 05:36:13 PM PDT 24
Peak memory 232880 kb
Host smart-26bddbec-c4e0-464b-a3e9-d2069dd64522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607908990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3607908990
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3254659235
Short name T952
Test name
Test status
Simulation time 222299917 ps
CPU time 3.86 seconds
Started Aug 12 05:35:39 PM PDT 24
Finished Aug 12 05:35:43 PM PDT 24
Peak memory 220388 kb
Host smart-6fdf4ddd-a0b4-4cd9-8409-2fdbb9867fb2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3254659235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3254659235
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1569488670
Short name T789
Test name
Test status
Simulation time 62251441224 ps
CPU time 183.06 seconds
Started Aug 12 05:35:47 PM PDT 24
Finished Aug 12 05:38:51 PM PDT 24
Peak memory 256192 kb
Host smart-59106b36-0467-4aa3-ad33-efd3fb5956a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569488670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1569488670
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1026633919
Short name T97
Test name
Test status
Simulation time 25937006433 ps
CPU time 26.04 seconds
Started Aug 12 05:35:49 PM PDT 24
Finished Aug 12 05:36:15 PM PDT 24
Peak memory 216488 kb
Host smart-70c0ef9e-b9e5-45d9-92ad-ad28de1fe5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026633919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1026633919
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.127900846
Short name T803
Test name
Test status
Simulation time 1166067368 ps
CPU time 3.44 seconds
Started Aug 12 05:35:35 PM PDT 24
Finished Aug 12 05:35:38 PM PDT 24
Peak memory 216340 kb
Host smart-02c3e917-8db9-4750-b0c9-fe0acf8b5ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127900846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.127900846
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1226318078
Short name T515
Test name
Test status
Simulation time 16937802 ps
CPU time 0.78 seconds
Started Aug 12 05:36:03 PM PDT 24
Finished Aug 12 05:36:04 PM PDT 24
Peak memory 206060 kb
Host smart-26eef49c-b993-430d-9edf-d9e8a1a4d23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226318078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1226318078
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1315423904
Short name T613
Test name
Test status
Simulation time 257944849 ps
CPU time 0.79 seconds
Started Aug 12 05:35:57 PM PDT 24
Finished Aug 12 05:35:58 PM PDT 24
Peak memory 206036 kb
Host smart-d4c9d627-2fc5-467c-abb9-d59b4047029b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315423904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1315423904
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1873831245
Short name T484
Test name
Test status
Simulation time 26361206335 ps
CPU time 19.1 seconds
Started Aug 12 05:35:55 PM PDT 24
Finished Aug 12 05:36:14 PM PDT 24
Peak memory 224728 kb
Host smart-34606e0a-5044-459e-b1c3-c46e323f011b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873831245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1873831245
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3768453491
Short name T606
Test name
Test status
Simulation time 13450478 ps
CPU time 0.74 seconds
Started Aug 12 05:36:14 PM PDT 24
Finished Aug 12 05:36:15 PM PDT 24
Peak memory 204768 kb
Host smart-e28809df-2384-405d-b4a8-22c9af1b3a79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768453491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
768453491
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2436200807
Short name T1022
Test name
Test status
Simulation time 53092580 ps
CPU time 1.97 seconds
Started Aug 12 05:35:45 PM PDT 24
Finished Aug 12 05:35:47 PM PDT 24
Peak memory 224600 kb
Host smart-b3f57f2a-3568-4e22-aba2-80ed5b11bd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436200807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2436200807
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1306129134
Short name T602
Test name
Test status
Simulation time 44869925 ps
CPU time 0.76 seconds
Started Aug 12 05:35:44 PM PDT 24
Finished Aug 12 05:35:45 PM PDT 24
Peak memory 205816 kb
Host smart-b0ba9296-8984-4354-a5fd-83d11eec3371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306129134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1306129134
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3934255679
Short name T569
Test name
Test status
Simulation time 5426165029 ps
CPU time 68.3 seconds
Started Aug 12 05:36:05 PM PDT 24
Finished Aug 12 05:37:14 PM PDT 24
Peak memory 241132 kb
Host smart-4d1ff046-7acb-4818-8c4e-78b3ebdd06b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934255679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3934255679
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.644449105
Short name T577
Test name
Test status
Simulation time 21650645146 ps
CPU time 165.78 seconds
Started Aug 12 05:35:59 PM PDT 24
Finished Aug 12 05:38:45 PM PDT 24
Peak memory 254348 kb
Host smart-780189da-97f1-4640-bb2f-4f4ffce41c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644449105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.644449105
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.44442760
Short name T536
Test name
Test status
Simulation time 173337328171 ps
CPU time 89.52 seconds
Started Aug 12 05:36:05 PM PDT 24
Finished Aug 12 05:37:34 PM PDT 24
Peak memory 252600 kb
Host smart-62b70991-1be3-46f3-a8f2-8bb12739726b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44442760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.44442760
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1728339958
Short name T190
Test name
Test status
Simulation time 1559602869 ps
CPU time 12.22 seconds
Started Aug 12 05:36:00 PM PDT 24
Finished Aug 12 05:36:12 PM PDT 24
Peak memory 238492 kb
Host smart-5edb8bed-d42f-40c6-9c4c-ec187f00297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728339958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1728339958
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2558226114
Short name T888
Test name
Test status
Simulation time 6345657725 ps
CPU time 77.7 seconds
Started Aug 12 05:36:05 PM PDT 24
Finished Aug 12 05:37:23 PM PDT 24
Peak memory 249548 kb
Host smart-2c05ac1f-ee6b-4bea-846a-b058a85d85bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558226114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2558226114
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2526370850
Short name T360
Test name
Test status
Simulation time 3816784670 ps
CPU time 10.48 seconds
Started Aug 12 05:36:12 PM PDT 24
Finished Aug 12 05:36:23 PM PDT 24
Peak memory 228444 kb
Host smart-76da674f-8d00-41e2-9e8f-a424faa3e2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526370850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2526370850
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1846350611
Short name T1032
Test name
Test status
Simulation time 1480876189 ps
CPU time 4.74 seconds
Started Aug 12 05:36:08 PM PDT 24
Finished Aug 12 05:36:13 PM PDT 24
Peak memory 232928 kb
Host smart-74222576-17fa-49f9-830a-f9468c736fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846350611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1846350611
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3724763769
Short name T456
Test name
Test status
Simulation time 30444253 ps
CPU time 1.02 seconds
Started Aug 12 05:36:01 PM PDT 24
Finished Aug 12 05:36:02 PM PDT 24
Peak memory 217972 kb
Host smart-012f0027-245c-4372-a800-0eacf92f9265
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724763769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3724763769
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2852429422
Short name T365
Test name
Test status
Simulation time 339961748 ps
CPU time 2.97 seconds
Started Aug 12 05:35:47 PM PDT 24
Finished Aug 12 05:35:50 PM PDT 24
Peak memory 224620 kb
Host smart-b2bc2f9f-2e65-4c07-b4a0-51d7a45f6d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852429422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2852429422
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1766626162
Short name T242
Test name
Test status
Simulation time 466363454 ps
CPU time 6.34 seconds
Started Aug 12 05:35:38 PM PDT 24
Finished Aug 12 05:35:44 PM PDT 24
Peak memory 232924 kb
Host smart-1e4c1c5a-bfd9-42ae-8e48-af25bff412cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766626162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1766626162
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1398765639
Short name T400
Test name
Test status
Simulation time 26632740263 ps
CPU time 14.5 seconds
Started Aug 12 05:35:58 PM PDT 24
Finished Aug 12 05:36:13 PM PDT 24
Peak memory 220556 kb
Host smart-c34cc553-a150-4b4a-b2ba-39cc9fc2936c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1398765639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1398765639
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2492871521
Short name T168
Test name
Test status
Simulation time 163214033 ps
CPU time 0.96 seconds
Started Aug 12 05:36:09 PM PDT 24
Finished Aug 12 05:36:10 PM PDT 24
Peak memory 206504 kb
Host smart-4145a72b-cc3c-433b-97d5-93f408210dee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492871521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2492871521
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2691967434
Short name T893
Test name
Test status
Simulation time 1344003052 ps
CPU time 7.81 seconds
Started Aug 12 05:35:43 PM PDT 24
Finished Aug 12 05:35:51 PM PDT 24
Peak memory 216636 kb
Host smart-62e03817-a847-4494-a25c-de4371e17369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691967434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2691967434
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.4243661490
Short name T1030
Test name
Test status
Simulation time 2829086129 ps
CPU time 5.75 seconds
Started Aug 12 05:35:57 PM PDT 24
Finished Aug 12 05:36:03 PM PDT 24
Peak memory 216348 kb
Host smart-c9ece7ed-2693-4912-8b54-c98f0b90b59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243661490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.4243661490
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2460271510
Short name T925
Test name
Test status
Simulation time 84507589 ps
CPU time 1.67 seconds
Started Aug 12 05:36:06 PM PDT 24
Finished Aug 12 05:36:08 PM PDT 24
Peak memory 216568 kb
Host smart-878bf08e-9c25-41f6-add4-e85fce7abd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460271510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2460271510
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1070410864
Short name T544
Test name
Test status
Simulation time 79881419 ps
CPU time 0.8 seconds
Started Aug 12 05:36:03 PM PDT 24
Finished Aug 12 05:36:03 PM PDT 24
Peak memory 205916 kb
Host smart-dd596b8f-bf19-4ad0-97d6-e6e0ce67a3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070410864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1070410864
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1154224257
Short name T272
Test name
Test status
Simulation time 311193518 ps
CPU time 2.9 seconds
Started Aug 12 05:36:04 PM PDT 24
Finished Aug 12 05:36:07 PM PDT 24
Peak memory 232864 kb
Host smart-76a4c40b-ae96-46b1-86b1-225e0732a52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154224257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1154224257
Directory /workspace/9.spi_device_upload/latest
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