Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3070496	1			T1	4275		T2	1		T3	1
all_values[1]	3070496	1			T1	4275		T2	1		T3	1
all_values[2]	3070496	1			T1	4275		T2	1		T3	1
all_values[3]	3070496	1			T1	4275		T2	1		T3	1
all_values[4]	3070496	1			T1	4275		T2	1		T3	1
all_values[5]	3070496	1			T1	4275		T2	1		T3	1
all_values[6]	3070496	1			T1	4275		T2	1		T3	1
all_values[7]	3070496	1			T1	4275		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23669824

1

T1

34200

T2

8

T3

8

auto[1]

894144

1

T8

73729

T11

89

T70

94

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24536060

1

T1

34200

T2

8

T3

8

auto[1]

27908

1

T6

368

T8

469

T11

70

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3009519	1			T1	4275		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	13083	1			T6	203		T8	230		T11	3
all_values[0]	auto[1]	auto[0]	47493	1			T8	2		T11	5		T70	4
all_values[0]	auto[1]	auto[1]	401	1			T11	6		T70	4		T17	97
all_values[1]	auto[0]	auto[0]	3007939	1			T1	4275		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	8360	1			T6	149		T8	169		T11	7
all_values[1]	auto[1]	auto[0]	53662	1			T11	1		T70	7		T17	2182
all_values[1]	auto[1]	auto[1]	535	1			T8	2		T11	2		T70	4
all_values[2]	auto[0]	auto[0]	2895233	1			T1	4275		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	3061	1			T6	16		T8	1		T11	4
all_values[2]	auto[1]	auto[0]	171767	1			T8	36802		T11	8		T70	7
all_values[2]	auto[1]	auto[1]	435	1			T8	59		T11	8		T70	6
all_values[3]	auto[0]	auto[0]	3010997	1			T1	4275		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	199	1			T8	1		T11	4		T70	4
all_values[3]	auto[1]	auto[0]	59064	1			T8	36859		T11	8		T70	8
all_values[3]	auto[1]	auto[1]	236	1			T8	2		T11	7		T70	7
all_values[4]	auto[0]	auto[0]	2893103	1			T1	4275		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	174	1			T70	5		T17	4		T18	4
all_values[4]	auto[1]	auto[0]	177009	1			T11	7		T70	7		T17	2
all_values[4]	auto[1]	auto[1]	210	1			T11	5		T70	5		T17	1
all_values[5]	auto[0]	auto[0]	3008289	1			T1	4275		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	211	1			T8	1		T11	5		T70	7
all_values[5]	auto[1]	auto[0]	61818	1			T11	9		T70	11		T17	4
all_values[5]	auto[1]	auto[1]	178	1			T8	1		T11	2		T70	2
all_values[6]	auto[0]	auto[0]	2928658	1			T1	4275		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	214	1			T11	7		T70	6		T17	3
all_values[6]	auto[1]	auto[0]	141390	1			T11	7		T70	3		T17	2244
all_values[6]	auto[1]	auto[1]	234	1			T8	1		T11	4		T70	9
all_values[7]	auto[0]	auto[0]	2890578	1			T1	4275		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	206	1			T8	2		T11	2		T70	7
all_values[7]	auto[1]	auto[0]	179541	1			T8	1		T11	6		T70	6
all_values[7]	auto[1]	auto[1]	171	1			T11	4		T70	4		T17	2