Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36488	1			T6	75		T8	110		T10	18
auto[SpiFlashAddrCfg]	8017	1			T6	19		T8	39		T15	27
auto[SpiFlashAddr3b]	9479	1			T3	1		T6	22		T8	35
auto[SpiFlashAddr4b]	7852	1			T3	1		T6	29		T8	28

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34162

1

T3

2

T6

71

T8

123

auto[1]

27674

1

T6

74

T8

89

T15

39

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33319

1

T3

1

T6

72

T8

106

auto[1]

28517

1

T3

1

T6

73

T8

106

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41425	1			T6	98		T8	137		T10	18
values[1]	1177	1			T6	5		T8	6		T15	7
values[2]	1456	1			T6	4		T8	1		T13	6
values[3]	1505	1			T6	6		T8	7		T13	4
values[4]	1491	1			T6	3		T8	3		T15	6
values[5]	1492	1			T6	1		T8	7		T15	1
values[6]	1483	1			T6	3		T8	3		T15	7
values[7]	1497	1			T8	1		T15	9		T26	3
values[8]	10310	1			T3	2		T6	25		T8	47

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34509

1

T10

18

T13

18

T14

8

auto[1]

27327

1

T3

2

T6

145

T8

212

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58416

1

T3

2

T6

133

T8

190

write

3420

1

T6

12

T8

22

T13

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20045

1

T3

2

T6

53

T8

83

valids[0x1]

41791

1

T6

92

T8

129

T13

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1675	1			T6	5		T8	8		T15	4
internal_process_ops[0x5a]	1559	1			T6	7		T8	9		T15	9
internal_process_ops[0x05]	21916	1			T6	29		T8	37		T15	4
internal_process_ops[0x35]	1637	1			T6	8		T8	6		T13	2
internal_process_ops[0x15]	1690	1			T6	5		T8	6		T15	2
internal_process_ops[0x03]	1098	1			T6	3		T8	1		T13	4
internal_process_ops[0x0b]	1123	1			T6	2		T8	2		T15	7
internal_process_ops[0x3b]	1164	1			T3	1		T8	4		T13	4
internal_process_ops[0x6b]	1134	1			T8	3		T15	3		T27	6
internal_process_ops[0xbb]	1113	1			T3	1		T15	5		T16	8
internal_process_ops[0xeb]	1140	1			T13	6		T27	3		T54	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60135

1

T3

2

T6

138

T8

200

auto[1]

1701

1

T6

7

T8

12

T15

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59311

1

T3

2

T6

134

T8

193

auto[1]

2525

1

T6

11

T8

19

T15

3

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11609

1

T10

18

T13

2

T14

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7356

1

T15

5

T27

22

T45

200

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2311

1

T15

14

T27

12

T54

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2035

1

T15

12

T27

18

T45

23

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2664

1

T13

4

T15

19

T16

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2495

1

T15

13

T27

23

T45

27

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2330

1

T13

10

T15

9

T16

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1960

1

T15

7

T27

18

T45

18

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

101

1

T27

1

T50

1

T51

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

94

1

T27

2

T18

4

T66

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

90

1

T51

2

T52

1

T53

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

103

1

T15

2

T46

2

T49

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

130

1

T15

1

T27

4

T46

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

104

1

T27

2

T17

1

T51

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

99

1

T45

1

T17

1

T18

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

131

1

T50

1

T52

1

T53

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

131

1

T13

2

T15

1

T45

5

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

118

1

T27

1

T50

2

T18

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

104

1

T27

1

T45

1

T18

5

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

100

1

T45

1

T50

1

T53

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

138

1

T27

1

T45

1

T50

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

115

1

T45

5

T17

1

T18

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

92

1

T45

1

T17

1

T50

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

99

1

T45

2

T46

1

T52

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8983

1

T6

34

T8

78

T26

79

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7780

1

T6

41

T8

26

T26

24

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1407

1

T6

6

T8

8

T26

15

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1360

1

T6

11

T8

25

T26

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1794

1

T3

1

T6

9

T8

12

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1639

1

T6

8

T8

16

T26

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1337

1

T3

1

T6

14

T8

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1356

1

T6

10

T8

15

T26

21

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

78

1

T8

2

T42

1

T165

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

85

1

T8

2

T26

2

T166

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

104

1

T8

1

T26

2

T42

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

105

1

T8

1

T26

2

T42

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

102

1

T8

2

T26

1

T67

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

110

1

T6

2

T8

1

T26

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

108

1

T8

1

T26

5

T42

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

120

1

T8

2

T26

2

T67

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

91

1

T8

3

T43

1

T167

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

119

1

T6

3

T8

4

T166

8

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

126

1

T42

3

T43

3

T67

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

98

1

T6

2

T166

2

T167

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

102

1

T6

3

T8

1

T42

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

109

1

T42

1

T43

2

T18

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

123

1

T6

2

T26

2

T42

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

91

1

T8

2

T26

1

T42

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4302	1			T10	18		T14	8		T15	18
auto[0]	values[0]	valids[0x1]	17898	1			T13	8		T15	19		T16	6
auto[0]	values[1]	valids[0x1]	648	1			T15	7		T27	4		T48	2
auto[0]	values[2]	valids[0x0]	557	1			T13	6		T15	5		T16	12
auto[0]	values[2]	valids[0x1]	347	1			T15	2		T27	1		T45	1
auto[0]	values[3]	valids[0x0]	639	1			T13	4		T15	1		T27	6
auto[0]	values[3]	valids[0x1]	300	1			T27	2		T45	1		T46	2
auto[0]	values[4]	valids[0x0]	580	1			T15	4		T27	5		T45	6
auto[0]	values[4]	valids[0x1]	328	1			T15	2		T47	2		T45	7
auto[0]	values[5]	valids[0x0]	566	1			T27	8		T47	2		T45	4
auto[0]	values[5]	valids[0x1]	323	1			T15	1		T27	2		T45	2
auto[0]	values[6]	valids[0x0]	599	1			T15	2		T27	7		T54	2
auto[0]	values[6]	valids[0x1]	308	1			T15	5		T27	1		T45	3
auto[0]	values[7]	valids[0x0]	658	1			T15	2		T27	4		T47	2
auto[0]	values[7]	valids[0x1]	298	1			T15	7		T27	6		T45	3
auto[0]	values[8]	valids[0x0]	3892	1			T15	9		T27	34		T54	6
auto[0]	values[8]	valids[0x1]	2266	1			T15	16		T16	4		T27	21
auto[1]	values[0]	valids[0x0]	3781	1			T6	28		T8	44		T26	47
auto[1]	values[0]	valids[0x1]	15444	1			T6	70		T8	93		T26	90
auto[1]	values[1]	valids[0x1]	529	1			T6	5		T8	6		T26	11
auto[1]	values[2]	valids[0x0]	337	1			T8	1		T26	6		T42	5
auto[1]	values[2]	valids[0x1]	215	1			T6	4		T26	3		T42	2
auto[1]	values[3]	valids[0x0]	356	1			T6	4		T8	7		T26	2
auto[1]	values[3]	valids[0x1]	210	1			T6	2		T26	4		T166	5
auto[1]	values[4]	valids[0x0]	334	1			T6	2		T26	6		T42	2
auto[1]	values[4]	valids[0x1]	249	1			T6	1		T8	3		T26	1
auto[1]	values[5]	valids[0x0]	353	1			T8	2		T26	13		T42	5
auto[1]	values[5]	valids[0x1]	250	1			T6	1		T8	5		T67	2
auto[1]	values[6]	valids[0x0]	339	1			T6	3		T8	2		T26	2
auto[1]	values[6]	valids[0x1]	237	1			T8	1		T26	6		T42	3
auto[1]	values[7]	valids[0x0]	295	1			T26	3		T42	3		T43	2
auto[1]	values[7]	valids[0x1]	246	1			T8	1		T42	3		T43	1
auto[1]	values[8]	valids[0x0]	2457	1			T3	2		T6	16		T8	27
auto[1]	values[8]	valids[0x1]	1695	1			T6	9		T8	20		T26	32