Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3452232

1

T3

5267

T6

8471

T8

9719

auto[1]

32978

1

T6

25

T8

32

T15

11

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

867746

1

T3

5267

T6

47

T8

79

auto[1]

2617464

1

T6

8449

T8

9672

T15

2764

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	688109	1			T3	1116		T6	1		T8	31
auto[524288:1048575]	407569	1			T6	2758		T8	20		T14	303
auto[1048576:1572863]	433376	1			T3	279		T6	4057		T8	6028
auto[1572864:2097151]	421796	1			T3	2		T6	175		T8	5
auto[2097152:2621439]	343068	1			T6	1		T8	2588		T10	45
auto[2621440:3145727]	408364	1			T3	807		T6	11		T8	1072
auto[3145728:3670015]	380623	1			T3	1909		T6	266		T8	2
auto[3670016:4194303]	402305	1			T3	1154		T6	1227		T8	5

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2653426

1

T3

18

T6

8495

T8

9749

auto[1]

831784

1

T3

5249

T6

1

T8

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2973200

1

T3

5267

T6

8479

T8

8969

auto[1]

512010

1

T6

17

T8

782

T10

242

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	215503	1			T3	1116		T6	1		T8	7
auto[0]	auto[0]	auto[0:524287]	auto[1]	402649	1			T8	23		T16	4126		T26	21
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	89692	1			T6	4		T8	4		T14	303
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	258550	1			T6	2748		T8	3		T15	512
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	99419	1			T3	279		T6	8		T8	6
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	250934	1			T6	4037		T8	5264		T26	782
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	97933	1			T3	2		T6	1		T8	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	245732	1			T6	173		T8	1		T26	1583
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	69099	1			T8	15		T14	1592		T15	22
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	222865	1			T8	2553		T15	1609		T26	1526
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	82214	1			T3	807		T6	4		T8	10
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	246987	1			T6	2		T8	1054		T15	256
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	95131	1			T3	1909		T6	3		T8	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	234231	1			T6	259		T15	259		T26	4703
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	107454	1			T3	1154		T6	8		T8	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	228619	1			T6	1209		T8	1		T26	926
auto[0]	auto[1]	auto[0:524287]	auto[0]	819	1			T10	2		T26	10		T27	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	63318	1			T42	392		T45	4373		T46	517
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	597	1			T8	3		T15	2		T26	5
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	54035	1			T8	1		T166	1		T167	512
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	682	1			T6	3		T8	2		T27	7
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	78786	1			T6	1		T8	749		T27	1519
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1971	1			T10	25		T26	14		T42	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	72239	1			T26	475		T45	1826		T18	3819
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	610	1			T6	1		T8	3		T10	45
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	46194	1			T8	9		T15	128		T18	2104
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1056	1			T8	3		T10	54		T15	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	73809	1			T8	1		T26	2		T42	1795
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	588	1			T6	1		T10	116		T15	24
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	47906	1			T166	1		T18	1302		T19	22
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	545	1			T6	2		T8	1		T26	12
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	62065	1			T6	6		T26	30		T166	1800
auto[1]	auto[0]	auto[0:524287]	auto[0]	559	1			T8	1		T26	3		T27	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3835	1			T27	1		T45	44		T46	82
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	559	1			T6	2		T8	3		T15	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3593	1			T6	4		T26	215		T42	15
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	368	1			T6	3		T8	4		T15	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2185	1			T6	4		T8	3		T166	82
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	444	1			T6	1		T8	1		T26	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2730	1			T45	88		T166	11		T50	17
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	468	1			T8	4		T15	5		T26	28
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2455	1			T8	2		T26	256		T45	10
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	447	1			T6	2		T8	2		T26	10
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3393	1			T6	3		T42	80		T43	23
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	363	1			T6	1		T26	11		T27	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1780	1			T6	2		T27	1		T45	38
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	463	1			T8	1		T26	19		T27	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2546	1			T8	1		T26	128		T27	7
auto[1]	auto[1]	auto[0:524287]	auto[0]	117	1			T26	5		T45	2		T50	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	1309	1			T45	16		T50	71		T187	50
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	96	1			T8	1		T26	3		T46	10
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	447	1			T8	5		T166	37		T17	7
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	92	1			T6	1		T27	3		T17	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	910	1			T27	3		T17	14		T18	28
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	117	1			T45	1		T167	5		T176	10
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	630	1			T45	4		T176	256		T185	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	87	1			T8	1		T224	4		T133	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	1290	1			T8	1		T133	5		T230	20
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	86	1			T8	1		T26	9		T66	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	372	1			T8	1		T66	7		T231	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	64	1			T166	1		T19	1		T66	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	560	1			T166	69		T66	8		T22	19
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	103	1			T6	1		T26	11		T66	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	510	1			T6	1		T26	28		T66	6

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2117733	1			T3	18		T6	8457		T8	8946
auto[0]	auto[0]	auto[1]	829279	1			T3	5249		T8	1		T10	1
auto[0]	auto[1]	auto[0]	503468	1			T6	14		T8	771		T10	69
auto[0]	auto[1]	auto[1]	1752	1			T8	1		T10	173		T166	2
auto[1]	auto[0]	auto[0]	25567	1			T6	21		T8	22		T15	8
auto[1]	auto[0]	auto[1]	621	1			T6	1		T15	3		T26	7
auto[1]	auto[1]	auto[0]	6658	1			T6	3		T8	10		T26	53
auto[1]	auto[1]	auto[1]	132	1			T26	3		T45	2		T46	1