Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3070496	1			T1	4275		T2	1		T3	1
all_pins[1]	3070496	1			T1	4275		T2	1		T3	1
all_pins[2]	3070496	1			T1	4275		T2	1		T3	1
all_pins[3]	3070496	1			T1	4275		T2	1		T3	1
all_pins[4]	3070496	1			T1	4275		T2	1		T3	1
all_pins[5]	3070496	1			T1	4275		T2	1		T3	1
all_pins[6]	3070496	1			T1	4275		T2	1		T3	1
all_pins[7]	3070496	1			T1	4275		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	24419391	1			T1	34200		T2	8		T3	8
values[0x1]	144577	1			T8	68		T11	38		T70	41
transitions[0x0=>0x1]	143324	1			T8	66		T11	26		T70	34
transitions[0x1=>0x0]	143341	1			T8	66		T11	26		T70	34

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3070069	1			T1	4275		T2	1		T3	1
all_pins[0]	values[0x1]	427	1			T11	6		T70	4		T17	107
all_pins[0]	transitions[0x0=>0x1]	228	1			T11	6		T70	3		T17	39
all_pins[0]	transitions[0x1=>0x0]	378	1			T8	2		T11	2		T70	3
all_pins[1]	values[0x0]	3069919	1			T1	4275		T2	1		T3	1
all_pins[1]	values[0x1]	577	1			T8	2		T11	2		T70	4
all_pins[1]	transitions[0x0=>0x1]	485	1			T8	2		T70	3		T17	73
all_pins[1]	transitions[0x1=>0x0]	360	1			T8	62		T11	6		T70	5
all_pins[2]	values[0x0]	3070044	1			T1	4275		T2	1		T3	1
all_pins[2]	values[0x1]	452	1			T8	62		T11	8		T70	6
all_pins[2]	transitions[0x0=>0x1]	379	1			T8	60		T11	4		T70	4
all_pins[2]	transitions[0x1=>0x0]	163	1			T11	3		T70	5		T17	5
all_pins[3]	values[0x0]	3070260	1			T1	4275		T2	1		T3	1
all_pins[3]	values[0x1]	236	1			T8	2		T11	7		T70	7
all_pins[3]	transitions[0x0=>0x1]	175	1			T8	2		T11	6		T70	6
all_pins[3]	transitions[0x1=>0x0]	149	1			T11	4		T70	4		T17	1
all_pins[4]	values[0x0]	3070286	1			T1	4275		T2	1		T3	1
all_pins[4]	values[0x1]	210	1			T11	5		T70	5		T17	1
all_pins[4]	transitions[0x0=>0x1]	171	1			T11	4		T70	5		T17	1
all_pins[4]	transitions[0x1=>0x0]	1284	1			T8	1		T11	1		T70	2
all_pins[5]	values[0x0]	3069173	1			T1	4275		T2	1		T3	1
all_pins[5]	values[0x1]	1323	1			T8	1		T11	2		T70	2
all_pins[5]	transitions[0x0=>0x1]	648	1			T8	1		T11	2		T70	2
all_pins[5]	transitions[0x1=>0x0]	140506	1			T8	1		T11	4		T70	9
all_pins[6]	values[0x0]	2929315	1			T1	4275		T2	1		T3	1
all_pins[6]	values[0x1]	141181	1			T8	1		T11	4		T70	9
all_pins[6]	transitions[0x0=>0x1]	141121	1			T8	1		T11	2		T70	8
all_pins[6]	transitions[0x1=>0x0]	111	1			T11	2		T70	3		T17	1
all_pins[7]	values[0x0]	3070325	1			T1	4275		T2	1		T3	1
all_pins[7]	values[0x1]	171	1			T11	4		T70	4		T17	2
all_pins[7]	transitions[0x0=>0x1]	117	1			T11	2		T70	3		T17	1
all_pins[7]	transitions[0x1=>0x0]	390	1			T11	4		T70	3		T17	107