Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19845

1

T10

18

T13

18

T14

8

auto[1]

14664

1

T15

39

T27

82

T45

274

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4477	1			T14	8		T27	20		T45	132
values[1]	4427	1			T15	20		T27	20		T47	16
values[2]	3960	1			T15	40		T16	22		T50	93
values[3]	4580	1			T27	42		T48	2		T54	14
values[4]	3970	1			T27	26		T45	64		T46	20
values[5]	5004	1			T15	20		T27	44		T45	180
values[6]	4353	1			T10	18		T13	18		T15	20
values[7]	3738	1			T27	28		T45	38		T46	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3582	1			T10	18		T15	20		T27	77
values[1]	4644	1			T15	20		T47	16		T97	12
values[2]	4254	1			T15	20		T45	83		T46	20
values[3]	4274	1			T16	22		T45	218		T46	20
values[4]	4546	1			T27	40		T48	2		T45	20
values[5]	4127	1			T14	8		T15	40		T27	24
values[6]	4590	1			T13	18		T27	42		T45	69
values[7]	4492	1			T27	21		T54	14		T45	24

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	259	1			T232	2		T218	12		T191	10
auto[0]	values[0]	values[1]	139	1			T136	14		T233	12		T194	4
auto[0]	values[0]	values[2]	304	1			T45	13		T18	9		T223	16
auto[0]	values[0]	values[3]	320	1			T52	12		T66	8		T133	8
auto[0]	values[0]	values[4]	274	1			T27	10		T53	12		T22	13
auto[0]	values[0]	values[5]	319	1			T14	8		T22	13		T218	13
auto[0]	values[0]	values[6]	310	1			T45	38		T50	45		T192	10
auto[0]	values[0]	values[7]	304	1			T46	13		T51	17		T139	8
auto[0]	values[1]	values[0]	167	1			T203	20		T204	9		T234	15
auto[0]	values[1]	values[1]	357	1			T47	16		T133	12		T22	46
auto[0]	values[1]	values[2]	398	1			T50	13		T198	2		T139	28
auto[0]	values[1]	values[3]	290	1			T17	9		T52	18		T18	17
auto[0]	values[1]	values[4]	358	1			T17	11		T53	11		T215	26
auto[0]	values[1]	values[5]	508	1			T15	14		T45	26		T17	13
auto[0]	values[1]	values[6]	456	1			T27	11		T183	16		T200	41
auto[0]	values[1]	values[7]	262	1			T17	19		T181	20		T235	11
auto[0]	values[2]	values[0]	382	1			T50	88		T18	8		T236	16
auto[0]	values[2]	values[1]	187	1			T15	13		T137	10		T22	15
auto[0]	values[2]	values[2]	163	1			T200	11		T160	15		T237	2
auto[0]	values[2]	values[3]	435	1			T16	22		T238	4		T239	10
auto[0]	values[2]	values[4]	344	1			T52	13		T53	8		T213	14
auto[0]	values[2]	values[5]	227	1			T15	15		T212	13		T191	10
auto[0]	values[2]	values[6]	307	1			T18	153		T212	19		T203	16
auto[0]	values[2]	values[7]	480	1			T139	36		T230	15		T85	18
auto[0]	values[3]	values[0]	166	1			T45	4		T52	6		T221	30
auto[0]	values[3]	values[1]	428	1			T177	12		T188	35		T240	56
auto[0]	values[3]	values[2]	227	1			T53	9		T178	18		T190	17
auto[0]	values[3]	values[3]	313	1			T46	14		T53	13		T223	14
auto[0]	values[3]	values[4]	316	1			T27	14		T48	2		T18	130
auto[0]	values[3]	values[5]	236	1			T92	6		T22	14		T241	8
auto[0]	values[3]	values[6]	432	1			T27	18		T22	15		T218	35
auto[0]	values[3]	values[7]	354	1			T54	14		T17	27		T53	12
auto[0]	values[4]	values[0]	324	1			T27	11		T142	10		T230	49
auto[0]	values[4]	values[1]	363	1			T51	13		T22	6		T187	8
auto[0]	values[4]	values[2]	355	1			T46	7		T52	15		T221	30
auto[0]	values[4]	values[3]	316	1			T242	12		T206	22		T139	11
auto[0]	values[4]	values[4]	197	1			T45	11		T217	10		T133	12
auto[0]	values[4]	values[5]	171	1			T214	10		T196	14		T187	12
auto[0]	values[4]	values[6]	452	1			T45	14		T18	7		T200	14
auto[0]	values[4]	values[7]	207	1			T45	7		T220	16		T218	11
auto[0]	values[5]	values[0]	323	1			T27	13		T139	8		T22	27
auto[0]	values[5]	values[1]	342	1			T97	12		T52	9		T243	8
auto[0]	values[5]	values[2]	322	1			T15	10		T244	2		T190	10
auto[0]	values[5]	values[3]	369	1			T45	75		T52	15		T66	11
auto[0]	values[5]	values[4]	293	1			T51	21		T53	8		T66	51
auto[0]	values[5]	values[5]	383	1			T53	12		T200	8		T142	15
auto[0]	values[5]	values[6]	207	1			T17	16		T51	14		T59	8
auto[0]	values[5]	values[7]	576	1			T27	15		T17	9		T139	12
auto[0]	values[6]	values[0]	231	1			T10	18		T15	9		T133	44
auto[0]	values[6]	values[1]	406	1			T200	89		T245	9		T246	35
auto[0]	values[6]	values[2]	257	1			T247	4		T66	11		T248	16
auto[0]	values[6]	values[3]	105	1			T133	8		T195	14		T249	10
auto[0]	values[6]	values[4]	652	1			T18	139		T139	45		T22	11
auto[0]	values[6]	values[5]	278	1			T27	14		T50	9		T51	12
auto[0]	values[6]	values[6]	371	1			T13	18		T250	6		T251	75
auto[0]	values[6]	values[7]	301	1			T139	12		T218	11		T187	14
auto[0]	values[7]	values[0]	319	1			T27	16		T52	16		T53	111
auto[0]	values[7]	values[1]	266	1			T91	8		T181	11		T212	10
auto[0]	values[7]	values[2]	274	1			T51	37		T53	10		T22	24
auto[0]	values[7]	values[3]	334	1			T45	29		T53	12		T252	14
auto[0]	values[7]	values[4]	99	1			T218	8		T253	10		T212	10
auto[0]	values[7]	values[5]	314	1			T46	15		T223	10		T142	13
auto[0]	values[7]	values[6]	196	1			T46	6		T50	11		T187	12
auto[0]	values[7]	values[7]	220	1			T139	12		T140	2		T230	8
auto[1]	values[0]	values[0]	141	1			T218	11		T254	8		T191	10
auto[1]	values[0]	values[1]	317	1			T255	2		T233	8		T256	4
auto[1]	values[0]	values[2]	440	1			T45	70		T18	175		T223	4
auto[1]	values[0]	values[3]	349	1			T52	9		T66	12		T133	14
auto[1]	values[0]	values[4]	370	1			T27	10		T53	8		T22	46
auto[1]	values[0]	values[5]	240	1			T22	7		T218	7		T257	16
auto[1]	values[0]	values[6]	176	1			T45	11		T50	11		T66	11
auto[1]	values[0]	values[7]	215	1			T46	7		T51	3		T139	12
auto[1]	values[1]	values[0]	207	1			T203	7		T204	11		T258	6
auto[1]	values[1]	values[1]	251	1			T133	8		T22	10		T187	6
auto[1]	values[1]	values[2]	289	1			T50	59		T139	9		T221	11
auto[1]	values[1]	values[3]	149	1			T17	34		T52	9		T18	3
auto[1]	values[1]	values[4]	198	1			T17	23		T53	9		T202	15
auto[1]	values[1]	values[5]	163	1			T15	6		T45	5		T17	7
auto[1]	values[1]	values[6]	242	1			T27	9		T200	8		T142	12
auto[1]	values[1]	values[7]	132	1			T17	9		T181	20		T235	9
auto[1]	values[2]	values[0]	205	1			T50	5		T18	52		T236	8
auto[1]	values[2]	values[1]	160	1			T15	7		T22	5		T191	17
auto[1]	values[2]	values[2]	55	1			T200	9		T160	9		T259	13
auto[1]	values[2]	values[3]	187	1			T260	4		T240	23		T261	13
auto[1]	values[2]	values[4]	265	1			T52	9		T53	12		T21	11
auto[1]	values[2]	values[5]	207	1			T15	5		T212	10		T191	12
auto[1]	values[2]	values[6]	183	1			T18	27		T182	24		T184	16
auto[1]	values[2]	values[7]	173	1			T139	5		T230	5		T212	9
auto[1]	values[3]	values[0]	227	1			T45	42		T52	27		T221	36
auto[1]	values[3]	values[1]	375	1			T262	2		T188	8		T240	5
auto[1]	values[3]	values[2]	407	1			T53	36		T190	3		T201	7
auto[1]	values[3]	values[3]	193	1			T46	6		T53	7		T223	6
auto[1]	values[3]	values[4]	144	1			T27	6		T18	4		T53	10
auto[1]	values[3]	values[5]	165	1			T22	36		T202	3		T221	12
auto[1]	values[3]	values[6]	280	1			T27	4		T22	6		T218	14
auto[1]	values[3]	values[7]	317	1			T17	9		T53	82		T63	9
auto[1]	values[4]	values[0]	161	1			T27	15		T263	18		T142	10
auto[1]	values[4]	values[1]	307	1			T51	9		T22	14		T187	12
auto[1]	values[4]	values[2]	181	1			T46	13		T52	20		T221	10
auto[1]	values[4]	values[3]	214	1			T96	16		T139	9		T218	39
auto[1]	values[4]	values[4]	154	1			T45	9		T49	14		T133	8
auto[1]	values[4]	values[5]	123	1			T187	8		T264	16		T228	50
auto[1]	values[4]	values[6]	285	1			T45	6		T18	37		T200	6
auto[1]	values[4]	values[7]	160	1			T45	17		T218	9		T265	10
auto[1]	values[5]	values[0]	157	1			T27	10		T139	12		T22	13
auto[1]	values[5]	values[1]	394	1			T52	13		T53	11		T63	8
auto[1]	values[5]	values[2]	224	1			T15	10		T190	10		T245	9
auto[1]	values[5]	values[3]	388	1			T45	105		T52	5		T66	32
auto[1]	values[5]	values[4]	474	1			T51	8		T53	132		T66	15
auto[1]	values[5]	values[5]	199	1			T53	8		T200	36		T142	8
auto[1]	values[5]	values[6]	155	1			T17	4		T51	6		T21	8
auto[1]	values[5]	values[7]	198	1			T27	6		T17	11		T139	8
auto[1]	values[6]	values[0]	123	1			T15	11		T133	14		T230	10
auto[1]	values[6]	values[1]	225	1			T200	25		T245	11		T240	6
auto[1]	values[6]	values[2]	167	1			T66	38		T266	2		T205	12
auto[1]	values[6]	values[3]	82	1			T199	14		T133	12		T267	4
auto[1]	values[6]	values[4]	296	1			T18	7		T139	11		T22	15
auto[1]	values[6]	values[5]	187	1			T27	10		T50	11		T51	8
auto[1]	values[6]	values[6]	334	1			T63	9		T133	7		T218	9
auto[1]	values[6]	values[7]	338	1			T139	22		T218	44		T187	6
auto[1]	values[7]	values[0]	190	1			T27	12		T52	4		T53	7
auto[1]	values[7]	values[1]	127	1			T181	9		T212	10		T233	6
auto[1]	values[7]	values[2]	191	1			T51	7		T53	35		T22	5
auto[1]	values[7]	values[3]	230	1			T45	9		T53	8		T203	10
auto[1]	values[7]	values[4]	112	1			T218	12		T268	2		T212	10
auto[1]	values[7]	values[5]	407	1			T46	5		T223	10		T142	7
auto[1]	values[7]	values[6]	204	1			T46	14		T50	9		T187	19
auto[1]	values[7]	values[7]	255	1			T269	14		T139	36		T230	12