Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	488	1			T15	3		T48	2		T54	2
auto[ReadAddrCrossIntoMailbox]	368	1			T15	2		T27	2		T54	2
auto[ReadAddrCrossOutOfMailbox]	328	1			T15	1		T27	1		T45	3
auto[ReadAddrCrossAllMailbox]	260	1			T15	3		T54	2		T45	1
auto[ReadAddrOutsideMailbox]	3867	1			T13	14		T15	17		T16	12

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2649

1

T13

7

T15

14

T16

6

auto[1]

2662

1

T13

7

T15

12

T16

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	850	1			T13	4		T15	6		T27	5
read_ops[0x0b]	907	1			T15	7		T27	5		T48	2
read_ops[0x3b]	882	1			T13	4		T15	5		T16	4
read_ops[0x6b]	890	1			T15	3		T27	6		T54	2
read_ops[0xbb]	876	1			T15	5		T16	8		T27	7
read_ops[0xeb]	906	1			T13	6		T27	3		T54	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T271	2		T221	2		T191	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T15	1		T139	2		T271	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T18	1		T221	2		T189	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T45	2		T17	1		T50	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T52	2		T18	2		T133	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T51	1		T22	1		T142	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T225	1		T221	1		T236	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	35	1			T15	2		T225	1		T200	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	321	1			T13	2		T15	1		T27	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	294	1			T13	2		T15	2		T27	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T15	1		T48	1		T54	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T15	1		T48	1		T54	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T27	1		T54	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T54	1		T218	1		T187	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T52	1		T218	1		T212	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T50	1		T63	1		T133	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T46	1		T52	1		T202	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T15	1		T18	1		T53	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	336	1			T15	1		T27	1		T54	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	327	1			T15	3		T27	3		T54	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T46	1		T50	1		T85	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T22	1		T218	1		T190	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T46	1		T51	1		T53	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T27	1		T53	1		T66	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T50	1		T53	1		T63	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T45	2		T46	1		T18	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T51	1		T142	1		T272	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T51	1		T18	1		T53	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	330	1			T13	2		T15	3		T16	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	348	1			T13	2		T15	2		T16	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T53	1		T250	2		T232	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T17	1		T250	2		T232	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	39	1			T15	1		T45	1		T53	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T53	1		T247	1		T218	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T17	1		T50	2		T202	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T52	1		T22	1		T218	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T50	1		T53	1		T22	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T22	1		T200	1		T221	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	342	1			T15	2		T27	5		T54	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	299	1			T27	1		T54	1		T47	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T46	1		T17	1		T51	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	51	1			T45	1		T53	1		T250	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T15	1		T17	1		T223	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T53	1		T139	1		T200	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T15	1		T27	1		T53	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T52	1		T213	1		T66	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T54	1		T46	1		T18	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T54	1		T45	1		T213	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	309	1			T15	3		T16	4		T27	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	303	1			T16	4		T27	4		T45	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T51	1		T18	1		T225	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T17	1		T53	2		T225	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T45	1		T53	1		T218	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	39	1			T45	1		T51	2		T52	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T45	1		T18	1		T53	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T18	1		T213	1		T63	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T53	1		T225	1		T218	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T225	1		T181	1		T221	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	318	1			T13	3		T27	1		T54	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	340	1			T13	3		T27	2		T54	1