Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5055	1			T10	18		T27	20		T49	14
values[1]	3876	1			T27	23		T54	14		T45	38
values[2]	4200	1			T27	21		T45	139		T17	63
values[3]	4022	1			T15	20		T27	94		T45	127
values[4]	4095	1			T13	18		T16	22		T27	26
values[5]	4353	1			T14	8		T15	40		T27	20
values[6]	3744	1			T15	40		T96	16		T18	44
values[7]	5164	1			T47	16		T45	187		T46	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3345	1			T13	18		T27	41		T48	2
values[1]	4897	1			T27	23		T45	226		T244	2
values[2]	4730	1			T27	42		T50	20		T18	340
values[3]	3620	1			T14	8		T15	20		T47	16
values[4]	4491	1			T15	20		T27	26		T45	100
values[5]	4025	1			T15	40		T16	22		T45	20
values[6]	4219	1			T10	18		T15	20		T27	72
values[7]	5182	1			T54	14		T46	20		T17	107

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33645

1

T10

18

T13

18

T14

8

auto[1]

864

1

T15

2

T27

5

T45

8

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	401	1			T27	20		T49	12		T22	26
auto[0]	values[0]	values[1]	746	1			T136	14		T181	18		T142	22
auto[0]	values[0]	values[2]	722	1			T18	144		T243	8		T22	59
auto[0]	values[0]	values[3]	597	1			T273	12		T142	30		T212	21
auto[0]	values[0]	values[4]	504	1			T139	19		T218	51		T37	21
auto[0]	values[0]	values[5]	687	1			T17	34		T225	18		T139	32
auto[0]	values[0]	values[6]	496	1			T10	18		T51	22		T202	26
auto[0]	values[0]	values[7]	784	1			T50	72		T52	20		T218	63
auto[0]	values[1]	values[0]	332	1			T50	20		T66	28		T181	20
auto[0]	values[1]	values[1]	689	1			T27	22		T50	90		T66	20
auto[0]	values[1]	values[2]	501	1			T50	19		T66	39		T133	19
auto[0]	values[1]	values[3]	394	1			T53	20		T221	20		T248	16
auto[0]	values[1]	values[4]	400	1			T52	29		T21	18		T271	10
auto[0]	values[1]	values[5]	307	1			T140	2		T22	18		T218	20
auto[0]	values[1]	values[6]	548	1			T45	36		T46	20		T133	20
auto[0]	values[1]	values[7]	577	1			T54	14		T17	27		T53	44
auto[0]	values[2]	values[0]	508	1			T27	21		T50	56		T53	20
auto[0]	values[2]	values[1]	481	1			T45	69		T187	19		T274	20
auto[0]	values[2]	values[2]	385	1			T18	131		T218	68		T200	25
auto[0]	values[2]	values[3]	379	1			T51	20		T199	14		T230	31
auto[0]	values[2]	values[4]	463	1			T45	47		T17	20		T51	20
auto[0]	values[2]	values[5]	452	1			T45	20		T206	22		T275	4
auto[0]	values[2]	values[6]	565	1			T232	2		T200	18		T188	27
auto[0]	values[2]	values[7]	879	1			T17	42		T52	35		T53	139
auto[0]	values[3]	values[0]	404	1			T52	20		T242	12		T138	22
auto[0]	values[3]	values[1]	606	1			T218	30		T197	14		T222	79
auto[0]	values[3]	values[2]	542	1			T27	41		T59	8		T22	19
auto[0]	values[3]	values[3]	264	1			T45	24		T37	22		T234	20
auto[0]	values[3]	values[4]	754	1			T45	20		T18	79		T177	12
auto[0]	values[3]	values[5]	452	1			T52	22		T139	36		T223	20
auto[0]	values[3]	values[6]	445	1			T15	20		T27	50		T45	81
auto[0]	values[3]	values[7]	455	1			T51	20		T250	6		T22	54
auto[0]	values[4]	values[0]	509	1			T13	18		T97	12		T200	20
auto[0]	values[4]	values[1]	562	1			T52	21		T53	27		T178	18
auto[0]	values[4]	values[2]	385	1			T53	20		T187	20		T276	8
auto[0]	values[4]	values[3]	478	1			T192	10		T217	10		T218	23
auto[0]	values[4]	values[4]	745	1			T27	25		T53	118		T216	6
auto[0]	values[4]	values[5]	484	1			T16	22		T198	2		T92	6
auto[0]	values[4]	values[6]	440	1			T221	73		T189	20		T277	6
auto[0]	values[4]	values[7]	385	1			T46	20		T18	29		T220	16
auto[0]	values[5]	values[0]	277	1			T48	2		T22	36		T187	20
auto[0]	values[5]	values[1]	480	1			T52	26		T18	19		T53	20
auto[0]	values[5]	values[2]	725	1			T18	60		T253	10		T278	14
auto[0]	values[5]	values[3]	368	1			T14	8		T52	22		T22	28
auto[0]	values[5]	values[4]	548	1			T15	20		T22	54		T279	15
auto[0]	values[5]	values[5]	503	1			T15	20		T46	17		T17	20
auto[0]	values[5]	values[6]	611	1			T27	20		T133	22		T280	4
auto[0]	values[5]	values[7]	738	1			T18	180		T269	12		T183	16
auto[0]	values[6]	values[0]	321	1			T196	14		T66	46		T223	18
auto[0]	values[6]	values[1]	564	1			T96	16		T281	22		T21	20
auto[0]	values[6]	values[2]	545	1			T91	8		T63	20		T21	20
auto[0]	values[6]	values[3]	344	1			T15	20		T53	18		T270	4
auto[0]	values[6]	values[4]	291	1			T139	20		T188	39		T282	19
auto[0]	values[6]	values[5]	420	1			T15	18		T133	29		T142	20
auto[0]	values[6]	values[6]	538	1			T18	43		T53	37		T238	4
auto[0]	values[6]	values[7]	632	1			T139	45		T142	20		T85	18
auto[0]	values[7]	values[0]	490	1			T46	20		T51	29		T247	4
auto[0]	values[7]	values[1]	660	1			T45	155		T244	2		T200	81
auto[0]	values[7]	values[2]	834	1			T53	17		T218	29		T212	19
auto[0]	values[7]	values[3]	699	1			T47	16		T218	67		T255	2
auto[0]	values[7]	values[4]	653	1			T45	31		T46	20		T17	20
auto[0]	values[7]	values[5]	621	1			T18	71		T209	20		T188	37
auto[0]	values[7]	values[6]	465	1			T53	44		T214	10		T133	20
auto[0]	values[7]	values[7]	611	1			T17	36		T53	94		T213	14
auto[1]	values[0]	values[0]	12	1			T49	2		T228	1		T283	1
auto[1]	values[0]	values[1]	17	1			T181	2		T142	1		T284	2
auto[1]	values[0]	values[2]	12	1			T18	2		T22	1		T226	1
auto[1]	values[0]	values[3]	16	1			T142	1		T212	3		T203	1
auto[1]	values[0]	values[4]	17	1			T139	1		T283	1		T285	1
auto[1]	values[0]	values[5]	18	1			T139	2		T233	1		T160	2
auto[1]	values[0]	values[6]	12	1			T202	3		T191	1		T209	1
auto[1]	values[0]	values[7]	14	1			T222	3		T264	4		T286	2
auto[1]	values[1]	values[0]	7	1			T287	1		T288	2		T227	1
auto[1]	values[1]	values[1]	22	1			T27	1		T50	3		T133	2
auto[1]	values[1]	values[2]	11	1			T50	1		T66	4		T133	1
auto[1]	values[1]	values[3]	17	1			T282	5		T289	1		T290	4
auto[1]	values[1]	values[4]	24	1			T52	4		T21	2		T223	2
auto[1]	values[1]	values[5]	13	1			T22	2		T233	1		T160	3
auto[1]	values[1]	values[6]	20	1			T45	2		T22	2		T245	1
auto[1]	values[1]	values[7]	14	1			T17	1		T53	1		T191	1
auto[1]	values[2]	values[0]	11	1			T189	3		T291	3		T292	4
auto[1]	values[2]	values[1]	12	1			T45	1		T187	1		T274	2
auto[1]	values[2]	values[2]	12	1			T18	3		T218	7		T293	1
auto[1]	values[2]	values[3]	5	1			T230	1		T228	1		T294	1
auto[1]	values[2]	values[4]	12	1			T45	2		T187	1		T240	4
auto[1]	values[2]	values[5]	10	1			T272	2		T234	1		T295	2
auto[1]	values[2]	values[6]	10	1			T200	2		T188	2		T261	2
auto[1]	values[2]	values[7]	16	1			T17	1		T53	1		T139	1
auto[1]	values[3]	values[0]	28	1			T296	4		T191	1		T285	1
auto[1]	values[3]	values[1]	9	1			T287	2		T297	1		T294	1
auto[1]	values[3]	values[2]	10	1			T27	1		T22	1		T191	1
auto[1]	values[3]	values[3]	8	1			T37	1		T160	3		T207	1
auto[1]	values[3]	values[4]	12	1			T18	1		T66	3		T191	3
auto[1]	values[3]	values[5]	8	1			T139	1		T298	1		T299	3
auto[1]	values[3]	values[6]	10	1			T27	2		T45	2		T187	3
auto[1]	values[3]	values[7]	15	1			T22	2		T283	4		T300	3
auto[1]	values[4]	values[0]	9	1			T282	3		T289	1		T290	1
auto[1]	values[4]	values[1]	7	1			T53	1		T284	1		T301	1
auto[1]	values[4]	values[2]	14	1			T188	2		T298	4		T301	2
auto[1]	values[4]	values[3]	18	1			T218	1		T200	1		T221	1
auto[1]	values[4]	values[4]	23	1			T27	1		T184	4		T282	1
auto[1]	values[4]	values[5]	8	1			T133	4		T299	2		T302	2
auto[1]	values[4]	values[6]	17	1			T221	4		T283	1		T284	3
auto[1]	values[4]	values[7]	11	1			T283	1		T303	4		T304	2
auto[1]	values[5]	values[0]	9	1			T22	1		T190	1		T201	1
auto[1]	values[5]	values[1]	8	1			T52	1		T18	1		T22	1
auto[1]	values[5]	values[2]	11	1			T261	4		T272	6		T305	1
auto[1]	values[5]	values[3]	10	1			T22	1		T202	1		T240	1
auto[1]	values[5]	values[4]	18	1			T22	5		T189	3		T287	3
auto[1]	values[5]	values[5]	15	1			T46	3		T51	2		T205	2
auto[1]	values[5]	values[6]	18	1			T240	1		T236	1		T306	1
auto[1]	values[5]	values[7]	14	1			T18	4		T269	2		T233	1
auto[1]	values[6]	values[0]	10	1			T66	3		T223	2		T261	1
auto[1]	values[6]	values[1]	8	1			T234	1		T160	5		T307	2
auto[1]	values[6]	values[2]	7	1			T200	1		T227	1		T308	1
auto[1]	values[6]	values[3]	4	1			T53	2		T233	1		T195	1
auto[1]	values[6]	values[4]	9	1			T282	1		T294	4		T286	1
auto[1]	values[6]	values[5]	11	1			T15	2		T212	1		T209	1
auto[1]	values[6]	values[6]	15	1			T18	1		T53	1		T283	2
auto[1]	values[6]	values[7]	25	1			T139	3		T240	1		T208	2
auto[1]	values[7]	values[0]	17	1			T63	1		T139	3		T200	3
auto[1]	values[7]	values[1]	26	1			T45	1		T200	4		T230	3
auto[1]	values[7]	values[2]	14	1			T53	3		T212	1		T306	2
auto[1]	values[7]	values[3]	19	1			T218	3		T212	3		T195	3
auto[1]	values[7]	values[4]	18	1			T203	4		T37	3		T283	1
auto[1]	values[7]	values[5]	16	1			T188	1		T309	2		T227	1
auto[1]	values[7]	values[6]	9	1			T53	1		T189	1		T203	2
auto[1]	values[7]	values[7]	12	1			T218	3		T190	2		T188	3