Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	867	1			T8	4		T11	17		T70	21
all_values[1]	867	1			T8	4		T11	17		T70	21
all_values[2]	867	1			T8	4		T11	17		T70	21
all_values[3]	867	1			T8	4		T11	17		T70	21
all_values[4]	867	1			T8	4		T11	17		T70	21
all_values[5]	867	1			T8	4		T11	17		T70	21
all_values[6]	867	1			T8	4		T11	17		T70	21
all_values[7]	867	1			T8	4		T11	17		T70	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3732

1

T8

21

T11

64

T70

88

auto[1]

3204

1

T8

11

T11

72

T70

80

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2714

1

T8

15

T11

48

T70

58

auto[1]

4222

1

T8

17

T11

88

T70

110

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3908

1

T8

20

T11

77

T70

94

auto[1]

3028

1

T8

12

T11

59

T70

74

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	202	1			T8	2		T11	3		T70	5
all_values[0]	auto[0]	auto[0]	auto[1]	93	1			T70	3		T17	1		T18	3
all_values[0]	auto[0]	auto[1]	auto[0]	150	1			T8	2		T11	1		T70	3
all_values[0]	auto[0]	auto[1]	auto[1]	77	1			T11	3		T70	1		T21	2
all_values[0]	auto[1]	auto[0]	auto[1]	189	1			T11	2		T70	5		T17	3
all_values[0]	auto[1]	auto[1]	auto[1]	156	1			T11	8		T70	4		T17	2
all_values[1]	auto[0]	auto[0]	auto[0]	165	1			T11	4		T70	5		T17	1
all_values[1]	auto[0]	auto[0]	auto[1]	97	1			T8	2		T11	4		T70	3
all_values[1]	auto[0]	auto[1]	auto[0]	142	1			T11	1		T70	4		T17	5
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T17	2		T19	1		T21	2
all_values[1]	auto[1]	auto[0]	auto[1]	220	1			T11	7		T70	5		T17	3
all_values[1]	auto[1]	auto[1]	auto[1]	158	1			T8	2		T11	1		T70	4
all_values[2]	auto[0]	auto[0]	auto[0]	155	1			T8	1		T11	1		T70	1
all_values[2]	auto[0]	auto[0]	auto[1]	89	1			T11	1		T70	3		T17	3
all_values[2]	auto[0]	auto[1]	auto[0]	150	1			T11	2		T70	4		T19	2
all_values[2]	auto[0]	auto[1]	auto[1]	83	1			T8	1		T11	2		T70	4
all_values[2]	auto[1]	auto[0]	auto[1]	213	1			T8	1		T11	4		T70	5
all_values[2]	auto[1]	auto[1]	auto[1]	177	1			T8	1		T11	7		T70	4
all_values[3]	auto[0]	auto[0]	auto[0]	174	1			T8	1		T11	1		T70	4
all_values[3]	auto[0]	auto[0]	auto[1]	80	1			T11	2		T70	2		T19	1
all_values[3]	auto[0]	auto[1]	auto[0]	130	1			T11	3		T70	2		T17	2
all_values[3]	auto[0]	auto[1]	auto[1]	87	1			T8	1		T11	3		T70	5
all_values[3]	auto[1]	auto[0]	auto[1]	210	1			T8	1		T11	5		T70	4
all_values[3]	auto[1]	auto[1]	auto[1]	186	1			T8	1		T11	3		T70	4
all_values[4]	auto[0]	auto[0]	auto[0]	174	1			T8	4		T11	6		T70	4
all_values[4]	auto[0]	auto[0]	auto[1]	75	1			T11	1		T70	2		T17	2
all_values[4]	auto[0]	auto[1]	auto[0]	165	1			T11	3		T70	3		T17	2
all_values[4]	auto[0]	auto[1]	auto[1]	83	1			T11	4		T70	1		T17	1
all_values[4]	auto[1]	auto[0]	auto[1]	186	1			T11	1		T70	3		T17	3
all_values[4]	auto[1]	auto[1]	auto[1]	184	1			T11	2		T70	8		T17	1
all_values[5]	auto[0]	auto[0]	auto[0]	253	1			T8	2		T11	3		T70	5
all_values[5]	auto[0]	auto[1]	auto[0]	225	1			T11	7		T70	7		T17	3
all_values[5]	auto[1]	auto[0]	auto[1]	229	1			T8	1		T11	5		T70	7
all_values[5]	auto[1]	auto[1]	auto[1]	160	1			T8	1		T11	2		T70	2
all_values[6]	auto[0]	auto[0]	auto[0]	167	1			T8	2		T11	2		T70	2
all_values[6]	auto[0]	auto[0]	auto[1]	88	1			T11	1		T70	4		T17	2
all_values[6]	auto[0]	auto[1]	auto[0]	113	1			T11	3		T70	2		T17	2
all_values[6]	auto[0]	auto[1]	auto[1]	102	1			T11	5		T70	4		T17	3
all_values[6]	auto[1]	auto[0]	auto[1]	219	1			T8	1		T11	5		T70	3
all_values[6]	auto[1]	auto[1]	auto[1]	178	1			T8	1		T11	1		T70	6
all_values[7]	auto[0]	auto[0]	auto[0]	186	1			T11	2		T70	5		T17	1
all_values[7]	auto[0]	auto[0]	auto[1]	90	1			T8	1		T11	2		T70	4
all_values[7]	auto[0]	auto[1]	auto[0]	163	1			T8	1		T11	6		T70	2
all_values[7]	auto[0]	auto[1]	auto[1]	65	1			T11	1		T22	1		T34	1
all_values[7]	auto[1]	auto[0]	auto[1]	178	1			T8	2		T11	2		T70	4
all_values[7]	auto[1]	auto[1]	auto[1]	185	1			T11	4		T70	6		T17	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal