Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1623

1

T1

7

T6

11

T7

15

auto[1]

1673

1

T1

3

T6

3

T7

9

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1701

1

T1

7

T6

14

T8

12

auto[1]

1595

1

T1

3

T7

24

T29

13

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2646

1

T1

10

T6

11

T7

24

auto[1]

650

1

T6

3

T8

6

T27

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	692	1			T1	1		T6	7		T7	4
valid[1]	675	1			T1	1		T6	3		T7	3
valid[2]	650	1			T1	4		T7	4		T8	2
valid[3]	652	1			T1	2		T6	2		T7	6
valid[4]	627	1			T1	2		T6	2		T7	7

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	104	1			T6	5		T8	1		T56	1
auto[0]	auto[0]	valid[0]	auto[1]	163	1			T7	3		T29	3		T30	1
auto[0]	auto[0]	valid[1]	auto[0]	107	1			T6	2		T57	3		T329	2
auto[0]	auto[0]	valid[1]	auto[1]	166	1			T1	1		T7	3		T29	2
auto[0]	auto[0]	valid[2]	auto[0]	102	1			T1	2		T56	1		T51	1
auto[0]	auto[0]	valid[2]	auto[1]	174	1			T1	2		T7	2		T29	2
auto[0]	auto[0]	valid[3]	auto[0]	99	1			T1	2		T8	1		T27	1
auto[0]	auto[0]	valid[3]	auto[1]	145	1			T7	2		T29	1		T30	1
auto[0]	auto[0]	valid[4]	auto[0]	91	1			T6	2		T56	1		T51	2
auto[0]	auto[0]	valid[4]	auto[1]	142	1			T7	5		T30	2		T31	1
auto[0]	auto[1]	valid[0]	auto[0]	116	1			T1	1		T6	2		T8	3
auto[0]	auto[1]	valid[0]	auto[1]	167	1			T7	1		T29	1		T30	1
auto[0]	auto[1]	valid[1]	auto[0]	94	1			T27	1		T56	1		T57	2
auto[0]	auto[1]	valid[1]	auto[1]	166	1			T29	1		T31	4		T17	2
auto[0]	auto[1]	valid[2]	auto[0]	112	1			T27	1		T51	3		T18	1
auto[0]	auto[1]	valid[2]	auto[1]	147	1			T7	2		T29	1		T30	1
auto[0]	auto[1]	valid[3]	auto[0]	103	1			T8	1		T17	1		T56	1
auto[0]	auto[1]	valid[3]	auto[1]	161	1			T7	4		T29	1		T30	2
auto[0]	auto[1]	valid[4]	auto[0]	123	1			T1	2		T56	2		T57	2
auto[0]	auto[1]	valid[4]	auto[1]	164	1			T7	2		T29	1		T30	1
auto[1]	auto[0]	valid[0]	auto[0]	72	1			T27	1		T51	1		T18	3
auto[1]	auto[0]	valid[1]	auto[0]	73	1			T8	1		T27	1		T51	4
auto[1]	auto[0]	valid[2]	auto[0]	66	1			T27	1		T51	1		T335	1
auto[1]	auto[0]	valid[3]	auto[0]	64	1			T6	2		T27	1		T56	1
auto[1]	auto[0]	valid[4]	auto[0]	55	1			T17	1		T56	1		T51	1
auto[1]	auto[1]	valid[0]	auto[0]	70	1			T27	1		T17	1		T57	1
auto[1]	auto[1]	valid[1]	auto[0]	69	1			T6	1		T27	1		T51	1
auto[1]	auto[1]	valid[2]	auto[0]	49	1			T8	2		T51	1		T52	1
auto[1]	auto[1]	valid[3]	auto[0]	80	1			T8	1		T51	1		T18	1
auto[1]	auto[1]	valid[4]	auto[0]	52	1			T8	2		T17	1		T51	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal