Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43846

1

T1

173

T6

350

T8

345

auto[1]

16387

1

T1

36

T7

245

T8

32

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44358

1

T1

158

T6

242

T7

245

auto[1]

15875

1

T1

51

T6

108

T8

134

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	30969	1			T1	114		T6	169		T7	120
others[1]	5073	1			T1	17		T6	35		T7	22
others[2]	5168	1			T1	16		T6	40		T7	22
others[3]	5780	1			T1	17		T6	40		T7	29
interest[1]	3400	1			T1	12		T6	17		T7	18
interest[4]	20266	1			T1	77		T6	109		T7	73
interest[64]	9843	1			T1	33		T6	49		T7	34

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14263	1			T1	63		T6	120		T8	110
auto[0]	auto[0]	others[1]	2327	1			T1	10		T6	26		T8	17
auto[0]	auto[0]	others[2]	2491	1			T1	11		T6	27		T8	21
auto[0]	auto[0]	others[3]	2742	1			T1	10		T6	28		T8	15
auto[0]	auto[0]	interest[1]	1570	1			T1	8		T6	11		T8	16
auto[0]	auto[0]	interest[4]	9286	1			T1	44		T6	80		T8	70
auto[0]	auto[0]	interest[64]	4578	1			T1	20		T6	30		T8	32
auto[0]	auto[1]	others[0]	8528	1			T1	22		T7	120		T8	19
auto[0]	auto[1]	others[1]	1421	1			T1	2		T7	22		T8	3
auto[0]	auto[1]	others[2]	1352	1			T1	2		T7	22		T8	3
auto[0]	auto[1]	others[3]	1492	1			T1	4		T7	29		T8	1
auto[0]	auto[1]	interest[1]	946	1			T1	2		T7	18		T8	1
auto[0]	auto[1]	interest[4]	5691	1			T1	14		T7	73		T8	8
auto[0]	auto[1]	interest[64]	2648	1			T1	4		T7	34		T8	5
auto[1]	auto[0]	others[0]	8178	1			T1	29		T6	49		T8	80
auto[1]	auto[0]	others[1]	1325	1			T1	5		T6	9		T8	6
auto[1]	auto[0]	others[2]	1325	1			T1	3		T6	13		T8	11
auto[1]	auto[0]	others[3]	1546	1			T1	3		T6	12		T8	13
auto[1]	auto[0]	interest[1]	884	1			T1	2		T6	6		T8	7
auto[1]	auto[0]	interest[4]	5289	1			T1	19		T6	29		T8	48
auto[1]	auto[0]	interest[64]	2617	1			T1	9		T6	19		T8	17

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal