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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1150
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T111 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3328318558 Aug 13 05:41:26 PM PDT 24 Aug 13 05:41:29 PM PDT 24 55309001 ps
T1036 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1219592657 Aug 13 05:41:35 PM PDT 24 Aug 13 05:41:37 PM PDT 24 58844613 ps
T117 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3359567686 Aug 13 05:41:16 PM PDT 24 Aug 13 05:41:30 PM PDT 24 1980469605 ps
T118 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2417163969 Aug 13 05:41:45 PM PDT 24 Aug 13 05:41:47 PM PDT 24 114521513 ps
T1037 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2047182302 Aug 13 05:41:49 PM PDT 24 Aug 13 05:41:50 PM PDT 24 12826553 ps
T1038 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.808517977 Aug 13 05:41:52 PM PDT 24 Aug 13 05:41:55 PM PDT 24 286620672 ps
T1039 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2685952655 Aug 13 05:41:25 PM PDT 24 Aug 13 05:41:29 PM PDT 24 58676341 ps
T126 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4095956258 Aug 13 05:41:26 PM PDT 24 Aug 13 05:41:28 PM PDT 24 71571810 ps
T155 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2203834363 Aug 13 05:40:55 PM PDT 24 Aug 13 05:41:04 PM PDT 24 1625362438 ps
T116 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.526995327 Aug 13 05:41:10 PM PDT 24 Aug 13 05:41:13 PM PDT 24 90880680 ps
T127 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.442163312 Aug 13 05:41:15 PM PDT 24 Aug 13 05:41:17 PM PDT 24 579298190 ps
T1040 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.477763483 Aug 13 05:41:49 PM PDT 24 Aug 13 05:41:50 PM PDT 24 12374077 ps
T1041 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1214825177 Aug 13 05:41:51 PM PDT 24 Aug 13 05:41:52 PM PDT 24 18800638 ps
T113 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.968566001 Aug 13 05:41:53 PM PDT 24 Aug 13 05:41:56 PM PDT 24 130449511 ps
T1042 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2706405102 Aug 13 05:41:53 PM PDT 24 Aug 13 05:41:54 PM PDT 24 43032690 ps
T168 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2934188706 Aug 13 05:41:42 PM PDT 24 Aug 13 05:41:58 PM PDT 24 605670658 ps
T1043 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3924036694 Aug 13 05:41:52 PM PDT 24 Aug 13 05:41:53 PM PDT 24 62805239 ps
T1044 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1090275853 Aug 13 05:41:16 PM PDT 24 Aug 13 05:41:29 PM PDT 24 4016073507 ps
T1045 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3853302735 Aug 13 05:41:58 PM PDT 24 Aug 13 05:41:59 PM PDT 24 56094209 ps
T1046 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.102827216 Aug 13 05:41:38 PM PDT 24 Aug 13 05:41:39 PM PDT 24 19524770 ps
T129 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2996433102 Aug 13 05:40:52 PM PDT 24 Aug 13 05:41:04 PM PDT 24 785911529 ps
T1047 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3874125291 Aug 13 05:41:45 PM PDT 24 Aug 13 05:41:46 PM PDT 24 15097655 ps
T1048 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2864583339 Aug 13 05:42:01 PM PDT 24 Aug 13 05:42:01 PM PDT 24 118266047 ps
T1049 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3572179143 Aug 13 05:41:09 PM PDT 24 Aug 13 05:41:10 PM PDT 24 19242303 ps
T1050 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2097235744 Aug 13 05:41:59 PM PDT 24 Aug 13 05:42:00 PM PDT 24 28379799 ps
T1051 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3766808800 Aug 13 05:41:53 PM PDT 24 Aug 13 05:41:54 PM PDT 24 11387008 ps
T1052 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1242505695 Aug 13 05:41:11 PM PDT 24 Aug 13 05:41:12 PM PDT 24 13269612 ps
T173 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3328204078 Aug 13 05:41:08 PM PDT 24 Aug 13 05:41:15 PM PDT 24 200776936 ps
T1053 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2545236088 Aug 13 05:41:43 PM PDT 24 Aug 13 05:41:45 PM PDT 24 51877920 ps
T1054 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.824744463 Aug 13 05:41:16 PM PDT 24 Aug 13 05:41:20 PM PDT 24 164828165 ps
T1055 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1623108742 Aug 13 05:41:24 PM PDT 24 Aug 13 05:41:25 PM PDT 24 11122658 ps
T1056 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1095478920 Aug 13 05:41:33 PM PDT 24 Aug 13 05:41:36 PM PDT 24 215982070 ps
T105 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3573955571 Aug 13 05:41:36 PM PDT 24 Aug 13 05:41:40 PM PDT 24 460154940 ps
T107 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.336099134 Aug 13 05:41:45 PM PDT 24 Aug 13 05:41:50 PM PDT 24 565330752 ps
T156 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2171091712 Aug 13 05:41:15 PM PDT 24 Aug 13 05:41:18 PM PDT 24 102397411 ps
T1057 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.478637639 Aug 13 05:41:01 PM PDT 24 Aug 13 05:41:02 PM PDT 24 220786853 ps
T109 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3971924951 Aug 13 05:41:24 PM PDT 24 Aug 13 05:41:28 PM PDT 24 103651716 ps
T88 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.579007356 Aug 13 05:40:53 PM PDT 24 Aug 13 05:40:55 PM PDT 24 21181719 ps
T1058 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1952117637 Aug 13 05:41:36 PM PDT 24 Aug 13 05:41:38 PM PDT 24 179530925 ps
T1059 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.914263663 Aug 13 05:41:16 PM PDT 24 Aug 13 05:41:17 PM PDT 24 48636070 ps
T108 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2186460504 Aug 13 05:41:36 PM PDT 24 Aug 13 05:41:40 PM PDT 24 61103668 ps
T1060 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3633492546 Aug 13 05:41:24 PM PDT 24 Aug 13 05:41:25 PM PDT 24 45208484 ps
T157 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3090650627 Aug 13 05:41:44 PM PDT 24 Aug 13 05:41:58 PM PDT 24 672199578 ps
T128 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.952975671 Aug 13 05:41:18 PM PDT 24 Aug 13 05:41:20 PM PDT 24 78741250 ps
T130 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1896793014 Aug 13 05:41:16 PM PDT 24 Aug 13 05:41:32 PM PDT 24 1223019562 ps
T131 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1866730001 Aug 13 05:41:12 PM PDT 24 Aug 13 05:41:14 PM PDT 24 241848159 ps
T158 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1962159019 Aug 13 05:40:52 PM PDT 24 Aug 13 05:40:56 PM PDT 24 151008344 ps
T132 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.444426277 Aug 13 05:41:24 PM PDT 24 Aug 13 05:41:27 PM PDT 24 67023773 ps
T1061 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1601518884 Aug 13 05:41:53 PM PDT 24 Aug 13 05:41:54 PM PDT 24 46097596 ps
T1062 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.587362116 Aug 13 05:41:35 PM PDT 24 Aug 13 05:41:36 PM PDT 24 16653089 ps
T1063 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1369293298 Aug 13 05:41:01 PM PDT 24 Aug 13 05:41:02 PM PDT 24 30942761 ps
T1064 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3878637365 Aug 13 05:41:51 PM PDT 24 Aug 13 05:41:52 PM PDT 24 13315647 ps
T1065 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1873643586 Aug 13 05:41:16 PM PDT 24 Aug 13 05:41:20 PM PDT 24 769485818 ps
T1066 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3998508542 Aug 13 05:41:52 PM PDT 24 Aug 13 05:41:53 PM PDT 24 47108343 ps
T1067 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.317919786 Aug 13 05:41:08 PM PDT 24 Aug 13 05:41:11 PM PDT 24 56940366 ps
T1068 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1215499740 Aug 13 05:41:26 PM PDT 24 Aug 13 05:41:27 PM PDT 24 13275664 ps
T1069 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3903507054 Aug 13 05:41:01 PM PDT 24 Aug 13 05:41:03 PM PDT 24 31287334 ps
T1070 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4365318 Aug 13 05:41:25 PM PDT 24 Aug 13 05:41:28 PM PDT 24 169925113 ps
T1071 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2885774339 Aug 13 05:41:43 PM PDT 24 Aug 13 05:41:45 PM PDT 24 28348497 ps
T1072 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1872145877 Aug 13 05:41:58 PM PDT 24 Aug 13 05:41:59 PM PDT 24 11618974 ps
T1073 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3204735085 Aug 13 05:41:24 PM PDT 24 Aug 13 05:41:27 PM PDT 24 131762023 ps
T1074 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3859759549 Aug 13 05:40:53 PM PDT 24 Aug 13 05:40:56 PM PDT 24 309580917 ps
T1075 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3289446390 Aug 13 05:42:00 PM PDT 24 Aug 13 05:42:00 PM PDT 24 12534310 ps
T106 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.840180058 Aug 13 05:40:53 PM PDT 24 Aug 13 05:40:58 PM PDT 24 214497256 ps
T1076 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.48811532 Aug 13 05:41:16 PM PDT 24 Aug 13 05:41:19 PM PDT 24 34558934 ps
T1077 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2070176489 Aug 13 05:41:36 PM PDT 24 Aug 13 05:41:45 PM PDT 24 377126390 ps
T114 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.614660655 Aug 13 05:41:26 PM PDT 24 Aug 13 05:41:28 PM PDT 24 88175688 ps
T1078 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1012467877 Aug 13 05:41:59 PM PDT 24 Aug 13 05:42:00 PM PDT 24 50364960 ps
T169 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1867654415 Aug 13 05:40:56 PM PDT 24 Aug 13 05:41:11 PM PDT 24 547779502 ps
T1079 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2478911771 Aug 13 05:41:51 PM PDT 24 Aug 13 05:41:52 PM PDT 24 28399167 ps
T1080 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1919351056 Aug 13 05:41:14 PM PDT 24 Aug 13 05:41:15 PM PDT 24 35803975 ps
T1081 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.592690483 Aug 13 05:41:16 PM PDT 24 Aug 13 05:41:41 PM PDT 24 2518906781 ps
T1082 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.17257112 Aug 13 05:41:53 PM PDT 24 Aug 13 05:41:53 PM PDT 24 16122119 ps
T1083 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2935411787 Aug 13 05:41:16 PM PDT 24 Aug 13 05:41:18 PM PDT 24 72540199 ps
T115 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3866808941 Aug 13 05:41:13 PM PDT 24 Aug 13 05:41:15 PM PDT 24 645983574 ps
T174 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2687078428 Aug 13 05:40:53 PM PDT 24 Aug 13 05:41:08 PM PDT 24 1119759405 ps
T1084 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.376603275 Aug 13 05:41:51 PM PDT 24 Aug 13 05:41:52 PM PDT 24 16270063 ps
T1085 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3065185647 Aug 13 05:41:36 PM PDT 24 Aug 13 05:41:38 PM PDT 24 48967690 ps
T170 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2080189560 Aug 13 05:41:43 PM PDT 24 Aug 13 05:42:00 PM PDT 24 2277318743 ps
T1086 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2906704700 Aug 13 05:41:44 PM PDT 24 Aug 13 05:41:46 PM PDT 24 360715991 ps
T1087 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.223639606 Aug 13 05:41:52 PM PDT 24 Aug 13 05:41:53 PM PDT 24 36305246 ps
T1088 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.959630297 Aug 13 05:41:02 PM PDT 24 Aug 13 05:41:03 PM PDT 24 20668938 ps
T1089 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4044858140 Aug 13 05:41:43 PM PDT 24 Aug 13 05:41:45 PM PDT 24 80537135 ps
T1090 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1823239558 Aug 13 05:41:10 PM PDT 24 Aug 13 05:41:12 PM PDT 24 229341616 ps
T1091 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1295195926 Aug 13 05:41:53 PM PDT 24 Aug 13 05:41:54 PM PDT 24 45379780 ps
T1092 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3821793242 Aug 13 05:41:44 PM PDT 24 Aug 13 05:41:45 PM PDT 24 155806509 ps
T1093 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1075227368 Aug 13 05:41:49 PM PDT 24 Aug 13 05:41:52 PM PDT 24 490780977 ps
T1094 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1354390811 Aug 13 05:41:55 PM PDT 24 Aug 13 05:41:56 PM PDT 24 12856795 ps
T1095 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2091223486 Aug 13 05:41:27 PM PDT 24 Aug 13 05:41:29 PM PDT 24 398120776 ps
T1096 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1730090175 Aug 13 05:41:44 PM PDT 24 Aug 13 05:41:51 PM PDT 24 300762511 ps
T1097 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2949965086 Aug 13 05:41:47 PM PDT 24 Aug 13 05:41:50 PM PDT 24 489530798 ps
T1098 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1733443578 Aug 13 05:41:37 PM PDT 24 Aug 13 05:41:40 PM PDT 24 324868504 ps
T172 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1082919789 Aug 13 05:41:28 PM PDT 24 Aug 13 05:41:34 PM PDT 24 102673796 ps
T1099 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3937394714 Aug 13 05:41:53 PM PDT 24 Aug 13 05:41:54 PM PDT 24 17929708 ps
T1100 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1216560919 Aug 13 05:41:37 PM PDT 24 Aug 13 05:41:50 PM PDT 24 951660756 ps
T1101 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.420145460 Aug 13 05:41:43 PM PDT 24 Aug 13 05:41:47 PM PDT 24 56047811 ps
T1102 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2314668712 Aug 13 05:40:53 PM PDT 24 Aug 13 05:40:57 PM PDT 24 142730501 ps
T1103 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1750420377 Aug 13 05:41:58 PM PDT 24 Aug 13 05:41:58 PM PDT 24 27921280 ps
T1104 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2046455407 Aug 13 05:41:36 PM PDT 24 Aug 13 05:41:39 PM PDT 24 210664062 ps
T110 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.572024912 Aug 13 05:41:42 PM PDT 24 Aug 13 05:41:47 PM PDT 24 351235409 ps
T1105 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2613891559 Aug 13 05:41:41 PM PDT 24 Aug 13 05:41:45 PM PDT 24 96948856 ps
T1106 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2631001406 Aug 13 05:41:36 PM PDT 24 Aug 13 05:41:37 PM PDT 24 119048222 ps
T1107 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1144662262 Aug 13 05:41:50 PM PDT 24 Aug 13 05:41:52 PM PDT 24 348107692 ps
T89 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1828990678 Aug 13 05:40:59 PM PDT 24 Aug 13 05:41:01 PM PDT 24 48620381 ps
T171 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1833304195 Aug 13 05:41:37 PM PDT 24 Aug 13 05:42:02 PM PDT 24 1068204361 ps
T1108 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.755309983 Aug 13 05:41:01 PM PDT 24 Aug 13 05:41:08 PM PDT 24 396888274 ps
T1109 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1104628023 Aug 13 05:41:36 PM PDT 24 Aug 13 05:41:38 PM PDT 24 62355022 ps
T1110 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.706242305 Aug 13 05:41:51 PM PDT 24 Aug 13 05:41:54 PM PDT 24 153076377 ps
T1111 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3871088028 Aug 13 05:41:35 PM PDT 24 Aug 13 05:41:38 PM PDT 24 81598469 ps
T1112 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.761804997 Aug 13 05:41:46 PM PDT 24 Aug 13 05:41:49 PM PDT 24 85984144 ps
T1113 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1964397273 Aug 13 05:41:36 PM PDT 24 Aug 13 05:41:54 PM PDT 24 1144411781 ps
T1114 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.196442912 Aug 13 05:41:01 PM PDT 24 Aug 13 05:41:03 PM PDT 24 42263654 ps
T1115 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2703841209 Aug 13 05:41:51 PM PDT 24 Aug 13 05:41:54 PM PDT 24 92408283 ps
T1116 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3606545467 Aug 13 05:41:27 PM PDT 24 Aug 13 05:41:29 PM PDT 24 151724971 ps
T90 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1856321554 Aug 13 05:41:09 PM PDT 24 Aug 13 05:41:11 PM PDT 24 196104764 ps
T1117 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.392372635 Aug 13 05:41:36 PM PDT 24 Aug 13 05:41:38 PM PDT 24 30807563 ps
T1118 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.950790336 Aug 13 05:41:36 PM PDT 24 Aug 13 05:41:37 PM PDT 24 36395419 ps
T1119 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.36618394 Aug 13 05:41:15 PM PDT 24 Aug 13 05:41:18 PM PDT 24 315489073 ps
T1120 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.271209969 Aug 13 05:41:09 PM PDT 24 Aug 13 05:41:10 PM PDT 24 165927147 ps
T1121 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1207755229 Aug 13 05:41:17 PM PDT 24 Aug 13 05:41:29 PM PDT 24 1190444936 ps
T175 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1832385015 Aug 13 05:41:52 PM PDT 24 Aug 13 05:42:00 PM PDT 24 439967965 ps
T1122 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.419031069 Aug 13 05:41:42 PM PDT 24 Aug 13 05:41:55 PM PDT 24 789476774 ps
T1123 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.570085238 Aug 13 05:41:25 PM PDT 24 Aug 13 05:41:26 PM PDT 24 56738915 ps
T1124 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1170697892 Aug 13 05:41:51 PM PDT 24 Aug 13 05:41:52 PM PDT 24 11916815 ps
T1125 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1876114692 Aug 13 05:41:35 PM PDT 24 Aug 13 05:41:39 PM PDT 24 306963739 ps
T1126 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1435584542 Aug 13 05:41:58 PM PDT 24 Aug 13 05:41:59 PM PDT 24 44886306 ps
T1127 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3006141761 Aug 13 05:41:35 PM PDT 24 Aug 13 05:41:39 PM PDT 24 122487234 ps
T1128 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4127252022 Aug 13 05:41:26 PM PDT 24 Aug 13 05:41:39 PM PDT 24 196249525 ps
T1129 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1191250214 Aug 13 05:41:53 PM PDT 24 Aug 13 05:41:54 PM PDT 24 13629383 ps
T1130 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1392703823 Aug 13 05:41:07 PM PDT 24 Aug 13 05:41:08 PM PDT 24 126245709 ps
T1131 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3715760089 Aug 13 05:41:16 PM PDT 24 Aug 13 05:41:23 PM PDT 24 96627739 ps
T1132 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1164666800 Aug 13 05:41:37 PM PDT 24 Aug 13 05:41:38 PM PDT 24 21028253 ps
T1133 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1362501867 Aug 13 05:40:55 PM PDT 24 Aug 13 05:40:56 PM PDT 24 38402164 ps
T1134 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1601517762 Aug 13 05:41:25 PM PDT 24 Aug 13 05:41:28 PM PDT 24 160855171 ps
T1135 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3321219156 Aug 13 05:41:38 PM PDT 24 Aug 13 05:41:39 PM PDT 24 23026898 ps
T1136 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2988391229 Aug 13 05:41:42 PM PDT 24 Aug 13 05:41:46 PM PDT 24 212617648 ps
T1137 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.719202172 Aug 13 05:41:25 PM PDT 24 Aug 13 05:41:26 PM PDT 24 23046161 ps
T1138 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2771372553 Aug 13 05:40:53 PM PDT 24 Aug 13 05:40:54 PM PDT 24 147119471 ps
T1139 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1354033787 Aug 13 05:41:24 PM PDT 24 Aug 13 05:41:25 PM PDT 24 79217178 ps
T1140 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1637049844 Aug 13 05:41:34 PM PDT 24 Aug 13 05:41:36 PM PDT 24 77819679 ps
T1141 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.341719511 Aug 13 05:41:51 PM PDT 24 Aug 13 05:41:51 PM PDT 24 44275785 ps
T1142 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3833961030 Aug 13 05:42:00 PM PDT 24 Aug 13 05:42:01 PM PDT 24 12632560 ps
T1143 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3693338698 Aug 13 05:41:43 PM PDT 24 Aug 13 05:41:47 PM PDT 24 612022816 ps
T1144 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1621414566 Aug 13 05:41:43 PM PDT 24 Aug 13 05:41:44 PM PDT 24 13611829 ps
T1145 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2024596446 Aug 13 05:41:08 PM PDT 24 Aug 13 05:41:45 PM PDT 24 1880755769 ps
T1146 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1107296529 Aug 13 05:40:52 PM PDT 24 Aug 13 05:40:54 PM PDT 24 172439279 ps
T1147 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1468391161 Aug 13 05:41:51 PM PDT 24 Aug 13 05:41:52 PM PDT 24 12354202 ps
T1148 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3962605102 Aug 13 05:40:53 PM PDT 24 Aug 13 05:40:54 PM PDT 24 54570032 ps
T1149 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2834911972 Aug 13 05:41:44 PM PDT 24 Aug 13 05:41:45 PM PDT 24 14094388 ps
T1150 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1884947712 Aug 13 05:41:11 PM PDT 24 Aug 13 05:41:14 PM PDT 24 103835295 ps


Test location /workspace/coverage/default/39.spi_device_stress_all.4075350577
Short name T8
Test name
Test status
Simulation time 33586786648 ps
CPU time 320.14 seconds
Started Aug 13 05:53:06 PM PDT 24
Finished Aug 13 05:58:26 PM PDT 24
Peak memory 263048 kb
Host smart-e6f1aacc-645a-469f-8066-ce419725fe34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075350577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4075350577
Directory /workspace/39.spi_device_stress_all/latest


Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1138882386
Short name T27
Test name
Test status
Simulation time 46818917810 ps
CPU time 424.8 seconds
Started Aug 13 05:52:51 PM PDT 24
Finished Aug 13 05:59:55 PM PDT 24
Peak memory 256536 kb
Host smart-ce518117-525a-4ee0-8a14-d5ad679aabd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138882386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1138882386
Directory /workspace/36.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/46.spi_device_stress_all.3627446279
Short name T18
Test name
Test status
Simulation time 43409908110 ps
CPU time 428.3 seconds
Started Aug 13 05:53:44 PM PDT 24
Finished Aug 13 06:00:53 PM PDT 24
Peak memory 265736 kb
Host smart-810ee65d-73ea-4fa1-9460-de5dabbb5baf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627446279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3627446279
Directory /workspace/46.spi_device_stress_all/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2476105456
Short name T103
Test name
Test status
Simulation time 3185794449 ps
CPU time 7.32 seconds
Started Aug 13 05:41:44 PM PDT 24
Finished Aug 13 05:41:51 PM PDT 24
Peak memory 216044 kb
Host smart-14636dd9-05b3-4d78-85c1-71ef5d2855e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476105456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2476105456
Directory /workspace/16.spi_device_tl_intg_err/latest


Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1774453719
Short name T51
Test name
Test status
Simulation time 11238076880 ps
CPU time 70.78 seconds
Started Aug 13 05:48:53 PM PDT 24
Finished Aug 13 05:50:04 PM PDT 24
Peak memory 251264 kb
Host smart-6e972102-a500-4e96-ba01-fd7cf4b94201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774453719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1774453719
Directory /workspace/1.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2635463287
Short name T142
Test name
Test status
Simulation time 133628038395 ps
CPU time 395.19 seconds
Started Aug 13 05:50:03 PM PDT 24
Finished Aug 13 05:56:38 PM PDT 24
Peak memory 266656 kb
Host smart-911ec7e2-3348-42e8-a037-02b39bad1c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635463287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2635463287
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/0.spi_device_ram_cfg.3846018235
Short name T71
Test name
Test status
Simulation time 28370812 ps
CPU time 0.78 seconds
Started Aug 13 05:48:32 PM PDT 24
Finished Aug 13 05:48:33 PM PDT 24
Peak memory 216264 kb
Host smart-ce3d4e8b-6f95-40ca-9093-1c9af8bec777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846018235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3846018235
Directory /workspace/0.spi_device_ram_cfg/latest


Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.4189073252
Short name T191
Test name
Test status
Simulation time 64556621968 ps
CPU time 622.28 seconds
Started Aug 13 05:49:55 PM PDT 24
Finished Aug 13 06:00:18 PM PDT 24
Peak memory 254324 kb
Host smart-a6da71fa-ec04-4757-8ebe-af318904365e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189073252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.4189073252
Directory /workspace/9.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/21.spi_device_flash_all.4160017155
Short name T45
Test name
Test status
Simulation time 196276408270 ps
CPU time 170 seconds
Started Aug 13 05:51:19 PM PDT 24
Finished Aug 13 05:54:09 PM PDT 24
Peak memory 268768 kb
Host smart-8695bcac-acfe-4277-84d5-906d585b6a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160017155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4160017155
Directory /workspace/21.spi_device_flash_all/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3968857548
Short name T101
Test name
Test status
Simulation time 878018271 ps
CPU time 5.46 seconds
Started Aug 13 05:41:43 PM PDT 24
Finished Aug 13 05:41:48 PM PDT 24
Peak memory 216260 kb
Host smart-a06774c3-4fb5-41ef-8a58-ed881b106070
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968857548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3968857548
Directory /workspace/13.spi_device_tl_errors/latest


Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3543930426
Short name T185
Test name
Test status
Simulation time 65666701971 ps
CPU time 345.32 seconds
Started Aug 13 05:53:53 PM PDT 24
Finished Aug 13 05:59:39 PM PDT 24
Peak memory 258772 kb
Host smart-830f1de9-5c9a-4624-98de-53cd99bcd8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543930426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3543930426
Directory /workspace/47.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/32.spi_device_stress_all.1564920650
Short name T22
Test name
Test status
Simulation time 36958373238 ps
CPU time 319.21 seconds
Started Aug 13 05:52:26 PM PDT 24
Finished Aug 13 05:57:46 PM PDT 24
Peak memory 281876 kb
Host smart-1c6728f6-1d95-440e-95d8-9f18e35ebbac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564920650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1564920650
Directory /workspace/32.spi_device_stress_all/latest


Test location /workspace/coverage/default/0.spi_device_flash_mode.2349830688
Short name T119
Test name
Test status
Simulation time 833152511 ps
CPU time 20.31 seconds
Started Aug 13 05:48:40 PM PDT 24
Finished Aug 13 05:49:01 PM PDT 24
Peak memory 237220 kb
Host smart-d0999531-5199-44d2-8631-7abe376b2d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349830688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2349830688
Directory /workspace/0.spi_device_flash_mode/latest


Test location /workspace/coverage/default/10.spi_device_alert_test.3945719476
Short name T365
Test name
Test status
Simulation time 190679461 ps
CPU time 0.72 seconds
Started Aug 13 05:50:11 PM PDT 24
Finished Aug 13 05:50:12 PM PDT 24
Peak memory 205548 kb
Host smart-1b052599-e3e6-4657-a533-ca40893072bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945719476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3945719476
Directory /workspace/10.spi_device_alert_test/latest


Test location /workspace/coverage/default/3.spi_device_stress_all.3837157814
Short name T160
Test name
Test status
Simulation time 114400080581 ps
CPU time 1079.05 seconds
Started Aug 13 05:49:12 PM PDT 24
Finished Aug 13 06:07:12 PM PDT 24
Peak memory 287004 kb
Host smart-68a56d4d-d130-404e-a9c1-2d4bb38d81ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837157814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3837157814
Directory /workspace/3.spi_device_stress_all/latest


Test location /workspace/coverage/default/2.spi_device_stress_all.3577056959
Short name T17
Test name
Test status
Simulation time 6299321177 ps
CPU time 64.33 seconds
Started Aug 13 05:49:03 PM PDT 24
Finished Aug 13 05:50:07 PM PDT 24
Peak memory 250476 kb
Host smart-f85c6a55-0184-4cee-8d24-485720f08c20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577056959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3577056959
Directory /workspace/2.spi_device_stress_all/latest


Test location /workspace/coverage/default/42.spi_device_flash_all.511826165
Short name T283
Test name
Test status
Simulation time 167011110959 ps
CPU time 290.62 seconds
Started Aug 13 05:53:22 PM PDT 24
Finished Aug 13 05:58:13 PM PDT 24
Peak memory 253008 kb
Host smart-a73f3ca4-9cc9-42e1-84b7-c12005e9b8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511826165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.511826165
Directory /workspace/42.spi_device_flash_all/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.579007356
Short name T88
Test name
Test status
Simulation time 21181719 ps
CPU time 1.17 seconds
Started Aug 13 05:40:53 PM PDT 24
Finished Aug 13 05:40:55 PM PDT 24
Peak memory 207724 kb
Host smart-a66beefa-a254-4677-9eb8-138eceed9eec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579007356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.579007356
Directory /workspace/0.spi_device_csr_hw_reset/latest


Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1988887197
Short name T293
Test name
Test status
Simulation time 664203431564 ps
CPU time 607.34 seconds
Started Aug 13 05:50:29 PM PDT 24
Finished Aug 13 06:00:36 PM PDT 24
Peak memory 273176 kb
Host smart-0f03e3af-909e-4bd4-a7dc-a0ffa89e4b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988887197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1988887197
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/40.spi_device_stress_all.742719897
Short name T133
Test name
Test status
Simulation time 82232828476 ps
CPU time 257.54 seconds
Started Aug 13 05:53:17 PM PDT 24
Finished Aug 13 05:57:35 PM PDT 24
Peak memory 257580 kb
Host smart-0778ef45-d4bd-45d9-bccb-e4ab2947fdb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742719897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.742719897
Directory /workspace/40.spi_device_stress_all/latest


Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2759769698
Short name T228
Test name
Test status
Simulation time 43377512898 ps
CPU time 390.53 seconds
Started Aug 13 05:50:45 PM PDT 24
Finished Aug 13 05:57:15 PM PDT 24
Peak memory 250884 kb
Host smart-672b10f3-0432-4afe-9e4e-b9fb7fb3cd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759769698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2759769698
Directory /workspace/15.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/1.spi_device_mem_parity.1373463313
Short name T465
Test name
Test status
Simulation time 54178024 ps
CPU time 1.04 seconds
Started Aug 13 05:48:44 PM PDT 24
Finished Aug 13 05:48:45 PM PDT 24
Peak memory 217936 kb
Host smart-58fb81d8-6779-4b78-9810-d4b268271a17
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373463313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1373463313
Directory /workspace/1.spi_device_mem_parity/latest


Test location /workspace/coverage/default/49.spi_device_stress_all.3819700313
Short name T272
Test name
Test status
Simulation time 38370535687 ps
CPU time 388.49 seconds
Started Aug 13 05:54:07 PM PDT 24
Finished Aug 13 06:00:35 PM PDT 24
Peak memory 273796 kb
Host smart-bf8e4147-88d7-4d45-b64d-2d0ba5b144e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819700313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3819700313
Directory /workspace/49.spi_device_stress_all/latest


Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1473141665
Short name T26
Test name
Test status
Simulation time 3692599948 ps
CPU time 66.82 seconds
Started Aug 13 05:52:01 PM PDT 24
Finished Aug 13 05:53:09 PM PDT 24
Peak memory 254836 kb
Host smart-ab6105ee-9b2f-4c98-a77d-da2968574a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473141665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1473141665
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/0.spi_device_sec_cm.892861244
Short name T76
Test name
Test status
Simulation time 182335072 ps
CPU time 1.11 seconds
Started Aug 13 05:48:39 PM PDT 24
Finished Aug 13 05:48:40 PM PDT 24
Peak memory 235968 kb
Host smart-7ac4e070-720f-4eca-8e19-2b7b4eb716fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892861244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.892861244
Directory /workspace/0.spi_device_sec_cm/latest


Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.4045745197
Short name T212
Test name
Test status
Simulation time 8790635794 ps
CPU time 142.53 seconds
Started Aug 13 05:53:12 PM PDT 24
Finished Aug 13 05:55:34 PM PDT 24
Peak memory 265204 kb
Host smart-7bec635c-90d2-4f94-ab9c-735c6ffca734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045745197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.4045745197
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/2.spi_device_flash_all.1799917452
Short name T53
Test name
Test status
Simulation time 13575331451 ps
CPU time 87 seconds
Started Aug 13 05:49:03 PM PDT 24
Finished Aug 13 05:50:30 PM PDT 24
Peak memory 257524 kb
Host smart-cbb4f13d-3213-4eea-852c-d09e152584dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799917452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1799917452
Directory /workspace/2.spi_device_flash_all/latest


Test location /workspace/coverage/default/1.spi_device_stress_all.115858623
Short name T19
Test name
Test status
Simulation time 3645827722 ps
CPU time 91.08 seconds
Started Aug 13 05:48:54 PM PDT 24
Finished Aug 13 05:50:26 PM PDT 24
Peak memory 249360 kb
Host smart-5538187c-c555-4b57-a0c7-dba0a26a8336
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115858623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.115858623
Directory /workspace/1.spi_device_stress_all/latest


Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.4294011398
Short name T256
Test name
Test status
Simulation time 53624765040 ps
CPU time 475.1 seconds
Started Aug 13 05:52:22 PM PDT 24
Finished Aug 13 06:00:17 PM PDT 24
Peak memory 264016 kb
Host smart-146f524c-58fc-41dc-aa6a-3625b0c38d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294011398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4294011398
Directory /workspace/30.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/31.spi_device_tpm_all.2280177246
Short name T469
Test name
Test status
Simulation time 7500064813 ps
CPU time 23.51 seconds
Started Aug 13 05:52:22 PM PDT 24
Finished Aug 13 05:52:46 PM PDT 24
Peak memory 216656 kb
Host smart-324ca2b4-69ad-4d57-ae1c-de85fe98af13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280177246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2280177246
Directory /workspace/31.spi_device_tpm_all/latest


Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.4126508003
Short name T291
Test name
Test status
Simulation time 70717896434 ps
CPU time 540.39 seconds
Started Aug 13 05:50:52 PM PDT 24
Finished Aug 13 05:59:53 PM PDT 24
Peak memory 262748 kb
Host smart-9b6d3d2c-2cb4-4f2f-a81e-da46c34aa7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126508003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.4126508003
Directory /workspace/17.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3090650627
Short name T157
Test name
Test status
Simulation time 672199578 ps
CPU time 14.01 seconds
Started Aug 13 05:41:44 PM PDT 24
Finished Aug 13 05:41:58 PM PDT 24
Peak memory 216592 kb
Host smart-15beba48-050d-4d96-bd1e-a6e9928cc02d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090650627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3090650627
Directory /workspace/15.spi_device_tl_intg_err/latest


Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3093953305
Short name T227
Test name
Test status
Simulation time 70917428734 ps
CPU time 181.1 seconds
Started Aug 13 05:51:35 PM PDT 24
Finished Aug 13 05:54:36 PM PDT 24
Peak memory 264516 kb
Host smart-fb5a8c6a-fbd8-4f86-a9c8-18842930da77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093953305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3093953305
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.840180058
Short name T106
Test name
Test status
Simulation time 214497256 ps
CPU time 5.07 seconds
Started Aug 13 05:40:53 PM PDT 24
Finished Aug 13 05:40:58 PM PDT 24
Peak memory 216120 kb
Host smart-7be31de5-3346-4c6a-b613-daea5133b783
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840180058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.840180058
Directory /workspace/1.spi_device_tl_errors/latest


Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.4160974856
Short name T31
Test name
Test status
Simulation time 22652746914 ps
CPU time 16.01 seconds
Started Aug 13 05:50:28 PM PDT 24
Finished Aug 13 05:50:44 PM PDT 24
Peak memory 216504 kb
Host smart-994784a5-3ae8-459c-b21b-5056699f508b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160974856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.4160974856
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2530157366
Short name T825
Test name
Test status
Simulation time 2823039364 ps
CPU time 72.78 seconds
Started Aug 13 05:52:29 PM PDT 24
Finished Aug 13 05:53:42 PM PDT 24
Peak memory 249708 kb
Host smart-4d62ae79-85b9-47b8-8804-6a8d91185528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530157366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2530157366
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/14.spi_device_flash_mode.3764215431
Short name T928
Test name
Test status
Simulation time 469518282 ps
CPU time 10.85 seconds
Started Aug 13 05:50:35 PM PDT 24
Finished Aug 13 05:50:46 PM PDT 24
Peak memory 241044 kb
Host smart-22861919-d3f1-46d1-b645-7d889b3a749f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764215431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3764215431
Directory /workspace/14.spi_device_flash_mode/latest


Test location /workspace/coverage/default/19.spi_device_stress_all.2266002122
Short name T286
Test name
Test status
Simulation time 91877434439 ps
CPU time 978.82 seconds
Started Aug 13 05:51:12 PM PDT 24
Finished Aug 13 06:07:31 PM PDT 24
Peak memory 282160 kb
Host smart-d772446a-991f-40de-bab5-b7dd47bb68df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266002122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2266002122
Directory /workspace/19.spi_device_stress_all/latest


Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1635887010
Short name T298
Test name
Test status
Simulation time 8499813628 ps
CPU time 64.07 seconds
Started Aug 13 05:52:28 PM PDT 24
Finished Aug 13 05:53:33 PM PDT 24
Peak memory 249360 kb
Host smart-51a9ae2c-d5ee-44ab-b3e0-aa1096be8fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635887010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1635887010
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/49.spi_device_flash_mode.4101319075
Short name T731
Test name
Test status
Simulation time 156486189 ps
CPU time 7.68 seconds
Started Aug 13 05:54:01 PM PDT 24
Finished Aug 13 05:54:09 PM PDT 24
Peak memory 241032 kb
Host smart-a8c88506-d835-417e-8ce9-7bbd8c2563fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101319075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.4101319075
Directory /workspace/49.spi_device_flash_mode/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2687078428
Short name T174
Test name
Test status
Simulation time 1119759405 ps
CPU time 15.25 seconds
Started Aug 13 05:40:53 PM PDT 24
Finished Aug 13 05:41:08 PM PDT 24
Peak memory 216140 kb
Host smart-dde2cb50-4922-40ff-bec7-30cc96d84c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687078428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2687078428
Directory /workspace/1.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2934188706
Short name T168
Test name
Test status
Simulation time 605670658 ps
CPU time 15.85 seconds
Started Aug 13 05:41:42 PM PDT 24
Finished Aug 13 05:41:58 PM PDT 24
Peak memory 216352 kb
Host smart-1313b8a2-36f7-4199-87f8-211049b11ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934188706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2934188706
Directory /workspace/13.spi_device_tl_intg_err/latest


Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3438578610
Short name T448
Test name
Test status
Simulation time 6948410390 ps
CPU time 59.58 seconds
Started Aug 13 05:50:02 PM PDT 24
Finished Aug 13 05:51:02 PM PDT 24
Peak memory 252372 kb
Host smart-e6058ee7-0283-4b78-84a6-9c9111942bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438578610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3438578610
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/17.spi_device_flash_all.1672177560
Short name T284
Test name
Test status
Simulation time 48898977825 ps
CPU time 146.47 seconds
Started Aug 13 05:50:58 PM PDT 24
Finished Aug 13 05:53:24 PM PDT 24
Peak memory 266128 kb
Host smart-5f964420-e500-4ea3-8357-e862df6143fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672177560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1672177560
Directory /workspace/17.spi_device_flash_all/latest


Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3408060330
Short name T236
Test name
Test status
Simulation time 71150261235 ps
CPU time 343.88 seconds
Started Aug 13 05:49:03 PM PDT 24
Finished Aug 13 05:54:47 PM PDT 24
Peak memory 252732 kb
Host smart-bb069afc-80d3-437c-a3e6-b7bbab5b9a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408060330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3408060330
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1407216248
Short name T93
Test name
Test status
Simulation time 168949411 ps
CPU time 2.78 seconds
Started Aug 13 05:48:40 PM PDT 24
Finished Aug 13 05:48:43 PM PDT 24
Peak memory 232864 kb
Host smart-9258dcc5-ab3f-4e78-a842-eff153db9870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407216248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1407216248
Directory /workspace/0.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.65587222
Short name T96
Test name
Test status
Simulation time 2204189482 ps
CPU time 11.95 seconds
Started Aug 13 05:50:45 PM PDT 24
Finished Aug 13 05:50:57 PM PDT 24
Peak memory 232964 kb
Host smart-c0ab6282-4587-41d0-9cea-155f362dd247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65587222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.65587222
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2314668712
Short name T1102
Test name
Test status
Simulation time 142730501 ps
CPU time 3.36 seconds
Started Aug 13 05:40:53 PM PDT 24
Finished Aug 13 05:40:57 PM PDT 24
Peak memory 216136 kb
Host smart-aa41446b-21d7-4758-a77b-64a059a7d56e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314668712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
314668712
Directory /workspace/0.spi_device_tl_errors/latest


Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2880740684
Short name T998
Test name
Test status
Simulation time 26197666238 ps
CPU time 169.47 seconds
Started Aug 13 05:48:40 PM PDT 24
Finished Aug 13 05:51:29 PM PDT 24
Peak memory 265772 kb
Host smart-dfced1f8-a51a-4118-9332-6b9aba975901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880740684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2880740684
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2203834363
Short name T155
Test name
Test status
Simulation time 1625362438 ps
CPU time 8.66 seconds
Started Aug 13 05:40:55 PM PDT 24
Finished Aug 13 05:41:04 PM PDT 24
Peak memory 207764 kb
Host smart-cff4a0a4-2cdb-4d1e-a6c0-28fe97a08a1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203834363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2203834363
Directory /workspace/0.spi_device_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2996433102
Short name T129
Test name
Test status
Simulation time 785911529 ps
CPU time 11.8 seconds
Started Aug 13 05:40:52 PM PDT 24
Finished Aug 13 05:41:04 PM PDT 24
Peak memory 207660 kb
Host smart-a3782bb2-cbd3-461b-b89b-578686cab4f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996433102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2996433102
Directory /workspace/0.spi_device_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1962159019
Short name T158
Test name
Test status
Simulation time 151008344 ps
CPU time 3.66 seconds
Started Aug 13 05:40:52 PM PDT 24
Finished Aug 13 05:40:56 PM PDT 24
Peak memory 218380 kb
Host smart-a56c9941-1441-433d-b839-b920f0d73e93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962159019 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1962159019
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2771372553
Short name T1138
Test name
Test status
Simulation time 147119471 ps
CPU time 1.29 seconds
Started Aug 13 05:40:53 PM PDT 24
Finished Aug 13 05:40:54 PM PDT 24
Peak memory 207712 kb
Host smart-500c2144-63f5-4838-98b8-692d66423d99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771372553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
771372553
Directory /workspace/0.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3962605102
Short name T1148
Test name
Test status
Simulation time 54570032 ps
CPU time 0.76 seconds
Started Aug 13 05:40:53 PM PDT 24
Finished Aug 13 05:40:54 PM PDT 24
Peak memory 204244 kb
Host smart-1f9af086-7c7a-41c4-a2dc-eab336064798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962605102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
962605102
Directory /workspace/0.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1107296529
Short name T1146
Test name
Test status
Simulation time 172439279 ps
CPU time 1.79 seconds
Started Aug 13 05:40:52 PM PDT 24
Finished Aug 13 05:40:54 PM PDT 24
Peak memory 215976 kb
Host smart-1f035226-05d8-46e8-ab24-4866bf4fc84d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107296529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1107296529
Directory /workspace/0.spi_device_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1362501867
Short name T1133
Test name
Test status
Simulation time 38402164 ps
CPU time 0.66 seconds
Started Aug 13 05:40:55 PM PDT 24
Finished Aug 13 05:40:56 PM PDT 24
Peak memory 204620 kb
Host smart-3f2d9df8-a874-4a83-95bb-33374a0328d1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362501867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1362501867
Directory /workspace/0.spi_device_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3859759549
Short name T1074
Test name
Test status
Simulation time 309580917 ps
CPU time 2 seconds
Started Aug 13 05:40:53 PM PDT 24
Finished Aug 13 05:40:56 PM PDT 24
Peak memory 207776 kb
Host smart-62ac201a-e738-47eb-945c-9c0860cd8017
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859759549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3859759549
Directory /workspace/0.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1867654415
Short name T169
Test name
Test status
Simulation time 547779502 ps
CPU time 15.28 seconds
Started Aug 13 05:40:56 PM PDT 24
Finished Aug 13 05:41:11 PM PDT 24
Peak memory 215948 kb
Host smart-cfb80b6a-6b91-420e-8d0c-e4bbdfec09ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867654415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1867654415
Directory /workspace/0.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.330806192
Short name T122
Test name
Test status
Simulation time 812974996 ps
CPU time 14.53 seconds
Started Aug 13 05:41:02 PM PDT 24
Finished Aug 13 05:41:17 PM PDT 24
Peak memory 207804 kb
Host smart-a181cb41-a4e7-4212-8ab5-d5b63df5f4af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330806192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.330806192
Directory /workspace/1.spi_device_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2000478436
Short name T120
Test name
Test status
Simulation time 7849274207 ps
CPU time 27.08 seconds
Started Aug 13 05:41:02 PM PDT 24
Finished Aug 13 05:41:29 PM PDT 24
Peak memory 207760 kb
Host smart-42659917-5e24-435c-a3e2-648779d88a36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000478436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2000478436
Directory /workspace/1.spi_device_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1828990678
Short name T89
Test name
Test status
Simulation time 48620381 ps
CPU time 1.51 seconds
Started Aug 13 05:40:59 PM PDT 24
Finished Aug 13 05:41:01 PM PDT 24
Peak memory 216892 kb
Host smart-fd7bc725-6965-4ac8-b760-a9014b02e196
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828990678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1828990678
Directory /workspace/1.spi_device_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.196442912
Short name T1114
Test name
Test status
Simulation time 42263654 ps
CPU time 1.58 seconds
Started Aug 13 05:41:01 PM PDT 24
Finished Aug 13 05:41:03 PM PDT 24
Peak memory 216252 kb
Host smart-ebec2178-58a5-4584-bfed-471a0f14ce62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196442912 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.196442912
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3903507054
Short name T1069
Test name
Test status
Simulation time 31287334 ps
CPU time 1.92 seconds
Started Aug 13 05:41:01 PM PDT 24
Finished Aug 13 05:41:03 PM PDT 24
Peak memory 207696 kb
Host smart-151fc70f-3bfb-4f36-b461-15e39558ae67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903507054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
903507054
Directory /workspace/1.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1369293298
Short name T1063
Test name
Test status
Simulation time 30942761 ps
CPU time 0.82 seconds
Started Aug 13 05:41:01 PM PDT 24
Finished Aug 13 05:41:02 PM PDT 24
Peak memory 204612 kb
Host smart-c5b961e1-2cb5-4b40-afa1-93af05ce2bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369293298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
369293298
Directory /workspace/1.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3546700746
Short name T124
Test name
Test status
Simulation time 120045220 ps
CPU time 1.32 seconds
Started Aug 13 05:41:00 PM PDT 24
Finished Aug 13 05:41:01 PM PDT 24
Peak memory 215984 kb
Host smart-4674fbb9-f085-43f9-9178-eb50596765ce
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546700746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3546700746
Directory /workspace/1.spi_device_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.959630297
Short name T1088
Test name
Test status
Simulation time 20668938 ps
CPU time 0.67 seconds
Started Aug 13 05:41:02 PM PDT 24
Finished Aug 13 05:41:03 PM PDT 24
Peak memory 204280 kb
Host smart-fb87aa91-ab76-46b2-9001-f1b7c2d3018b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959630297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.959630297
Directory /workspace/1.spi_device_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3698443411
Short name T1035
Test name
Test status
Simulation time 227352646 ps
CPU time 3.98 seconds
Started Aug 13 05:41:00 PM PDT 24
Finished Aug 13 05:41:04 PM PDT 24
Peak memory 215820 kb
Host smart-231e9aae-56f0-4893-b43f-68c495d49c32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698443411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3698443411
Directory /workspace/1.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3006141761
Short name T1127
Test name
Test status
Simulation time 122487234 ps
CPU time 3.93 seconds
Started Aug 13 05:41:35 PM PDT 24
Finished Aug 13 05:41:39 PM PDT 24
Peak memory 218548 kb
Host smart-87e07e7c-51a0-4c97-ad0a-29a0196fd7fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006141761 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3006141761
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1104628023
Short name T1109
Test name
Test status
Simulation time 62355022 ps
CPU time 1.96 seconds
Started Aug 13 05:41:36 PM PDT 24
Finished Aug 13 05:41:38 PM PDT 24
Peak memory 215904 kb
Host smart-a56d5f19-8d31-4d27-9932-6b47e2ae684f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104628023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1104628023
Directory /workspace/10.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.587362116
Short name T1062
Test name
Test status
Simulation time 16653089 ps
CPU time 0.72 seconds
Started Aug 13 05:41:35 PM PDT 24
Finished Aug 13 05:41:36 PM PDT 24
Peak memory 204636 kb
Host smart-6b371b0f-5468-4a27-9ae7-17d111c3316f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587362116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.587362116
Directory /workspace/10.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1637049844
Short name T1140
Test name
Test status
Simulation time 77819679 ps
CPU time 1.9 seconds
Started Aug 13 05:41:34 PM PDT 24
Finished Aug 13 05:41:36 PM PDT 24
Peak memory 215836 kb
Host smart-5f7b2206-771b-4601-a060-22e3b380de90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637049844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1637049844
Directory /workspace/10.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3573955571
Short name T105
Test name
Test status
Simulation time 460154940 ps
CPU time 2.96 seconds
Started Aug 13 05:41:36 PM PDT 24
Finished Aug 13 05:41:40 PM PDT 24
Peak memory 216188 kb
Host smart-61dd674a-c207-4319-8d48-ae84428a825a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573955571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3573955571
Directory /workspace/10.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1216560919
Short name T1100
Test name
Test status
Simulation time 951660756 ps
CPU time 13.25 seconds
Started Aug 13 05:41:37 PM PDT 24
Finished Aug 13 05:41:50 PM PDT 24
Peak memory 216232 kb
Host smart-01f50d04-2ba3-4f10-bd39-e14c19838422
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216560919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1216560919
Directory /workspace/10.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3065185647
Short name T1085
Test name
Test status
Simulation time 48967690 ps
CPU time 1.83 seconds
Started Aug 13 05:41:36 PM PDT 24
Finished Aug 13 05:41:38 PM PDT 24
Peak memory 217044 kb
Host smart-e82fd7ea-88d0-4d01-a99c-fe74844ba5ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065185647 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3065185647
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.392372635
Short name T1117
Test name
Test status
Simulation time 30807563 ps
CPU time 1.94 seconds
Started Aug 13 05:41:36 PM PDT 24
Finished Aug 13 05:41:38 PM PDT 24
Peak memory 207712 kb
Host smart-948125f6-e7fe-45ee-a43a-ee501e311c84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392372635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.392372635
Directory /workspace/11.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.950790336
Short name T1118
Test name
Test status
Simulation time 36395419 ps
CPU time 0.77 seconds
Started Aug 13 05:41:36 PM PDT 24
Finished Aug 13 05:41:37 PM PDT 24
Peak memory 204364 kb
Host smart-7cd3116c-f863-49c8-b5a9-369922e81e73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950790336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.950790336
Directory /workspace/11.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2046455407
Short name T1104
Test name
Test status
Simulation time 210664062 ps
CPU time 2.81 seconds
Started Aug 13 05:41:36 PM PDT 24
Finished Aug 13 05:41:39 PM PDT 24
Peak memory 216000 kb
Host smart-dc5f784c-ba67-47b1-8054-3b6ce297ba3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046455407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2046455407
Directory /workspace/11.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2631001406
Short name T1106
Test name
Test status
Simulation time 119048222 ps
CPU time 1.48 seconds
Started Aug 13 05:41:36 PM PDT 24
Finished Aug 13 05:41:37 PM PDT 24
Peak memory 216124 kb
Host smart-e3bdf1d1-a9ab-46a1-a62b-817f0d573b20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631001406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2631001406
Directory /workspace/11.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1833304195
Short name T171
Test name
Test status
Simulation time 1068204361 ps
CPU time 24.47 seconds
Started Aug 13 05:41:37 PM PDT 24
Finished Aug 13 05:42:02 PM PDT 24
Peak memory 215932 kb
Host smart-547de460-4725-4852-955e-334cc02ad331
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833304195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1833304195
Directory /workspace/11.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1876114692
Short name T1125
Test name
Test status
Simulation time 306963739 ps
CPU time 4.13 seconds
Started Aug 13 05:41:35 PM PDT 24
Finished Aug 13 05:41:39 PM PDT 24
Peak memory 217508 kb
Host smart-e43e6dc8-f5f0-4967-9cff-77202a870c06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876114692 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1876114692
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1733443578
Short name T1098
Test name
Test status
Simulation time 324868504 ps
CPU time 2.57 seconds
Started Aug 13 05:41:37 PM PDT 24
Finished Aug 13 05:41:40 PM PDT 24
Peak memory 215884 kb
Host smart-7a14c783-fa7b-469e-b951-6805cdfa0a3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733443578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1733443578
Directory /workspace/12.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1164666800
Short name T1132
Test name
Test status
Simulation time 21028253 ps
CPU time 0.74 seconds
Started Aug 13 05:41:37 PM PDT 24
Finished Aug 13 05:41:38 PM PDT 24
Peak memory 204360 kb
Host smart-d9e585ab-c4c4-4bec-8e49-7571e973efb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164666800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1164666800
Directory /workspace/12.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1095478920
Short name T1056
Test name
Test status
Simulation time 215982070 ps
CPU time 3 seconds
Started Aug 13 05:41:33 PM PDT 24
Finished Aug 13 05:41:36 PM PDT 24
Peak memory 215904 kb
Host smart-f266e072-64e5-4d25-8364-f62170cdd956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095478920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1095478920
Directory /workspace/12.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2186460504
Short name T108
Test name
Test status
Simulation time 61103668 ps
CPU time 3.87 seconds
Started Aug 13 05:41:36 PM PDT 24
Finished Aug 13 05:41:40 PM PDT 24
Peak memory 216160 kb
Host smart-193d3b78-6607-416f-8e10-2ce604913b44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186460504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2186460504
Directory /workspace/12.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2070176489
Short name T1077
Test name
Test status
Simulation time 377126390 ps
CPU time 8.54 seconds
Started Aug 13 05:41:36 PM PDT 24
Finished Aug 13 05:41:45 PM PDT 24
Peak memory 216012 kb
Host smart-d358421a-d4a8-4d14-af61-376dab2a7512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070176489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2070176489
Directory /workspace/12.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1036278920
Short name T99
Test name
Test status
Simulation time 1191661458 ps
CPU time 4.02 seconds
Started Aug 13 05:41:46 PM PDT 24
Finished Aug 13 05:41:50 PM PDT 24
Peak memory 218852 kb
Host smart-7baf775b-138c-4ccc-9238-ab1a9ca7508f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036278920 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1036278920
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2906704700
Short name T1086
Test name
Test status
Simulation time 360715991 ps
CPU time 2.47 seconds
Started Aug 13 05:41:44 PM PDT 24
Finished Aug 13 05:41:46 PM PDT 24
Peak memory 216088 kb
Host smart-216572bd-3bbb-412a-a16b-921552b164e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906704700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2906704700
Directory /workspace/13.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1621414566
Short name T1144
Test name
Test status
Simulation time 13611829 ps
CPU time 0.78 seconds
Started Aug 13 05:41:43 PM PDT 24
Finished Aug 13 05:41:44 PM PDT 24
Peak memory 204360 kb
Host smart-8a214df5-3b0a-499d-a008-d942e4d2b023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621414566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1621414566
Directory /workspace/13.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2545236088
Short name T1053
Test name
Test status
Simulation time 51877920 ps
CPU time 1.79 seconds
Started Aug 13 05:41:43 PM PDT 24
Finished Aug 13 05:41:45 PM PDT 24
Peak memory 207668 kb
Host smart-346566a1-21ff-4c41-9c21-7b1cce9de627
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545236088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2545236088
Directory /workspace/13.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2417163969
Short name T118
Test name
Test status
Simulation time 114521513 ps
CPU time 1.8 seconds
Started Aug 13 05:41:45 PM PDT 24
Finished Aug 13 05:41:47 PM PDT 24
Peak memory 217108 kb
Host smart-ff753de4-b6e5-4a3c-86d3-c5a7f99d6d9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417163969 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2417163969
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2564857228
Short name T123
Test name
Test status
Simulation time 69671839 ps
CPU time 1.23 seconds
Started Aug 13 05:41:43 PM PDT 24
Finished Aug 13 05:41:45 PM PDT 24
Peak memory 207780 kb
Host smart-3cd1aa08-ebac-4b95-9647-8b766c1c6bb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564857228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2564857228
Directory /workspace/14.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3821793242
Short name T1092
Test name
Test status
Simulation time 155806509 ps
CPU time 0.7 seconds
Started Aug 13 05:41:44 PM PDT 24
Finished Aug 13 05:41:45 PM PDT 24
Peak memory 204372 kb
Host smart-aa0aa7d7-5c0a-42b7-9307-5ba7eb8b3670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821793242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3821793242
Directory /workspace/14.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2885774339
Short name T1071
Test name
Test status
Simulation time 28348497 ps
CPU time 1.74 seconds
Started Aug 13 05:41:43 PM PDT 24
Finished Aug 13 05:41:45 PM PDT 24
Peak memory 215940 kb
Host smart-fd716a4c-48b7-45de-8d60-6ed3b23bd064
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885774339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2885774339
Directory /workspace/14.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1730090175
Short name T1096
Test name
Test status
Simulation time 300762511 ps
CPU time 7.34 seconds
Started Aug 13 05:41:44 PM PDT 24
Finished Aug 13 05:41:51 PM PDT 24
Peak memory 218400 kb
Host smart-6854011c-a45c-4e0c-af50-04e5333b2dd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730090175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1730090175
Directory /workspace/14.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.419031069
Short name T1122
Test name
Test status
Simulation time 789476774 ps
CPU time 13.06 seconds
Started Aug 13 05:41:42 PM PDT 24
Finished Aug 13 05:41:55 PM PDT 24
Peak memory 215932 kb
Host smart-8e44c22b-075a-428b-93da-b7e517027bde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419031069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.419031069
Directory /workspace/14.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2988391229
Short name T1136
Test name
Test status
Simulation time 212617648 ps
CPU time 3.72 seconds
Started Aug 13 05:41:42 PM PDT 24
Finished Aug 13 05:41:46 PM PDT 24
Peak memory 217560 kb
Host smart-ee718954-b0a7-4ed3-8d58-442b0726949d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988391229 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2988391229
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.761804997
Short name T1112
Test name
Test status
Simulation time 85984144 ps
CPU time 2.38 seconds
Started Aug 13 05:41:46 PM PDT 24
Finished Aug 13 05:41:49 PM PDT 24
Peak memory 215988 kb
Host smart-c542d9c3-7f21-4b1f-a48f-14450c0ddedb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761804997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.761804997
Directory /workspace/15.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.102827216
Short name T1046
Test name
Test status
Simulation time 19524770 ps
CPU time 0.76 seconds
Started Aug 13 05:41:38 PM PDT 24
Finished Aug 13 05:41:39 PM PDT 24
Peak memory 204208 kb
Host smart-30a90efc-dd8c-4c93-b81a-40c777c25bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102827216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.102827216
Directory /workspace/15.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4044858140
Short name T1089
Test name
Test status
Simulation time 80537135 ps
CPU time 1.74 seconds
Started Aug 13 05:41:43 PM PDT 24
Finished Aug 13 05:41:45 PM PDT 24
Peak memory 215860 kb
Host smart-7a1be36c-fee9-4432-816a-c1eb31dcff37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044858140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4044858140
Directory /workspace/15.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2613891559
Short name T1105
Test name
Test status
Simulation time 96948856 ps
CPU time 3.56 seconds
Started Aug 13 05:41:41 PM PDT 24
Finished Aug 13 05:41:45 PM PDT 24
Peak memory 215992 kb
Host smart-3786fcd9-9b05-48a5-8cfa-116da916a5b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613891559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2613891559
Directory /workspace/15.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.420145460
Short name T1101
Test name
Test status
Simulation time 56047811 ps
CPU time 3.46 seconds
Started Aug 13 05:41:43 PM PDT 24
Finished Aug 13 05:41:47 PM PDT 24
Peak memory 217736 kb
Host smart-c0c122cd-6b18-422b-894a-273aaede2703
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420145460 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.420145460
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3595552991
Short name T146
Test name
Test status
Simulation time 90653629 ps
CPU time 2.38 seconds
Started Aug 13 05:41:43 PM PDT 24
Finished Aug 13 05:41:46 PM PDT 24
Peak memory 207692 kb
Host smart-acde63c0-d9b2-44a6-b46b-4c9e11d87992
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595552991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3595552991
Directory /workspace/16.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3874125291
Short name T1047
Test name
Test status
Simulation time 15097655 ps
CPU time 0.77 seconds
Started Aug 13 05:41:45 PM PDT 24
Finished Aug 13 05:41:46 PM PDT 24
Peak memory 204584 kb
Host smart-1533e3b8-ce29-4075-9ff2-d6d25caecc2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874125291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3874125291
Directory /workspace/16.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4284573149
Short name T148
Test name
Test status
Simulation time 40764421 ps
CPU time 2.57 seconds
Started Aug 13 05:41:44 PM PDT 24
Finished Aug 13 05:41:47 PM PDT 24
Peak memory 215916 kb
Host smart-ff14040d-249d-49ba-b766-e2ba7edd8755
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284573149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4284573149
Directory /workspace/16.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2949965086
Short name T1097
Test name
Test status
Simulation time 489530798 ps
CPU time 3.23 seconds
Started Aug 13 05:41:47 PM PDT 24
Finished Aug 13 05:41:50 PM PDT 24
Peak memory 216140 kb
Host smart-49f416ac-b6ef-4940-b6fb-3bb63e99ffc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949965086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2949965086
Directory /workspace/16.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.878298333
Short name T100
Test name
Test status
Simulation time 252366235 ps
CPU time 3.68 seconds
Started Aug 13 05:41:44 PM PDT 24
Finished Aug 13 05:41:48 PM PDT 24
Peak memory 218220 kb
Host smart-e9a7efc1-64ce-41fd-8f12-3325e3a39bc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878298333 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.878298333
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.326267931
Short name T145
Test name
Test status
Simulation time 256410713 ps
CPU time 1.41 seconds
Started Aug 13 05:41:47 PM PDT 24
Finished Aug 13 05:41:48 PM PDT 24
Peak memory 207780 kb
Host smart-78934b08-8535-4710-bcea-7dba5a3f31b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326267931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.326267931
Directory /workspace/17.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2834911972
Short name T1149
Test name
Test status
Simulation time 14094388 ps
CPU time 0.78 seconds
Started Aug 13 05:41:44 PM PDT 24
Finished Aug 13 05:41:45 PM PDT 24
Peak memory 204320 kb
Host smart-8f7d385d-ab77-4e41-bdab-9e23b28416a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834911972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2834911972
Directory /workspace/17.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3693338698
Short name T1143
Test name
Test status
Simulation time 612022816 ps
CPU time 3.8 seconds
Started Aug 13 05:41:43 PM PDT 24
Finished Aug 13 05:41:47 PM PDT 24
Peak memory 216040 kb
Host smart-b7ded869-d4b7-462e-8907-c9a39fb65bf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693338698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3693338698
Directory /workspace/17.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.336099134
Short name T107
Test name
Test status
Simulation time 565330752 ps
CPU time 4.08 seconds
Started Aug 13 05:41:45 PM PDT 24
Finished Aug 13 05:41:50 PM PDT 24
Peak memory 216220 kb
Host smart-30669bbb-bcb7-4cb6-b2c5-b9dec9b0d49e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336099134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.336099134
Directory /workspace/17.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2080189560
Short name T170
Test name
Test status
Simulation time 2277318743 ps
CPU time 16.34 seconds
Started Aug 13 05:41:43 PM PDT 24
Finished Aug 13 05:42:00 PM PDT 24
Peak memory 216000 kb
Host smart-a8afbad3-cdef-48f5-be14-67044bc3f588
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080189560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2080189560
Directory /workspace/17.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.968566001
Short name T113
Test name
Test status
Simulation time 130449511 ps
CPU time 2.48 seconds
Started Aug 13 05:41:53 PM PDT 24
Finished Aug 13 05:41:56 PM PDT 24
Peak memory 217252 kb
Host smart-b0051a3a-b8ab-4fdf-ad6b-00d20787761a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968566001 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.968566001
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4088335861
Short name T121
Test name
Test status
Simulation time 110173293 ps
CPU time 2.15 seconds
Started Aug 13 05:41:53 PM PDT 24
Finished Aug 13 05:41:55 PM PDT 24
Peak memory 215960 kb
Host smart-aff58378-f1b2-4c74-9cf6-2d9722880a77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088335861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4088335861
Directory /workspace/18.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1214825177
Short name T1041
Test name
Test status
Simulation time 18800638 ps
CPU time 0.76 seconds
Started Aug 13 05:41:51 PM PDT 24
Finished Aug 13 05:41:52 PM PDT 24
Peak memory 204624 kb
Host smart-44e56009-5b03-4c36-bc10-b977ec51b5b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214825177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1214825177
Directory /workspace/18.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1075227368
Short name T1093
Test name
Test status
Simulation time 490780977 ps
CPU time 1.86 seconds
Started Aug 13 05:41:49 PM PDT 24
Finished Aug 13 05:41:52 PM PDT 24
Peak memory 215976 kb
Host smart-4fa994c7-77d8-44b9-85cf-cbbbb3688d1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075227368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1075227368
Directory /workspace/18.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.572024912
Short name T110
Test name
Test status
Simulation time 351235409 ps
CPU time 4.93 seconds
Started Aug 13 05:41:42 PM PDT 24
Finished Aug 13 05:41:47 PM PDT 24
Peak memory 216056 kb
Host smart-f8c60cf6-614a-4ec4-af48-a92f2e099bb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572024912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.572024912
Directory /workspace/18.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1832385015
Short name T175
Test name
Test status
Simulation time 439967965 ps
CPU time 7.55 seconds
Started Aug 13 05:41:52 PM PDT 24
Finished Aug 13 05:42:00 PM PDT 24
Peak memory 215800 kb
Host smart-db93274c-1a5a-4820-8beb-3cf570f73842
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832385015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1832385015
Directory /workspace/18.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.706242305
Short name T1110
Test name
Test status
Simulation time 153076377 ps
CPU time 2.87 seconds
Started Aug 13 05:41:51 PM PDT 24
Finished Aug 13 05:41:54 PM PDT 24
Peak memory 218716 kb
Host smart-18a33678-9f41-4a3d-8e96-601c9f261ca0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706242305 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.706242305
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1144662262
Short name T1107
Test name
Test status
Simulation time 348107692 ps
CPU time 2.56 seconds
Started Aug 13 05:41:50 PM PDT 24
Finished Aug 13 05:41:52 PM PDT 24
Peak memory 215912 kb
Host smart-4b42aaa0-527d-4596-b48f-14a620718df0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144662262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1144662262
Directory /workspace/19.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1468391161
Short name T1147
Test name
Test status
Simulation time 12354202 ps
CPU time 0.75 seconds
Started Aug 13 05:41:51 PM PDT 24
Finished Aug 13 05:41:52 PM PDT 24
Peak memory 204360 kb
Host smart-9842ccdb-97ee-431a-bb30-a5f9764fb492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468391161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1468391161
Directory /workspace/19.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.808517977
Short name T1038
Test name
Test status
Simulation time 286620672 ps
CPU time 2.04 seconds
Started Aug 13 05:41:52 PM PDT 24
Finished Aug 13 05:41:55 PM PDT 24
Peak memory 216016 kb
Host smart-2763c09e-c593-46d2-ab00-9fb7860a8ec5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808517977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.808517977
Directory /workspace/19.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2703841209
Short name T1115
Test name
Test status
Simulation time 92408283 ps
CPU time 2.83 seconds
Started Aug 13 05:41:51 PM PDT 24
Finished Aug 13 05:41:54 PM PDT 24
Peak memory 216260 kb
Host smart-15eeb014-2324-4c48-890a-af41615e507d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703841209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2703841209
Directory /workspace/19.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3414188056
Short name T98
Test name
Test status
Simulation time 442321777 ps
CPU time 6.83 seconds
Started Aug 13 05:41:51 PM PDT 24
Finished Aug 13 05:41:58 PM PDT 24
Peak memory 216260 kb
Host smart-108944ff-5d74-46e3-a606-f51b2ec6f0df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414188056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3414188056
Directory /workspace/19.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2115957025
Short name T125
Test name
Test status
Simulation time 2642702218 ps
CPU time 14.49 seconds
Started Aug 13 05:41:11 PM PDT 24
Finished Aug 13 05:41:26 PM PDT 24
Peak memory 216068 kb
Host smart-10184a8c-0433-49c8-b8f8-da7ff2cf0f18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115957025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2115957025
Directory /workspace/2.spi_device_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2024596446
Short name T1145
Test name
Test status
Simulation time 1880755769 ps
CPU time 36.15 seconds
Started Aug 13 05:41:08 PM PDT 24
Finished Aug 13 05:41:45 PM PDT 24
Peak memory 207856 kb
Host smart-20e5c721-a391-4925-820c-070fc8d9259c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024596446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2024596446
Directory /workspace/2.spi_device_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2867688395
Short name T1032
Test name
Test status
Simulation time 50656753 ps
CPU time 0.93 seconds
Started Aug 13 05:41:09 PM PDT 24
Finished Aug 13 05:41:10 PM PDT 24
Peak memory 207352 kb
Host smart-9253b090-0c76-41d2-9984-fe0af31d8c94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867688395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2867688395
Directory /workspace/2.spi_device_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.526995327
Short name T116
Test name
Test status
Simulation time 90880680 ps
CPU time 2.69 seconds
Started Aug 13 05:41:10 PM PDT 24
Finished Aug 13 05:41:13 PM PDT 24
Peak memory 216912 kb
Host smart-097889ca-60c3-46af-b73d-fb11315ea9c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526995327 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.526995327
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.317919786
Short name T1067
Test name
Test status
Simulation time 56940366 ps
CPU time 2.53 seconds
Started Aug 13 05:41:08 PM PDT 24
Finished Aug 13 05:41:11 PM PDT 24
Peak memory 215984 kb
Host smart-fc9254b9-37fd-4025-8f81-3f34e2244784
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317919786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.317919786
Directory /workspace/2.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.478637639
Short name T1057
Test name
Test status
Simulation time 220786853 ps
CPU time 0.75 seconds
Started Aug 13 05:41:01 PM PDT 24
Finished Aug 13 05:41:02 PM PDT 24
Peak memory 204676 kb
Host smart-eef83680-2e2e-4eaa-a800-5acac62c8440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478637639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.478637639
Directory /workspace/2.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1866730001
Short name T131
Test name
Test status
Simulation time 241848159 ps
CPU time 2.12 seconds
Started Aug 13 05:41:12 PM PDT 24
Finished Aug 13 05:41:14 PM PDT 24
Peak memory 216032 kb
Host smart-893fd505-0c84-4548-aae4-6e989185734d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866730001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1866730001
Directory /workspace/2.spi_device_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1392703823
Short name T1130
Test name
Test status
Simulation time 126245709 ps
CPU time 0.66 seconds
Started Aug 13 05:41:07 PM PDT 24
Finished Aug 13 05:41:08 PM PDT 24
Peak memory 204608 kb
Host smart-75ecadef-af6d-4912-82eb-b930e873ab9b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392703823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1392703823
Directory /workspace/2.spi_device_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1823239558
Short name T1090
Test name
Test status
Simulation time 229341616 ps
CPU time 2.87 seconds
Started Aug 13 05:41:10 PM PDT 24
Finished Aug 13 05:41:12 PM PDT 24
Peak memory 215932 kb
Host smart-0a4cb4b4-bb7c-4816-8d94-f232f6ad9fef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823239558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1823239558
Directory /workspace/2.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1998268867
Short name T102
Test name
Test status
Simulation time 89011935 ps
CPU time 5.57 seconds
Started Aug 13 05:41:01 PM PDT 24
Finished Aug 13 05:41:07 PM PDT 24
Peak memory 216136 kb
Host smart-f4363326-84fc-48a3-941d-ba3a5ce1ae9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998268867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
998268867
Directory /workspace/2.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.755309983
Short name T1108
Test name
Test status
Simulation time 396888274 ps
CPU time 6.9 seconds
Started Aug 13 05:41:01 PM PDT 24
Finished Aug 13 05:41:08 PM PDT 24
Peak memory 216320 kb
Host smart-e1a073ec-edf5-4ad8-a7c6-a9a133655069
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755309983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.755309983
Directory /workspace/2.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2478911771
Short name T1079
Test name
Test status
Simulation time 28399167 ps
CPU time 0.7 seconds
Started Aug 13 05:41:51 PM PDT 24
Finished Aug 13 05:41:52 PM PDT 24
Peak memory 204568 kb
Host smart-438b0f61-34a8-4ed0-b7ea-372b0b46009f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478911771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2478911771
Directory /workspace/20.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2047182302
Short name T1037
Test name
Test status
Simulation time 12826553 ps
CPU time 0.72 seconds
Started Aug 13 05:41:49 PM PDT 24
Finished Aug 13 05:41:50 PM PDT 24
Peak memory 204420 kb
Host smart-43bb49dd-fa2a-492a-b346-311ad52bad15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047182302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2047182302
Directory /workspace/21.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2706405102
Short name T1042
Test name
Test status
Simulation time 43032690 ps
CPU time 0.75 seconds
Started Aug 13 05:41:53 PM PDT 24
Finished Aug 13 05:41:54 PM PDT 24
Peak memory 204224 kb
Host smart-7a3b05c9-d507-42cf-93ed-d9050dce51d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706405102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2706405102
Directory /workspace/22.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1191250214
Short name T1129
Test name
Test status
Simulation time 13629383 ps
CPU time 0.71 seconds
Started Aug 13 05:41:53 PM PDT 24
Finished Aug 13 05:41:54 PM PDT 24
Peak memory 204360 kb
Host smart-c02618df-2a03-4a10-a13f-ff4a7f8ad3bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191250214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1191250214
Directory /workspace/23.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.477763483
Short name T1040
Test name
Test status
Simulation time 12374077 ps
CPU time 0.72 seconds
Started Aug 13 05:41:49 PM PDT 24
Finished Aug 13 05:41:50 PM PDT 24
Peak memory 204332 kb
Host smart-e5983bb3-6184-4db8-b115-cb27cc3396b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477763483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.477763483
Directory /workspace/24.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.223639606
Short name T1087
Test name
Test status
Simulation time 36305246 ps
CPU time 0.73 seconds
Started Aug 13 05:41:52 PM PDT 24
Finished Aug 13 05:41:53 PM PDT 24
Peak memory 204332 kb
Host smart-0afb18f8-d346-4704-a20e-a64f5767b52e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223639606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.223639606
Directory /workspace/25.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3924036694
Short name T1043
Test name
Test status
Simulation time 62805239 ps
CPU time 0.75 seconds
Started Aug 13 05:41:52 PM PDT 24
Finished Aug 13 05:41:53 PM PDT 24
Peak memory 204380 kb
Host smart-8d036bbc-2a7a-42c0-8714-bcd6519594bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924036694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3924036694
Directory /workspace/26.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1170697892
Short name T1124
Test name
Test status
Simulation time 11916815 ps
CPU time 0.74 seconds
Started Aug 13 05:41:51 PM PDT 24
Finished Aug 13 05:41:52 PM PDT 24
Peak memory 204676 kb
Host smart-1c14d34b-c63b-4341-b83a-009b65ecbdb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170697892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1170697892
Directory /workspace/27.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3878637365
Short name T1064
Test name
Test status
Simulation time 13315647 ps
CPU time 0.72 seconds
Started Aug 13 05:41:51 PM PDT 24
Finished Aug 13 05:41:52 PM PDT 24
Peak memory 204320 kb
Host smart-a015a553-33a3-4273-80cd-7d72a9b29b95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878637365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3878637365
Directory /workspace/28.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3937394714
Short name T1099
Test name
Test status
Simulation time 17929708 ps
CPU time 0.75 seconds
Started Aug 13 05:41:53 PM PDT 24
Finished Aug 13 05:41:54 PM PDT 24
Peak memory 204552 kb
Host smart-0156aed2-6990-4eef-8bff-a02c405c21c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937394714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3937394714
Directory /workspace/29.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1896793014
Short name T130
Test name
Test status
Simulation time 1223019562 ps
CPU time 16.07 seconds
Started Aug 13 05:41:16 PM PDT 24
Finished Aug 13 05:41:32 PM PDT 24
Peak memory 215804 kb
Host smart-51c69c02-f025-467e-b9a3-1a4de8bb2a92
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896793014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1896793014
Directory /workspace/3.spi_device_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1090275853
Short name T1044
Test name
Test status
Simulation time 4016073507 ps
CPU time 13.27 seconds
Started Aug 13 05:41:16 PM PDT 24
Finished Aug 13 05:41:29 PM PDT 24
Peak memory 207868 kb
Host smart-39617bc0-891e-4d2b-a24f-7e2162b5c075
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090275853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1090275853
Directory /workspace/3.spi_device_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1856321554
Short name T90
Test name
Test status
Simulation time 196104764 ps
CPU time 1.43 seconds
Started Aug 13 05:41:09 PM PDT 24
Finished Aug 13 05:41:11 PM PDT 24
Peak memory 207760 kb
Host smart-f41c9fcf-4899-4446-a954-3bc26e692642
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856321554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1856321554
Directory /workspace/3.spi_device_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2171091712
Short name T156
Test name
Test status
Simulation time 102397411 ps
CPU time 2.72 seconds
Started Aug 13 05:41:15 PM PDT 24
Finished Aug 13 05:41:18 PM PDT 24
Peak memory 217972 kb
Host smart-b6d17745-fbe2-4c38-ba58-8a4f2de34aaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171091712 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2171091712
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1354033787
Short name T1139
Test name
Test status
Simulation time 79217178 ps
CPU time 1.28 seconds
Started Aug 13 05:41:24 PM PDT 24
Finished Aug 13 05:41:25 PM PDT 24
Peak memory 215916 kb
Host smart-d3a4cb4a-21bf-4dd5-8394-944a2780de98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354033787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
354033787
Directory /workspace/3.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3572179143
Short name T1049
Test name
Test status
Simulation time 19242303 ps
CPU time 0.76 seconds
Started Aug 13 05:41:09 PM PDT 24
Finished Aug 13 05:41:10 PM PDT 24
Peak memory 204340 kb
Host smart-a1d44a2a-bf9d-4f45-aeea-6bf66fd98eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572179143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
572179143
Directory /workspace/3.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.271209969
Short name T1120
Test name
Test status
Simulation time 165927147 ps
CPU time 1.7 seconds
Started Aug 13 05:41:09 PM PDT 24
Finished Aug 13 05:41:10 PM PDT 24
Peak memory 215900 kb
Host smart-21ba633c-3802-4332-9bf2-7214f63723b3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271209969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.271209969
Directory /workspace/3.spi_device_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1242505695
Short name T1052
Test name
Test status
Simulation time 13269612 ps
CPU time 0.7 seconds
Started Aug 13 05:41:11 PM PDT 24
Finished Aug 13 05:41:12 PM PDT 24
Peak memory 204640 kb
Host smart-ca197183-5c9d-47d0-a098-f614e24e35ea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242505695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1242505695
Directory /workspace/3.spi_device_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2935411787
Short name T1083
Test name
Test status
Simulation time 72540199 ps
CPU time 1.67 seconds
Started Aug 13 05:41:16 PM PDT 24
Finished Aug 13 05:41:18 PM PDT 24
Peak memory 207736 kb
Host smart-61e71baa-e0a6-4693-8981-6e4c2cb1702e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935411787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2935411787
Directory /workspace/3.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1884947712
Short name T1150
Test name
Test status
Simulation time 103835295 ps
CPU time 3.18 seconds
Started Aug 13 05:41:11 PM PDT 24
Finished Aug 13 05:41:14 PM PDT 24
Peak memory 216156 kb
Host smart-c35a9408-bd4e-4cc8-be89-cde7083a2404
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884947712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
884947712
Directory /workspace/3.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3328204078
Short name T173
Test name
Test status
Simulation time 200776936 ps
CPU time 6.57 seconds
Started Aug 13 05:41:08 PM PDT 24
Finished Aug 13 05:41:15 PM PDT 24
Peak memory 216056 kb
Host smart-3b8ca411-8e36-40a4-9156-e17a310b7fe9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328204078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3328204078
Directory /workspace/3.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.17257112
Short name T1082
Test name
Test status
Simulation time 16122119 ps
CPU time 0.76 seconds
Started Aug 13 05:41:53 PM PDT 24
Finished Aug 13 05:41:53 PM PDT 24
Peak memory 204636 kb
Host smart-0d44854f-a02e-43d5-92b0-32ad88963cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17257112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.17257112
Directory /workspace/30.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1601518884
Short name T1061
Test name
Test status
Simulation time 46097596 ps
CPU time 0.8 seconds
Started Aug 13 05:41:53 PM PDT 24
Finished Aug 13 05:41:54 PM PDT 24
Peak memory 204268 kb
Host smart-5591f89f-9e00-4d93-8619-5cb6319f93e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601518884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1601518884
Directory /workspace/31.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.376603275
Short name T1084
Test name
Test status
Simulation time 16270063 ps
CPU time 0.71 seconds
Started Aug 13 05:41:51 PM PDT 24
Finished Aug 13 05:41:52 PM PDT 24
Peak memory 204384 kb
Host smart-26f89d5c-00c3-4bd9-9a51-e109ab52e99c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376603275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.376603275
Directory /workspace/32.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3998508542
Short name T1066
Test name
Test status
Simulation time 47108343 ps
CPU time 0.76 seconds
Started Aug 13 05:41:52 PM PDT 24
Finished Aug 13 05:41:53 PM PDT 24
Peak memory 204364 kb
Host smart-c0e2d188-39d1-402e-b6ec-dc327730fb92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998508542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3998508542
Directory /workspace/33.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3766808800
Short name T1051
Test name
Test status
Simulation time 11387008 ps
CPU time 0.76 seconds
Started Aug 13 05:41:53 PM PDT 24
Finished Aug 13 05:41:54 PM PDT 24
Peak memory 204592 kb
Host smart-67046585-9af9-48a6-ad0f-52bca133fb58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766808800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3766808800
Directory /workspace/34.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.341719511
Short name T1141
Test name
Test status
Simulation time 44275785 ps
CPU time 0.74 seconds
Started Aug 13 05:41:51 PM PDT 24
Finished Aug 13 05:41:51 PM PDT 24
Peak memory 204676 kb
Host smart-26559a11-2077-4c8c-9603-dc01903d4059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341719511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.341719511
Directory /workspace/35.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1295195926
Short name T1091
Test name
Test status
Simulation time 45379780 ps
CPU time 0.71 seconds
Started Aug 13 05:41:53 PM PDT 24
Finished Aug 13 05:41:54 PM PDT 24
Peak memory 204620 kb
Host smart-af3ce8a7-7fef-4f15-8fb7-efc98d741faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295195926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1295195926
Directory /workspace/36.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3289446390
Short name T1075
Test name
Test status
Simulation time 12534310 ps
CPU time 0.74 seconds
Started Aug 13 05:42:00 PM PDT 24
Finished Aug 13 05:42:00 PM PDT 24
Peak memory 204356 kb
Host smart-ec07a359-ef37-464d-89db-dd92a024fbc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289446390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3289446390
Directory /workspace/37.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.797776060
Short name T1031
Test name
Test status
Simulation time 14636278 ps
CPU time 0.74 seconds
Started Aug 13 05:41:58 PM PDT 24
Finished Aug 13 05:41:59 PM PDT 24
Peak memory 204652 kb
Host smart-11d83291-93e2-4d3a-ae02-37da23e283c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797776060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.797776060
Directory /workspace/38.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2097235744
Short name T1050
Test name
Test status
Simulation time 28379799 ps
CPU time 0.73 seconds
Started Aug 13 05:41:59 PM PDT 24
Finished Aug 13 05:42:00 PM PDT 24
Peak memory 204356 kb
Host smart-d909a940-d169-4a82-a5b3-1dc6f91e0bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097235744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2097235744
Directory /workspace/39.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.592690483
Short name T1081
Test name
Test status
Simulation time 2518906781 ps
CPU time 25.31 seconds
Started Aug 13 05:41:16 PM PDT 24
Finished Aug 13 05:41:41 PM PDT 24
Peak memory 207792 kb
Host smart-87a212fa-8372-435b-915f-50a53f213d2f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592690483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.592690483
Directory /workspace/4.spi_device_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1207755229
Short name T1121
Test name
Test status
Simulation time 1190444936 ps
CPU time 12.17 seconds
Started Aug 13 05:41:17 PM PDT 24
Finished Aug 13 05:41:29 PM PDT 24
Peak memory 216328 kb
Host smart-3f31b924-cff5-4252-b72e-2b2033a56a9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207755229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1207755229
Directory /workspace/4.spi_device_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3737436448
Short name T87
Test name
Test status
Simulation time 91994490 ps
CPU time 0.99 seconds
Started Aug 13 05:41:15 PM PDT 24
Finished Aug 13 05:41:17 PM PDT 24
Peak memory 207488 kb
Host smart-7c5fb391-990b-4469-8c0f-de2c478d0a4f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737436448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3737436448
Directory /workspace/4.spi_device_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.570085238
Short name T1123
Test name
Test status
Simulation time 56738915 ps
CPU time 1.62 seconds
Started Aug 13 05:41:25 PM PDT 24
Finished Aug 13 05:41:26 PM PDT 24
Peak memory 216012 kb
Host smart-407ede43-7012-4f07-9505-95e311e27814
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570085238 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.570085238
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.444426277
Short name T132
Test name
Test status
Simulation time 67023773 ps
CPU time 2.45 seconds
Started Aug 13 05:41:24 PM PDT 24
Finished Aug 13 05:41:27 PM PDT 24
Peak memory 216000 kb
Host smart-4bc07f80-7a1b-489e-abc9-0185834458bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444426277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.444426277
Directory /workspace/4.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1919351056
Short name T1080
Test name
Test status
Simulation time 35803975 ps
CPU time 0.74 seconds
Started Aug 13 05:41:14 PM PDT 24
Finished Aug 13 05:41:15 PM PDT 24
Peak memory 204328 kb
Host smart-9d8d5cc0-d5ca-490d-8bb3-bff96d635fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919351056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
919351056
Directory /workspace/4.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.442163312
Short name T127
Test name
Test status
Simulation time 579298190 ps
CPU time 2.09 seconds
Started Aug 13 05:41:15 PM PDT 24
Finished Aug 13 05:41:17 PM PDT 24
Peak memory 215944 kb
Host smart-8c4283a5-4119-48fd-8c40-cfd210beb215
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442163312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.442163312
Directory /workspace/4.spi_device_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1623108742
Short name T1055
Test name
Test status
Simulation time 11122658 ps
CPU time 0.67 seconds
Started Aug 13 05:41:24 PM PDT 24
Finished Aug 13 05:41:25 PM PDT 24
Peak memory 204308 kb
Host smart-12f4a58b-e030-4462-a215-53f478aa77d9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623108742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1623108742
Directory /workspace/4.spi_device_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.36618394
Short name T1119
Test name
Test status
Simulation time 315489073 ps
CPU time 3.63 seconds
Started Aug 13 05:41:15 PM PDT 24
Finished Aug 13 05:41:18 PM PDT 24
Peak memory 216496 kb
Host smart-bd953810-0582-463d-b72e-bababede648c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36618394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_same_csr_outstanding.36618394
Directory /workspace/4.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.48811532
Short name T1076
Test name
Test status
Simulation time 34558934 ps
CPU time 2.36 seconds
Started Aug 13 05:41:16 PM PDT 24
Finished Aug 13 05:41:19 PM PDT 24
Peak memory 216124 kb
Host smart-8981c657-0f36-474f-99a9-f78c77df5b90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48811532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.48811532
Directory /workspace/4.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3359567686
Short name T117
Test name
Test status
Simulation time 1980469605 ps
CPU time 14.12 seconds
Started Aug 13 05:41:16 PM PDT 24
Finished Aug 13 05:41:30 PM PDT 24
Peak memory 216352 kb
Host smart-7cd960fe-f9fd-4d81-a4e6-fc245dee1a1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359567686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3359567686
Directory /workspace/4.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3833961030
Short name T1142
Test name
Test status
Simulation time 12632560 ps
CPU time 0.71 seconds
Started Aug 13 05:42:00 PM PDT 24
Finished Aug 13 05:42:01 PM PDT 24
Peak memory 204680 kb
Host smart-86ed7573-3f8c-4f25-9cbb-dd61c1384b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833961030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3833961030
Directory /workspace/40.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1435584542
Short name T1126
Test name
Test status
Simulation time 44886306 ps
CPU time 0.77 seconds
Started Aug 13 05:41:58 PM PDT 24
Finished Aug 13 05:41:59 PM PDT 24
Peak memory 204332 kb
Host smart-5143cfed-bbbf-4aa6-bd7d-fe62864dbdd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435584542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1435584542
Directory /workspace/41.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2864583339
Short name T1048
Test name
Test status
Simulation time 118266047 ps
CPU time 0.72 seconds
Started Aug 13 05:42:01 PM PDT 24
Finished Aug 13 05:42:01 PM PDT 24
Peak memory 204656 kb
Host smart-1f339e16-6c63-4aef-8fd0-f789ee5dacfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864583339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2864583339
Directory /workspace/42.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1012467877
Short name T1078
Test name
Test status
Simulation time 50364960 ps
CPU time 0.76 seconds
Started Aug 13 05:41:59 PM PDT 24
Finished Aug 13 05:42:00 PM PDT 24
Peak memory 204312 kb
Host smart-c84e7e70-287a-49b7-bad5-f336e0f9d32f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012467877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1012467877
Directory /workspace/43.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1750420377
Short name T1103
Test name
Test status
Simulation time 27921280 ps
CPU time 0.73 seconds
Started Aug 13 05:41:58 PM PDT 24
Finished Aug 13 05:41:58 PM PDT 24
Peak memory 204560 kb
Host smart-4147cd42-01f6-4e9a-a74b-ade1c5eab716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750420377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1750420377
Directory /workspace/44.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3276423989
Short name T1030
Test name
Test status
Simulation time 39556712 ps
CPU time 0.7 seconds
Started Aug 13 05:42:00 PM PDT 24
Finished Aug 13 05:42:00 PM PDT 24
Peak memory 204364 kb
Host smart-d453232e-2f0c-4510-b0c1-42ec1d7f7357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276423989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3276423989
Directory /workspace/45.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2749542564
Short name T1033
Test name
Test status
Simulation time 32688975 ps
CPU time 0.72 seconds
Started Aug 13 05:41:58 PM PDT 24
Finished Aug 13 05:41:59 PM PDT 24
Peak memory 204348 kb
Host smart-11529b28-5189-4b36-adb3-7890e133a645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749542564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2749542564
Directory /workspace/46.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3853302735
Short name T1045
Test name
Test status
Simulation time 56094209 ps
CPU time 0.76 seconds
Started Aug 13 05:41:58 PM PDT 24
Finished Aug 13 05:41:59 PM PDT 24
Peak memory 204696 kb
Host smart-19a83a70-6b09-48a1-8124-e5c80741d3ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853302735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3853302735
Directory /workspace/47.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1354390811
Short name T1094
Test name
Test status
Simulation time 12856795 ps
CPU time 0.73 seconds
Started Aug 13 05:41:55 PM PDT 24
Finished Aug 13 05:41:56 PM PDT 24
Peak memory 204668 kb
Host smart-1871775c-0990-479d-9e47-1825de45e5b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354390811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1354390811
Directory /workspace/48.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1872145877
Short name T1072
Test name
Test status
Simulation time 11618974 ps
CPU time 0.79 seconds
Started Aug 13 05:41:58 PM PDT 24
Finished Aug 13 05:41:59 PM PDT 24
Peak memory 204676 kb
Host smart-d7c6ff7a-95f8-4248-b78c-ead186171628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872145877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1872145877
Directory /workspace/49.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1873643586
Short name T1065
Test name
Test status
Simulation time 769485818 ps
CPU time 3.96 seconds
Started Aug 13 05:41:16 PM PDT 24
Finished Aug 13 05:41:20 PM PDT 24
Peak memory 217792 kb
Host smart-6597f753-e1a3-402d-8cd0-bd7e88c2164b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873643586 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1873643586
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.952975671
Short name T128
Test name
Test status
Simulation time 78741250 ps
CPU time 2.55 seconds
Started Aug 13 05:41:18 PM PDT 24
Finished Aug 13 05:41:20 PM PDT 24
Peak memory 207628 kb
Host smart-8da6ff9e-bca3-4007-8366-2bbfafe8a664
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952975671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.952975671
Directory /workspace/5.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.914263663
Short name T1059
Test name
Test status
Simulation time 48636070 ps
CPU time 0.73 seconds
Started Aug 13 05:41:16 PM PDT 24
Finished Aug 13 05:41:17 PM PDT 24
Peak memory 204376 kb
Host smart-fe67676a-6742-4065-8374-f27d3d5ba60f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914263663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.914263663
Directory /workspace/5.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.824744463
Short name T1054
Test name
Test status
Simulation time 164828165 ps
CPU time 4.28 seconds
Started Aug 13 05:41:16 PM PDT 24
Finished Aug 13 05:41:20 PM PDT 24
Peak memory 215912 kb
Host smart-1c0dcda8-7f17-44a0-bec9-e2134c0e8af0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824744463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.824744463
Directory /workspace/5.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3971924951
Short name T109
Test name
Test status
Simulation time 103651716 ps
CPU time 3 seconds
Started Aug 13 05:41:24 PM PDT 24
Finished Aug 13 05:41:28 PM PDT 24
Peak memory 216204 kb
Host smart-f8387e60-d159-43b4-b7ed-645d8eff9855
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971924951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
971924951
Directory /workspace/5.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3715760089
Short name T1131
Test name
Test status
Simulation time 96627739 ps
CPU time 6.23 seconds
Started Aug 13 05:41:16 PM PDT 24
Finished Aug 13 05:41:23 PM PDT 24
Peak memory 215864 kb
Host smart-378dbda4-7728-43d6-b837-d6d3e2a8b83d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715760089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3715760089
Directory /workspace/5.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3328318558
Short name T111
Test name
Test status
Simulation time 55309001 ps
CPU time 3.62 seconds
Started Aug 13 05:41:26 PM PDT 24
Finished Aug 13 05:41:29 PM PDT 24
Peak memory 218272 kb
Host smart-d939ce20-b629-4dcb-ac76-a584be9cead8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328318558 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3328318558
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3204735085
Short name T1073
Test name
Test status
Simulation time 131762023 ps
CPU time 2.24 seconds
Started Aug 13 05:41:24 PM PDT 24
Finished Aug 13 05:41:27 PM PDT 24
Peak memory 207676 kb
Host smart-185f5a23-147b-44dd-9e11-09558a25e850
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204735085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
204735085
Directory /workspace/6.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.719202172
Short name T1137
Test name
Test status
Simulation time 23046161 ps
CPU time 0.77 seconds
Started Aug 13 05:41:25 PM PDT 24
Finished Aug 13 05:41:26 PM PDT 24
Peak memory 204412 kb
Host smart-ab92749c-8563-4ed7-8c94-0e273b83b67e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719202172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.719202172
Directory /workspace/6.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4365318
Short name T1070
Test name
Test status
Simulation time 169925113 ps
CPU time 3.11 seconds
Started Aug 13 05:41:25 PM PDT 24
Finished Aug 13 05:41:28 PM PDT 24
Peak memory 215948 kb
Host smart-f721fd94-acaa-429d-9495-58c71f00d2a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4365318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_
device_same_csr_outstanding.4365318
Directory /workspace/6.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3866808941
Short name T115
Test name
Test status
Simulation time 645983574 ps
CPU time 2.69 seconds
Started Aug 13 05:41:13 PM PDT 24
Finished Aug 13 05:41:15 PM PDT 24
Peak memory 216120 kb
Host smart-5ee03f74-d909-4538-bdd4-d44a943b71c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866808941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
866808941
Directory /workspace/6.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.300268150
Short name T104
Test name
Test status
Simulation time 808860427 ps
CPU time 12.99 seconds
Started Aug 13 05:41:24 PM PDT 24
Finished Aug 13 05:41:38 PM PDT 24
Peak memory 216284 kb
Host smart-ff506131-acd4-40a2-b0b3-92be99757ad8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300268150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.300268150
Directory /workspace/6.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2091223486
Short name T1095
Test name
Test status
Simulation time 398120776 ps
CPU time 2.79 seconds
Started Aug 13 05:41:27 PM PDT 24
Finished Aug 13 05:41:29 PM PDT 24
Peak memory 218248 kb
Host smart-17253890-9ff8-45fe-97eb-7e2d033c8b43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091223486 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2091223486
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2083178667
Short name T147
Test name
Test status
Simulation time 38201686 ps
CPU time 1.35 seconds
Started Aug 13 05:41:26 PM PDT 24
Finished Aug 13 05:41:27 PM PDT 24
Peak memory 215980 kb
Host smart-ecaa282c-a4e5-47d6-8681-eb85e9346f06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083178667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
083178667
Directory /workspace/7.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1215499740
Short name T1068
Test name
Test status
Simulation time 13275664 ps
CPU time 0.72 seconds
Started Aug 13 05:41:26 PM PDT 24
Finished Aug 13 05:41:27 PM PDT 24
Peak memory 204320 kb
Host smart-24423f7e-c080-4290-ac58-ce5bf88c01e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215499740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
215499740
Directory /workspace/7.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1601517762
Short name T1134
Test name
Test status
Simulation time 160855171 ps
CPU time 2.88 seconds
Started Aug 13 05:41:25 PM PDT 24
Finished Aug 13 05:41:28 PM PDT 24
Peak memory 216004 kb
Host smart-234c198f-f688-4863-aafb-7a49ab021cae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601517762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1601517762
Directory /workspace/7.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.614660655
Short name T114
Test name
Test status
Simulation time 88175688 ps
CPU time 1.62 seconds
Started Aug 13 05:41:26 PM PDT 24
Finished Aug 13 05:41:28 PM PDT 24
Peak memory 215996 kb
Host smart-8091c140-e8b7-425f-8e24-54b1a3564edf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614660655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.614660655
Directory /workspace/7.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1082919789
Short name T172
Test name
Test status
Simulation time 102673796 ps
CPU time 6.19 seconds
Started Aug 13 05:41:28 PM PDT 24
Finished Aug 13 05:41:34 PM PDT 24
Peak memory 216012 kb
Host smart-cfbd7995-d038-400a-97a4-b6fc44532e90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082919789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1082919789
Directory /workspace/7.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.867323290
Short name T112
Test name
Test status
Simulation time 38540634 ps
CPU time 2.58 seconds
Started Aug 13 05:41:37 PM PDT 24
Finished Aug 13 05:41:39 PM PDT 24
Peak memory 217880 kb
Host smart-e43bd9db-c4b1-4367-840f-e9fb83f6ed7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867323290 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.867323290
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4095956258
Short name T126
Test name
Test status
Simulation time 71571810 ps
CPU time 1.84 seconds
Started Aug 13 05:41:26 PM PDT 24
Finished Aug 13 05:41:28 PM PDT 24
Peak memory 216012 kb
Host smart-49a88479-d7b3-4476-915e-da73398b758d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095956258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
095956258
Directory /workspace/8.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3633492546
Short name T1060
Test name
Test status
Simulation time 45208484 ps
CPU time 0.7 seconds
Started Aug 13 05:41:24 PM PDT 24
Finished Aug 13 05:41:25 PM PDT 24
Peak memory 204656 kb
Host smart-61ff39b3-72a2-4ef5-b938-ce3b8f85a998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633492546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
633492546
Directory /workspace/8.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2685952655
Short name T1039
Test name
Test status
Simulation time 58676341 ps
CPU time 4.07 seconds
Started Aug 13 05:41:25 PM PDT 24
Finished Aug 13 05:41:29 PM PDT 24
Peak memory 215852 kb
Host smart-797de9a6-c003-4ad9-9a75-e2b86f543a04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685952655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2685952655
Directory /workspace/8.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3606545467
Short name T1116
Test name
Test status
Simulation time 151724971 ps
CPU time 2.37 seconds
Started Aug 13 05:41:27 PM PDT 24
Finished Aug 13 05:41:29 PM PDT 24
Peak memory 217184 kb
Host smart-9f5fb886-7f8b-49f5-bd5e-2c05c4e8accb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606545467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
606545467
Directory /workspace/8.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4127252022
Short name T1128
Test name
Test status
Simulation time 196249525 ps
CPU time 12.74 seconds
Started Aug 13 05:41:26 PM PDT 24
Finished Aug 13 05:41:39 PM PDT 24
Peak memory 215924 kb
Host smart-a9b9d9e3-9891-446e-b8f7-7c9ad5a224d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127252022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4127252022
Directory /workspace/8.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1952117637
Short name T1058
Test name
Test status
Simulation time 179530925 ps
CPU time 1.77 seconds
Started Aug 13 05:41:36 PM PDT 24
Finished Aug 13 05:41:38 PM PDT 24
Peak memory 216084 kb
Host smart-6eaffb18-756e-46ab-8612-3633f68d011e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952117637 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1952117637
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1026194694
Short name T1034
Test name
Test status
Simulation time 276461888 ps
CPU time 1.46 seconds
Started Aug 13 05:41:35 PM PDT 24
Finished Aug 13 05:41:37 PM PDT 24
Peak memory 207656 kb
Host smart-b607938b-cc47-451e-badf-b70edc2a3aab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026194694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
026194694
Directory /workspace/9.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3321219156
Short name T1135
Test name
Test status
Simulation time 23026898 ps
CPU time 0.76 seconds
Started Aug 13 05:41:38 PM PDT 24
Finished Aug 13 05:41:39 PM PDT 24
Peak memory 204356 kb
Host smart-63d49567-c5cd-4668-993b-f3ad72119d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321219156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
321219156
Directory /workspace/9.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1219592657
Short name T1036
Test name
Test status
Simulation time 58844613 ps
CPU time 1.86 seconds
Started Aug 13 05:41:35 PM PDT 24
Finished Aug 13 05:41:37 PM PDT 24
Peak memory 207604 kb
Host smart-7e96bbe9-3571-4944-811f-9966d45dd3fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219592657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1219592657
Directory /workspace/9.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3871088028
Short name T1111
Test name
Test status
Simulation time 81598469 ps
CPU time 2.16 seconds
Started Aug 13 05:41:35 PM PDT 24
Finished Aug 13 05:41:38 PM PDT 24
Peak memory 216288 kb
Host smart-86af50ed-2962-4908-b493-22b3da6fdb80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871088028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
871088028
Directory /workspace/9.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1964397273
Short name T1113
Test name
Test status
Simulation time 1144411781 ps
CPU time 18.5 seconds
Started Aug 13 05:41:36 PM PDT 24
Finished Aug 13 05:41:54 PM PDT 24
Peak memory 215980 kb
Host smart-94524d36-2a3a-465b-9c2d-14a10f0e42ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964397273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1964397273
Directory /workspace/9.spi_device_tl_intg_err/latest


Test location /workspace/coverage/default/0.spi_device_alert_test.3367478334
Short name T869
Test name
Test status
Simulation time 16009903 ps
CPU time 0.79 seconds
Started Aug 13 05:48:39 PM PDT 24
Finished Aug 13 05:48:40 PM PDT 24
Peak memory 204972 kb
Host smart-a6b6c818-ecca-493c-86ee-8073d02ae049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367478334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
367478334
Directory /workspace/0.spi_device_alert_test/latest


Test location /workspace/coverage/default/0.spi_device_csb_read.2945717449
Short name T534
Test name
Test status
Simulation time 22231111 ps
CPU time 0.76 seconds
Started Aug 13 05:48:35 PM PDT 24
Finished Aug 13 05:48:36 PM PDT 24
Peak memory 205948 kb
Host smart-fcf7d2b3-8756-4293-96e6-788427b3bc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945717449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2945717449
Directory /workspace/0.spi_device_csb_read/latest


Test location /workspace/coverage/default/0.spi_device_flash_all.3456596902
Short name T580
Test name
Test status
Simulation time 3766372434 ps
CPU time 53.6 seconds
Started Aug 13 05:48:42 PM PDT 24
Finished Aug 13 05:49:35 PM PDT 24
Peak memory 249296 kb
Host smart-73350df2-f877-4101-bf0f-b51b870b4e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456596902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3456596902
Directory /workspace/0.spi_device_flash_all/latest


Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2532852977
Short name T419
Test name
Test status
Simulation time 15975498514 ps
CPU time 152.83 seconds
Started Aug 13 05:48:44 PM PDT 24
Finished Aug 13 05:51:17 PM PDT 24
Peak memory 249392 kb
Host smart-c165f412-df48-43f6-bce0-19bbde646929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532852977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2532852977
Directory /workspace/0.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2145663160
Short name T285
Test name
Test status
Simulation time 79322083816 ps
CPU time 308.33 seconds
Started Aug 13 05:48:44 PM PDT 24
Finished Aug 13 05:53:52 PM PDT 24
Peak memory 250836 kb
Host smart-63456263-177c-4536-bf59-1f550a9d3c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145663160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2145663160
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/0.spi_device_intercept.2654580543
Short name T535
Test name
Test status
Simulation time 4113883247 ps
CPU time 11.47 seconds
Started Aug 13 05:48:40 PM PDT 24
Finished Aug 13 05:48:52 PM PDT 24
Peak memory 230992 kb
Host smart-5381015d-1892-4ff7-9e75-dffdab871130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654580543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2654580543
Directory /workspace/0.spi_device_intercept/latest


Test location /workspace/coverage/default/0.spi_device_mailbox.3420543317
Short name T456
Test name
Test status
Simulation time 264749397 ps
CPU time 2.37 seconds
Started Aug 13 05:48:44 PM PDT 24
Finished Aug 13 05:48:46 PM PDT 24
Peak memory 224616 kb
Host smart-9142c415-29d7-4d3f-83e1-09ec1fd724ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420543317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3420543317
Directory /workspace/0.spi_device_mailbox/latest


Test location /workspace/coverage/default/0.spi_device_mem_parity.2387826221
Short name T583
Test name
Test status
Simulation time 33953778 ps
CPU time 1.16 seconds
Started Aug 13 05:48:35 PM PDT 24
Finished Aug 13 05:48:36 PM PDT 24
Peak memory 216752 kb
Host smart-7c80948d-061b-452c-9be3-f0629f273b3e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387826221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2387826221
Directory /workspace/0.spi_device_mem_parity/latest


Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2971476267
Short name T309
Test name
Test status
Simulation time 736502219 ps
CPU time 5.46 seconds
Started Aug 13 05:48:42 PM PDT 24
Finished Aug 13 05:48:47 PM PDT 24
Peak memory 224568 kb
Host smart-d0a122cf-cf2c-4ee5-88fb-f7711e55a359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971476267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2971476267
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1952416002
Short name T867
Test name
Test status
Simulation time 171374900 ps
CPU time 3.53 seconds
Started Aug 13 05:48:33 PM PDT 24
Finished Aug 13 05:48:36 PM PDT 24
Peak memory 232840 kb
Host smart-ba10e753-6bf9-4b2c-af54-95bafb066bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952416002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1952416002
Directory /workspace/0.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2465479570
Short name T766
Test name
Test status
Simulation time 165307195 ps
CPU time 3.95 seconds
Started Aug 13 05:48:40 PM PDT 24
Finished Aug 13 05:48:44 PM PDT 24
Peak memory 220088 kb
Host smart-8cc5b1ae-6051-4021-a8e0-6698d042f106
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2465479570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2465479570
Directory /workspace/0.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/0.spi_device_stress_all.1440812102
Short name T934
Test name
Test status
Simulation time 50935035293 ps
CPU time 269.04 seconds
Started Aug 13 05:48:40 PM PDT 24
Finished Aug 13 05:53:09 PM PDT 24
Peak memory 253748 kb
Host smart-486091f7-ed31-4bf0-b80b-356e096fa162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440812102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1440812102
Directory /workspace/0.spi_device_stress_all/latest


Test location /workspace/coverage/default/0.spi_device_tpm_all.3330720570
Short name T321
Test name
Test status
Simulation time 938997444 ps
CPU time 10.79 seconds
Started Aug 13 05:48:33 PM PDT 24
Finished Aug 13 05:48:44 PM PDT 24
Peak memory 219064 kb
Host smart-0b9ac78a-7c77-477a-a1b7-cce8bb7c0d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330720570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3330720570
Directory /workspace/0.spi_device_tpm_all/latest


Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2750154504
Short name T503
Test name
Test status
Simulation time 29659738 ps
CPU time 0.72 seconds
Started Aug 13 05:48:33 PM PDT 24
Finished Aug 13 05:48:33 PM PDT 24
Peak memory 205728 kb
Host smart-99a056b7-18ce-4b89-814b-915b41c2c627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750154504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2750154504
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/0.spi_device_tpm_rw.3750269568
Short name T361
Test name
Test status
Simulation time 83654107 ps
CPU time 1.22 seconds
Started Aug 13 05:48:30 PM PDT 24
Finished Aug 13 05:48:31 PM PDT 24
Peak memory 216488 kb
Host smart-13e7aac1-9de7-44fe-b397-00f96e2754c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750269568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3750269568
Directory /workspace/0.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1888878507
Short name T357
Test name
Test status
Simulation time 160741525 ps
CPU time 0.95 seconds
Started Aug 13 05:48:33 PM PDT 24
Finished Aug 13 05:48:34 PM PDT 24
Peak memory 207144 kb
Host smart-a2d5cd3c-c151-441b-b24e-e5d702745f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888878507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1888878507
Directory /workspace/0.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/0.spi_device_upload.2141421844
Short name T848
Test name
Test status
Simulation time 2677604292 ps
CPU time 13.92 seconds
Started Aug 13 05:48:40 PM PDT 24
Finished Aug 13 05:48:54 PM PDT 24
Peak memory 232992 kb
Host smart-87e4af39-0fb7-4577-881c-3ae38c4d8615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141421844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2141421844
Directory /workspace/0.spi_device_upload/latest


Test location /workspace/coverage/default/1.spi_device_alert_test.31126966
Short name T721
Test name
Test status
Simulation time 30544169 ps
CPU time 0.7 seconds
Started Aug 13 05:48:57 PM PDT 24
Finished Aug 13 05:48:57 PM PDT 24
Peak memory 204932 kb
Host smart-acac7cff-fc95-4dca-8b56-629b1c48db70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31126966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.31126966
Directory /workspace/1.spi_device_alert_test/latest


Test location /workspace/coverage/default/1.spi_device_cfg_cmd.4173542537
Short name T553
Test name
Test status
Simulation time 301609095 ps
CPU time 3.58 seconds
Started Aug 13 05:48:48 PM PDT 24
Finished Aug 13 05:48:52 PM PDT 24
Peak memory 224588 kb
Host smart-c620cfe9-0dd9-4932-b025-7395e3f9eb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173542537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.4173542537
Directory /workspace/1.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/1.spi_device_csb_read.449097368
Short name T886
Test name
Test status
Simulation time 221783055 ps
CPU time 0.74 seconds
Started Aug 13 05:48:39 PM PDT 24
Finished Aug 13 05:48:40 PM PDT 24
Peak memory 205544 kb
Host smart-37330621-391c-4166-bc7d-61200e698ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449097368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.449097368
Directory /workspace/1.spi_device_csb_read/latest


Test location /workspace/coverage/default/1.spi_device_flash_all.2637718687
Short name T304
Test name
Test status
Simulation time 14008057819 ps
CPU time 75.28 seconds
Started Aug 13 05:48:52 PM PDT 24
Finished Aug 13 05:50:08 PM PDT 24
Peak memory 251920 kb
Host smart-483fd0af-bda1-45c1-b17c-c4cf6342064e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637718687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2637718687
Directory /workspace/1.spi_device_flash_all/latest


Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3585309771
Short name T754
Test name
Test status
Simulation time 7262968797 ps
CPU time 32.49 seconds
Started Aug 13 05:48:52 PM PDT 24
Finished Aug 13 05:49:25 PM PDT 24
Peak memory 249096 kb
Host smart-12a7656f-5716-481b-95cb-f08d7cf9ae1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585309771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3585309771
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/1.spi_device_flash_mode.2807680556
Short name T659
Test name
Test status
Simulation time 9010488424 ps
CPU time 34.32 seconds
Started Aug 13 05:48:49 PM PDT 24
Finished Aug 13 05:49:23 PM PDT 24
Peak memory 232988 kb
Host smart-4ac414e2-8ed3-42b5-b321-02f1db1e9ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807680556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2807680556
Directory /workspace/1.spi_device_flash_mode/latest


Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.975736083
Short name T900
Test name
Test status
Simulation time 30999738744 ps
CPU time 204.11 seconds
Started Aug 13 05:48:54 PM PDT 24
Finished Aug 13 05:52:19 PM PDT 24
Peak memory 249384 kb
Host smart-5a929ba5-7793-4447-9f96-08c7e99d4c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975736083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
975736083
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/1.spi_device_intercept.3796025945
Short name T823
Test name
Test status
Simulation time 2700234896 ps
CPU time 11.57 seconds
Started Aug 13 05:48:49 PM PDT 24
Finished Aug 13 05:49:01 PM PDT 24
Peak memory 232968 kb
Host smart-4849f508-3842-420f-9208-4f29b9950660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796025945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3796025945
Directory /workspace/1.spi_device_intercept/latest


Test location /workspace/coverage/default/1.spi_device_mailbox.515229043
Short name T277
Test name
Test status
Simulation time 6558711012 ps
CPU time 75.9 seconds
Started Aug 13 05:48:48 PM PDT 24
Finished Aug 13 05:50:04 PM PDT 24
Peak memory 232992 kb
Host smart-88acc27a-4cd0-4ea7-a1c9-80441331a4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515229043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.515229043
Directory /workspace/1.spi_device_mailbox/latest


Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3174027882
Short name T827
Test name
Test status
Simulation time 1211419301 ps
CPU time 8 seconds
Started Aug 13 05:48:45 PM PDT 24
Finished Aug 13 05:48:54 PM PDT 24
Peak memory 232936 kb
Host smart-b1a6551e-38ba-449c-b454-517be576efc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174027882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3174027882
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1167927582
Short name T485
Test name
Test status
Simulation time 4461999493 ps
CPU time 18.42 seconds
Started Aug 13 05:48:46 PM PDT 24
Finished Aug 13 05:49:05 PM PDT 24
Peak memory 233068 kb
Host smart-8f2327bd-28a4-401c-b717-2dea124367ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167927582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1167927582
Directory /workspace/1.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.656723547
Short name T683
Test name
Test status
Simulation time 148419867 ps
CPU time 3.98 seconds
Started Aug 13 05:48:56 PM PDT 24
Finished Aug 13 05:49:00 PM PDT 24
Peak memory 219384 kb
Host smart-dd305320-8ba6-4d59-8e46-767185a6192e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=656723547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.656723547
Directory /workspace/1.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/1.spi_device_sec_cm.2241848884
Short name T75
Test name
Test status
Simulation time 90034600 ps
CPU time 1.27 seconds
Started Aug 13 05:48:56 PM PDT 24
Finished Aug 13 05:48:57 PM PDT 24
Peak memory 235656 kb
Host smart-9750c480-b0e7-45cd-b80b-2d536385a951
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241848884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2241848884
Directory /workspace/1.spi_device_sec_cm/latest


Test location /workspace/coverage/default/1.spi_device_tpm_all.509515280
Short name T330
Test name
Test status
Simulation time 2411013405 ps
CPU time 26.81 seconds
Started Aug 13 05:48:47 PM PDT 24
Finished Aug 13 05:49:14 PM PDT 24
Peak memory 219972 kb
Host smart-67111522-eeaf-4bdd-8788-46d0180e86d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509515280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.509515280
Directory /workspace/1.spi_device_tpm_all/latest


Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1564763262
Short name T863
Test name
Test status
Simulation time 629995089 ps
CPU time 2.7 seconds
Started Aug 13 05:48:48 PM PDT 24
Finished Aug 13 05:48:51 PM PDT 24
Peak memory 216464 kb
Host smart-c4077b86-bdc6-4b45-943f-b9e572398774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564763262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1564763262
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/1.spi_device_tpm_rw.895783580
Short name T83
Test name
Test status
Simulation time 35290330 ps
CPU time 0.97 seconds
Started Aug 13 05:48:47 PM PDT 24
Finished Aug 13 05:48:48 PM PDT 24
Peak memory 206944 kb
Host smart-1657f5b7-f9e3-4c5a-a600-86f14b2e63f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895783580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.895783580
Directory /workspace/1.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2455459335
Short name T967
Test name
Test status
Simulation time 35309544 ps
CPU time 0.67 seconds
Started Aug 13 05:48:47 PM PDT 24
Finished Aug 13 05:48:48 PM PDT 24
Peak memory 205600 kb
Host smart-a730b3ef-5cb0-46e9-a5f8-f0a5dfebaa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455459335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2455459335
Directory /workspace/1.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/1.spi_device_upload.2036383163
Short name T856
Test name
Test status
Simulation time 2049616338 ps
CPU time 11.69 seconds
Started Aug 13 05:48:47 PM PDT 24
Finished Aug 13 05:48:59 PM PDT 24
Peak memory 249868 kb
Host smart-b1d239e5-5d57-4237-8227-b56ad17f9ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036383163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2036383163
Directory /workspace/1.spi_device_upload/latest


Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2538506449
Short name T966
Test name
Test status
Simulation time 137850288 ps
CPU time 3.3 seconds
Started Aug 13 05:50:02 PM PDT 24
Finished Aug 13 05:50:06 PM PDT 24
Peak memory 232808 kb
Host smart-a03c6cd5-dd06-4dca-8e89-8d9c30537fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538506449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2538506449
Directory /workspace/10.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/10.spi_device_csb_read.3747175656
Short name T734
Test name
Test status
Simulation time 49679725 ps
CPU time 0.81 seconds
Started Aug 13 05:49:57 PM PDT 24
Finished Aug 13 05:49:58 PM PDT 24
Peak memory 206616 kb
Host smart-a8787fc8-d35e-4de8-ac97-fc4d8d99e43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747175656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3747175656
Directory /workspace/10.spi_device_csb_read/latest


Test location /workspace/coverage/default/10.spi_device_flash_all.1810545942
Short name T907
Test name
Test status
Simulation time 43665264 ps
CPU time 0.82 seconds
Started Aug 13 05:50:02 PM PDT 24
Finished Aug 13 05:50:03 PM PDT 24
Peak memory 207680 kb
Host smart-2eda7201-6cba-48e8-b00c-f79c456b18ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810545942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1810545942
Directory /workspace/10.spi_device_flash_all/latest


Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3823526061
Short name T744
Test name
Test status
Simulation time 13101916602 ps
CPU time 80.53 seconds
Started Aug 13 05:50:04 PM PDT 24
Finished Aug 13 05:51:24 PM PDT 24
Peak memory 256804 kb
Host smart-7d8b7ce1-dc94-4dc7-9364-70d063b0e068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823526061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3823526061
Directory /workspace/10.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/10.spi_device_flash_mode.797746587
Short name T440
Test name
Test status
Simulation time 200586476 ps
CPU time 2.93 seconds
Started Aug 13 05:50:01 PM PDT 24
Finished Aug 13 05:50:04 PM PDT 24
Peak memory 224676 kb
Host smart-1b58dd7a-54d7-4d31-98b1-75787451f6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797746587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.797746587
Directory /workspace/10.spi_device_flash_mode/latest


Test location /workspace/coverage/default/10.spi_device_intercept.339144851
Short name T795
Test name
Test status
Simulation time 1107896881 ps
CPU time 4.36 seconds
Started Aug 13 05:50:06 PM PDT 24
Finished Aug 13 05:50:11 PM PDT 24
Peak memory 224656 kb
Host smart-0e899ade-9d62-4ae9-86fa-b0cbcdcaab36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339144851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.339144851
Directory /workspace/10.spi_device_intercept/latest


Test location /workspace/coverage/default/10.spi_device_mailbox.3334312332
Short name T587
Test name
Test status
Simulation time 33214233 ps
CPU time 2.81 seconds
Started Aug 13 05:50:03 PM PDT 24
Finished Aug 13 05:50:06 PM PDT 24
Peak memory 232556 kb
Host smart-e18090fc-f9d7-4576-a7d9-b5f81c0aab33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334312332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3334312332
Directory /workspace/10.spi_device_mailbox/latest


Test location /workspace/coverage/default/10.spi_device_mem_parity.2425673384
Short name T562
Test name
Test status
Simulation time 105857645 ps
CPU time 1.1 seconds
Started Aug 13 05:50:02 PM PDT 24
Finished Aug 13 05:50:04 PM PDT 24
Peak memory 216744 kb
Host smart-ebb98cf4-0a2c-4e62-8f9a-b420b180a2a7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425673384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2425673384
Directory /workspace/10.spi_device_mem_parity/latest


Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.668771613
Short name T980
Test name
Test status
Simulation time 32952032 ps
CPU time 2.55 seconds
Started Aug 13 05:50:03 PM PDT 24
Finished Aug 13 05:50:06 PM PDT 24
Peak memory 232916 kb
Host smart-0121695b-781b-47b5-bcdf-831ccaf152b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668771613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.668771613
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4109165055
Short name T64
Test name
Test status
Simulation time 30317422 ps
CPU time 2.23 seconds
Started Aug 13 05:50:04 PM PDT 24
Finished Aug 13 05:50:06 PM PDT 24
Peak memory 232536 kb
Host smart-21203007-1c16-492a-91d1-803d5cb29edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109165055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4109165055
Directory /workspace/10.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1660222860
Short name T487
Test name
Test status
Simulation time 1015420244 ps
CPU time 11.71 seconds
Started Aug 13 05:50:02 PM PDT 24
Finished Aug 13 05:50:14 PM PDT 24
Peak memory 220496 kb
Host smart-cc93797e-3ef9-49c4-9fbf-8db9799dd5d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1660222860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1660222860
Directory /workspace/10.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/10.spi_device_stress_all.3928827419
Short name T34
Test name
Test status
Simulation time 127234818 ps
CPU time 1.08 seconds
Started Aug 13 05:50:01 PM PDT 24
Finished Aug 13 05:50:03 PM PDT 24
Peak memory 206920 kb
Host smart-214f2963-7fab-4d02-8395-41109d5e0edb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928827419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3928827419
Directory /workspace/10.spi_device_stress_all/latest


Test location /workspace/coverage/default/10.spi_device_tpm_all.3852575379
Short name T674
Test name
Test status
Simulation time 5984818245 ps
CPU time 35.44 seconds
Started Aug 13 05:50:05 PM PDT 24
Finished Aug 13 05:50:40 PM PDT 24
Peak memory 217868 kb
Host smart-e52ef917-8292-415e-bb00-bea06d47b19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852575379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3852575379
Directory /workspace/10.spi_device_tpm_all/latest


Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1834870940
Short name T402
Test name
Test status
Simulation time 1683368524 ps
CPU time 3.26 seconds
Started Aug 13 05:50:04 PM PDT 24
Finished Aug 13 05:50:07 PM PDT 24
Peak memory 216448 kb
Host smart-c008f1df-4698-4d1e-bbfe-cc425f4ac74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834870940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1834870940
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/10.spi_device_tpm_rw.4219577923
Short name T500
Test name
Test status
Simulation time 30688572 ps
CPU time 0.71 seconds
Started Aug 13 05:50:06 PM PDT 24
Finished Aug 13 05:50:07 PM PDT 24
Peak memory 205672 kb
Host smart-d6ba500b-95bf-4aa0-b311-feb983dfe54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219577923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.4219577923
Directory /workspace/10.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1447178474
Short name T406
Test name
Test status
Simulation time 99103910 ps
CPU time 1.08 seconds
Started Aug 13 05:50:03 PM PDT 24
Finished Aug 13 05:50:04 PM PDT 24
Peak memory 206160 kb
Host smart-6efe3ca4-6a6f-44f8-ae74-ccfeb4a29615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447178474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1447178474
Directory /workspace/10.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/10.spi_device_upload.342494786
Short name T884
Test name
Test status
Simulation time 5075800003 ps
CPU time 20.43 seconds
Started Aug 13 05:50:03 PM PDT 24
Finished Aug 13 05:50:23 PM PDT 24
Peak memory 240812 kb
Host smart-7590bee5-8619-4776-8867-63f98b5b1c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342494786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.342494786
Directory /workspace/10.spi_device_upload/latest


Test location /workspace/coverage/default/11.spi_device_alert_test.3548548766
Short name T569
Test name
Test status
Simulation time 32854251 ps
CPU time 0.7 seconds
Started Aug 13 05:50:19 PM PDT 24
Finished Aug 13 05:50:20 PM PDT 24
Peak memory 205532 kb
Host smart-3e102f57-a29c-44f0-bb06-1488db30f547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548548766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3548548766
Directory /workspace/11.spi_device_alert_test/latest


Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3090801221
Short name T701
Test name
Test status
Simulation time 1006892731 ps
CPU time 5.7 seconds
Started Aug 13 05:50:09 PM PDT 24
Finished Aug 13 05:50:15 PM PDT 24
Peak memory 232892 kb
Host smart-35962026-5386-47a0-9fbf-b6203f654a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090801221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3090801221
Directory /workspace/11.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/11.spi_device_csb_read.2391316345
Short name T566
Test name
Test status
Simulation time 69129048 ps
CPU time 0.79 seconds
Started Aug 13 05:50:12 PM PDT 24
Finished Aug 13 05:50:13 PM PDT 24
Peak memory 206616 kb
Host smart-bc6e9d77-3b9f-4cdc-8c2e-90f1356c7456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391316345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2391316345
Directory /workspace/11.spi_device_csb_read/latest


Test location /workspace/coverage/default/11.spi_device_flash_all.3858970924
Short name T264
Test name
Test status
Simulation time 20468194543 ps
CPU time 151.92 seconds
Started Aug 13 05:50:15 PM PDT 24
Finished Aug 13 05:52:47 PM PDT 24
Peak memory 252120 kb
Host smart-1f1c6c42-9cd2-4796-bca6-93d5eb40b0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858970924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3858970924
Directory /workspace/11.spi_device_flash_all/latest


Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.567721078
Short name T773
Test name
Test status
Simulation time 25614005755 ps
CPU time 101.65 seconds
Started Aug 13 05:50:18 PM PDT 24
Finished Aug 13 05:52:00 PM PDT 24
Peak memory 261268 kb
Host smart-d801341c-d3f7-49d7-8e4d-0dd18fc0e53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567721078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.567721078
Directory /workspace/11.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1935427438
Short name T9
Test name
Test status
Simulation time 268040798 ps
CPU time 3.58 seconds
Started Aug 13 05:50:18 PM PDT 24
Finished Aug 13 05:50:22 PM PDT 24
Peak memory 217540 kb
Host smart-ea97d426-172f-497b-9cb0-09e778e41852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935427438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1935427438
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/11.spi_device_flash_mode.3174817987
Short name T828
Test name
Test status
Simulation time 2318408646 ps
CPU time 10.35 seconds
Started Aug 13 05:50:15 PM PDT 24
Finished Aug 13 05:50:25 PM PDT 24
Peak memory 224748 kb
Host smart-fdfd475e-bcd4-4c73-9cc3-8516d34ed18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174817987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3174817987
Directory /workspace/11.spi_device_flash_mode/latest


Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2216214531
Short name T643
Test name
Test status
Simulation time 1076227165 ps
CPU time 16.81 seconds
Started Aug 13 05:50:13 PM PDT 24
Finished Aug 13 05:50:30 PM PDT 24
Peak memory 249268 kb
Host smart-16265119-56b3-4909-800b-9ddea7867b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216214531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2216214531
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/11.spi_device_intercept.3584076984
Short name T340
Test name
Test status
Simulation time 69155873 ps
CPU time 2.86 seconds
Started Aug 13 05:50:12 PM PDT 24
Finished Aug 13 05:50:15 PM PDT 24
Peak memory 224736 kb
Host smart-5d6f2366-0d84-4087-bc75-36ae8198e021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584076984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3584076984
Directory /workspace/11.spi_device_intercept/latest


Test location /workspace/coverage/default/11.spi_device_mailbox.2419508706
Short name T995
Test name
Test status
Simulation time 36198451941 ps
CPU time 78.26 seconds
Started Aug 13 05:50:13 PM PDT 24
Finished Aug 13 05:51:31 PM PDT 24
Peak memory 219852 kb
Host smart-0956876b-c84c-4180-9a56-66d503211a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419508706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2419508706
Directory /workspace/11.spi_device_mailbox/latest


Test location /workspace/coverage/default/11.spi_device_mem_parity.2563121139
Short name T40
Test name
Test status
Simulation time 42780302 ps
CPU time 1.01 seconds
Started Aug 13 05:50:12 PM PDT 24
Finished Aug 13 05:50:13 PM PDT 24
Peak memory 216744 kb
Host smart-9d080ccf-2ff6-476f-86d0-896f8bb10060
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563121139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2563121139
Directory /workspace/11.spi_device_mem_parity/latest


Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2780856961
Short name T262
Test name
Test status
Simulation time 1175074363 ps
CPU time 6.21 seconds
Started Aug 13 05:50:12 PM PDT 24
Finished Aug 13 05:50:19 PM PDT 24
Peak memory 232932 kb
Host smart-55a6b4e0-4315-486b-97b8-298601dc5ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780856961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2780856961
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2256778593
Short name T584
Test name
Test status
Simulation time 15826353126 ps
CPU time 18.31 seconds
Started Aug 13 05:50:13 PM PDT 24
Finished Aug 13 05:50:31 PM PDT 24
Peak memory 249288 kb
Host smart-5ff53947-537a-4eb2-93e3-64ac5d53a090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256778593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2256778593
Directory /workspace/11.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.418614838
Short name T811
Test name
Test status
Simulation time 1694795463 ps
CPU time 9.17 seconds
Started Aug 13 05:50:15 PM PDT 24
Finished Aug 13 05:50:25 PM PDT 24
Peak memory 222412 kb
Host smart-3b8abaf4-eb75-4428-9e10-ae78bc950600
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=418614838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.418614838
Directory /workspace/11.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/11.spi_device_stress_all.1936611374
Short name T164
Test name
Test status
Simulation time 48472240 ps
CPU time 1.04 seconds
Started Aug 13 05:50:19 PM PDT 24
Finished Aug 13 05:50:20 PM PDT 24
Peak memory 207584 kb
Host smart-dc82d718-4a19-4468-bfd0-d420f455c88b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936611374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1936611374
Directory /workspace/11.spi_device_stress_all/latest


Test location /workspace/coverage/default/11.spi_device_tpm_all.2671397743
Short name T528
Test name
Test status
Simulation time 943244769 ps
CPU time 13.22 seconds
Started Aug 13 05:50:12 PM PDT 24
Finished Aug 13 05:50:25 PM PDT 24
Peak memory 216452 kb
Host smart-b3aed63b-9190-4b2f-b5a0-9b81025675e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671397743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2671397743
Directory /workspace/11.spi_device_tpm_all/latest


Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1187636068
Short name T427
Test name
Test status
Simulation time 293356364 ps
CPU time 1.07 seconds
Started Aug 13 05:50:14 PM PDT 24
Finished Aug 13 05:50:15 PM PDT 24
Peak memory 207268 kb
Host smart-e3c4d107-d827-4c86-9730-b11af6b1b717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187636068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1187636068
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/11.spi_device_tpm_rw.619364669
Short name T864
Test name
Test status
Simulation time 414572324 ps
CPU time 6.03 seconds
Started Aug 13 05:50:12 PM PDT 24
Finished Aug 13 05:50:18 PM PDT 24
Peak memory 216408 kb
Host smart-c13577ac-8acb-49cd-b8cf-104ed962a201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619364669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.619364669
Directory /workspace/11.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3367999387
Short name T543
Test name
Test status
Simulation time 116456365 ps
CPU time 0.86 seconds
Started Aug 13 05:50:13 PM PDT 24
Finished Aug 13 05:50:14 PM PDT 24
Peak memory 206112 kb
Host smart-ffb70f25-b9f9-4b9a-9132-4eb5941f0b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367999387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3367999387
Directory /workspace/11.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/11.spi_device_upload.313450992
Short name T793
Test name
Test status
Simulation time 162403301 ps
CPU time 3.26 seconds
Started Aug 13 05:50:14 PM PDT 24
Finished Aug 13 05:50:18 PM PDT 24
Peak memory 224680 kb
Host smart-505fad15-cf16-4667-b4fc-9805c92fc98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313450992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.313450992
Directory /workspace/11.spi_device_upload/latest


Test location /workspace/coverage/default/12.spi_device_alert_test.2576997827
Short name T505
Test name
Test status
Simulation time 33361474 ps
CPU time 0.71 seconds
Started Aug 13 05:50:29 PM PDT 24
Finished Aug 13 05:50:30 PM PDT 24
Peak memory 205588 kb
Host smart-e4da9002-08ff-4493-8803-f0d51438774e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576997827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2576997827
Directory /workspace/12.spi_device_alert_test/latest


Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3706299831
Short name T974
Test name
Test status
Simulation time 221688073 ps
CPU time 3.37 seconds
Started Aug 13 05:50:19 PM PDT 24
Finished Aug 13 05:50:22 PM PDT 24
Peak memory 224648 kb
Host smart-273a18bd-20e6-4859-aec6-db69517da7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706299831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3706299831
Directory /workspace/12.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/12.spi_device_csb_read.1454978506
Short name T604
Test name
Test status
Simulation time 29356139 ps
CPU time 0.75 seconds
Started Aug 13 05:50:17 PM PDT 24
Finished Aug 13 05:50:18 PM PDT 24
Peak memory 205564 kb
Host smart-253c6d55-c6b7-4cc3-9753-8c7e37316c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454978506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1454978506
Directory /workspace/12.spi_device_csb_read/latest


Test location /workspace/coverage/default/12.spi_device_flash_all.1234641700
Short name T221
Test name
Test status
Simulation time 46906479059 ps
CPU time 343.03 seconds
Started Aug 13 05:50:17 PM PDT 24
Finished Aug 13 05:56:00 PM PDT 24
Peak memory 256168 kb
Host smart-03c5a610-61d6-4db8-960c-a6ce0593d9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234641700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1234641700
Directory /workspace/12.spi_device_flash_all/latest


Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.4022277429
Short name T249
Test name
Test status
Simulation time 59146016775 ps
CPU time 129.98 seconds
Started Aug 13 05:50:18 PM PDT 24
Finished Aug 13 05:52:28 PM PDT 24
Peak memory 265804 kb
Host smart-560be721-661f-46b0-843f-c1764e95a0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022277429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4022277429
Directory /workspace/12.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2052031215
Short name T299
Test name
Test status
Simulation time 172587005220 ps
CPU time 397.21 seconds
Started Aug 13 05:50:18 PM PDT 24
Finished Aug 13 05:56:55 PM PDT 24
Peak memory 266612 kb
Host smart-52f9a362-c797-4290-8334-790f5036c437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052031215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2052031215
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/12.spi_device_flash_mode.2710971381
Short name T3
Test name
Test status
Simulation time 4267739318 ps
CPU time 17.17 seconds
Started Aug 13 05:50:17 PM PDT 24
Finished Aug 13 05:50:34 PM PDT 24
Peak memory 224692 kb
Host smart-31856756-2736-4e77-bca9-d778492cff34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710971381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2710971381
Directory /workspace/12.spi_device_flash_mode/latest


Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1130648401
Short name T233
Test name
Test status
Simulation time 154197346999 ps
CPU time 252.82 seconds
Started Aug 13 05:50:18 PM PDT 24
Finished Aug 13 05:54:31 PM PDT 24
Peak memory 250408 kb
Host smart-77391b82-5c99-4ed4-9479-a5fb041f3abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130648401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1130648401
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/12.spi_device_intercept.1775572833
Short name T85
Test name
Test status
Simulation time 239342494 ps
CPU time 5.98 seconds
Started Aug 13 05:50:17 PM PDT 24
Finished Aug 13 05:50:24 PM PDT 24
Peak memory 228580 kb
Host smart-70ad3ccb-df36-4c58-a469-b634bd34743e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775572833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1775572833
Directory /workspace/12.spi_device_intercept/latest


Test location /workspace/coverage/default/12.spi_device_mailbox.1452976623
Short name T186
Test name
Test status
Simulation time 751029793 ps
CPU time 15 seconds
Started Aug 13 05:50:18 PM PDT 24
Finished Aug 13 05:50:33 PM PDT 24
Peak memory 250068 kb
Host smart-24770880-c0e3-4bab-afd1-ec178fdc43b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452976623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1452976623
Directory /workspace/12.spi_device_mailbox/latest


Test location /workspace/coverage/default/12.spi_device_mem_parity.1866759712
Short name T389
Test name
Test status
Simulation time 27298767 ps
CPU time 1.11 seconds
Started Aug 13 05:50:17 PM PDT 24
Finished Aug 13 05:50:18 PM PDT 24
Peak memory 216760 kb
Host smart-c06ace74-1863-4ab6-afda-da410939d299
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866759712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1866759712
Directory /workspace/12.spi_device_mem_parity/latest


Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3339143690
Short name T280
Test name
Test status
Simulation time 537064628 ps
CPU time 2.59 seconds
Started Aug 13 05:50:18 PM PDT 24
Finished Aug 13 05:50:21 PM PDT 24
Peak memory 224624 kb
Host smart-67b09f9f-9b96-41ef-af9f-6512ddc1e8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339143690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3339143690
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2768206975
Short name T696
Test name
Test status
Simulation time 905290200 ps
CPU time 8.04 seconds
Started Aug 13 05:50:18 PM PDT 24
Finished Aug 13 05:50:26 PM PDT 24
Peak memory 239172 kb
Host smart-cce0d364-c68c-4862-8012-35bb92d50241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768206975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2768206975
Directory /workspace/12.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.11189436
Short name T883
Test name
Test status
Simulation time 412836859 ps
CPU time 4.32 seconds
Started Aug 13 05:50:20 PM PDT 24
Finished Aug 13 05:50:24 PM PDT 24
Peak memory 221952 kb
Host smart-43f26625-6751-4947-b60a-115b0a1983a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=11189436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direc
t.11189436
Directory /workspace/12.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/12.spi_device_stress_all.2693999673
Short name T163
Test name
Test status
Simulation time 378868891375 ps
CPU time 832.83 seconds
Started Aug 13 05:50:17 PM PDT 24
Finished Aug 13 06:04:10 PM PDT 24
Peak memory 289384 kb
Host smart-cc9ffe10-a90e-4b43-bd2a-b3b24ebd614d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693999673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2693999673
Directory /workspace/12.spi_device_stress_all/latest


Test location /workspace/coverage/default/12.spi_device_tpm_all.2607502944
Short name T322
Test name
Test status
Simulation time 4152155551 ps
CPU time 26.31 seconds
Started Aug 13 05:50:17 PM PDT 24
Finished Aug 13 05:50:44 PM PDT 24
Peak memory 220280 kb
Host smart-1a996982-2388-431a-906f-fe59fd5e9263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607502944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2607502944
Directory /workspace/12.spi_device_tpm_all/latest


Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3501141296
Short name T892
Test name
Test status
Simulation time 14347259228 ps
CPU time 21.6 seconds
Started Aug 13 05:50:18 PM PDT 24
Finished Aug 13 05:50:39 PM PDT 24
Peak memory 216464 kb
Host smart-1936f6f5-f48d-4d21-899e-54db64aa3039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501141296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3501141296
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/12.spi_device_tpm_rw.475175437
Short name T1001
Test name
Test status
Simulation time 110464371 ps
CPU time 3.52 seconds
Started Aug 13 05:50:19 PM PDT 24
Finished Aug 13 05:50:22 PM PDT 24
Peak memory 216508 kb
Host smart-d522eed1-f4c9-43a8-a39d-2629fc4bd03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475175437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.475175437
Directory /workspace/12.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3687879132
Short name T891
Test name
Test status
Simulation time 52684716 ps
CPU time 0.83 seconds
Started Aug 13 05:50:20 PM PDT 24
Finished Aug 13 05:50:21 PM PDT 24
Peak memory 206108 kb
Host smart-e0b76f66-a2e0-4dd1-98cf-d6f9ac91411e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687879132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3687879132
Directory /workspace/12.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/12.spi_device_upload.1010836761
Short name T251
Test name
Test status
Simulation time 2114379248 ps
CPU time 7.21 seconds
Started Aug 13 05:50:17 PM PDT 24
Finished Aug 13 05:50:25 PM PDT 24
Peak memory 238216 kb
Host smart-ea715c72-aa11-4716-bd38-e827a9d830c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010836761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1010836761
Directory /workspace/12.spi_device_upload/latest


Test location /workspace/coverage/default/13.spi_device_alert_test.1078915
Short name T792
Test name
Test status
Simulation time 24427225 ps
CPU time 0.73 seconds
Started Aug 13 05:50:29 PM PDT 24
Finished Aug 13 05:50:30 PM PDT 24
Peak memory 205908 kb
Host smart-a050b72f-9824-4f32-9dab-5853ae9e597b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.1078915
Directory /workspace/13.spi_device_alert_test/latest


Test location /workspace/coverage/default/13.spi_device_cfg_cmd.93220228
Short name T410
Test name
Test status
Simulation time 598555057 ps
CPU time 3.03 seconds
Started Aug 13 05:50:29 PM PDT 24
Finished Aug 13 05:50:32 PM PDT 24
Peak memory 232872 kb
Host smart-5906c026-d09b-4963-a0ab-c54750a7f23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93220228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.93220228
Directory /workspace/13.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/13.spi_device_csb_read.3173485392
Short name T622
Test name
Test status
Simulation time 20268996 ps
CPU time 0.81 seconds
Started Aug 13 05:50:28 PM PDT 24
Finished Aug 13 05:50:29 PM PDT 24
Peak memory 206632 kb
Host smart-20d07f5f-c34d-43d4-883a-ab8b833ae4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173485392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3173485392
Directory /workspace/13.spi_device_csb_read/latest


Test location /workspace/coverage/default/13.spi_device_flash_all.1844196038
Short name T1019
Test name
Test status
Simulation time 30693137034 ps
CPU time 277.63 seconds
Started Aug 13 05:50:27 PM PDT 24
Finished Aug 13 05:55:05 PM PDT 24
Peak memory 265764 kb
Host smart-8b971ffe-467f-43db-a5ef-a3583d9e3498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844196038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1844196038
Directory /workspace/13.spi_device_flash_all/latest


Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1659299964
Short name T654
Test name
Test status
Simulation time 2018282622 ps
CPU time 46.35 seconds
Started Aug 13 05:50:28 PM PDT 24
Finished Aug 13 05:51:15 PM PDT 24
Peak memory 239736 kb
Host smart-9159843f-c7ed-4b84-a8c4-9bdc66c19187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659299964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1659299964
Directory /workspace/13.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3493400269
Short name T800
Test name
Test status
Simulation time 326999502700 ps
CPU time 536.46 seconds
Started Aug 13 05:50:27 PM PDT 24
Finished Aug 13 05:59:24 PM PDT 24
Peak memory 253992 kb
Host smart-d31d6615-3ed0-4b56-9670-a025ed7eff8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493400269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3493400269
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/13.spi_device_flash_mode.1358225660
Short name T575
Test name
Test status
Simulation time 66670598 ps
CPU time 3.93 seconds
Started Aug 13 05:50:28 PM PDT 24
Finished Aug 13 05:50:32 PM PDT 24
Peak memory 232896 kb
Host smart-aebe32fe-a293-4ff9-92b5-1fcc21fa9fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358225660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1358225660
Directory /workspace/13.spi_device_flash_mode/latest


Test location /workspace/coverage/default/13.spi_device_intercept.3642806174
Short name T488
Test name
Test status
Simulation time 1725450952 ps
CPU time 7 seconds
Started Aug 13 05:50:27 PM PDT 24
Finished Aug 13 05:50:34 PM PDT 24
Peak memory 232940 kb
Host smart-4a8da98c-68bc-416d-b18b-cf1960532cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642806174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3642806174
Directory /workspace/13.spi_device_intercept/latest


Test location /workspace/coverage/default/13.spi_device_mailbox.2868094252
Short name T242
Test name
Test status
Simulation time 2157889777 ps
CPU time 18.98 seconds
Started Aug 13 05:50:28 PM PDT 24
Finished Aug 13 05:50:47 PM PDT 24
Peak memory 224784 kb
Host smart-6993eaeb-23cd-4628-8291-697777c680c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868094252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2868094252
Directory /workspace/13.spi_device_mailbox/latest


Test location /workspace/coverage/default/13.spi_device_mem_parity.3955857853
Short name T23
Test name
Test status
Simulation time 35106876 ps
CPU time 1.08 seconds
Started Aug 13 05:50:27 PM PDT 24
Finished Aug 13 05:50:29 PM PDT 24
Peak memory 216752 kb
Host smart-86c7073c-5f78-4f52-b0de-aab60496fc97
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955857853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3955857853
Directory /workspace/13.spi_device_mem_parity/latest


Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3128271025
Short name T182
Test name
Test status
Simulation time 453428987 ps
CPU time 6.22 seconds
Started Aug 13 05:50:27 PM PDT 24
Finished Aug 13 05:50:34 PM PDT 24
Peak memory 232892 kb
Host smart-770e52bc-7abf-4d28-863f-ac5aac0be296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128271025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3128271025
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3233705477
Short name T613
Test name
Test status
Simulation time 1738223801 ps
CPU time 5.42 seconds
Started Aug 13 05:50:28 PM PDT 24
Finished Aug 13 05:50:34 PM PDT 24
Peak memory 232868 kb
Host smart-5c70f1f5-39e0-450a-86b7-f7faafa31c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233705477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3233705477
Directory /workspace/13.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.4070147295
Short name T625
Test name
Test status
Simulation time 663562592 ps
CPU time 4.8 seconds
Started Aug 13 05:50:31 PM PDT 24
Finished Aug 13 05:50:36 PM PDT 24
Peak memory 220948 kb
Host smart-3ca4200f-ba64-46e0-8429-bff6ad5db2ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4070147295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.4070147295
Directory /workspace/13.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/13.spi_device_stress_all.3672181139
Short name T11
Test name
Test status
Simulation time 141408580 ps
CPU time 1.31 seconds
Started Aug 13 05:50:26 PM PDT 24
Finished Aug 13 05:50:28 PM PDT 24
Peak memory 207048 kb
Host smart-1bbc6287-b311-440f-b555-b68f364e897f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672181139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3672181139
Directory /workspace/13.spi_device_stress_all/latest


Test location /workspace/coverage/default/13.spi_device_tpm_all.274131606
Short name T785
Test name
Test status
Simulation time 25052044890 ps
CPU time 25.98 seconds
Started Aug 13 05:50:28 PM PDT 24
Finished Aug 13 05:50:54 PM PDT 24
Peak memory 216548 kb
Host smart-097bc1a2-0718-40fd-a8de-e04c2dc9ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274131606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.274131606
Directory /workspace/13.spi_device_tpm_all/latest


Test location /workspace/coverage/default/13.spi_device_tpm_rw.1652868931
Short name T345
Test name
Test status
Simulation time 118749971 ps
CPU time 1.49 seconds
Started Aug 13 05:50:25 PM PDT 24
Finished Aug 13 05:50:27 PM PDT 24
Peak memory 208040 kb
Host smart-0b438eb6-1a6a-4a4f-9fc9-24880bf131bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652868931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1652868931
Directory /workspace/13.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1619791932
Short name T351
Test name
Test status
Simulation time 158585190 ps
CPU time 0.92 seconds
Started Aug 13 05:50:28 PM PDT 24
Finished Aug 13 05:50:29 PM PDT 24
Peak memory 206120 kb
Host smart-aed58263-e59e-4b6a-81cf-eaf2a8145d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619791932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1619791932
Directory /workspace/13.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/13.spi_device_upload.3547573027
Short name T783
Test name
Test status
Simulation time 485033640 ps
CPU time 5.09 seconds
Started Aug 13 05:50:27 PM PDT 24
Finished Aug 13 05:50:32 PM PDT 24
Peak memory 220564 kb
Host smart-3d52c3f3-53b5-425f-8f7e-8fd6fb5ead68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547573027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3547573027
Directory /workspace/13.spi_device_upload/latest


Test location /workspace/coverage/default/14.spi_device_alert_test.4266861701
Short name T68
Test name
Test status
Simulation time 37795610 ps
CPU time 0.73 seconds
Started Aug 13 05:50:35 PM PDT 24
Finished Aug 13 05:50:36 PM PDT 24
Peak memory 205904 kb
Host smart-110c5129-3120-41bd-bda0-59b8295e2db7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266861701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
4266861701
Directory /workspace/14.spi_device_alert_test/latest


Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3541771601
Short name T699
Test name
Test status
Simulation time 3146068736 ps
CPU time 9.15 seconds
Started Aug 13 05:50:35 PM PDT 24
Finished Aug 13 05:50:44 PM PDT 24
Peak memory 232928 kb
Host smart-84fbc81e-0cd0-4e99-af1b-80e0b28e216b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541771601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3541771601
Directory /workspace/14.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/14.spi_device_csb_read.2222801793
Short name T707
Test name
Test status
Simulation time 99438498 ps
CPU time 0.72 seconds
Started Aug 13 05:50:27 PM PDT 24
Finished Aug 13 05:50:28 PM PDT 24
Peak memory 205960 kb
Host smart-314f83c1-f560-41c7-9303-f8fe8b5c64a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222801793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2222801793
Directory /workspace/14.spi_device_csb_read/latest


Test location /workspace/coverage/default/14.spi_device_flash_all.4290034076
Short name T723
Test name
Test status
Simulation time 21152590895 ps
CPU time 169.72 seconds
Started Aug 13 05:50:36 PM PDT 24
Finished Aug 13 05:53:25 PM PDT 24
Peak memory 249376 kb
Host smart-2ab4229e-ad5a-4e82-8680-a1f26b56ee69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290034076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4290034076
Directory /workspace/14.spi_device_flash_all/latest


Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2665897263
Short name T484
Test name
Test status
Simulation time 93327162039 ps
CPU time 74.21 seconds
Started Aug 13 05:50:37 PM PDT 24
Finished Aug 13 05:51:51 PM PDT 24
Peak memory 249288 kb
Host smart-01cf12e2-ea7d-48ca-96d4-6dd157584ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665897263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2665897263
Directory /workspace/14.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.197074839
Short name T234
Test name
Test status
Simulation time 66079818969 ps
CPU time 360.02 seconds
Started Aug 13 05:50:36 PM PDT 24
Finished Aug 13 05:56:36 PM PDT 24
Peak memory 257520 kb
Host smart-82b3444f-4a56-42b4-b5af-63addf30a2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197074839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.197074839
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.4228531200
Short name T836
Test name
Test status
Simulation time 1150765592 ps
CPU time 6.29 seconds
Started Aug 13 05:50:35 PM PDT 24
Finished Aug 13 05:50:41 PM PDT 24
Peak memory 224652 kb
Host smart-14bae0b4-3ddf-4a86-91a1-c2b0dcf830a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228531200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.4228531200
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/14.spi_device_intercept.318743231
Short name T400
Test name
Test status
Simulation time 41436248 ps
CPU time 2.6 seconds
Started Aug 13 05:50:27 PM PDT 24
Finished Aug 13 05:50:30 PM PDT 24
Peak memory 232520 kb
Host smart-40044698-dc88-4ac2-82c6-f2f28fd55749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318743231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.318743231
Directory /workspace/14.spi_device_intercept/latest


Test location /workspace/coverage/default/14.spi_device_mailbox.772016409
Short name T594
Test name
Test status
Simulation time 6508302960 ps
CPU time 11.81 seconds
Started Aug 13 05:50:32 PM PDT 24
Finished Aug 13 05:50:45 PM PDT 24
Peak memory 232968 kb
Host smart-bf37ff23-64ad-49f9-a563-d2577f0ab1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772016409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.772016409
Directory /workspace/14.spi_device_mailbox/latest


Test location /workspace/coverage/default/14.spi_device_mem_parity.3489420297
Short name T453
Test name
Test status
Simulation time 44720765 ps
CPU time 1.14 seconds
Started Aug 13 05:50:29 PM PDT 24
Finished Aug 13 05:50:30 PM PDT 24
Peak memory 216752 kb
Host smart-1f269ca2-ef8f-497f-a531-87899bba900c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489420297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3489420297
Directory /workspace/14.spi_device_mem_parity/latest


Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2586872702
Short name T697
Test name
Test status
Simulation time 47839127 ps
CPU time 2.65 seconds
Started Aug 13 05:50:29 PM PDT 24
Finished Aug 13 05:50:32 PM PDT 24
Peak memory 232852 kb
Host smart-f7c7ed75-2952-4028-aad7-1e571626db60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586872702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2586872702
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1036586173
Short name T787
Test name
Test status
Simulation time 203117334287 ps
CPU time 26.67 seconds
Started Aug 13 05:50:29 PM PDT 24
Finished Aug 13 05:50:56 PM PDT 24
Peak memory 234048 kb
Host smart-f40f2860-3206-4c6d-93aa-bc7b603de5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036586173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1036586173
Directory /workspace/14.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1637357888
Short name T764
Test name
Test status
Simulation time 392567756 ps
CPU time 5.36 seconds
Started Aug 13 05:50:36 PM PDT 24
Finished Aug 13 05:50:41 PM PDT 24
Peak memory 220528 kb
Host smart-b7a477e3-c17a-4948-8226-90a4fb3d685f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1637357888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1637357888
Directory /workspace/14.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/14.spi_device_stress_all.2245496399
Short name T70
Test name
Test status
Simulation time 94190813 ps
CPU time 1.22 seconds
Started Aug 13 05:50:36 PM PDT 24
Finished Aug 13 05:50:38 PM PDT 24
Peak memory 207184 kb
Host smart-aa3cfdb1-50d7-4b6d-9826-127fc267f814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245496399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2245496399
Directory /workspace/14.spi_device_stress_all/latest


Test location /workspace/coverage/default/14.spi_device_tpm_all.611602715
Short name T735
Test name
Test status
Simulation time 46352340764 ps
CPU time 37.04 seconds
Started Aug 13 05:50:29 PM PDT 24
Finished Aug 13 05:51:06 PM PDT 24
Peak memory 216588 kb
Host smart-e6d6054c-2765-4e2c-8885-2917faf5146e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611602715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.611602715
Directory /workspace/14.spi_device_tpm_all/latest


Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1234083234
Short name T851
Test name
Test status
Simulation time 397352798 ps
CPU time 1.65 seconds
Started Aug 13 05:50:26 PM PDT 24
Finished Aug 13 05:50:28 PM PDT 24
Peak memory 207976 kb
Host smart-89f002d7-c6f9-475d-a052-b248ed0e8896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234083234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1234083234
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/14.spi_device_tpm_rw.1372525608
Short name T859
Test name
Test status
Simulation time 24096219 ps
CPU time 0.83 seconds
Started Aug 13 05:50:28 PM PDT 24
Finished Aug 13 05:50:29 PM PDT 24
Peak memory 206132 kb
Host smart-996b3080-c514-4bba-ad84-f73c9e09d29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372525608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1372525608
Directory /workspace/14.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2552643171
Short name T641
Test name
Test status
Simulation time 44854024 ps
CPU time 0.81 seconds
Started Aug 13 05:50:28 PM PDT 24
Finished Aug 13 05:50:29 PM PDT 24
Peak memory 206144 kb
Host smart-bc9f2205-ca7f-47b2-b015-19ffe3be8bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552643171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2552643171
Directory /workspace/14.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/14.spi_device_upload.2548413153
Short name T229
Test name
Test status
Simulation time 459916083 ps
CPU time 4.8 seconds
Started Aug 13 05:50:36 PM PDT 24
Finished Aug 13 05:50:41 PM PDT 24
Peak memory 236540 kb
Host smart-e2ab414a-1e3b-4fb8-a4bb-43532586b521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548413153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2548413153
Directory /workspace/14.spi_device_upload/latest


Test location /workspace/coverage/default/15.spi_device_alert_test.2235960427
Short name T740
Test name
Test status
Simulation time 16744651 ps
CPU time 0.78 seconds
Started Aug 13 05:50:44 PM PDT 24
Finished Aug 13 05:50:45 PM PDT 24
Peak memory 205552 kb
Host smart-162ae40d-ae29-4824-950c-fde4ee25bd0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235960427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2235960427
Directory /workspace/15.spi_device_alert_test/latest


Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1378397099
Short name T930
Test name
Test status
Simulation time 104563568 ps
CPU time 3.44 seconds
Started Aug 13 05:50:44 PM PDT 24
Finished Aug 13 05:50:48 PM PDT 24
Peak memory 224708 kb
Host smart-0b5b6d39-fb89-495b-af69-457b0e06b5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378397099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1378397099
Directory /workspace/15.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/15.spi_device_csb_read.1558165455
Short name T842
Test name
Test status
Simulation time 16935490 ps
CPU time 0.76 seconds
Started Aug 13 05:50:36 PM PDT 24
Finished Aug 13 05:50:37 PM PDT 24
Peak memory 205592 kb
Host smart-c856a096-f2e8-4c4e-96b8-c963cc7658e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558165455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1558165455
Directory /workspace/15.spi_device_csb_read/latest


Test location /workspace/coverage/default/15.spi_device_flash_all.2510828562
Short name T843
Test name
Test status
Simulation time 4213778892 ps
CPU time 9.89 seconds
Started Aug 13 05:50:45 PM PDT 24
Finished Aug 13 05:50:55 PM PDT 24
Peak memory 224776 kb
Host smart-35691370-c6f6-4e0d-a984-29f135195087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510828562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2510828562
Directory /workspace/15.spi_device_flash_all/latest


Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1641912309
Short name T240
Test name
Test status
Simulation time 21041432855 ps
CPU time 183.11 seconds
Started Aug 13 05:50:45 PM PDT 24
Finished Aug 13 05:53:49 PM PDT 24
Peak memory 250376 kb
Host smart-669e60fc-3327-4469-8d45-d0bc0b0f492c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641912309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1641912309
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/15.spi_device_flash_mode.3731026508
Short name T424
Test name
Test status
Simulation time 129146158 ps
CPU time 2.58 seconds
Started Aug 13 05:50:45 PM PDT 24
Finished Aug 13 05:50:48 PM PDT 24
Peak memory 232852 kb
Host smart-432fc283-8ee4-41e0-bd5b-d5cf763aa501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731026508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3731026508
Directory /workspace/15.spi_device_flash_mode/latest


Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1109386090
Short name T586
Test name
Test status
Simulation time 302371537312 ps
CPU time 237.12 seconds
Started Aug 13 05:50:44 PM PDT 24
Finished Aug 13 05:54:41 PM PDT 24
Peak memory 250672 kb
Host smart-0e57e879-9d8f-4388-bc85-6e6bbda89f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109386090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1109386090
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/15.spi_device_intercept.760076922
Short name T736
Test name
Test status
Simulation time 4311496562 ps
CPU time 10.81 seconds
Started Aug 13 05:50:45 PM PDT 24
Finished Aug 13 05:50:56 PM PDT 24
Peak memory 232912 kb
Host smart-f2a31c48-2d72-4497-b69c-8a4e330ab8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760076922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.760076922
Directory /workspace/15.spi_device_intercept/latest


Test location /workspace/coverage/default/15.spi_device_mailbox.3426007915
Short name T657
Test name
Test status
Simulation time 333375821 ps
CPU time 5.67 seconds
Started Aug 13 05:50:44 PM PDT 24
Finished Aug 13 05:50:50 PM PDT 24
Peak memory 232904 kb
Host smart-81b7d489-9b87-4c85-8d60-472e8a0dc150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426007915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3426007915
Directory /workspace/15.spi_device_mailbox/latest


Test location /workspace/coverage/default/15.spi_device_mem_parity.1296226285
Short name T441
Test name
Test status
Simulation time 17103083 ps
CPU time 1.05 seconds
Started Aug 13 05:50:33 PM PDT 24
Finished Aug 13 05:50:34 PM PDT 24
Peak memory 217996 kb
Host smart-f5323a81-b6ee-4abb-92d4-820c0a0791f2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296226285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1296226285
Directory /workspace/15.spi_device_mem_parity/latest


Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2009808798
Short name T837
Test name
Test status
Simulation time 333011157 ps
CPU time 6.1 seconds
Started Aug 13 05:50:43 PM PDT 24
Finished Aug 13 05:50:49 PM PDT 24
Peak memory 232880 kb
Host smart-43993917-e5d6-492d-9d9a-f66259ab01e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009808798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2009808798
Directory /workspace/15.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2757258003
Short name T983
Test name
Test status
Simulation time 80122141 ps
CPU time 4.07 seconds
Started Aug 13 05:50:43 PM PDT 24
Finished Aug 13 05:50:48 PM PDT 24
Peak memory 222532 kb
Host smart-91e27c65-bb0a-45e7-9ded-ee3f50267eda
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2757258003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2757258003
Directory /workspace/15.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/15.spi_device_stress_all.1934792614
Short name T36
Test name
Test status
Simulation time 8824371141 ps
CPU time 91.29 seconds
Started Aug 13 05:50:42 PM PDT 24
Finished Aug 13 05:52:14 PM PDT 24
Peak memory 249432 kb
Host smart-4378a62d-f9f9-4148-aeff-d01320664c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934792614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1934792614
Directory /workspace/15.spi_device_stress_all/latest


Test location /workspace/coverage/default/15.spi_device_tpm_all.2017052703
Short name T376
Test name
Test status
Simulation time 536281424 ps
CPU time 3.26 seconds
Started Aug 13 05:50:35 PM PDT 24
Finished Aug 13 05:50:38 PM PDT 24
Peak memory 216532 kb
Host smart-3e1eed1d-7eb0-4c81-b65f-a30a4527940b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017052703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2017052703
Directory /workspace/15.spi_device_tpm_all/latest


Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2365383907
Short name T753
Test name
Test status
Simulation time 2683116838 ps
CPU time 5.54 seconds
Started Aug 13 05:50:35 PM PDT 24
Finished Aug 13 05:50:41 PM PDT 24
Peak memory 216536 kb
Host smart-c22851e8-7f03-40f0-9aa6-c5a3004676d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365383907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2365383907
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/15.spi_device_tpm_rw.4135011554
Short name T412
Test name
Test status
Simulation time 340984224 ps
CPU time 4.31 seconds
Started Aug 13 05:50:45 PM PDT 24
Finished Aug 13 05:50:49 PM PDT 24
Peak memory 216480 kb
Host smart-8f0f3bff-05d1-47e9-9465-20045cac0316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135011554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.4135011554
Directory /workspace/15.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3363923035
Short name T831
Test name
Test status
Simulation time 75589384 ps
CPU time 0.81 seconds
Started Aug 13 05:50:39 PM PDT 24
Finished Aug 13 05:50:40 PM PDT 24
Peak memory 206060 kb
Host smart-77b9d29e-6ec4-4595-bdb1-d8d8fd9cd2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363923035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3363923035
Directory /workspace/15.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/15.spi_device_upload.3625244057
Short name T382
Test name
Test status
Simulation time 10683764868 ps
CPU time 13.07 seconds
Started Aug 13 05:50:45 PM PDT 24
Finished Aug 13 05:50:58 PM PDT 24
Peak memory 224756 kb
Host smart-3f9548e1-b471-40b9-bb9f-8ebd569343dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625244057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3625244057
Directory /workspace/15.spi_device_upload/latest


Test location /workspace/coverage/default/16.spi_device_alert_test.3429408560
Short name T473
Test name
Test status
Simulation time 241072043 ps
CPU time 0.76 seconds
Started Aug 13 05:50:53 PM PDT 24
Finished Aug 13 05:50:54 PM PDT 24
Peak memory 204956 kb
Host smart-c63428a1-b0bd-4a42-ac82-407430dd36b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429408560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3429408560
Directory /workspace/16.spi_device_alert_test/latest


Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2048208229
Short name T710
Test name
Test status
Simulation time 1133338808 ps
CPU time 13.53 seconds
Started Aug 13 05:50:47 PM PDT 24
Finished Aug 13 05:51:01 PM PDT 24
Peak memory 224728 kb
Host smart-e7b5c984-cc9b-4231-b089-0ad04357767f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048208229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2048208229
Directory /workspace/16.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/16.spi_device_csb_read.1010956621
Short name T772
Test name
Test status
Simulation time 48067594 ps
CPU time 0.81 seconds
Started Aug 13 05:50:41 PM PDT 24
Finished Aug 13 05:50:42 PM PDT 24
Peak memory 205552 kb
Host smart-404be0ea-617e-4d37-9283-17e5c6029222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010956621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1010956621
Directory /workspace/16.spi_device_csb_read/latest


Test location /workspace/coverage/default/16.spi_device_flash_all.2931979013
Short name T730
Test name
Test status
Simulation time 17201951209 ps
CPU time 44.76 seconds
Started Aug 13 05:50:45 PM PDT 24
Finished Aug 13 05:51:29 PM PDT 24
Peak memory 240436 kb
Host smart-122a3f6b-b992-43c0-bf79-2c1130422473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931979013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2931979013
Directory /workspace/16.spi_device_flash_all/latest


Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3272448271
Short name T750
Test name
Test status
Simulation time 18520491813 ps
CPU time 43.44 seconds
Started Aug 13 05:50:46 PM PDT 24
Finished Aug 13 05:51:30 PM PDT 24
Peak memory 252356 kb
Host smart-e559ba75-7f0e-4e9d-9931-7b854526afea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272448271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3272448271
Directory /workspace/16.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2375725955
Short name T636
Test name
Test status
Simulation time 840741671 ps
CPU time 4.8 seconds
Started Aug 13 05:50:45 PM PDT 24
Finished Aug 13 05:50:50 PM PDT 24
Peak memory 217744 kb
Host smart-1d25fc91-cb1f-41d8-ab6a-141facfef48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375725955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2375725955
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/16.spi_device_flash_mode.4283489671
Short name T416
Test name
Test status
Simulation time 2351234348 ps
CPU time 46 seconds
Started Aug 13 05:50:47 PM PDT 24
Finished Aug 13 05:51:33 PM PDT 24
Peak memory 224760 kb
Host smart-3aee47d1-95ee-49d8-bbe7-368227320cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283489671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4283489671
Directory /workspace/16.spi_device_flash_mode/latest


Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1731476659
Short name T207
Test name
Test status
Simulation time 9151003050 ps
CPU time 33.65 seconds
Started Aug 13 05:50:43 PM PDT 24
Finished Aug 13 05:51:17 PM PDT 24
Peak memory 250900 kb
Host smart-68014ada-16ea-4f64-84bf-640bd565e341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731476659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1731476659
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/16.spi_device_intercept.2183419100
Short name T211
Test name
Test status
Simulation time 245058010 ps
CPU time 3.49 seconds
Started Aug 13 05:50:45 PM PDT 24
Finished Aug 13 05:50:49 PM PDT 24
Peak memory 224632 kb
Host smart-6e514cc4-c152-4925-a6a3-a5ae14fdffb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183419100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2183419100
Directory /workspace/16.spi_device_intercept/latest


Test location /workspace/coverage/default/16.spi_device_mailbox.2394926887
Short name T81
Test name
Test status
Simulation time 5493515783 ps
CPU time 45.62 seconds
Started Aug 13 05:50:44 PM PDT 24
Finished Aug 13 05:51:30 PM PDT 24
Peak memory 235452 kb
Host smart-9f55af37-4577-4ce8-8984-4529bdbb4357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394926887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2394926887
Directory /workspace/16.spi_device_mailbox/latest


Test location /workspace/coverage/default/16.spi_device_mem_parity.3478780397
Short name T558
Test name
Test status
Simulation time 36503792 ps
CPU time 1.12 seconds
Started Aug 13 05:50:45 PM PDT 24
Finished Aug 13 05:50:46 PM PDT 24
Peak memory 216748 kb
Host smart-da69f1b0-8feb-477f-b08e-e9b22ded54fb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478780397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3478780397
Directory /workspace/16.spi_device_mem_parity/latest


Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1881122816
Short name T267
Test name
Test status
Simulation time 2171431691 ps
CPU time 3.04 seconds
Started Aug 13 05:50:45 PM PDT 24
Finished Aug 13 05:50:48 PM PDT 24
Peak memory 224724 kb
Host smart-6d82ccfc-74f6-4ea2-be9e-5b3138362d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881122816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1881122816
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2962458255
Short name T281
Test name
Test status
Simulation time 1234311784 ps
CPU time 6.29 seconds
Started Aug 13 05:50:46 PM PDT 24
Finished Aug 13 05:50:52 PM PDT 24
Peak memory 232916 kb
Host smart-d3258e84-200f-4565-8c14-d7361e226815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962458255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2962458255
Directory /workspace/16.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.305916493
Short name T890
Test name
Test status
Simulation time 2834401990 ps
CPU time 5.59 seconds
Started Aug 13 05:50:45 PM PDT 24
Finished Aug 13 05:50:51 PM PDT 24
Peak memory 222568 kb
Host smart-be6fa752-577d-4b5b-82c7-f5c82976bc80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=305916493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.305916493
Directory /workspace/16.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/16.spi_device_stress_all.22323100
Short name T929
Test name
Test status
Simulation time 49696938221 ps
CPU time 475.48 seconds
Started Aug 13 05:50:52 PM PDT 24
Finished Aug 13 05:58:48 PM PDT 24
Peak memory 257212 kb
Host smart-03ffd6ac-a9fa-4b53-b8c7-c34ae98141fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22323100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress
_all.22323100
Directory /workspace/16.spi_device_stress_all/latest


Test location /workspace/coverage/default/16.spi_device_tpm_all.2024815067
Short name T564
Test name
Test status
Simulation time 24535863 ps
CPU time 0.73 seconds
Started Aug 13 05:50:44 PM PDT 24
Finished Aug 13 05:50:45 PM PDT 24
Peak memory 205760 kb
Host smart-61c0d0e5-ac28-4a3e-8a98-ae95d2d80bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024815067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2024815067
Directory /workspace/16.spi_device_tpm_all/latest


Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3164371079
Short name T363
Test name
Test status
Simulation time 1043133171 ps
CPU time 3.06 seconds
Started Aug 13 05:50:47 PM PDT 24
Finished Aug 13 05:50:50 PM PDT 24
Peak memory 216476 kb
Host smart-20210861-4176-4ae0-bc75-7072c5df4324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164371079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3164371079
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/16.spi_device_tpm_rw.2895049556
Short name T443
Test name
Test status
Simulation time 82316103 ps
CPU time 1.71 seconds
Started Aug 13 05:50:44 PM PDT 24
Finished Aug 13 05:50:46 PM PDT 24
Peak memory 216408 kb
Host smart-e6c6bf82-6bfa-4db6-b2a7-e61b62ee0f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895049556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2895049556
Directory /workspace/16.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2081449267
Short name T990
Test name
Test status
Simulation time 346190347 ps
CPU time 1 seconds
Started Aug 13 05:50:46 PM PDT 24
Finished Aug 13 05:50:47 PM PDT 24
Peak memory 206152 kb
Host smart-5f12821c-e512-46a1-9259-cd410fe72930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081449267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2081449267
Directory /workspace/16.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/16.spi_device_upload.3239596277
Short name T1022
Test name
Test status
Simulation time 56997747 ps
CPU time 2.27 seconds
Started Aug 13 05:50:46 PM PDT 24
Finished Aug 13 05:50:49 PM PDT 24
Peak memory 223848 kb
Host smart-5862674a-5250-4e3f-b297-293d01c4ea2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239596277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3239596277
Directory /workspace/16.spi_device_upload/latest


Test location /workspace/coverage/default/17.spi_device_alert_test.1486847775
Short name T768
Test name
Test status
Simulation time 13307341 ps
CPU time 0.67 seconds
Started Aug 13 05:50:53 PM PDT 24
Finished Aug 13 05:50:53 PM PDT 24
Peak memory 204888 kb
Host smart-ed362f38-f090-4274-b6ab-3e20ffbab5ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486847775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1486847775
Directory /workspace/17.spi_device_alert_test/latest


Test location /workspace/coverage/default/17.spi_device_cfg_cmd.4197406689
Short name T854
Test name
Test status
Simulation time 858384309 ps
CPU time 5.91 seconds
Started Aug 13 05:50:58 PM PDT 24
Finished Aug 13 05:51:04 PM PDT 24
Peak memory 232920 kb
Host smart-cc85ca46-58b4-441b-a60e-02acbc1fa81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197406689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.4197406689
Directory /workspace/17.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/17.spi_device_csb_read.3479918061
Short name T611
Test name
Test status
Simulation time 130240184 ps
CPU time 0.75 seconds
Started Aug 13 05:50:54 PM PDT 24
Finished Aug 13 05:50:55 PM PDT 24
Peak memory 205948 kb
Host smart-7bd0c06e-96ab-44cc-8c6c-2cdb69397f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479918061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3479918061
Directory /workspace/17.spi_device_csb_read/latest


Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.462204787
Short name T78
Test name
Test status
Simulation time 144973362210 ps
CPU time 359.91 seconds
Started Aug 13 05:50:53 PM PDT 24
Finished Aug 13 05:56:53 PM PDT 24
Peak memory 257612 kb
Host smart-4732ea46-938c-4f6c-92cc-9371d144e462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462204787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.462204787
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/17.spi_device_flash_mode.1332427795
Short name T763
Test name
Test status
Simulation time 118046312 ps
CPU time 3.48 seconds
Started Aug 13 05:50:53 PM PDT 24
Finished Aug 13 05:50:57 PM PDT 24
Peak memory 224716 kb
Host smart-86ebbd02-2fe8-4c2b-a4e7-2001502f0952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332427795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1332427795
Directory /workspace/17.spi_device_flash_mode/latest


Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2466673352
Short name T433
Test name
Test status
Simulation time 45984477985 ps
CPU time 250.55 seconds
Started Aug 13 05:50:51 PM PDT 24
Finished Aug 13 05:55:02 PM PDT 24
Peak memory 250840 kb
Host smart-701bae7f-ea70-434b-b201-dedf9f1bcd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466673352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2466673352
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/17.spi_device_intercept.995892689
Short name T668
Test name
Test status
Simulation time 3009957476 ps
CPU time 27.89 seconds
Started Aug 13 05:50:53 PM PDT 24
Finished Aug 13 05:51:21 PM PDT 24
Peak memory 224664 kb
Host smart-e5ec2726-8e61-4d51-815e-40241e043ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995892689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.995892689
Directory /workspace/17.spi_device_intercept/latest


Test location /workspace/coverage/default/17.spi_device_mailbox.360771213
Short name T342
Test name
Test status
Simulation time 1803501710 ps
CPU time 24.11 seconds
Started Aug 13 05:50:54 PM PDT 24
Finished Aug 13 05:51:18 PM PDT 24
Peak memory 232848 kb
Host smart-833915c2-3f2d-4fd9-a51f-69dc2b3f6900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360771213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.360771213
Directory /workspace/17.spi_device_mailbox/latest


Test location /workspace/coverage/default/17.spi_device_mem_parity.992639960
Short name T407
Test name
Test status
Simulation time 92565893 ps
CPU time 1.1 seconds
Started Aug 13 05:50:54 PM PDT 24
Finished Aug 13 05:50:56 PM PDT 24
Peak memory 217960 kb
Host smart-f17c2461-853c-46d0-a709-952c9e235b54
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992639960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.992639960
Directory /workspace/17.spi_device_mem_parity/latest


Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2612398035
Short name T666
Test name
Test status
Simulation time 1036526527 ps
CPU time 6.45 seconds
Started Aug 13 05:50:52 PM PDT 24
Finished Aug 13 05:50:58 PM PDT 24
Peak memory 224684 kb
Host smart-d7519cf9-0e6f-4258-b4bc-7aae36e6eb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612398035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2612398035
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.712317574
Short name T546
Test name
Test status
Simulation time 315342982 ps
CPU time 3.51 seconds
Started Aug 13 05:50:51 PM PDT 24
Finished Aug 13 05:50:55 PM PDT 24
Peak memory 224692 kb
Host smart-12d501dc-378d-43a4-aac8-a80f7ccdea51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712317574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.712317574
Directory /workspace/17.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3048427368
Short name T607
Test name
Test status
Simulation time 164727498 ps
CPU time 4.98 seconds
Started Aug 13 05:50:58 PM PDT 24
Finished Aug 13 05:51:03 PM PDT 24
Peak memory 222520 kb
Host smart-b50a040f-05ae-43bc-b6ca-c0141071ea45
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3048427368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3048427368
Directory /workspace/17.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/17.spi_device_stress_all.4050819786
Short name T832
Test name
Test status
Simulation time 41286337942 ps
CPU time 399.8 seconds
Started Aug 13 05:50:53 PM PDT 24
Finished Aug 13 05:57:33 PM PDT 24
Peak memory 273124 kb
Host smart-15527c75-3640-4d15-bf7d-0edcf3fc4554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050819786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.4050819786
Directory /workspace/17.spi_device_stress_all/latest


Test location /workspace/coverage/default/17.spi_device_tpm_all.3973349044
Short name T897
Test name
Test status
Simulation time 982726704 ps
CPU time 12.74 seconds
Started Aug 13 05:50:53 PM PDT 24
Finished Aug 13 05:51:06 PM PDT 24
Peak memory 216484 kb
Host smart-ff63e800-0855-4a35-8e72-aa2e90bd3620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973349044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3973349044
Directory /workspace/17.spi_device_tpm_all/latest


Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1888576748
Short name T661
Test name
Test status
Simulation time 3815602304 ps
CPU time 3.25 seconds
Started Aug 13 05:50:53 PM PDT 24
Finished Aug 13 05:50:56 PM PDT 24
Peak memory 208208 kb
Host smart-84e00823-4957-4f0e-8812-aa8fdbc77b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888576748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1888576748
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/17.spi_device_tpm_rw.864904651
Short name T756
Test name
Test status
Simulation time 122779650 ps
CPU time 6.63 seconds
Started Aug 13 05:50:55 PM PDT 24
Finished Aug 13 05:51:02 PM PDT 24
Peak memory 216372 kb
Host smart-b5476aaf-de69-4e2e-acf6-35a51475d28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864904651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.864904651
Directory /workspace/17.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3035957095
Short name T871
Test name
Test status
Simulation time 47241504 ps
CPU time 0.79 seconds
Started Aug 13 05:50:53 PM PDT 24
Finished Aug 13 05:50:53 PM PDT 24
Peak memory 206100 kb
Host smart-85a98d3b-80cd-4030-8cda-fe9aca322f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035957095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3035957095
Directory /workspace/17.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/17.spi_device_upload.1267745375
Short name T887
Test name
Test status
Simulation time 1737738193 ps
CPU time 5.81 seconds
Started Aug 13 05:50:57 PM PDT 24
Finished Aug 13 05:51:03 PM PDT 24
Peak memory 224692 kb
Host smart-c64fee97-62d1-49d6-bcf8-22e9dc4fb7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267745375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1267745375
Directory /workspace/17.spi_device_upload/latest


Test location /workspace/coverage/default/18.spi_device_alert_test.1807796834
Short name T660
Test name
Test status
Simulation time 39730621 ps
CPU time 0.72 seconds
Started Aug 13 05:51:01 PM PDT 24
Finished Aug 13 05:51:02 PM PDT 24
Peak memory 205556 kb
Host smart-95cbaad3-988b-4b5b-a0e5-4c08b494a43c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807796834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1807796834
Directory /workspace/18.spi_device_alert_test/latest


Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1940620841
Short name T405
Test name
Test status
Simulation time 143901318 ps
CPU time 3.96 seconds
Started Aug 13 05:51:01 PM PDT 24
Finished Aug 13 05:51:05 PM PDT 24
Peak memory 232844 kb
Host smart-fbd23b8b-f1aa-4caa-9111-8297c8d4408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940620841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1940620841
Directory /workspace/18.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/18.spi_device_csb_read.2356968286
Short name T694
Test name
Test status
Simulation time 27530969 ps
CPU time 0.76 seconds
Started Aug 13 05:50:53 PM PDT 24
Finished Aug 13 05:50:54 PM PDT 24
Peak memory 206616 kb
Host smart-0ba20b5f-5d12-4b4d-9261-0e2d0c4ca467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356968286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2356968286
Directory /workspace/18.spi_device_csb_read/latest


Test location /workspace/coverage/default/18.spi_device_flash_all.2904967836
Short name T904
Test name
Test status
Simulation time 12973419 ps
CPU time 0.76 seconds
Started Aug 13 05:51:00 PM PDT 24
Finished Aug 13 05:51:01 PM PDT 24
Peak memory 215836 kb
Host smart-230327c9-8918-4c31-b0e2-f162b6806b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904967836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2904967836
Directory /workspace/18.spi_device_flash_all/latest


Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2448468615
Short name T333
Test name
Test status
Simulation time 13339738961 ps
CPU time 32.3 seconds
Started Aug 13 05:51:01 PM PDT 24
Finished Aug 13 05:51:34 PM PDT 24
Peak memory 241188 kb
Host smart-dedaf796-ad6f-41df-b80e-2057f81d76d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448468615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2448468615
Directory /workspace/18.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3541754845
Short name T231
Test name
Test status
Simulation time 239577263786 ps
CPU time 193.24 seconds
Started Aug 13 05:51:04 PM PDT 24
Finished Aug 13 05:54:18 PM PDT 24
Peak memory 250424 kb
Host smart-fc867907-b306-4bfc-b4bd-0618e21aa2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541754845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3541754845
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/18.spi_device_flash_mode.2439701396
Short name T956
Test name
Test status
Simulation time 3233976790 ps
CPU time 43.08 seconds
Started Aug 13 05:51:00 PM PDT 24
Finished Aug 13 05:51:43 PM PDT 24
Peak memory 232904 kb
Host smart-16876fd1-c3bf-48b2-9f6e-c9b023b2482c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439701396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2439701396
Directory /workspace/18.spi_device_flash_mode/latest


Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.590759905
Short name T755
Test name
Test status
Simulation time 104635972149 ps
CPU time 199.7 seconds
Started Aug 13 05:51:01 PM PDT 24
Finished Aug 13 05:54:21 PM PDT 24
Peak memory 249388 kb
Host smart-d1276ee0-888a-48da-a380-d3a81d66b085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590759905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.590759905
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/18.spi_device_intercept.1377382009
Short name T275
Test name
Test status
Simulation time 16420074718 ps
CPU time 12.37 seconds
Started Aug 13 05:51:01 PM PDT 24
Finished Aug 13 05:51:14 PM PDT 24
Peak memory 232968 kb
Host smart-37895e33-37a1-44a0-9e96-91c383654c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377382009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1377382009
Directory /workspace/18.spi_device_intercept/latest


Test location /workspace/coverage/default/18.spi_device_mailbox.203803050
Short name T58
Test name
Test status
Simulation time 11956038525 ps
CPU time 91.5 seconds
Started Aug 13 05:51:02 PM PDT 24
Finished Aug 13 05:52:33 PM PDT 24
Peak memory 241248 kb
Host smart-240c026f-bb4b-44df-8cbb-fb1977d6b278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203803050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.203803050
Directory /workspace/18.spi_device_mailbox/latest


Test location /workspace/coverage/default/18.spi_device_mem_parity.2590149591
Short name T574
Test name
Test status
Simulation time 25919768 ps
CPU time 1.09 seconds
Started Aug 13 05:50:53 PM PDT 24
Finished Aug 13 05:50:54 PM PDT 24
Peak memory 216744 kb
Host smart-ac8dd855-b73d-4ac0-952c-09196b8cc688
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590149591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2590149591
Directory /workspace/18.spi_device_mem_parity/latest


Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2401788608
Short name T258
Test name
Test status
Simulation time 2429233053 ps
CPU time 3.47 seconds
Started Aug 13 05:51:02 PM PDT 24
Finished Aug 13 05:51:06 PM PDT 24
Peak memory 232968 kb
Host smart-76434058-652a-444c-b2b1-14a55a62e477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401788608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2401788608
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1761439101
Short name T819
Test name
Test status
Simulation time 742887644 ps
CPU time 9.05 seconds
Started Aug 13 05:51:01 PM PDT 24
Finished Aug 13 05:51:10 PM PDT 24
Peak memory 232840 kb
Host smart-0975a76b-cb63-40f1-b19e-348d83bc2d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761439101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1761439101
Directory /workspace/18.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.858251446
Short name T391
Test name
Test status
Simulation time 457389353 ps
CPU time 3.69 seconds
Started Aug 13 05:51:01 PM PDT 24
Finished Aug 13 05:51:05 PM PDT 24
Peak memory 220504 kb
Host smart-fdd7e4ca-abca-4eb1-894c-3de2f0acd47f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=858251446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.858251446
Directory /workspace/18.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/18.spi_device_stress_all.353881822
Short name T858
Test name
Test status
Simulation time 5503441227 ps
CPU time 39.17 seconds
Started Aug 13 05:51:05 PM PDT 24
Finished Aug 13 05:51:45 PM PDT 24
Peak memory 256308 kb
Host smart-da8e795c-bd41-4a9d-84d7-65fe0d81ac06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353881822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.353881822
Directory /workspace/18.spi_device_stress_all/latest


Test location /workspace/coverage/default/18.spi_device_tpm_all.1016188436
Short name T958
Test name
Test status
Simulation time 1243766324 ps
CPU time 9.39 seconds
Started Aug 13 05:51:02 PM PDT 24
Finished Aug 13 05:51:11 PM PDT 24
Peak memory 216640 kb
Host smart-37e7631e-9e78-4c61-abe9-a7678344ae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016188436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1016188436
Directory /workspace/18.spi_device_tpm_all/latest


Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2293312530
Short name T629
Test name
Test status
Simulation time 2751190261 ps
CPU time 8.68 seconds
Started Aug 13 05:50:54 PM PDT 24
Finished Aug 13 05:51:02 PM PDT 24
Peak memory 216484 kb
Host smart-183d2107-8a45-4874-9467-3ed680042b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293312530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2293312530
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/18.spi_device_tpm_rw.2872170588
Short name T332
Test name
Test status
Simulation time 61098042 ps
CPU time 3.1 seconds
Started Aug 13 05:51:01 PM PDT 24
Finished Aug 13 05:51:04 PM PDT 24
Peak memory 216520 kb
Host smart-b9531462-df92-453a-9a1a-0c24d914b1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872170588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2872170588
Directory /workspace/18.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1872103615
Short name T866
Test name
Test status
Simulation time 124147682 ps
CPU time 0.89 seconds
Started Aug 13 05:51:00 PM PDT 24
Finished Aug 13 05:51:01 PM PDT 24
Peak memory 207164 kb
Host smart-20a38584-db82-43cf-9055-245db83277c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872103615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1872103615
Directory /workspace/18.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/18.spi_device_upload.211100131
Short name T84
Test name
Test status
Simulation time 889191927 ps
CPU time 7.13 seconds
Started Aug 13 05:51:00 PM PDT 24
Finished Aug 13 05:51:08 PM PDT 24
Peak memory 232808 kb
Host smart-c284b1d6-27a2-4c87-8d72-f6a79c415567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211100131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.211100131
Directory /workspace/18.spi_device_upload/latest


Test location /workspace/coverage/default/19.spi_device_alert_test.39453494
Short name T447
Test name
Test status
Simulation time 41537816 ps
CPU time 0.75 seconds
Started Aug 13 05:51:09 PM PDT 24
Finished Aug 13 05:51:10 PM PDT 24
Peak memory 205560 kb
Host smart-40e5dbd8-4251-432e-ab80-9508f9556595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39453494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.39453494
Directory /workspace/19.spi_device_alert_test/latest


Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1371997431
Short name T984
Test name
Test status
Simulation time 40165135 ps
CPU time 2.33 seconds
Started Aug 13 05:51:10 PM PDT 24
Finished Aug 13 05:51:13 PM PDT 24
Peak memory 224684 kb
Host smart-89057969-b0e7-418a-9283-56fb61062d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371997431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1371997431
Directory /workspace/19.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/19.spi_device_csb_read.4095345680
Short name T523
Test name
Test status
Simulation time 189197359 ps
CPU time 0.81 seconds
Started Aug 13 05:51:00 PM PDT 24
Finished Aug 13 05:51:01 PM PDT 24
Peak memory 206600 kb
Host smart-68f560c6-99ae-4a64-b6b0-7207f7d4e752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095345680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4095345680
Directory /workspace/19.spi_device_csb_read/latest


Test location /workspace/coverage/default/19.spi_device_flash_all.2953196028
Short name T688
Test name
Test status
Simulation time 1859555119 ps
CPU time 9.09 seconds
Started Aug 13 05:51:12 PM PDT 24
Finished Aug 13 05:51:21 PM PDT 24
Peak memory 233928 kb
Host smart-c29b76e6-feaf-486d-9cb2-12f102de8b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953196028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2953196028
Directory /workspace/19.spi_device_flash_all/latest


Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1298104673
Short name T1002
Test name
Test status
Simulation time 3673176164 ps
CPU time 95.15 seconds
Started Aug 13 05:51:11 PM PDT 24
Finished Aug 13 05:52:46 PM PDT 24
Peak memory 257508 kb
Host smart-7c093a14-98bd-40c5-b924-3e037455e4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298104673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1298104673
Directory /workspace/19.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.344628462
Short name T920
Test name
Test status
Simulation time 20880201490 ps
CPU time 174.82 seconds
Started Aug 13 05:51:11 PM PDT 24
Finished Aug 13 05:54:05 PM PDT 24
Peak memory 266768 kb
Host smart-8d74549e-ba91-4f55-9e5e-3f89a71bb580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344628462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.344628462
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/19.spi_device_flash_mode.4163075529
Short name T165
Test name
Test status
Simulation time 6612477531 ps
CPU time 30.43 seconds
Started Aug 13 05:51:09 PM PDT 24
Finished Aug 13 05:51:39 PM PDT 24
Peak memory 241176 kb
Host smart-b46e6d27-28eb-4811-afe7-2bdd2bf026f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163075529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4163075529
Directory /workspace/19.spi_device_flash_mode/latest


Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2175696757
Short name T919
Test name
Test status
Simulation time 24954938402 ps
CPU time 248.79 seconds
Started Aug 13 05:51:10 PM PDT 24
Finished Aug 13 05:55:19 PM PDT 24
Peak memory 265704 kb
Host smart-f5df0433-fc72-4b42-b166-c3d90837a75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175696757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2175696757
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/19.spi_device_intercept.2505236389
Short name T684
Test name
Test status
Simulation time 169606127 ps
CPU time 2.94 seconds
Started Aug 13 05:51:10 PM PDT 24
Finished Aug 13 05:51:13 PM PDT 24
Peak memory 232900 kb
Host smart-bdadc6ae-9202-49a6-8b77-697a429c3bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505236389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2505236389
Directory /workspace/19.spi_device_intercept/latest


Test location /workspace/coverage/default/19.spi_device_mailbox.1895895746
Short name T198
Test name
Test status
Simulation time 205488844 ps
CPU time 2.66 seconds
Started Aug 13 05:51:11 PM PDT 24
Finished Aug 13 05:51:14 PM PDT 24
Peak memory 232904 kb
Host smart-41d24e21-4366-402f-8b4d-ec17a6ee0613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895895746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1895895746
Directory /workspace/19.spi_device_mailbox/latest


Test location /workspace/coverage/default/19.spi_device_mem_parity.1377222196
Short name T936
Test name
Test status
Simulation time 52193349 ps
CPU time 1.05 seconds
Started Aug 13 05:50:59 PM PDT 24
Finished Aug 13 05:51:00 PM PDT 24
Peak memory 216752 kb
Host smart-c469980f-e996-4d5a-a316-0870c4a95066
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377222196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1377222196
Directory /workspace/19.spi_device_mem_parity/latest


Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3063857337
Short name T254
Test name
Test status
Simulation time 693197721 ps
CPU time 6.68 seconds
Started Aug 13 05:51:06 PM PDT 24
Finished Aug 13 05:51:13 PM PDT 24
Peak memory 240996 kb
Host smart-fc88e241-58ae-4836-b6ce-b4f0f6a6f759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063857337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3063857337
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.4043842678
Short name T217
Test name
Test status
Simulation time 4747548854 ps
CPU time 6.53 seconds
Started Aug 13 05:51:11 PM PDT 24
Finished Aug 13 05:51:18 PM PDT 24
Peak memory 232900 kb
Host smart-49010ab4-3c28-421c-9a4b-9d601706ccbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043842678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.4043842678
Directory /workspace/19.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3275625764
Short name T971
Test name
Test status
Simulation time 4966237669 ps
CPU time 11.34 seconds
Started Aug 13 05:51:08 PM PDT 24
Finished Aug 13 05:51:19 PM PDT 24
Peak memory 222036 kb
Host smart-f9e8bdc3-0237-42ae-b208-54644e6876dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3275625764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3275625764
Directory /workspace/19.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/19.spi_device_tpm_all.3144890313
Short name T325
Test name
Test status
Simulation time 1835493168 ps
CPU time 10.68 seconds
Started Aug 13 05:51:02 PM PDT 24
Finished Aug 13 05:51:13 PM PDT 24
Peak memory 216504 kb
Host smart-03066af1-8452-4e9f-b971-8856d5cccaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144890313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3144890313
Directory /workspace/19.spi_device_tpm_all/latest


Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1892502313
Short name T868
Test name
Test status
Simulation time 6490493827 ps
CPU time 8.34 seconds
Started Aug 13 05:51:00 PM PDT 24
Finished Aug 13 05:51:09 PM PDT 24
Peak memory 216556 kb
Host smart-35c6bec8-2b08-4085-b929-edabdcfcb3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892502313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1892502313
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/19.spi_device_tpm_rw.1262406325
Short name T442
Test name
Test status
Simulation time 47895761 ps
CPU time 3.12 seconds
Started Aug 13 05:51:13 PM PDT 24
Finished Aug 13 05:51:16 PM PDT 24
Peak memory 216468 kb
Host smart-fb44f424-b844-4877-8441-e7bffd913417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262406325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1262406325
Directory /workspace/19.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2435920138
Short name T1003
Test name
Test status
Simulation time 34475771 ps
CPU time 0.92 seconds
Started Aug 13 05:51:01 PM PDT 24
Finished Aug 13 05:51:03 PM PDT 24
Peak memory 206136 kb
Host smart-11e09c9d-4251-4eb8-ab51-c58410ec9ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435920138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2435920138
Directory /workspace/19.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/19.spi_device_upload.3698515017
Short name T508
Test name
Test status
Simulation time 2072147036 ps
CPU time 9.61 seconds
Started Aug 13 05:51:14 PM PDT 24
Finished Aug 13 05:51:24 PM PDT 24
Peak memory 232868 kb
Host smart-4f90feac-905f-47ef-ab18-bc226095b170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698515017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3698515017
Directory /workspace/19.spi_device_upload/latest


Test location /workspace/coverage/default/2.spi_device_alert_test.2357720741
Short name T964
Test name
Test status
Simulation time 13161129 ps
CPU time 0.73 seconds
Started Aug 13 05:49:04 PM PDT 24
Finished Aug 13 05:49:05 PM PDT 24
Peak memory 205576 kb
Host smart-2c5a949c-1e8a-498d-b8c4-3412d72617fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357720741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
357720741
Directory /workspace/2.spi_device_alert_test/latest


Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3426608456
Short name T675
Test name
Test status
Simulation time 4113553396 ps
CPU time 32.83 seconds
Started Aug 13 05:48:53 PM PDT 24
Finished Aug 13 05:49:26 PM PDT 24
Peak memory 232896 kb
Host smart-fd65b9c0-e221-4627-b9ba-ff629e8087d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426608456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3426608456
Directory /workspace/2.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/2.spi_device_csb_read.2908725163
Short name T925
Test name
Test status
Simulation time 59674252 ps
CPU time 0.73 seconds
Started Aug 13 05:48:54 PM PDT 24
Finished Aug 13 05:48:55 PM PDT 24
Peak memory 206636 kb
Host smart-8b052ae0-5531-47d4-9e18-83c31000be0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908725163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2908725163
Directory /workspace/2.spi_device_csb_read/latest


Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3960106605
Short name T1013
Test name
Test status
Simulation time 30108495054 ps
CPU time 293.07 seconds
Started Aug 13 05:49:02 PM PDT 24
Finished Aug 13 05:53:55 PM PDT 24
Peak memory 254048 kb
Host smart-360a3802-e17c-49d7-bd88-89d51a3d8018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960106605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3960106605
Directory /workspace/2.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/2.spi_device_flash_mode.2892463001
Short name T579
Test name
Test status
Simulation time 160497402 ps
CPU time 3.08 seconds
Started Aug 13 05:49:02 PM PDT 24
Finished Aug 13 05:49:05 PM PDT 24
Peak memory 232828 kb
Host smart-d4d46c2c-f18b-4b3a-8a6a-4fe67985567f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892463001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2892463001
Directory /workspace/2.spi_device_flash_mode/latest


Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2133100404
Short name T294
Test name
Test status
Simulation time 10303056909 ps
CPU time 63.05 seconds
Started Aug 13 05:49:02 PM PDT 24
Finished Aug 13 05:50:06 PM PDT 24
Peak memory 251408 kb
Host smart-d7567625-f273-45d7-8b62-dce0deaf9309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133100404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2133100404
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/2.spi_device_intercept.65822663
Short name T137
Test name
Test status
Simulation time 2276609223 ps
CPU time 10.52 seconds
Started Aug 13 05:48:56 PM PDT 24
Finished Aug 13 05:49:06 PM PDT 24
Peak memory 224728 kb
Host smart-50ba837b-cca9-4a14-bd1e-e65c66371624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65822663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.65822663
Directory /workspace/2.spi_device_intercept/latest


Test location /workspace/coverage/default/2.spi_device_mailbox.821282395
Short name T571
Test name
Test status
Simulation time 1439668388 ps
CPU time 19.94 seconds
Started Aug 13 05:48:57 PM PDT 24
Finished Aug 13 05:49:17 PM PDT 24
Peak memory 232824 kb
Host smart-ecf75e45-f976-4df9-a9ae-89d8194d92cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821282395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.821282395
Directory /workspace/2.spi_device_mailbox/latest


Test location /workspace/coverage/default/2.spi_device_mem_parity.2389854241
Short name T356
Test name
Test status
Simulation time 89847667 ps
CPU time 1.09 seconds
Started Aug 13 05:48:54 PM PDT 24
Finished Aug 13 05:48:56 PM PDT 24
Peak memory 217948 kb
Host smart-11920aa2-5e45-4b46-b9f1-9d43cfacbc88
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389854241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2389854241
Directory /workspace/2.spi_device_mem_parity/latest


Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2211786185
Short name T265
Test name
Test status
Simulation time 27175173638 ps
CPU time 16.9 seconds
Started Aug 13 05:48:53 PM PDT 24
Finished Aug 13 05:49:10 PM PDT 24
Peak memory 237624 kb
Host smart-087bf26f-0473-473e-b793-0394c778ca8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211786185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2211786185
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2483835244
Short name T252
Test name
Test status
Simulation time 2327948139 ps
CPU time 7.97 seconds
Started Aug 13 05:48:57 PM PDT 24
Finished Aug 13 05:49:05 PM PDT 24
Peak memory 232916 kb
Host smart-cc07ed2c-bd0d-4aa0-8f35-1d71cc61ff43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483835244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2483835244
Directory /workspace/2.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.625740310
Short name T44
Test name
Test status
Simulation time 80948172 ps
CPU time 3.84 seconds
Started Aug 13 05:49:02 PM PDT 24
Finished Aug 13 05:49:06 PM PDT 24
Peak memory 222712 kb
Host smart-d7846557-5631-4fc2-a9e8-ddd814b3b7ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=625740310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.625740310
Directory /workspace/2.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/2.spi_device_sec_cm.2131456668
Short name T72
Test name
Test status
Simulation time 128491525 ps
CPU time 1.04 seconds
Started Aug 13 05:49:03 PM PDT 24
Finished Aug 13 05:49:04 PM PDT 24
Peak memory 235892 kb
Host smart-c466b07b-429d-4ac3-9696-f5eb52838452
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131456668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2131456668
Directory /workspace/2.spi_device_sec_cm/latest


Test location /workspace/coverage/default/2.spi_device_tpm_all.2598674586
Short name T479
Test name
Test status
Simulation time 1736793244 ps
CPU time 11.55 seconds
Started Aug 13 05:48:53 PM PDT 24
Finished Aug 13 05:49:04 PM PDT 24
Peak memory 216648 kb
Host smart-70d9f0b6-80d3-4f8c-bdc9-69e9e263abd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598674586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2598674586
Directory /workspace/2.spi_device_tpm_all/latest


Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4119555042
Short name T838
Test name
Test status
Simulation time 2074803798 ps
CPU time 7.58 seconds
Started Aug 13 05:48:56 PM PDT 24
Finished Aug 13 05:49:04 PM PDT 24
Peak memory 216512 kb
Host smart-16e46b4d-3174-40c2-84d5-9d49cb00b43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119555042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4119555042
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/2.spi_device_tpm_rw.1915866275
Short name T33
Test name
Test status
Simulation time 193865016 ps
CPU time 2.75 seconds
Started Aug 13 05:48:53 PM PDT 24
Finished Aug 13 05:48:56 PM PDT 24
Peak memory 216460 kb
Host smart-57166dcc-e9b8-4e1a-b29d-386913d3c556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915866275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1915866275
Directory /workspace/2.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.830429424
Short name T638
Test name
Test status
Simulation time 121225332 ps
CPU time 0.74 seconds
Started Aug 13 05:48:55 PM PDT 24
Finished Aug 13 05:48:57 PM PDT 24
Peak memory 206136 kb
Host smart-e2cdb320-943c-4df2-abf7-a2bf5e6bb9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830429424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.830429424
Directory /workspace/2.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/2.spi_device_upload.1419226992
Short name T183
Test name
Test status
Simulation time 1412432368 ps
CPU time 8.29 seconds
Started Aug 13 05:48:54 PM PDT 24
Finished Aug 13 05:49:03 PM PDT 24
Peak memory 224644 kb
Host smart-3a3d84d6-e729-4a94-86f7-7aa0dfe43ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419226992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1419226992
Directory /workspace/2.spi_device_upload/latest


Test location /workspace/coverage/default/20.spi_device_alert_test.206483099
Short name T556
Test name
Test status
Simulation time 13607893 ps
CPU time 0.73 seconds
Started Aug 13 05:51:09 PM PDT 24
Finished Aug 13 05:51:10 PM PDT 24
Peak memory 205592 kb
Host smart-7b2473d2-e9f8-4ad2-b1fd-f54fec8461d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206483099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.206483099
Directory /workspace/20.spi_device_alert_test/latest


Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2322390740
Short name T894
Test name
Test status
Simulation time 89106542 ps
CPU time 2.68 seconds
Started Aug 13 05:51:12 PM PDT 24
Finished Aug 13 05:51:15 PM PDT 24
Peak memory 232908 kb
Host smart-608939e8-ee01-4600-bd60-0457fc72d458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322390740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2322390740
Directory /workspace/20.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/20.spi_device_csb_read.2640820482
Short name T945
Test name
Test status
Simulation time 219732314 ps
CPU time 0.84 seconds
Started Aug 13 05:51:11 PM PDT 24
Finished Aug 13 05:51:12 PM PDT 24
Peak memory 206560 kb
Host smart-e62ba87b-d6f4-4079-aff4-e1abb5668104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640820482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2640820482
Directory /workspace/20.spi_device_csb_read/latest


Test location /workspace/coverage/default/20.spi_device_flash_all.4062633067
Short name T941
Test name
Test status
Simulation time 44453076176 ps
CPU time 100.59 seconds
Started Aug 13 05:51:11 PM PDT 24
Finished Aug 13 05:52:52 PM PDT 24
Peak memory 252680 kb
Host smart-fb2c8574-ddaa-400e-822f-ec15962a17ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062633067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.4062633067
Directory /workspace/20.spi_device_flash_all/latest


Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.377369228
Short name T598
Test name
Test status
Simulation time 83316592296 ps
CPU time 411.6 seconds
Started Aug 13 05:51:13 PM PDT 24
Finished Aug 13 05:58:04 PM PDT 24
Peak memory 249440 kb
Host smart-1ae2b702-9116-4c36-bec2-464bbed60a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377369228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.377369228
Directory /workspace/20.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.998081278
Short name T292
Test name
Test status
Simulation time 296129030680 ps
CPU time 240.26 seconds
Started Aug 13 05:51:10 PM PDT 24
Finished Aug 13 05:55:10 PM PDT 24
Peak memory 257432 kb
Host smart-6a4fa44d-41d1-4fa7-8644-8881fddeb54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998081278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.998081278
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/20.spi_device_flash_mode.3743151813
Short name T510
Test name
Test status
Simulation time 659487215 ps
CPU time 4.76 seconds
Started Aug 13 05:51:11 PM PDT 24
Finished Aug 13 05:51:15 PM PDT 24
Peak memory 224692 kb
Host smart-35b732cc-0a47-4487-a724-4fdc88598afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743151813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3743151813
Directory /workspace/20.spi_device_flash_mode/latest


Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2674399154
Short name T190
Test name
Test status
Simulation time 47872637176 ps
CPU time 96.82 seconds
Started Aug 13 05:51:12 PM PDT 24
Finished Aug 13 05:52:49 PM PDT 24
Peak memory 241160 kb
Host smart-0fd67a54-d8c4-497f-9724-65d8b5c93617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674399154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2674399154
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/20.spi_device_intercept.268594809
Short name T705
Test name
Test status
Simulation time 186846992 ps
CPU time 2.79 seconds
Started Aug 13 05:51:12 PM PDT 24
Finished Aug 13 05:51:15 PM PDT 24
Peak memory 232860 kb
Host smart-c35940cb-8234-4186-b49d-4be364e36a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268594809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.268594809
Directory /workspace/20.spi_device_intercept/latest


Test location /workspace/coverage/default/20.spi_device_mailbox.4138205136
Short name T436
Test name
Test status
Simulation time 515428803 ps
CPU time 8.27 seconds
Started Aug 13 05:51:07 PM PDT 24
Finished Aug 13 05:51:16 PM PDT 24
Peak memory 232904 kb
Host smart-f6038f0b-c8a4-486a-9a59-b504d3579674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138205136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4138205136
Directory /workspace/20.spi_device_mailbox/latest


Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3897723701
Short name T725
Test name
Test status
Simulation time 12263783297 ps
CPU time 10.77 seconds
Started Aug 13 05:51:09 PM PDT 24
Finished Aug 13 05:51:20 PM PDT 24
Peak memory 232920 kb
Host smart-3a82e315-7b4a-4a5f-aee8-c13746ea706f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897723701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3897723701
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3301481638
Short name T516
Test name
Test status
Simulation time 3668672557 ps
CPU time 15.25 seconds
Started Aug 13 05:51:10 PM PDT 24
Finished Aug 13 05:51:25 PM PDT 24
Peak memory 232908 kb
Host smart-335349f7-3ac6-4d30-b15a-851f9a0fb664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301481638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3301481638
Directory /workspace/20.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.971273211
Short name T152
Test name
Test status
Simulation time 1032299106 ps
CPU time 12.18 seconds
Started Aug 13 05:51:11 PM PDT 24
Finished Aug 13 05:51:24 PM PDT 24
Peak memory 222152 kb
Host smart-e59a008e-e2be-42e5-99dd-1c246462247e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=971273211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.971273211
Directory /workspace/20.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/20.spi_device_stress_all.1959691976
Short name T20
Test name
Test status
Simulation time 12141325966 ps
CPU time 59.76 seconds
Started Aug 13 05:51:10 PM PDT 24
Finished Aug 13 05:52:10 PM PDT 24
Peak memory 241180 kb
Host smart-1db55198-ff3f-4991-b8e9-a4c51304f18a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959691976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1959691976
Directory /workspace/20.spi_device_stress_all/latest


Test location /workspace/coverage/default/20.spi_device_tpm_all.2344456381
Short name T973
Test name
Test status
Simulation time 4174403126 ps
CPU time 22.27 seconds
Started Aug 13 05:51:11 PM PDT 24
Finished Aug 13 05:51:33 PM PDT 24
Peak memory 216504 kb
Host smart-96a51a9e-6c10-455f-87c8-0289f77ce5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344456381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2344456381
Directory /workspace/20.spi_device_tpm_all/latest


Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1310751772
Short name T396
Test name
Test status
Simulation time 714654511 ps
CPU time 3.03 seconds
Started Aug 13 05:51:14 PM PDT 24
Finished Aug 13 05:51:17 PM PDT 24
Peak memory 216508 kb
Host smart-7938bc0a-9b6e-4d90-b5f5-094bf6890ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310751772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1310751772
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/20.spi_device_tpm_rw.4065996491
Short name T521
Test name
Test status
Simulation time 35298885 ps
CPU time 1.08 seconds
Started Aug 13 05:51:10 PM PDT 24
Finished Aug 13 05:51:11 PM PDT 24
Peak memory 208120 kb
Host smart-0bf573e4-ff9a-476f-9d75-3a15a83ac2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065996491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.4065996491
Directory /workspace/20.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1462960301
Short name T865
Test name
Test status
Simulation time 43187974 ps
CPU time 0.82 seconds
Started Aug 13 05:51:10 PM PDT 24
Finished Aug 13 05:51:11 PM PDT 24
Peak memory 206136 kb
Host smart-836988d3-7a15-4c17-adf1-a35e6c75c6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462960301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1462960301
Directory /workspace/20.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/20.spi_device_upload.3977675414
Short name T628
Test name
Test status
Simulation time 7947286445 ps
CPU time 4.39 seconds
Started Aug 13 05:51:12 PM PDT 24
Finished Aug 13 05:51:16 PM PDT 24
Peak memory 232984 kb
Host smart-b9b2d1e2-5e07-4a49-aba5-c53694253a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977675414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3977675414
Directory /workspace/20.spi_device_upload/latest


Test location /workspace/coverage/default/21.spi_device_alert_test.3991131309
Short name T917
Test name
Test status
Simulation time 15841883 ps
CPU time 0.73 seconds
Started Aug 13 05:51:19 PM PDT 24
Finished Aug 13 05:51:20 PM PDT 24
Peak memory 205588 kb
Host smart-25748fb3-062f-435e-a2b6-ff87bdc3ffa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991131309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3991131309
Directory /workspace/21.spi_device_alert_test/latest


Test location /workspace/coverage/default/21.spi_device_cfg_cmd.205786602
Short name T608
Test name
Test status
Simulation time 433587709 ps
CPU time 2.58 seconds
Started Aug 13 05:51:18 PM PDT 24
Finished Aug 13 05:51:21 PM PDT 24
Peak memory 224572 kb
Host smart-d991bc72-2a9f-43eb-afcc-d5f75ca0ed18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205786602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.205786602
Directory /workspace/21.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/21.spi_device_csb_read.1367382376
Short name T367
Test name
Test status
Simulation time 41459533 ps
CPU time 0.76 seconds
Started Aug 13 05:51:18 PM PDT 24
Finished Aug 13 05:51:19 PM PDT 24
Peak memory 205524 kb
Host smart-a8422fd8-fb71-4a48-a417-658b8b36fcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367382376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1367382376
Directory /workspace/21.spi_device_csb_read/latest


Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.780787001
Short name T180
Test name
Test status
Simulation time 35765252374 ps
CPU time 182.3 seconds
Started Aug 13 05:51:20 PM PDT 24
Finished Aug 13 05:54:22 PM PDT 24
Peak memory 254624 kb
Host smart-0bc26a74-fcf2-4a3c-8182-52fbd98cf193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780787001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.780787001
Directory /workspace/21.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.262050840
Short name T1028
Test name
Test status
Simulation time 26405482467 ps
CPU time 61.51 seconds
Started Aug 13 05:51:20 PM PDT 24
Finished Aug 13 05:52:21 PM PDT 24
Peak memory 249340 kb
Host smart-1da85b2d-0fb2-4ba2-91c5-38a613b9d6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262050840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.262050840
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/21.spi_device_flash_mode.725520944
Short name T876
Test name
Test status
Simulation time 144671099 ps
CPU time 5.43 seconds
Started Aug 13 05:51:16 PM PDT 24
Finished Aug 13 05:51:22 PM PDT 24
Peak memory 232808 kb
Host smart-5ec3b52e-f438-4820-aa8b-aac5510be7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725520944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.725520944
Directory /workspace/21.spi_device_flash_mode/latest


Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1648601877
Short name T414
Test name
Test status
Simulation time 9778166842 ps
CPU time 31.03 seconds
Started Aug 13 05:51:19 PM PDT 24
Finished Aug 13 05:51:50 PM PDT 24
Peak memory 239824 kb
Host smart-a19de790-8ecd-4d24-acfc-c1bd285308e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648601877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1648601877
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/21.spi_device_intercept.1956777677
Short name T727
Test name
Test status
Simulation time 10647654425 ps
CPU time 9.84 seconds
Started Aug 13 05:51:19 PM PDT 24
Finished Aug 13 05:51:29 PM PDT 24
Peak memory 232956 kb
Host smart-5650188d-86d4-44e7-a4aa-b43205d8f875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956777677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1956777677
Directory /workspace/21.spi_device_intercept/latest


Test location /workspace/coverage/default/21.spi_device_mailbox.303609784
Short name T893
Test name
Test status
Simulation time 3913288319 ps
CPU time 25.39 seconds
Started Aug 13 05:51:18 PM PDT 24
Finished Aug 13 05:51:44 PM PDT 24
Peak memory 232916 kb
Host smart-0a2c9d84-da02-4336-a98e-d362a1d808db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303609784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.303609784
Directory /workspace/21.spi_device_mailbox/latest


Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2406129334
Short name T960
Test name
Test status
Simulation time 13451360354 ps
CPU time 42.21 seconds
Started Aug 13 05:51:20 PM PDT 24
Finished Aug 13 05:52:02 PM PDT 24
Peak memory 232908 kb
Host smart-e7db6913-947a-4cc6-aa98-ae2f6e2c7a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406129334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2406129334
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2059221219
Short name T437
Test name
Test status
Simulation time 675827222 ps
CPU time 4.02 seconds
Started Aug 13 05:51:18 PM PDT 24
Finished Aug 13 05:51:22 PM PDT 24
Peak memory 224604 kb
Host smart-3921df3a-c4f6-4f8c-851f-28ac05425c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059221219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2059221219
Directory /workspace/21.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2453247372
Short name T154
Test name
Test status
Simulation time 747577176 ps
CPU time 8.52 seconds
Started Aug 13 05:51:21 PM PDT 24
Finished Aug 13 05:51:30 PM PDT 24
Peak memory 220368 kb
Host smart-06b490cf-e1fe-4cc0-a7cf-8292c408778d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2453247372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2453247372
Directory /workspace/21.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/21.spi_device_stress_all.2660721013
Short name T732
Test name
Test status
Simulation time 12347020448 ps
CPU time 156.57 seconds
Started Aug 13 05:51:20 PM PDT 24
Finished Aug 13 05:53:56 PM PDT 24
Peak memory 269520 kb
Host smart-88d6c9bb-244d-45eb-aed5-b77e183c8c9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660721013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2660721013
Directory /workspace/21.spi_device_stress_all/latest


Test location /workspace/coverage/default/21.spi_device_tpm_all.1808930678
Short name T720
Test name
Test status
Simulation time 24254111 ps
CPU time 0.75 seconds
Started Aug 13 05:51:17 PM PDT 24
Finished Aug 13 05:51:18 PM PDT 24
Peak memory 205720 kb
Host smart-6bcf6a34-f647-446f-9739-967ef90244bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808930678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1808930678
Directory /workspace/21.spi_device_tpm_all/latest


Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.964746642
Short name T982
Test name
Test status
Simulation time 3578085040 ps
CPU time 5.79 seconds
Started Aug 13 05:51:19 PM PDT 24
Finished Aug 13 05:51:25 PM PDT 24
Peak memory 216496 kb
Host smart-389abe3e-c685-4755-9cd2-4eaa84605906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964746642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.964746642
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/21.spi_device_tpm_rw.1203968675
Short name T404
Test name
Test status
Simulation time 39354880 ps
CPU time 0.98 seconds
Started Aug 13 05:51:16 PM PDT 24
Finished Aug 13 05:51:17 PM PDT 24
Peak memory 207084 kb
Host smart-b80bd9aa-2a88-498f-b88c-ec4e627ccffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203968675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1203968675
Directory /workspace/21.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2813823128
Short name T492
Test name
Test status
Simulation time 52769129 ps
CPU time 0.74 seconds
Started Aug 13 05:51:18 PM PDT 24
Finished Aug 13 05:51:19 PM PDT 24
Peak memory 206160 kb
Host smart-17685c5f-2ac9-4cfc-9fbb-5a42a9b6a15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813823128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2813823128
Directory /workspace/21.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/21.spi_device_upload.1981360748
Short name T246
Test name
Test status
Simulation time 3668553912 ps
CPU time 11.07 seconds
Started Aug 13 05:51:20 PM PDT 24
Finished Aug 13 05:51:31 PM PDT 24
Peak memory 241120 kb
Host smart-a70f5bf4-bd82-4388-9a99-fcc027d54b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981360748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1981360748
Directory /workspace/21.spi_device_upload/latest


Test location /workspace/coverage/default/22.spi_device_alert_test.2092386229
Short name T663
Test name
Test status
Simulation time 36074999 ps
CPU time 0.71 seconds
Started Aug 13 05:51:29 PM PDT 24
Finished Aug 13 05:51:30 PM PDT 24
Peak memory 204976 kb
Host smart-d9357c38-07a1-444b-8271-0e61167e7531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092386229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2092386229
Directory /workspace/22.spi_device_alert_test/latest


Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2135489573
Short name T346
Test name
Test status
Simulation time 1940671056 ps
CPU time 4.77 seconds
Started Aug 13 05:51:29 PM PDT 24
Finished Aug 13 05:51:34 PM PDT 24
Peak memory 224728 kb
Host smart-9c71a501-f523-452b-a1eb-3367c69b7b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135489573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2135489573
Directory /workspace/22.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/22.spi_device_csb_read.363158601
Short name T493
Test name
Test status
Simulation time 153883843 ps
CPU time 0.78 seconds
Started Aug 13 05:51:20 PM PDT 24
Finished Aug 13 05:51:21 PM PDT 24
Peak memory 206612 kb
Host smart-b62e31b3-60d3-4ab2-9bfa-70e558e45c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363158601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.363158601
Directory /workspace/22.spi_device_csb_read/latest


Test location /workspace/coverage/default/22.spi_device_flash_all.1592610512
Short name T589
Test name
Test status
Simulation time 59695536 ps
CPU time 0.77 seconds
Started Aug 13 05:51:26 PM PDT 24
Finished Aug 13 05:51:27 PM PDT 24
Peak memory 215900 kb
Host smart-a06fe3c9-116d-4246-b713-d0f7305f4d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592610512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1592610512
Directory /workspace/22.spi_device_flash_all/latest


Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1386711575
Short name T222
Test name
Test status
Simulation time 15751568142 ps
CPU time 59.97 seconds
Started Aug 13 05:51:25 PM PDT 24
Finished Aug 13 05:52:25 PM PDT 24
Peak memory 253788 kb
Host smart-79ad5483-e0ba-44c7-b4ba-5663ee936bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386711575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1386711575
Directory /workspace/22.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.4279673920
Short name T288
Test name
Test status
Simulation time 101907377607 ps
CPU time 224.97 seconds
Started Aug 13 05:51:27 PM PDT 24
Finished Aug 13 05:55:12 PM PDT 24
Peak memory 249376 kb
Host smart-ad0b9fb3-d164-4431-83d6-0dcca72d0e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279673920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.4279673920
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/22.spi_device_flash_mode.1612423157
Short name T418
Test name
Test status
Simulation time 288445661 ps
CPU time 6.51 seconds
Started Aug 13 05:51:28 PM PDT 24
Finished Aug 13 05:51:34 PM PDT 24
Peak memory 224836 kb
Host smart-223aae11-7097-459a-ba52-b1521baa8d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612423157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1612423157
Directory /workspace/22.spi_device_flash_mode/latest


Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2507209295
Short name T204
Test name
Test status
Simulation time 24253559235 ps
CPU time 174.82 seconds
Started Aug 13 05:51:25 PM PDT 24
Finished Aug 13 05:54:20 PM PDT 24
Peak memory 252628 kb
Host smart-fdd5f334-acab-43e1-92e9-abc8f4db5f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507209295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2507209295
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/22.spi_device_intercept.3024193787
Short name T219
Test name
Test status
Simulation time 4775799568 ps
CPU time 11.35 seconds
Started Aug 13 05:51:21 PM PDT 24
Finished Aug 13 05:51:32 PM PDT 24
Peak memory 232900 kb
Host smart-6e59564e-7761-41ab-bc31-45d322a02a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024193787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3024193787
Directory /workspace/22.spi_device_intercept/latest


Test location /workspace/coverage/default/22.spi_device_mailbox.3895722904
Short name T253
Test name
Test status
Simulation time 2885230121 ps
CPU time 14.63 seconds
Started Aug 13 05:51:21 PM PDT 24
Finished Aug 13 05:51:35 PM PDT 24
Peak memory 236536 kb
Host smart-49384d74-88de-4d8e-a493-7ecd67360deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895722904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3895722904
Directory /workspace/22.spi_device_mailbox/latest


Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1371025820
Short name T746
Test name
Test status
Simulation time 10697815254 ps
CPU time 8.36 seconds
Started Aug 13 05:51:23 PM PDT 24
Finished Aug 13 05:51:32 PM PDT 24
Peak memory 224688 kb
Host smart-d5c4a34f-f0af-4e7d-9b23-df3caace896a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371025820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1371025820
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3652188827
Short name T220
Test name
Test status
Simulation time 2017605591 ps
CPU time 8.17 seconds
Started Aug 13 05:51:23 PM PDT 24
Finished Aug 13 05:51:32 PM PDT 24
Peak memory 232880 kb
Host smart-335f7e77-67e5-4224-b0b0-07ae137e1577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652188827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3652188827
Directory /workspace/22.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3268417265
Short name T924
Test name
Test status
Simulation time 743133459 ps
CPU time 10.35 seconds
Started Aug 13 05:51:25 PM PDT 24
Finished Aug 13 05:51:36 PM PDT 24
Peak memory 220104 kb
Host smart-58c6b98d-8de2-47f5-88a7-5cdb32c0262b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3268417265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3268417265
Directory /workspace/22.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/22.spi_device_stress_all.1428861388
Short name T752
Test name
Test status
Simulation time 68223248 ps
CPU time 1.03 seconds
Started Aug 13 05:51:25 PM PDT 24
Finished Aug 13 05:51:26 PM PDT 24
Peak memory 206872 kb
Host smart-10fbf806-134f-4fcb-80ee-a1b2911197a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428861388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1428861388
Directory /workspace/22.spi_device_stress_all/latest


Test location /workspace/coverage/default/22.spi_device_tpm_all.2823879325
Short name T994
Test name
Test status
Simulation time 5420309165 ps
CPU time 33.16 seconds
Started Aug 13 05:51:20 PM PDT 24
Finished Aug 13 05:51:53 PM PDT 24
Peak memory 216580 kb
Host smart-c3e3412e-a5ec-4e2c-ba41-f91adb52ea83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823879325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2823879325
Directory /workspace/22.spi_device_tpm_all/latest


Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.322927820
Short name T452
Test name
Test status
Simulation time 9533915119 ps
CPU time 6.4 seconds
Started Aug 13 05:51:19 PM PDT 24
Finished Aug 13 05:51:26 PM PDT 24
Peak memory 216600 kb
Host smart-8cfd3af9-0f46-401b-b6e1-14737cd264c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322927820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.322927820
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/22.spi_device_tpm_rw.744309229
Short name T383
Test name
Test status
Simulation time 31166893 ps
CPU time 0.69 seconds
Started Aug 13 05:51:24 PM PDT 24
Finished Aug 13 05:51:24 PM PDT 24
Peak memory 205624 kb
Host smart-3afb3901-b0cb-48ef-b914-4dc788659081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744309229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.744309229
Directory /workspace/22.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2284490357
Short name T774
Test name
Test status
Simulation time 112843723 ps
CPU time 0.95 seconds
Started Aug 13 05:51:21 PM PDT 24
Finished Aug 13 05:51:22 PM PDT 24
Peak memory 206108 kb
Host smart-9ec746ce-89fc-43c5-b17e-bcf96e3447d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284490357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2284490357
Directory /workspace/22.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/22.spi_device_upload.1481095326
Short name T403
Test name
Test status
Simulation time 106046910 ps
CPU time 4.19 seconds
Started Aug 13 05:51:27 PM PDT 24
Finished Aug 13 05:51:31 PM PDT 24
Peak memory 232924 kb
Host smart-bb634b26-8441-4896-9145-760b777cb833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481095326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1481095326
Directory /workspace/22.spi_device_upload/latest


Test location /workspace/coverage/default/23.spi_device_alert_test.2111051922
Short name T509
Test name
Test status
Simulation time 14344234 ps
CPU time 0.72 seconds
Started Aug 13 05:51:33 PM PDT 24
Finished Aug 13 05:51:34 PM PDT 24
Peak memory 205000 kb
Host smart-2ae568ac-2dd8-4420-a072-67c65a0d5195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111051922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2111051922
Directory /workspace/23.spi_device_alert_test/latest


Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2456749359
Short name T177
Test name
Test status
Simulation time 1401688109 ps
CPU time 6.76 seconds
Started Aug 13 05:51:25 PM PDT 24
Finished Aug 13 05:51:32 PM PDT 24
Peak memory 232868 kb
Host smart-f7428f8d-dd7b-47b3-88a0-b42b3c0949e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456749359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2456749359
Directory /workspace/23.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/23.spi_device_csb_read.2023787354
Short name T572
Test name
Test status
Simulation time 61723267 ps
CPU time 0.85 seconds
Started Aug 13 05:51:27 PM PDT 24
Finished Aug 13 05:51:28 PM PDT 24
Peak memory 206636 kb
Host smart-41ad6110-70e1-46ba-9096-c872e26d708d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023787354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2023787354
Directory /workspace/23.spi_device_csb_read/latest


Test location /workspace/coverage/default/23.spi_device_flash_all.773938372
Short name T1011
Test name
Test status
Simulation time 18516734448 ps
CPU time 99.93 seconds
Started Aug 13 05:51:26 PM PDT 24
Finished Aug 13 05:53:07 PM PDT 24
Peak memory 249316 kb
Host smart-7b63e52b-6623-4397-ac64-21f080d5871b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773938372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.773938372
Directory /workspace/23.spi_device_flash_all/latest


Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1221876883
Short name T796
Test name
Test status
Simulation time 4685882908 ps
CPU time 65.59 seconds
Started Aug 13 05:51:27 PM PDT 24
Finished Aug 13 05:52:32 PM PDT 24
Peak memory 249544 kb
Host smart-2f4441a7-22d2-4dd9-bbe7-eb6af9541383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221876883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1221876883
Directory /workspace/23.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/23.spi_device_flash_mode.2321649065
Short name T319
Test name
Test status
Simulation time 567239373 ps
CPU time 12.54 seconds
Started Aug 13 05:51:28 PM PDT 24
Finished Aug 13 05:51:40 PM PDT 24
Peak memory 233956 kb
Host smart-0465c1d6-a8f2-4dd1-ad4d-9f85dc2724ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321649065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2321649065
Directory /workspace/23.spi_device_flash_mode/latest


Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2921173226
Short name T181
Test name
Test status
Simulation time 34750507998 ps
CPU time 240.2 seconds
Started Aug 13 05:51:26 PM PDT 24
Finished Aug 13 05:55:26 PM PDT 24
Peak memory 251672 kb
Host smart-cab95b61-63fd-47af-9c3e-e8c050b62316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921173226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2921173226
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/23.spi_device_intercept.3958817539
Short name T651
Test name
Test status
Simulation time 402135323 ps
CPU time 4.37 seconds
Started Aug 13 05:51:26 PM PDT 24
Finished Aug 13 05:51:30 PM PDT 24
Peak memory 224672 kb
Host smart-d99da97f-52dd-44b5-962c-f6cf294581ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958817539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3958817539
Directory /workspace/23.spi_device_intercept/latest


Test location /workspace/coverage/default/23.spi_device_mailbox.1803498730
Short name T481
Test name
Test status
Simulation time 48089164443 ps
CPU time 139.29 seconds
Started Aug 13 05:51:25 PM PDT 24
Finished Aug 13 05:53:45 PM PDT 24
Peak memory 240920 kb
Host smart-a4bae78e-a066-429d-95a9-c5266cff8701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803498730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1803498730
Directory /workspace/23.spi_device_mailbox/latest


Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.873420930
Short name T515
Test name
Test status
Simulation time 3317617282 ps
CPU time 6.68 seconds
Started Aug 13 05:51:24 PM PDT 24
Finished Aug 13 05:51:31 PM PDT 24
Peak memory 232952 kb
Host smart-549de787-e9a9-4d26-a2de-030e00561a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873420930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.873420930
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1877958510
Short name T216
Test name
Test status
Simulation time 2097342354 ps
CPU time 5.7 seconds
Started Aug 13 05:51:27 PM PDT 24
Finished Aug 13 05:51:32 PM PDT 24
Peak memory 232912 kb
Host smart-f255677e-a41a-4f5b-b8a5-112d6197dc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877958510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1877958510
Directory /workspace/23.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3778154739
Short name T637
Test name
Test status
Simulation time 4079631147 ps
CPU time 11.68 seconds
Started Aug 13 05:51:26 PM PDT 24
Finished Aug 13 05:51:37 PM PDT 24
Peak memory 220264 kb
Host smart-6af4378a-f210-4582-a20b-9d7336b8272a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3778154739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3778154739
Directory /workspace/23.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/23.spi_device_stress_all.737152483
Short name T826
Test name
Test status
Simulation time 7173071672 ps
CPU time 13.1 seconds
Started Aug 13 05:51:34 PM PDT 24
Finished Aug 13 05:51:47 PM PDT 24
Peak memory 217688 kb
Host smart-beb9a26e-c74a-4dc0-a592-36819df0e5f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737152483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.737152483
Directory /workspace/23.spi_device_stress_all/latest


Test location /workspace/coverage/default/23.spi_device_tpm_all.796045355
Short name T671
Test name
Test status
Simulation time 576270493 ps
CPU time 2.17 seconds
Started Aug 13 05:51:27 PM PDT 24
Finished Aug 13 05:51:29 PM PDT 24
Peak memory 216520 kb
Host smart-cf9ac634-db0e-4d82-bc9a-4f72ba8a1acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796045355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.796045355
Directory /workspace/23.spi_device_tpm_all/latest


Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.165985105
Short name T686
Test name
Test status
Simulation time 15796570316 ps
CPU time 12.93 seconds
Started Aug 13 05:51:29 PM PDT 24
Finished Aug 13 05:51:42 PM PDT 24
Peak memory 216552 kb
Host smart-4fff8a21-89de-4228-bcdc-56b581f90ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165985105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.165985105
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/23.spi_device_tpm_rw.615707439
Short name T375
Test name
Test status
Simulation time 69134387 ps
CPU time 1.5 seconds
Started Aug 13 05:51:26 PM PDT 24
Finished Aug 13 05:51:28 PM PDT 24
Peak memory 216548 kb
Host smart-bab77798-69c2-49ad-a001-f7ebc0752998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615707439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.615707439
Directory /workspace/23.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3628351024
Short name T61
Test name
Test status
Simulation time 366479788 ps
CPU time 0.96 seconds
Started Aug 13 05:51:25 PM PDT 24
Finished Aug 13 05:51:26 PM PDT 24
Peak memory 207152 kb
Host smart-5b42903e-2bc9-4ed1-826a-d04f46a3008e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628351024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3628351024
Directory /workspace/23.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/23.spi_device_upload.1942425841
Short name T737
Test name
Test status
Simulation time 671856311 ps
CPU time 6.66 seconds
Started Aug 13 05:51:28 PM PDT 24
Finished Aug 13 05:51:35 PM PDT 24
Peak memory 232892 kb
Host smart-41fd8434-04dc-4a27-a180-d7f389a581ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942425841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1942425841
Directory /workspace/23.spi_device_upload/latest


Test location /workspace/coverage/default/24.spi_device_alert_test.2998615989
Short name T25
Test name
Test status
Simulation time 15887811 ps
CPU time 0.74 seconds
Started Aug 13 05:51:34 PM PDT 24
Finished Aug 13 05:51:35 PM PDT 24
Peak memory 205560 kb
Host smart-c527ae5d-dfdc-49cd-a055-e6884ee387d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998615989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2998615989
Directory /workspace/24.spi_device_alert_test/latest


Test location /workspace/coverage/default/24.spi_device_cfg_cmd.960136466
Short name T642
Test name
Test status
Simulation time 1164677559 ps
CPU time 2.42 seconds
Started Aug 13 05:51:35 PM PDT 24
Finished Aug 13 05:51:38 PM PDT 24
Peak memory 224728 kb
Host smart-36f8363c-05c8-4f68-aa8c-97d1f4cb3cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960136466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.960136466
Directory /workspace/24.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/24.spi_device_csb_read.3253585610
Short name T386
Test name
Test status
Simulation time 31326481 ps
CPU time 0.77 seconds
Started Aug 13 05:51:34 PM PDT 24
Finished Aug 13 05:51:35 PM PDT 24
Peak memory 206904 kb
Host smart-535dd177-b91e-4909-8427-cdb7da3a7099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253585610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3253585610
Directory /workspace/24.spi_device_csb_read/latest


Test location /workspace/coverage/default/24.spi_device_flash_all.3771859454
Short name T226
Test name
Test status
Simulation time 3451410200 ps
CPU time 62.78 seconds
Started Aug 13 05:51:34 PM PDT 24
Finished Aug 13 05:52:37 PM PDT 24
Peak memory 250372 kb
Host smart-bffbe6e7-1c4d-4d21-bdac-58d7aba0b854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771859454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3771859454
Directory /workspace/24.spi_device_flash_all/latest


Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2697645929
Short name T37
Test name
Test status
Simulation time 40534673843 ps
CPU time 384.51 seconds
Started Aug 13 05:51:34 PM PDT 24
Finished Aug 13 05:57:59 PM PDT 24
Peak memory 267256 kb
Host smart-d886b743-b145-43be-8268-2529bcdfea02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697645929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2697645929
Directory /workspace/24.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2974576041
Short name T303
Test name
Test status
Simulation time 70263005414 ps
CPU time 601.11 seconds
Started Aug 13 05:51:38 PM PDT 24
Finished Aug 13 06:01:40 PM PDT 24
Peak memory 254920 kb
Host smart-c310609f-ebe6-4c95-97c3-85ee3a6b9f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974576041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2974576041
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/24.spi_device_flash_mode.3478459618
Short name T311
Test name
Test status
Simulation time 883258092 ps
CPU time 10.39 seconds
Started Aug 13 05:51:40 PM PDT 24
Finished Aug 13 05:51:50 PM PDT 24
Peak memory 232784 kb
Host smart-b7059ed6-2b33-4304-83c1-430547c33a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478459618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3478459618
Directory /workspace/24.spi_device_flash_mode/latest


Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.827121617
Short name T445
Test name
Test status
Simulation time 68091917287 ps
CPU time 123.01 seconds
Started Aug 13 05:51:34 PM PDT 24
Finished Aug 13 05:53:37 PM PDT 24
Peak memory 241196 kb
Host smart-4492543a-ff04-461e-af9e-94933a943357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827121617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.827121617
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/24.spi_device_intercept.3417539888
Short name T353
Test name
Test status
Simulation time 436373717 ps
CPU time 2.54 seconds
Started Aug 13 05:51:36 PM PDT 24
Finished Aug 13 05:51:38 PM PDT 24
Peak memory 232528 kb
Host smart-bd245031-eb0b-41cb-a6aa-ee10b508ad9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417539888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3417539888
Directory /workspace/24.spi_device_intercept/latest


Test location /workspace/coverage/default/24.spi_device_mailbox.666778772
Short name T952
Test name
Test status
Simulation time 2468310801 ps
CPU time 26.84 seconds
Started Aug 13 05:51:34 PM PDT 24
Finished Aug 13 05:52:01 PM PDT 24
Peak memory 224672 kb
Host smart-064dcb45-a4d4-47a7-a71a-227c8c77f1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666778772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.666778772
Directory /workspace/24.spi_device_mailbox/latest


Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3368605234
Short name T1006
Test name
Test status
Simulation time 1084153482 ps
CPU time 8.11 seconds
Started Aug 13 05:51:34 PM PDT 24
Finished Aug 13 05:51:42 PM PDT 24
Peak memory 232916 kb
Host smart-bba544da-8001-488d-b558-4219bc9f4778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368605234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3368605234
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3215472614
Short name T557
Test name
Test status
Simulation time 77423626 ps
CPU time 2.29 seconds
Started Aug 13 05:51:39 PM PDT 24
Finished Aug 13 05:51:42 PM PDT 24
Peak memory 223724 kb
Host smart-d9f85fd7-69cf-4653-a5de-4eca0c6eae84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215472614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3215472614
Directory /workspace/24.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2309122758
Short name T824
Test name
Test status
Simulation time 4286794226 ps
CPU time 19.91 seconds
Started Aug 13 05:51:34 PM PDT 24
Finished Aug 13 05:51:54 PM PDT 24
Peak memory 222132 kb
Host smart-d4f4756b-31f1-464f-a3c5-859de5f9e5f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2309122758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2309122758
Directory /workspace/24.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/24.spi_device_stress_all.4014979327
Short name T261
Test name
Test status
Simulation time 5286133770 ps
CPU time 75.57 seconds
Started Aug 13 05:51:35 PM PDT 24
Finished Aug 13 05:52:50 PM PDT 24
Peak memory 262508 kb
Host smart-ee20bd02-8327-4264-9d0b-aac351626974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014979327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4014979327
Directory /workspace/24.spi_device_stress_all/latest


Test location /workspace/coverage/default/24.spi_device_tpm_all.3103369226
Short name T789
Test name
Test status
Simulation time 20233269566 ps
CPU time 31.07 seconds
Started Aug 13 05:51:39 PM PDT 24
Finished Aug 13 05:52:10 PM PDT 24
Peak memory 216468 kb
Host smart-746649b1-4fab-4c6b-a512-69a5fba33587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103369226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3103369226
Directory /workspace/24.spi_device_tpm_all/latest


Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3611739377
Short name T387
Test name
Test status
Simulation time 18126322457 ps
CPU time 8.43 seconds
Started Aug 13 05:51:34 PM PDT 24
Finished Aug 13 05:51:43 PM PDT 24
Peak memory 216532 kb
Host smart-05244f48-7070-4680-b95e-444f281f94e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611739377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3611739377
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/24.spi_device_tpm_rw.1839973654
Short name T552
Test name
Test status
Simulation time 119767805 ps
CPU time 1.81 seconds
Started Aug 13 05:51:35 PM PDT 24
Finished Aug 13 05:51:37 PM PDT 24
Peak memory 216552 kb
Host smart-5e0345c2-61e8-4520-934c-44cd40c2999c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839973654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1839973654
Directory /workspace/24.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3227686873
Short name T350
Test name
Test status
Simulation time 29717832 ps
CPU time 0.72 seconds
Started Aug 13 05:51:40 PM PDT 24
Finished Aug 13 05:51:41 PM PDT 24
Peak memory 206040 kb
Host smart-f0726368-0d0e-41b7-8d37-592bbe3023ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227686873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3227686873
Directory /workspace/24.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/24.spi_device_upload.3191357125
Short name T279
Test name
Test status
Simulation time 3644848624 ps
CPU time 14.32 seconds
Started Aug 13 05:51:32 PM PDT 24
Finished Aug 13 05:51:47 PM PDT 24
Peak memory 239524 kb
Host smart-94c54c7f-2203-4b82-9b86-33638beb8271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191357125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3191357125
Directory /workspace/24.spi_device_upload/latest


Test location /workspace/coverage/default/25.spi_device_alert_test.2318507230
Short name T468
Test name
Test status
Simulation time 12119821 ps
CPU time 0.72 seconds
Started Aug 13 05:51:45 PM PDT 24
Finished Aug 13 05:51:46 PM PDT 24
Peak memory 205912 kb
Host smart-ef914dc5-db18-49f6-a4f7-eb866be7d797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318507230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2318507230
Directory /workspace/25.spi_device_alert_test/latest


Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2663601586
Short name T239
Test name
Test status
Simulation time 172723671 ps
CPU time 4.67 seconds
Started Aug 13 05:51:44 PM PDT 24
Finished Aug 13 05:51:48 PM PDT 24
Peak memory 224712 kb
Host smart-dec9cb84-620d-4669-b391-a38a7a5e9b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663601586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2663601586
Directory /workspace/25.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/25.spi_device_csb_read.4147899461
Short name T899
Test name
Test status
Simulation time 19499592 ps
CPU time 0.84 seconds
Started Aug 13 05:51:35 PM PDT 24
Finished Aug 13 05:51:36 PM PDT 24
Peak memory 206900 kb
Host smart-449683a9-d54c-4311-9a41-e04f46137532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147899461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4147899461
Directory /workspace/25.spi_device_csb_read/latest


Test location /workspace/coverage/default/25.spi_device_flash_all.3113043764
Short name T1027
Test name
Test status
Simulation time 15834152609 ps
CPU time 118.26 seconds
Started Aug 13 05:51:44 PM PDT 24
Finished Aug 13 05:53:42 PM PDT 24
Peak memory 240592 kb
Host smart-6d012e81-edfa-4cbe-b475-8908d4d0ab69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113043764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3113043764
Directory /workspace/25.spi_device_flash_all/latest


Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2200012552
Short name T326
Test name
Test status
Simulation time 4099295183 ps
CPU time 11.41 seconds
Started Aug 13 05:51:45 PM PDT 24
Finished Aug 13 05:51:57 PM PDT 24
Peak memory 219432 kb
Host smart-2bd517ef-bb9e-4a92-b240-1a44914f7726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200012552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2200012552
Directory /workspace/25.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2971545115
Short name T635
Test name
Test status
Simulation time 87191774522 ps
CPU time 146.34 seconds
Started Aug 13 05:51:42 PM PDT 24
Finished Aug 13 05:54:09 PM PDT 24
Peak memory 235380 kb
Host smart-6a12e984-2915-4179-acf9-51c8849fe170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971545115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2971545115
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/25.spi_device_flash_mode.4232123101
Short name T318
Test name
Test status
Simulation time 2106897377 ps
CPU time 22.76 seconds
Started Aug 13 05:51:43 PM PDT 24
Finished Aug 13 05:52:06 PM PDT 24
Peak memory 240984 kb
Host smart-bab6f3e7-3e22-46bf-8db2-d4fe52606442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232123101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4232123101
Directory /workspace/25.spi_device_flash_mode/latest


Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2935869462
Short name T338
Test name
Test status
Simulation time 32805034 ps
CPU time 0.84 seconds
Started Aug 13 05:51:43 PM PDT 24
Finished Aug 13 05:51:44 PM PDT 24
Peak memory 216096 kb
Host smart-f61fa698-5b63-4c44-9d54-9ae499c1aab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935869462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2935869462
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/25.spi_device_intercept.2730840255
Short name T210
Test name
Test status
Simulation time 3398577699 ps
CPU time 24.99 seconds
Started Aug 13 05:51:44 PM PDT 24
Finished Aug 13 05:52:09 PM PDT 24
Peak memory 232984 kb
Host smart-097d8122-7777-4d23-9b68-8276d73b3472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730840255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2730840255
Directory /workspace/25.spi_device_intercept/latest


Test location /workspace/coverage/default/25.spi_device_mailbox.2929070871
Short name T804
Test name
Test status
Simulation time 13476419552 ps
CPU time 8.24 seconds
Started Aug 13 05:51:44 PM PDT 24
Finished Aug 13 05:51:52 PM PDT 24
Peak memory 224676 kb
Host smart-4dac8de9-dbcb-4f85-8b17-b41a1f5b1c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929070871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2929070871
Directory /workspace/25.spi_device_mailbox/latest


Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2654570072
Short name T1000
Test name
Test status
Simulation time 146474251 ps
CPU time 2.73 seconds
Started Aug 13 05:51:44 PM PDT 24
Finished Aug 13 05:51:47 PM PDT 24
Peak memory 232912 kb
Host smart-c3f20f5a-dd9a-43d3-b73e-22305a7150e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654570072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2654570072
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.4010708308
Short name T908
Test name
Test status
Simulation time 3645400579 ps
CPU time 11.84 seconds
Started Aug 13 05:51:44 PM PDT 24
Finished Aug 13 05:51:56 PM PDT 24
Peak memory 232876 kb
Host smart-eac37b0e-47bc-4b3d-84c5-943474407b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010708308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.4010708308
Directory /workspace/25.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.585000264
Short name T497
Test name
Test status
Simulation time 145420798 ps
CPU time 4.39 seconds
Started Aug 13 05:51:45 PM PDT 24
Finished Aug 13 05:51:50 PM PDT 24
Peak memory 222688 kb
Host smart-5ca5f405-1637-454d-993d-f4d0a18fabd1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=585000264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.585000264
Directory /workspace/25.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/25.spi_device_stress_all.862885613
Short name T161
Test name
Test status
Simulation time 59140142098 ps
CPU time 136.61 seconds
Started Aug 13 05:51:43 PM PDT 24
Finished Aug 13 05:53:59 PM PDT 24
Peak memory 249416 kb
Host smart-fdda3fe9-5dad-4c3a-9020-c1271a4ec3e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862885613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.862885613
Directory /workspace/25.spi_device_stress_all/latest


Test location /workspace/coverage/default/25.spi_device_tpm_all.3993629533
Short name T610
Test name
Test status
Simulation time 4820357679 ps
CPU time 30.16 seconds
Started Aug 13 05:51:43 PM PDT 24
Finished Aug 13 05:52:14 PM PDT 24
Peak memory 216520 kb
Host smart-e1c26781-bcbb-4b5b-8375-0ae1e330a884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993629533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3993629533
Directory /workspace/25.spi_device_tpm_all/latest


Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3038918682
Short name T599
Test name
Test status
Simulation time 2746187728 ps
CPU time 9.71 seconds
Started Aug 13 05:51:33 PM PDT 24
Finished Aug 13 05:51:43 PM PDT 24
Peak memory 216484 kb
Host smart-c6e7436f-0dd1-48eb-b3aa-2663abba18ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038918682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3038918682
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/25.spi_device_tpm_rw.2046428939
Short name T860
Test name
Test status
Simulation time 131689444 ps
CPU time 0.96 seconds
Started Aug 13 05:51:44 PM PDT 24
Finished Aug 13 05:51:45 PM PDT 24
Peak memory 208132 kb
Host smart-f7495347-63fb-4418-a1dc-e80d798c819e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046428939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2046428939
Directory /workspace/25.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3748236684
Short name T538
Test name
Test status
Simulation time 18065773 ps
CPU time 0.72 seconds
Started Aug 13 05:51:44 PM PDT 24
Finished Aug 13 05:51:45 PM PDT 24
Peak memory 206140 kb
Host smart-38e8cb2b-f53f-46fe-ac17-226a830860d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748236684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3748236684
Directory /workspace/25.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/25.spi_device_upload.2342902081
Short name T687
Test name
Test status
Simulation time 40087154709 ps
CPU time 31.75 seconds
Started Aug 13 05:51:44 PM PDT 24
Finished Aug 13 05:52:16 PM PDT 24
Peak memory 249088 kb
Host smart-6ff0db25-4176-4a7b-857e-a6ff8bdb37ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342902081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2342902081
Directory /workspace/25.spi_device_upload/latest


Test location /workspace/coverage/default/26.spi_device_alert_test.1970848104
Short name T786
Test name
Test status
Simulation time 11842789 ps
CPU time 0.71 seconds
Started Aug 13 05:51:53 PM PDT 24
Finished Aug 13 05:51:54 PM PDT 24
Peak memory 205004 kb
Host smart-85938d89-035b-4392-b909-ec14d8b74b7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970848104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1970848104
Directory /workspace/26.spi_device_alert_test/latest


Test location /workspace/coverage/default/26.spi_device_cfg_cmd.548485467
Short name T581
Test name
Test status
Simulation time 1504632590 ps
CPU time 7.98 seconds
Started Aug 13 05:51:54 PM PDT 24
Finished Aug 13 05:52:02 PM PDT 24
Peak memory 224704 kb
Host smart-081ec35b-a3de-4a02-87ca-9f4e1caf2e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548485467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.548485467
Directory /workspace/26.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/26.spi_device_csb_read.1075647618
Short name T349
Test name
Test status
Simulation time 47260876 ps
CPU time 0.75 seconds
Started Aug 13 05:51:43 PM PDT 24
Finished Aug 13 05:51:44 PM PDT 24
Peak memory 205604 kb
Host smart-cb86a20d-80aa-45c1-b895-ec6d3ff4e90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075647618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1075647618
Directory /workspace/26.spi_device_csb_read/latest


Test location /workspace/coverage/default/26.spi_device_flash_all.3958397249
Short name T896
Test name
Test status
Simulation time 1410166806 ps
CPU time 14.06 seconds
Started Aug 13 05:51:57 PM PDT 24
Finished Aug 13 05:52:11 PM PDT 24
Peak memory 233968 kb
Host smart-6246a83f-8461-4e2a-a0c7-10e3bdb8037a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958397249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3958397249
Directory /workspace/26.spi_device_flash_all/latest


Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2903309812
Short name T979
Test name
Test status
Simulation time 33744779628 ps
CPU time 254.23 seconds
Started Aug 13 05:51:54 PM PDT 24
Finished Aug 13 05:56:09 PM PDT 24
Peak memory 257620 kb
Host smart-a9503726-c47b-4246-8f33-fb914756afc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903309812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2903309812
Directory /workspace/26.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3656819004
Short name T554
Test name
Test status
Simulation time 81437041917 ps
CPU time 210.82 seconds
Started Aug 13 05:51:52 PM PDT 24
Finished Aug 13 05:55:23 PM PDT 24
Peak memory 249396 kb
Host smart-481e7cf0-d24b-42a2-9264-b89a3f265679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656819004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3656819004
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/26.spi_device_flash_mode.3928850280
Short name T151
Test name
Test status
Simulation time 1439577526 ps
CPU time 21.88 seconds
Started Aug 13 05:51:54 PM PDT 24
Finished Aug 13 05:52:16 PM PDT 24
Peak memory 224688 kb
Host smart-0ee0612d-0734-40e5-929e-164e335833f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928850280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3928850280
Directory /workspace/26.spi_device_flash_mode/latest


Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2522597101
Short name T714
Test name
Test status
Simulation time 7444799709 ps
CPU time 99.23 seconds
Started Aug 13 05:51:54 PM PDT 24
Finished Aug 13 05:53:33 PM PDT 24
Peak memory 256292 kb
Host smart-b482fcce-1423-41aa-846b-fd888092f574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522597101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2522597101
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/26.spi_device_intercept.972763200
Short name T91
Test name
Test status
Simulation time 3902974843 ps
CPU time 19.66 seconds
Started Aug 13 05:51:43 PM PDT 24
Finished Aug 13 05:52:03 PM PDT 24
Peak memory 224732 kb
Host smart-edff5f1e-90a7-41f6-b0aa-55beca6b0ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972763200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.972763200
Directory /workspace/26.spi_device_intercept/latest


Test location /workspace/coverage/default/26.spi_device_mailbox.3197803305
Short name T244
Test name
Test status
Simulation time 946555854 ps
CPU time 5.81 seconds
Started Aug 13 05:51:54 PM PDT 24
Finished Aug 13 05:52:00 PM PDT 24
Peak memory 224648 kb
Host smart-35097488-44a1-4d9d-8e8b-3836b3ae26ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197803305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3197803305
Directory /workspace/26.spi_device_mailbox/latest


Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2245614940
Short name T296
Test name
Test status
Simulation time 9410960238 ps
CPU time 12.58 seconds
Started Aug 13 05:51:42 PM PDT 24
Finished Aug 13 05:51:55 PM PDT 24
Peak memory 224704 kb
Host smart-4574272d-aaeb-4f4d-af85-356d2cdbeb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245614940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2245614940
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.547840313
Short name T522
Test name
Test status
Simulation time 1332228737 ps
CPU time 9.02 seconds
Started Aug 13 05:51:45 PM PDT 24
Finished Aug 13 05:51:54 PM PDT 24
Peak memory 224708 kb
Host smart-d94386e7-c796-46b4-8758-eb71402ce43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547840313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.547840313
Directory /workspace/26.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.749093906
Short name T417
Test name
Test status
Simulation time 1486578151 ps
CPU time 15.5 seconds
Started Aug 13 05:51:57 PM PDT 24
Finished Aug 13 05:52:13 PM PDT 24
Peak memory 219488 kb
Host smart-b2f098b9-06af-4619-9095-0227c673ea42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=749093906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.749093906
Directory /workspace/26.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/26.spi_device_stress_all.2608119256
Short name T927
Test name
Test status
Simulation time 246637542 ps
CPU time 0.91 seconds
Started Aug 13 05:51:50 PM PDT 24
Finished Aug 13 05:51:51 PM PDT 24
Peak memory 206652 kb
Host smart-2a71e54a-faa2-4dac-b693-a1122d9c57ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608119256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2608119256
Directory /workspace/26.spi_device_stress_all/latest


Test location /workspace/coverage/default/26.spi_device_tpm_all.2554732237
Short name T82
Test name
Test status
Simulation time 3574897823 ps
CPU time 16.93 seconds
Started Aug 13 05:51:42 PM PDT 24
Finished Aug 13 05:51:59 PM PDT 24
Peak memory 216684 kb
Host smart-b9761619-45a7-419b-93c2-13fed35881b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554732237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2554732237
Directory /workspace/26.spi_device_tpm_all/latest


Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1039343081
Short name T673
Test name
Test status
Simulation time 7658114696 ps
CPU time 20 seconds
Started Aug 13 05:51:46 PM PDT 24
Finished Aug 13 05:52:06 PM PDT 24
Peak memory 216552 kb
Host smart-18fb1014-03c9-4b10-adb2-26041f03aa5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039343081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1039343081
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/26.spi_device_tpm_rw.3068657600
Short name T770
Test name
Test status
Simulation time 331258562 ps
CPU time 1.94 seconds
Started Aug 13 05:51:44 PM PDT 24
Finished Aug 13 05:51:46 PM PDT 24
Peak memory 216480 kb
Host smart-acc23131-53fe-4995-a071-1ab6d37249b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068657600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3068657600
Directory /workspace/26.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2923771671
Short name T478
Test name
Test status
Simulation time 39157243 ps
CPU time 0.72 seconds
Started Aug 13 05:51:42 PM PDT 24
Finished Aug 13 05:51:43 PM PDT 24
Peak memory 206136 kb
Host smart-9511bf99-a7d4-4990-b70e-5b2a457d489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923771671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2923771671
Directory /workspace/26.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/26.spi_device_upload.1995552840
Short name T467
Test name
Test status
Simulation time 6333557808 ps
CPU time 22.54 seconds
Started Aug 13 05:51:56 PM PDT 24
Finished Aug 13 05:52:18 PM PDT 24
Peak memory 249200 kb
Host smart-953fbf20-5e26-4862-845b-731097114401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995552840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1995552840
Directory /workspace/26.spi_device_upload/latest


Test location /workspace/coverage/default/27.spi_device_alert_test.812672827
Short name T729
Test name
Test status
Simulation time 24876013 ps
CPU time 0.78 seconds
Started Aug 13 05:51:58 PM PDT 24
Finished Aug 13 05:51:59 PM PDT 24
Peak memory 205504 kb
Host smart-523866e5-d4da-43bc-8d1b-5983c92bb83a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812672827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.812672827
Directory /workspace/27.spi_device_alert_test/latest


Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1898632769
Short name T489
Test name
Test status
Simulation time 2784419571 ps
CPU time 22.98 seconds
Started Aug 13 05:51:50 PM PDT 24
Finished Aug 13 05:52:14 PM PDT 24
Peak memory 224788 kb
Host smart-67652afd-cfd1-4e6d-84ed-ad68bfee9686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898632769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1898632769
Directory /workspace/27.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/27.spi_device_csb_read.1873853466
Short name T633
Test name
Test status
Simulation time 13023048 ps
CPU time 0.79 seconds
Started Aug 13 05:51:57 PM PDT 24
Finished Aug 13 05:51:58 PM PDT 24
Peak memory 206624 kb
Host smart-c2260be8-05a6-49f6-a392-6b444a8522db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873853466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1873853466
Directory /workspace/27.spi_device_csb_read/latest


Test location /workspace/coverage/default/27.spi_device_flash_all.2975887457
Short name T791
Test name
Test status
Simulation time 2927743850 ps
CPU time 14.59 seconds
Started Aug 13 05:51:57 PM PDT 24
Finished Aug 13 05:52:12 PM PDT 24
Peak memory 232992 kb
Host smart-3ded1eea-389a-436b-b3ed-42d044c3c1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975887457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2975887457
Directory /workspace/27.spi_device_flash_all/latest


Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2044726523
Short name T230
Test name
Test status
Simulation time 26907609888 ps
CPU time 217.58 seconds
Started Aug 13 05:51:53 PM PDT 24
Finished Aug 13 05:55:30 PM PDT 24
Peak memory 256556 kb
Host smart-0088fee2-5d3e-4d6f-980d-da9e9930778b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044726523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2044726523
Directory /workspace/27.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2518265290
Short name T324
Test name
Test status
Simulation time 14798434707 ps
CPU time 116.14 seconds
Started Aug 13 05:51:49 PM PDT 24
Finished Aug 13 05:53:46 PM PDT 24
Peak memory 262896 kb
Host smart-a1454156-a79c-455b-877e-ab3710feac74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518265290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2518265290
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/27.spi_device_flash_mode.848973895
Short name T632
Test name
Test status
Simulation time 1245722164 ps
CPU time 4.42 seconds
Started Aug 13 05:51:54 PM PDT 24
Finished Aug 13 05:51:59 PM PDT 24
Peak memory 232936 kb
Host smart-2bd691b3-d5ff-4083-b182-316c59c91ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848973895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.848973895
Directory /workspace/27.spi_device_flash_mode/latest


Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2460814121
Short name T623
Test name
Test status
Simulation time 33176736939 ps
CPU time 77.4 seconds
Started Aug 13 05:51:52 PM PDT 24
Finished Aug 13 05:53:10 PM PDT 24
Peak memory 251976 kb
Host smart-01aef3c3-024c-444f-9316-0670dec1938c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460814121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2460814121
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/27.spi_device_intercept.2836863461
Short name T798
Test name
Test status
Simulation time 87868152 ps
CPU time 2.14 seconds
Started Aug 13 05:52:00 PM PDT 24
Finished Aug 13 05:52:02 PM PDT 24
Peak memory 224660 kb
Host smart-933d8f9b-8fbb-4853-9004-2b0e94b250c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836863461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2836863461
Directory /workspace/27.spi_device_intercept/latest


Test location /workspace/coverage/default/27.spi_device_mailbox.3653461015
Short name T617
Test name
Test status
Simulation time 757229822 ps
CPU time 2.47 seconds
Started Aug 13 05:51:54 PM PDT 24
Finished Aug 13 05:51:57 PM PDT 24
Peak memory 219052 kb
Host smart-0df7573c-8443-4dfe-a979-74bd56843960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653461015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3653461015
Directory /workspace/27.spi_device_mailbox/latest


Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3051040611
Short name T263
Test name
Test status
Simulation time 2664559237 ps
CPU time 11.2 seconds
Started Aug 13 05:51:52 PM PDT 24
Finished Aug 13 05:52:03 PM PDT 24
Peak memory 232888 kb
Host smart-f6b4445f-a37a-4002-b1bf-b452afb4c6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051040611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3051040611
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2455155914
Short name T624
Test name
Test status
Simulation time 19862890204 ps
CPU time 26.67 seconds
Started Aug 13 05:51:56 PM PDT 24
Finished Aug 13 05:52:22 PM PDT 24
Peak memory 240912 kb
Host smart-b8275bfc-b489-40fe-b15e-c78c544289c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455155914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2455155914
Directory /workspace/27.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3705456115
Short name T149
Test name
Test status
Simulation time 172987453 ps
CPU time 5.17 seconds
Started Aug 13 05:51:54 PM PDT 24
Finished Aug 13 05:51:59 PM PDT 24
Peak memory 221908 kb
Host smart-15cc31e4-84d4-46bc-a586-3b79743aa253
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3705456115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3705456115
Directory /workspace/27.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/27.spi_device_stress_all.1725047956
Short name T652
Test name
Test status
Simulation time 7862223432 ps
CPU time 105.14 seconds
Started Aug 13 05:51:53 PM PDT 24
Finished Aug 13 05:53:38 PM PDT 24
Peak memory 265768 kb
Host smart-d36e4107-434e-4cfb-97a1-1b3838c8b181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725047956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1725047956
Directory /workspace/27.spi_device_stress_all/latest


Test location /workspace/coverage/default/27.spi_device_tpm_all.814647671
Short name T560
Test name
Test status
Simulation time 1591300127 ps
CPU time 6.25 seconds
Started Aug 13 05:51:54 PM PDT 24
Finished Aug 13 05:52:01 PM PDT 24
Peak memory 216504 kb
Host smart-11f75125-f0a9-4b79-b888-6a53ad1bab37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814647671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.814647671
Directory /workspace/27.spi_device_tpm_all/latest


Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3291539998
Short name T631
Test name
Test status
Simulation time 47088513 ps
CPU time 0.72 seconds
Started Aug 13 05:51:53 PM PDT 24
Finished Aug 13 05:51:54 PM PDT 24
Peak memory 205648 kb
Host smart-b7fea790-5854-4ab3-b498-817aa7c1119a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291539998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3291539998
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/27.spi_device_tpm_rw.3673763395
Short name T1026
Test name
Test status
Simulation time 2516012687 ps
CPU time 2.29 seconds
Started Aug 13 05:51:52 PM PDT 24
Finished Aug 13 05:51:54 PM PDT 24
Peak memory 216532 kb
Host smart-73b7979e-d9bf-4612-a413-552728dfed1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673763395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3673763395
Directory /workspace/27.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3695973550
Short name T1010
Test name
Test status
Simulation time 574578349 ps
CPU time 0.83 seconds
Started Aug 13 05:51:53 PM PDT 24
Finished Aug 13 05:51:54 PM PDT 24
Peak memory 206168 kb
Host smart-05e4ca15-57b4-43fe-a9b8-5e8e350c3bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695973550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3695973550
Directory /workspace/27.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/27.spi_device_upload.890053445
Short name T957
Test name
Test status
Simulation time 1251731664 ps
CPU time 6.11 seconds
Started Aug 13 05:51:53 PM PDT 24
Finished Aug 13 05:51:59 PM PDT 24
Peak memory 240904 kb
Host smart-68dd8d7e-068d-4683-8a7e-1388efd92ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890053445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.890053445
Directory /workspace/27.spi_device_upload/latest


Test location /workspace/coverage/default/28.spi_device_alert_test.4223523234
Short name T358
Test name
Test status
Simulation time 33061434 ps
CPU time 0.72 seconds
Started Aug 13 05:51:59 PM PDT 24
Finished Aug 13 05:52:00 PM PDT 24
Peak memory 205860 kb
Host smart-bfb1c4e3-44ba-46f0-9d1d-51cbf0b5a127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223523234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
4223523234
Directory /workspace/28.spi_device_alert_test/latest


Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2732897233
Short name T276
Test name
Test status
Simulation time 625670881 ps
CPU time 9.04 seconds
Started Aug 13 05:52:01 PM PDT 24
Finished Aug 13 05:52:10 PM PDT 24
Peak memory 232912 kb
Host smart-95559460-0c0d-4778-9e92-a62f0fbd0c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732897233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2732897233
Directory /workspace/28.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/28.spi_device_csb_read.3564706274
Short name T565
Test name
Test status
Simulation time 13294613 ps
CPU time 0.79 seconds
Started Aug 13 05:52:01 PM PDT 24
Finished Aug 13 05:52:02 PM PDT 24
Peak memory 205536 kb
Host smart-7d19971e-2bfa-461f-a737-da9c4868c88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564706274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3564706274
Directory /workspace/28.spi_device_csb_read/latest


Test location /workspace/coverage/default/28.spi_device_flash_all.3736328836
Short name T814
Test name
Test status
Simulation time 12154870477 ps
CPU time 123.48 seconds
Started Aug 13 05:52:05 PM PDT 24
Finished Aug 13 05:54:09 PM PDT 24
Peak memory 265580 kb
Host smart-dc59c581-30ca-414e-a56d-5694aaec35c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736328836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3736328836
Directory /workspace/28.spi_device_flash_all/latest


Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3100779930
Short name T1021
Test name
Test status
Simulation time 25537901 ps
CPU time 0.84 seconds
Started Aug 13 05:51:59 PM PDT 24
Finished Aug 13 05:52:00 PM PDT 24
Peak memory 216964 kb
Host smart-dde33cd7-6e1a-4cd0-84a3-0389d01f1468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100779930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3100779930
Directory /workspace/28.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3052312665
Short name T777
Test name
Test status
Simulation time 3324612758 ps
CPU time 27.55 seconds
Started Aug 13 05:51:56 PM PDT 24
Finished Aug 13 05:52:24 PM PDT 24
Peak memory 240956 kb
Host smart-dea0427e-3bd2-4fb6-9911-addfa35238b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052312665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3052312665
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/28.spi_device_flash_mode.3031731432
Short name T620
Test name
Test status
Simulation time 133227020 ps
CPU time 4.63 seconds
Started Aug 13 05:51:57 PM PDT 24
Finished Aug 13 05:52:01 PM PDT 24
Peak memory 233068 kb
Host smart-ff67b491-9543-4535-ae5a-a6ec8b5d3f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031731432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3031731432
Directory /workspace/28.spi_device_flash_mode/latest


Test location /workspace/coverage/default/28.spi_device_intercept.2877462113
Short name T646
Test name
Test status
Simulation time 917194333 ps
CPU time 3.5 seconds
Started Aug 13 05:51:58 PM PDT 24
Finished Aug 13 05:52:01 PM PDT 24
Peak memory 224640 kb
Host smart-2a741234-1e1a-4d84-bfd5-092fcbd3d406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877462113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2877462113
Directory /workspace/28.spi_device_intercept/latest


Test location /workspace/coverage/default/28.spi_device_mailbox.2070880611
Short name T944
Test name
Test status
Simulation time 3787988066 ps
CPU time 17.51 seconds
Started Aug 13 05:51:59 PM PDT 24
Finished Aug 13 05:52:16 PM PDT 24
Peak memory 249232 kb
Host smart-665d2a26-3e44-4c4a-9437-6acc4b6c31ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070880611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2070880611
Directory /workspace/28.spi_device_mailbox/latest


Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3062942896
Short name T847
Test name
Test status
Simulation time 1308393040 ps
CPU time 5.99 seconds
Started Aug 13 05:51:58 PM PDT 24
Finished Aug 13 05:52:04 PM PDT 24
Peak memory 224628 kb
Host smart-1db2aee5-425e-478f-97d1-36901e22ef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062942896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3062942896
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3732932829
Short name T138
Test name
Test status
Simulation time 3154650027 ps
CPU time 10.99 seconds
Started Aug 13 05:52:05 PM PDT 24
Finished Aug 13 05:52:16 PM PDT 24
Peak memory 232976 kb
Host smart-ef21cdf7-a835-45aa-9509-f57774f0485a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732932829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3732932829
Directory /workspace/28.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2238877237
Short name T576
Test name
Test status
Simulation time 150002794 ps
CPU time 5.33 seconds
Started Aug 13 05:52:02 PM PDT 24
Finished Aug 13 05:52:07 PM PDT 24
Peak memory 223292 kb
Host smart-656192a1-8f1a-479f-9fdb-ee57ec96112a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2238877237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2238877237
Directory /workspace/28.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/28.spi_device_stress_all.1605068285
Short name T545
Test name
Test status
Simulation time 63217475 ps
CPU time 1.24 seconds
Started Aug 13 05:51:59 PM PDT 24
Finished Aug 13 05:52:00 PM PDT 24
Peak memory 207852 kb
Host smart-4d85325a-4f40-407c-8a83-bc08b0e10d36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605068285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1605068285
Directory /workspace/28.spi_device_stress_all/latest


Test location /workspace/coverage/default/28.spi_device_tpm_all.1815732707
Short name T329
Test name
Test status
Simulation time 10050763536 ps
CPU time 32.36 seconds
Started Aug 13 05:51:59 PM PDT 24
Finished Aug 13 05:52:31 PM PDT 24
Peak memory 216608 kb
Host smart-3fda06ae-de64-4007-9a28-22662f602bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815732707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1815732707
Directory /workspace/28.spi_device_tpm_all/latest


Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.75365500
Short name T1018
Test name
Test status
Simulation time 1071872372 ps
CPU time 6.4 seconds
Started Aug 13 05:52:05 PM PDT 24
Finished Aug 13 05:52:11 PM PDT 24
Peak memory 216472 kb
Host smart-cbde91f3-227c-4894-892f-861af053f355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75365500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.75365500
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/28.spi_device_tpm_rw.3481357181
Short name T585
Test name
Test status
Simulation time 161173690 ps
CPU time 1.47 seconds
Started Aug 13 05:51:58 PM PDT 24
Finished Aug 13 05:52:00 PM PDT 24
Peak memory 216452 kb
Host smart-e26aaad5-760f-437b-998a-ad6b15c3790e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481357181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3481357181
Directory /workspace/28.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.899180993
Short name T882
Test name
Test status
Simulation time 292057835 ps
CPU time 0.95 seconds
Started Aug 13 05:51:57 PM PDT 24
Finished Aug 13 05:51:58 PM PDT 24
Peak memory 207168 kb
Host smart-c2d5bbd8-08d6-4925-bb4e-c5d2fdbdd1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899180993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.899180993
Directory /workspace/28.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/28.spi_device_upload.3202832672
Short name T830
Test name
Test status
Simulation time 10071873452 ps
CPU time 6.89 seconds
Started Aug 13 05:52:01 PM PDT 24
Finished Aug 13 05:52:09 PM PDT 24
Peak memory 224664 kb
Host smart-fc392b93-6ad1-4805-9c15-8152b4a47ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202832672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3202832672
Directory /workspace/28.spi_device_upload/latest


Test location /workspace/coverage/default/29.spi_device_alert_test.2895560731
Short name T344
Test name
Test status
Simulation time 25267172 ps
CPU time 0.73 seconds
Started Aug 13 05:52:09 PM PDT 24
Finished Aug 13 05:52:10 PM PDT 24
Peak memory 205524 kb
Host smart-5efb2c62-4742-4cde-ae13-bf7029eecdad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895560731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2895560731
Directory /workspace/29.spi_device_alert_test/latest


Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2385495341
Short name T992
Test name
Test status
Simulation time 1585489913 ps
CPU time 18.59 seconds
Started Aug 13 05:52:09 PM PDT 24
Finished Aug 13 05:52:28 PM PDT 24
Peak memory 224640 kb
Host smart-4e05e75d-1567-4622-b57a-2beb044fd2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385495341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2385495341
Directory /workspace/29.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/29.spi_device_csb_read.1868045074
Short name T630
Test name
Test status
Simulation time 46675801 ps
CPU time 0.79 seconds
Started Aug 13 05:51:59 PM PDT 24
Finished Aug 13 05:52:00 PM PDT 24
Peak memory 206584 kb
Host smart-df0bda27-925a-40e9-8861-bef13a4aff2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868045074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1868045074
Directory /workspace/29.spi_device_csb_read/latest


Test location /workspace/coverage/default/29.spi_device_flash_all.2325220290
Short name T189
Test name
Test status
Simulation time 1373501500 ps
CPU time 36.34 seconds
Started Aug 13 05:52:11 PM PDT 24
Finished Aug 13 05:52:47 PM PDT 24
Peak memory 249288 kb
Host smart-af3dd1fb-a8f7-4528-a910-9accfd32206e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325220290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2325220290
Directory /workspace/29.spi_device_flash_all/latest


Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1411832343
Short name T195
Test name
Test status
Simulation time 328650382792 ps
CPU time 565.7 seconds
Started Aug 13 05:52:11 PM PDT 24
Finished Aug 13 06:01:37 PM PDT 24
Peak memory 255424 kb
Host smart-adf6e038-c53b-4b80-b2f8-83cca8091992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411832343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1411832343
Directory /workspace/29.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3589224712
Short name T716
Test name
Test status
Simulation time 4354932827 ps
CPU time 62.84 seconds
Started Aug 13 05:52:11 PM PDT 24
Finished Aug 13 05:53:14 PM PDT 24
Peak memory 252696 kb
Host smart-9375958e-d61a-4b70-8892-526296e3864e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589224712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3589224712
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/29.spi_device_flash_mode.892660593
Short name T380
Test name
Test status
Simulation time 542449417 ps
CPU time 4.63 seconds
Started Aug 13 05:52:10 PM PDT 24
Finished Aug 13 05:52:15 PM PDT 24
Peak memory 224636 kb
Host smart-f417ea35-c178-4838-b519-da0c2d23700a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892660593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.892660593
Directory /workspace/29.spi_device_flash_mode/latest


Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.1688422427
Short name T915
Test name
Test status
Simulation time 10570168382 ps
CPU time 73.19 seconds
Started Aug 13 05:52:11 PM PDT 24
Finished Aug 13 05:53:24 PM PDT 24
Peak memory 253440 kb
Host smart-fa742041-4bde-4d0b-9dda-e72953c4d0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688422427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.1688422427
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/29.spi_device_intercept.1776995298
Short name T996
Test name
Test status
Simulation time 61762024 ps
CPU time 3.15 seconds
Started Aug 13 05:52:05 PM PDT 24
Finished Aug 13 05:52:09 PM PDT 24
Peak memory 232884 kb
Host smart-82fc373e-ad44-42fe-82d4-b32eca6f3378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776995298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1776995298
Directory /workspace/29.spi_device_intercept/latest


Test location /workspace/coverage/default/29.spi_device_mailbox.985482058
Short name T743
Test name
Test status
Simulation time 269580267 ps
CPU time 2.35 seconds
Started Aug 13 05:51:58 PM PDT 24
Finished Aug 13 05:52:01 PM PDT 24
Peak memory 232500 kb
Host smart-46893dfe-733b-4bc6-ac5c-106469527f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985482058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.985482058
Directory /workspace/29.spi_device_mailbox/latest


Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3539774541
Short name T199
Test name
Test status
Simulation time 3786597262 ps
CPU time 8.34 seconds
Started Aug 13 05:51:59 PM PDT 24
Finished Aug 13 05:52:08 PM PDT 24
Peak memory 232968 kb
Host smart-536a2e00-a24d-43f6-9856-f7feb531eb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539774541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3539774541
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3148073308
Short name T393
Test name
Test status
Simulation time 3610054591 ps
CPU time 7.46 seconds
Started Aug 13 05:52:00 PM PDT 24
Finished Aug 13 05:52:08 PM PDT 24
Peak memory 224776 kb
Host smart-49bff3af-aa8c-4df9-bd14-b3cbf78d5d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148073308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3148073308
Directory /workspace/29.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2069299783
Short name T368
Test name
Test status
Simulation time 3441615875 ps
CPU time 22.33 seconds
Started Aug 13 05:52:10 PM PDT 24
Finished Aug 13 05:52:33 PM PDT 24
Peak memory 222288 kb
Host smart-cb6956f7-84f6-48c1-9085-4808a8acdc01
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2069299783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2069299783
Directory /workspace/29.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/29.spi_device_stress_all.1545913329
Short name T302
Test name
Test status
Simulation time 38877367711 ps
CPU time 127.71 seconds
Started Aug 13 05:52:10 PM PDT 24
Finished Aug 13 05:54:18 PM PDT 24
Peak memory 273884 kb
Host smart-26b1b599-00ed-482e-aeb4-9e480985e995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545913329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1545913329
Directory /workspace/29.spi_device_stress_all/latest


Test location /workspace/coverage/default/29.spi_device_tpm_all.3914199495
Short name T680
Test name
Test status
Simulation time 8307172214 ps
CPU time 37.88 seconds
Started Aug 13 05:52:00 PM PDT 24
Finished Aug 13 05:52:38 PM PDT 24
Peak memory 216444 kb
Host smart-28749770-157f-43b2-9059-59d09436afbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914199495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3914199495
Directory /workspace/29.spi_device_tpm_all/latest


Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.120040034
Short name T933
Test name
Test status
Simulation time 1434431752 ps
CPU time 3.96 seconds
Started Aug 13 05:52:06 PM PDT 24
Finished Aug 13 05:52:10 PM PDT 24
Peak memory 216524 kb
Host smart-15820956-ec6a-4e76-83e4-515b5ea6e44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120040034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.120040034
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/29.spi_device_tpm_rw.1096054048
Short name T374
Test name
Test status
Simulation time 111950983 ps
CPU time 2.27 seconds
Started Aug 13 05:52:01 PM PDT 24
Finished Aug 13 05:52:03 PM PDT 24
Peak memory 216536 kb
Host smart-96fdf92a-634e-40b7-844a-479298666870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096054048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1096054048
Directory /workspace/29.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3855419337
Short name T588
Test name
Test status
Simulation time 194934358 ps
CPU time 0.85 seconds
Started Aug 13 05:51:58 PM PDT 24
Finished Aug 13 05:51:59 PM PDT 24
Peak memory 206092 kb
Host smart-c8c122b4-ef9b-4477-b5a7-ef823a40cab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855419337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3855419337
Directory /workspace/29.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/29.spi_device_upload.2474774145
Short name T813
Test name
Test status
Simulation time 697744401 ps
CPU time 5.16 seconds
Started Aug 13 05:52:10 PM PDT 24
Finished Aug 13 05:52:15 PM PDT 24
Peak memory 224648 kb
Host smart-1c2469d6-4ea3-4a81-a760-db21fa0a9821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474774145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2474774145
Directory /workspace/29.spi_device_upload/latest


Test location /workspace/coverage/default/3.spi_device_alert_test.921708583
Short name T381
Test name
Test status
Simulation time 14381745 ps
CPU time 0.74 seconds
Started Aug 13 05:49:13 PM PDT 24
Finished Aug 13 05:49:14 PM PDT 24
Peak memory 204936 kb
Host smart-0101c461-e167-4ac2-877a-b9a0646597f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921708583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.921708583
Directory /workspace/3.spi_device_alert_test/latest


Test location /workspace/coverage/default/3.spi_device_cfg_cmd.4195247883
Short name T861
Test name
Test status
Simulation time 78167607 ps
CPU time 2.55 seconds
Started Aug 13 05:49:11 PM PDT 24
Finished Aug 13 05:49:14 PM PDT 24
Peak memory 232452 kb
Host smart-cfb9d8b8-28e7-4d06-9129-ac92f96168e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195247883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.4195247883
Directory /workspace/3.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/3.spi_device_csb_read.926994885
Short name T788
Test name
Test status
Simulation time 49317889 ps
CPU time 0.78 seconds
Started Aug 13 05:49:04 PM PDT 24
Finished Aug 13 05:49:05 PM PDT 24
Peak memory 206596 kb
Host smart-fa013a5a-8a2a-41d8-9997-7ae9c1a4369f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926994885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.926994885
Directory /workspace/3.spi_device_csb_read/latest


Test location /workspace/coverage/default/3.spi_device_flash_all.3753063880
Short name T655
Test name
Test status
Simulation time 18013026692 ps
CPU time 50.59 seconds
Started Aug 13 05:49:09 PM PDT 24
Finished Aug 13 05:50:00 PM PDT 24
Peak memory 250684 kb
Host smart-cccc3eb5-e942-4cf7-a3b8-9fedcc791bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753063880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3753063880
Directory /workspace/3.spi_device_flash_all/latest


Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.798778105
Short name T282
Test name
Test status
Simulation time 24699731091 ps
CPU time 202.21 seconds
Started Aug 13 05:49:12 PM PDT 24
Finished Aug 13 05:52:34 PM PDT 24
Peak memory 255352 kb
Host smart-b77730e9-9580-4364-927b-5c590ec66337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798778105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.798778105
Directory /workspace/3.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2498456894
Short name T274
Test name
Test status
Simulation time 176926496995 ps
CPU time 154.46 seconds
Started Aug 13 05:49:11 PM PDT 24
Finished Aug 13 05:51:46 PM PDT 24
Peak memory 250136 kb
Host smart-1a470098-5fd4-4887-b5f0-4d416cfccab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498456894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2498456894
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/3.spi_device_flash_mode.2635561218
Short name T55
Test name
Test status
Simulation time 1387811568 ps
CPU time 23.74 seconds
Started Aug 13 05:49:11 PM PDT 24
Finished Aug 13 05:49:35 PM PDT 24
Peak memory 232940 kb
Host smart-343f8adb-cc90-4058-b277-4a50858ab27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635561218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2635561218
Directory /workspace/3.spi_device_flash_mode/latest


Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2897199253
Short name T459
Test name
Test status
Simulation time 10955076021 ps
CPU time 23.96 seconds
Started Aug 13 05:49:08 PM PDT 24
Finished Aug 13 05:49:32 PM PDT 24
Peak memory 241384 kb
Host smart-f6e9257c-e69a-43c9-b6fb-3a18ef683945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897199253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2897199253
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/3.spi_device_intercept.2708258193
Short name T807
Test name
Test status
Simulation time 423881165 ps
CPU time 3.83 seconds
Started Aug 13 05:49:11 PM PDT 24
Finished Aug 13 05:49:15 PM PDT 24
Peak memory 232876 kb
Host smart-67d4df16-1847-461e-ab68-7e729fe39e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708258193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2708258193
Directory /workspace/3.spi_device_intercept/latest


Test location /workspace/coverage/default/3.spi_device_mailbox.1165311366
Short name T54
Test name
Test status
Simulation time 107748576499 ps
CPU time 52.22 seconds
Started Aug 13 05:49:13 PM PDT 24
Finished Aug 13 05:50:05 PM PDT 24
Peak memory 240804 kb
Host smart-d2252b2f-d4c3-41e2-88e1-ceea84bdc623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165311366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1165311366
Directory /workspace/3.spi_device_mailbox/latest


Test location /workspace/coverage/default/3.spi_device_mem_parity.2900654416
Short name T423
Test name
Test status
Simulation time 117285941 ps
CPU time 1.18 seconds
Started Aug 13 05:49:03 PM PDT 24
Finished Aug 13 05:49:04 PM PDT 24
Peak memory 216748 kb
Host smart-aa9b7823-a162-4529-aa46-62492d2a19c3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900654416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2900654416
Directory /workspace/3.spi_device_mem_parity/latest


Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3992788711
Short name T360
Test name
Test status
Simulation time 82059854 ps
CPU time 2.69 seconds
Started Aug 13 05:49:12 PM PDT 24
Finished Aug 13 05:49:15 PM PDT 24
Peak memory 224620 kb
Host smart-abe169d3-f72e-4092-9da7-6571edc24194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992788711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3992788711
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1883670993
Short name T713
Test name
Test status
Simulation time 20761786477 ps
CPU time 30.42 seconds
Started Aug 13 05:49:12 PM PDT 24
Finished Aug 13 05:49:42 PM PDT 24
Peak memory 251032 kb
Host smart-653922d4-77e1-4e7e-817a-e7c89e1f9fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883670993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1883670993
Directory /workspace/3.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3489757363
Short name T711
Test name
Test status
Simulation time 194579690 ps
CPU time 4.92 seconds
Started Aug 13 05:49:10 PM PDT 24
Finished Aug 13 05:49:15 PM PDT 24
Peak memory 220384 kb
Host smart-d5950977-53fe-407a-a691-226a9bf50fe7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3489757363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3489757363
Directory /workspace/3.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/3.spi_device_sec_cm.602998002
Short name T74
Test name
Test status
Simulation time 267500147 ps
CPU time 1.09 seconds
Started Aug 13 05:49:10 PM PDT 24
Finished Aug 13 05:49:11 PM PDT 24
Peak memory 236016 kb
Host smart-4f7cb87c-9b86-4305-abf8-fb94ca86f21e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602998002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.602998002
Directory /workspace/3.spi_device_sec_cm/latest


Test location /workspace/coverage/default/3.spi_device_tpm_all.784116971
Short name T717
Test name
Test status
Simulation time 17361695045 ps
CPU time 13 seconds
Started Aug 13 05:49:03 PM PDT 24
Finished Aug 13 05:49:16 PM PDT 24
Peak memory 216532 kb
Host smart-9d4f9afb-621e-4519-b386-7543bd4979e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784116971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.784116971
Directory /workspace/3.spi_device_tpm_all/latest


Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1815478754
Short name T747
Test name
Test status
Simulation time 133155947 ps
CPU time 1.51 seconds
Started Aug 13 05:49:03 PM PDT 24
Finished Aug 13 05:49:05 PM PDT 24
Peak memory 207968 kb
Host smart-1774ab9a-07ea-422f-8a1a-1458f97c002c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815478754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1815478754
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/3.spi_device_tpm_rw.1964593629
Short name T712
Test name
Test status
Simulation time 130408788 ps
CPU time 0.97 seconds
Started Aug 13 05:49:03 PM PDT 24
Finished Aug 13 05:49:04 PM PDT 24
Peak memory 208132 kb
Host smart-96784af8-f0c5-468e-bae9-a4479cc7b210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964593629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1964593629
Directory /workspace/3.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2616645085
Short name T749
Test name
Test status
Simulation time 92657383 ps
CPU time 1.09 seconds
Started Aug 13 05:49:03 PM PDT 24
Finished Aug 13 05:49:04 PM PDT 24
Peak memory 207176 kb
Host smart-9889d67e-cb0a-4405-a347-588879d93277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616645085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2616645085
Directory /workspace/3.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/3.spi_device_upload.862736981
Short name T371
Test name
Test status
Simulation time 118559388 ps
CPU time 2.33 seconds
Started Aug 13 05:49:08 PM PDT 24
Finished Aug 13 05:49:10 PM PDT 24
Peak memory 224168 kb
Host smart-4c19ac67-950d-4ae4-86f8-d7f85c097516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862736981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.862736981
Directory /workspace/3.spi_device_upload/latest


Test location /workspace/coverage/default/30.spi_device_alert_test.1507648048
Short name T378
Test name
Test status
Simulation time 37736385 ps
CPU time 0.74 seconds
Started Aug 13 05:52:22 PM PDT 24
Finished Aug 13 05:52:23 PM PDT 24
Peak memory 204976 kb
Host smart-98bcbd3c-8548-4ece-9540-5d6e742bb238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507648048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1507648048
Directory /workspace/30.spi_device_alert_test/latest


Test location /workspace/coverage/default/30.spi_device_cfg_cmd.180565317
Short name T80
Test name
Test status
Simulation time 354031093 ps
CPU time 2.15 seconds
Started Aug 13 05:52:11 PM PDT 24
Finished Aug 13 05:52:13 PM PDT 24
Peak memory 223616 kb
Host smart-c4820407-8cd0-4d72-869b-b4ac77e1d5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180565317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.180565317
Directory /workspace/30.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/30.spi_device_csb_read.96314766
Short name T429
Test name
Test status
Simulation time 67461423 ps
CPU time 0.78 seconds
Started Aug 13 05:52:11 PM PDT 24
Finished Aug 13 05:52:12 PM PDT 24
Peak memory 206916 kb
Host smart-fa102f7c-7144-4d2c-9d1d-312df966c679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96314766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.96314766
Directory /workspace/30.spi_device_csb_read/latest


Test location /workspace/coverage/default/30.spi_device_flash_all.4210888978
Short name T200
Test name
Test status
Simulation time 20495695857 ps
CPU time 185.93 seconds
Started Aug 13 05:52:11 PM PDT 24
Finished Aug 13 05:55:17 PM PDT 24
Peak memory 256356 kb
Host smart-0403537f-3707-4660-a77f-c31c53b4abaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210888978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.4210888978
Directory /workspace/30.spi_device_flash_all/latest


Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1543017115
Short name T52
Test name
Test status
Simulation time 8763915092 ps
CPU time 132.92 seconds
Started Aug 13 05:52:20 PM PDT 24
Finished Aug 13 05:54:33 PM PDT 24
Peak memory 263980 kb
Host smart-822dec3e-13b7-44f3-9d81-377e8b1f5635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543017115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1543017115
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/30.spi_device_flash_mode.2383472472
Short name T310
Test name
Test status
Simulation time 21723138773 ps
CPU time 52.03 seconds
Started Aug 13 05:52:10 PM PDT 24
Finished Aug 13 05:53:02 PM PDT 24
Peak memory 232956 kb
Host smart-1e527fab-53bb-432a-8d08-c03ed3eeee9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383472472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2383472472
Directory /workspace/30.spi_device_flash_mode/latest


Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2586539301
Short name T259
Test name
Test status
Simulation time 27777596263 ps
CPU time 65.19 seconds
Started Aug 13 05:52:10 PM PDT 24
Finished Aug 13 05:53:15 PM PDT 24
Peak memory 255528 kb
Host smart-add81b5d-9be4-42be-ad4d-8909fa4e4718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586539301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2586539301
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/30.spi_device_intercept.372947681
Short name T741
Test name
Test status
Simulation time 10644296570 ps
CPU time 28.89 seconds
Started Aug 13 05:52:11 PM PDT 24
Finished Aug 13 05:52:40 PM PDT 24
Peak memory 224788 kb
Host smart-7f3a52bb-c272-4157-b3a3-86a88857a2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372947681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.372947681
Directory /workspace/30.spi_device_intercept/latest


Test location /workspace/coverage/default/30.spi_device_mailbox.2548436114
Short name T634
Test name
Test status
Simulation time 7324042230 ps
CPU time 40.35 seconds
Started Aug 13 05:52:11 PM PDT 24
Finished Aug 13 05:52:51 PM PDT 24
Peak memory 236404 kb
Host smart-45375397-83da-4707-8c4c-96fcca663352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548436114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2548436114
Directory /workspace/30.spi_device_mailbox/latest


Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2656012738
Short name T955
Test name
Test status
Simulation time 10138491016 ps
CPU time 11.59 seconds
Started Aug 13 05:52:11 PM PDT 24
Finished Aug 13 05:52:23 PM PDT 24
Peak memory 249356 kb
Host smart-7df170cb-0a4d-4bed-aee9-ee73dac51fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656012738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2656012738
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3758869548
Short name T97
Test name
Test status
Simulation time 1120355781 ps
CPU time 5.58 seconds
Started Aug 13 05:52:11 PM PDT 24
Finished Aug 13 05:52:17 PM PDT 24
Peak memory 224724 kb
Host smart-eb1e51c7-7949-4280-9338-1bcdce63fe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758869548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3758869548
Directory /workspace/30.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3421573428
Short name T805
Test name
Test status
Simulation time 3892404166 ps
CPU time 7.08 seconds
Started Aug 13 05:52:11 PM PDT 24
Finished Aug 13 05:52:18 PM PDT 24
Peak memory 222632 kb
Host smart-b8825bbd-92d2-4adc-b2b0-35d0f5354f4e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3421573428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3421573428
Directory /workspace/30.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/30.spi_device_stress_all.1859487875
Short name T159
Test name
Test status
Simulation time 48253797 ps
CPU time 1.1 seconds
Started Aug 13 05:52:19 PM PDT 24
Finished Aug 13 05:52:21 PM PDT 24
Peak memory 206888 kb
Host smart-27666bf6-8c5f-40b0-a8e3-6c4101c9dce3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859487875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1859487875
Directory /workspace/30.spi_device_stress_all/latest


Test location /workspace/coverage/default/30.spi_device_tpm_all.1286113740
Short name T320
Test name
Test status
Simulation time 1619846711 ps
CPU time 10.98 seconds
Started Aug 13 05:52:10 PM PDT 24
Finished Aug 13 05:52:21 PM PDT 24
Peak memory 216528 kb
Host smart-1a894e73-82f2-428b-8a15-bcd57f0883c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286113740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1286113740
Directory /workspace/30.spi_device_tpm_all/latest


Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2937840331
Short name T347
Test name
Test status
Simulation time 2970832082 ps
CPU time 8.91 seconds
Started Aug 13 05:52:10 PM PDT 24
Finished Aug 13 05:52:19 PM PDT 24
Peak memory 216548 kb
Host smart-9dcef99b-04ff-48fe-b33a-89cb8e521f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937840331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2937840331
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/30.spi_device_tpm_rw.215215242
Short name T1016
Test name
Test status
Simulation time 166635596 ps
CPU time 3.24 seconds
Started Aug 13 05:52:11 PM PDT 24
Finished Aug 13 05:52:15 PM PDT 24
Peak memory 216464 kb
Host smart-5006b052-ea2c-42b5-8ee1-019fbe4a344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215215242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.215215242
Directory /workspace/30.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3120447892
Short name T434
Test name
Test status
Simulation time 689631744 ps
CPU time 1.02 seconds
Started Aug 13 05:52:11 PM PDT 24
Finished Aug 13 05:52:12 PM PDT 24
Peak memory 206044 kb
Host smart-b9aa0302-dcbb-4f7b-aec8-1c0766b869ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120447892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3120447892
Directory /workspace/30.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/30.spi_device_upload.609605316
Short name T140
Test name
Test status
Simulation time 515950333 ps
CPU time 2.56 seconds
Started Aug 13 05:52:11 PM PDT 24
Finished Aug 13 05:52:14 PM PDT 24
Peak memory 224692 kb
Host smart-10a54c6a-7f69-419e-b4d7-728749f12001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609605316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.609605316
Directory /workspace/30.spi_device_upload/latest


Test location /workspace/coverage/default/31.spi_device_alert_test.3510001458
Short name T767
Test name
Test status
Simulation time 44258750 ps
CPU time 0.72 seconds
Started Aug 13 05:52:21 PM PDT 24
Finished Aug 13 05:52:22 PM PDT 24
Peak memory 204968 kb
Host smart-ecb47e62-beb3-4df1-a00d-d61c29523b4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510001458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3510001458
Directory /workspace/31.spi_device_alert_test/latest


Test location /workspace/coverage/default/31.spi_device_cfg_cmd.791687823
Short name T14
Test name
Test status
Simulation time 2303487541 ps
CPU time 9.18 seconds
Started Aug 13 05:52:22 PM PDT 24
Finished Aug 13 05:52:31 PM PDT 24
Peak memory 224800 kb
Host smart-1fe47838-71fc-4734-8cd7-e436f6e21df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791687823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.791687823
Directory /workspace/31.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/31.spi_device_csb_read.3659195809
Short name T689
Test name
Test status
Simulation time 30318492 ps
CPU time 0.82 seconds
Started Aug 13 05:52:22 PM PDT 24
Finished Aug 13 05:52:23 PM PDT 24
Peak memory 205876 kb
Host smart-9b071150-9a39-4e0a-8d27-f51292ad8466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659195809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3659195809
Directory /workspace/31.spi_device_csb_read/latest


Test location /workspace/coverage/default/31.spi_device_flash_all.3753163480
Short name T518
Test name
Test status
Simulation time 2113434080 ps
CPU time 12.73 seconds
Started Aug 13 05:52:22 PM PDT 24
Finished Aug 13 05:52:35 PM PDT 24
Peak memory 235244 kb
Host smart-37d0e9cf-dac1-4729-94bb-683617497fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753163480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3753163480
Directory /workspace/31.spi_device_flash_all/latest


Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3502417810
Short name T474
Test name
Test status
Simulation time 51876832607 ps
CPU time 271.49 seconds
Started Aug 13 05:52:19 PM PDT 24
Finished Aug 13 05:56:50 PM PDT 24
Peak memory 250616 kb
Host smart-4eb408cf-3ae3-419b-ba50-3b19fcbea4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502417810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3502417810
Directory /workspace/31.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4048939837
Short name T511
Test name
Test status
Simulation time 21169370455 ps
CPU time 177.36 seconds
Started Aug 13 05:52:20 PM PDT 24
Finished Aug 13 05:55:17 PM PDT 24
Peak memory 264552 kb
Host smart-fc8392fa-03c6-4653-afbd-46e831d5d1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048939837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4048939837
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/31.spi_device_flash_mode.1562904227
Short name T942
Test name
Test status
Simulation time 1015599525 ps
CPU time 9.7 seconds
Started Aug 13 05:52:22 PM PDT 24
Finished Aug 13 05:52:32 PM PDT 24
Peak memory 241080 kb
Host smart-2e5abfa6-45fa-421e-8a57-00ce54fe86d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562904227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1562904227
Directory /workspace/31.spi_device_flash_mode/latest


Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1250117831
Short name T224
Test name
Test status
Simulation time 9844312137 ps
CPU time 76.74 seconds
Started Aug 13 05:52:22 PM PDT 24
Finished Aug 13 05:53:39 PM PDT 24
Peak memory 249696 kb
Host smart-fc39834e-e830-4a04-b22b-23b6e4ec1cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250117831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1250117831
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/31.spi_device_intercept.2652512977
Short name T555
Test name
Test status
Simulation time 1113209927 ps
CPU time 5.41 seconds
Started Aug 13 05:52:22 PM PDT 24
Finished Aug 13 05:52:27 PM PDT 24
Peak memory 224656 kb
Host smart-27337632-86b8-4ed8-98ac-137f79635bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652512977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2652512977
Directory /workspace/31.spi_device_intercept/latest


Test location /workspace/coverage/default/31.spi_device_mailbox.610458458
Short name T482
Test name
Test status
Simulation time 10452800735 ps
CPU time 15.48 seconds
Started Aug 13 05:52:20 PM PDT 24
Finished Aug 13 05:52:36 PM PDT 24
Peak memory 224676 kb
Host smart-4441fa70-ee59-4879-92c9-ccf083d2dd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610458458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.610458458
Directory /workspace/31.spi_device_mailbox/latest


Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3270006901
Short name T49
Test name
Test status
Simulation time 5312890034 ps
CPU time 13.34 seconds
Started Aug 13 05:52:22 PM PDT 24
Finished Aug 13 05:52:36 PM PDT 24
Peak memory 224764 kb
Host smart-54587e1d-cbc6-43d1-924c-8c5bc844b47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270006901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3270006901
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3100057176
Short name T527
Test name
Test status
Simulation time 1668269021 ps
CPU time 6.33 seconds
Started Aug 13 05:52:20 PM PDT 24
Finished Aug 13 05:52:27 PM PDT 24
Peak memory 232892 kb
Host smart-a09407c7-4fb9-4658-aefb-c447d555b6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100057176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3100057176
Directory /workspace/31.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1854262407
Short name T430
Test name
Test status
Simulation time 2257484920 ps
CPU time 12.61 seconds
Started Aug 13 05:52:23 PM PDT 24
Finished Aug 13 05:52:35 PM PDT 24
Peak memory 222044 kb
Host smart-2ed762be-52ce-43b6-86f1-543601f37519
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1854262407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1854262407
Directory /workspace/31.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/31.spi_device_stress_all.729414161
Short name T35
Test name
Test status
Simulation time 10484738583 ps
CPU time 157.39 seconds
Started Aug 13 05:52:19 PM PDT 24
Finished Aug 13 05:54:56 PM PDT 24
Peak memory 273976 kb
Host smart-870bd719-63f6-4494-a0a6-9af204523022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729414161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.729414161
Directory /workspace/31.spi_device_stress_all/latest


Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3899753318
Short name T704
Test name
Test status
Simulation time 11686662570 ps
CPU time 13.63 seconds
Started Aug 13 05:52:19 PM PDT 24
Finished Aug 13 05:52:33 PM PDT 24
Peak memory 216624 kb
Host smart-5b19fdbb-f4b0-4db4-aea6-e54225a0a1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899753318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3899753318
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/31.spi_device_tpm_rw.878445018
Short name T530
Test name
Test status
Simulation time 26878362 ps
CPU time 0.69 seconds
Started Aug 13 05:52:20 PM PDT 24
Finished Aug 13 05:52:21 PM PDT 24
Peak memory 205640 kb
Host smart-653f71bd-9dc1-4280-90bd-ceab0bf3c287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878445018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.878445018
Directory /workspace/31.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.422869082
Short name T567
Test name
Test status
Simulation time 128330264 ps
CPU time 0.81 seconds
Started Aug 13 05:52:21 PM PDT 24
Finished Aug 13 05:52:22 PM PDT 24
Peak memory 206136 kb
Host smart-d2833fed-4996-43a3-8c6d-3b76632b97db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422869082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.422869082
Directory /workspace/31.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/31.spi_device_upload.1852779351
Short name T16
Test name
Test status
Simulation time 3493691926 ps
CPU time 6.19 seconds
Started Aug 13 05:52:18 PM PDT 24
Finished Aug 13 05:52:25 PM PDT 24
Peak memory 224736 kb
Host smart-8651e8bc-20c0-4d3c-82e5-0d7ffca6cd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852779351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1852779351
Directory /workspace/31.spi_device_upload/latest


Test location /workspace/coverage/default/32.spi_device_alert_test.2658831425
Short name T439
Test name
Test status
Simulation time 14406396 ps
CPU time 0.72 seconds
Started Aug 13 05:52:28 PM PDT 24
Finished Aug 13 05:52:29 PM PDT 24
Peak memory 205908 kb
Host smart-0f4937f4-b21e-409a-a39b-3f1751ebaf55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658831425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2658831425
Directory /workspace/32.spi_device_alert_test/latest


Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2732970970
Short name T413
Test name
Test status
Simulation time 2457708497 ps
CPU time 5.72 seconds
Started Aug 13 05:52:22 PM PDT 24
Finished Aug 13 05:52:28 PM PDT 24
Peak memory 224752 kb
Host smart-310fe7ba-2e8e-489e-973b-4f157dfd2f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732970970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2732970970
Directory /workspace/32.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/32.spi_device_csb_read.830112231
Short name T988
Test name
Test status
Simulation time 266040956 ps
CPU time 0.8 seconds
Started Aug 13 05:52:22 PM PDT 24
Finished Aug 13 05:52:23 PM PDT 24
Peak memory 206040 kb
Host smart-045e989b-1807-4a24-abca-d1e5e9ede7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830112231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.830112231
Directory /workspace/32.spi_device_csb_read/latest


Test location /workspace/coverage/default/32.spi_device_flash_all.3765347810
Short name T903
Test name
Test status
Simulation time 21153594421 ps
CPU time 76.14 seconds
Started Aug 13 05:52:29 PM PDT 24
Finished Aug 13 05:53:45 PM PDT 24
Peak memory 239916 kb
Host smart-171fd460-87cc-4e37-8397-4f0a9f26b06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765347810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3765347810
Directory /workspace/32.spi_device_flash_all/latest


Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3910702018
Short name T245
Test name
Test status
Simulation time 86665595368 ps
CPU time 180.89 seconds
Started Aug 13 05:52:30 PM PDT 24
Finished Aug 13 05:55:31 PM PDT 24
Peak memory 253696 kb
Host smart-b6f4b429-b9ff-4657-a259-dc1e16899faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910702018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3910702018
Directory /workspace/32.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/32.spi_device_flash_mode.2356379998
Short name T317
Test name
Test status
Simulation time 983535767 ps
CPU time 18.08 seconds
Started Aug 13 05:52:17 PM PDT 24
Finished Aug 13 05:52:35 PM PDT 24
Peak memory 231780 kb
Host smart-8d941aeb-b6cd-4080-8642-ab0b5535cdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356379998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2356379998
Directory /workspace/32.spi_device_flash_mode/latest


Test location /workspace/coverage/default/32.spi_device_intercept.2647826580
Short name T194
Test name
Test status
Simulation time 587357446 ps
CPU time 5.96 seconds
Started Aug 13 05:52:23 PM PDT 24
Finished Aug 13 05:52:29 PM PDT 24
Peak memory 232868 kb
Host smart-1e816fbd-85ff-43c4-97af-097862556a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647826580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2647826580
Directory /workspace/32.spi_device_intercept/latest


Test location /workspace/coverage/default/32.spi_device_mailbox.3321974651
Short name T618
Test name
Test status
Simulation time 20267335577 ps
CPU time 80.74 seconds
Started Aug 13 05:52:21 PM PDT 24
Finished Aug 13 05:53:42 PM PDT 24
Peak memory 224716 kb
Host smart-0c769727-3d76-47c1-81e6-e6778f668c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321974651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3321974651
Directory /workspace/32.spi_device_mailbox/latest


Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.4114134291
Short name T426
Test name
Test status
Simulation time 301501290 ps
CPU time 2.12 seconds
Started Aug 13 05:52:22 PM PDT 24
Finished Aug 13 05:52:24 PM PDT 24
Peak memory 223128 kb
Host smart-437b5fe0-493f-455c-be66-d9194d1148bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114134291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.4114134291
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2291496830
Short name T136
Test name
Test status
Simulation time 9991896856 ps
CPU time 17.71 seconds
Started Aug 13 05:52:21 PM PDT 24
Finished Aug 13 05:52:39 PM PDT 24
Peak memory 241124 kb
Host smart-00e6775f-7f81-4c8b-8de8-c7b00ef879e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291496830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2291496830
Directory /workspace/32.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2692557076
Short name T475
Test name
Test status
Simulation time 385150566 ps
CPU time 6.22 seconds
Started Aug 13 05:52:27 PM PDT 24
Finished Aug 13 05:52:34 PM PDT 24
Peak memory 222708 kb
Host smart-79ea380a-d161-415a-b211-b49b812c7885
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2692557076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2692557076
Directory /workspace/32.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/32.spi_device_tpm_all.3958777055
Short name T323
Test name
Test status
Simulation time 1021108223 ps
CPU time 4.48 seconds
Started Aug 13 05:52:21 PM PDT 24
Finished Aug 13 05:52:25 PM PDT 24
Peak memory 216456 kb
Host smart-21c2facb-aa72-4dd3-b9eb-b7b10d850161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958777055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3958777055
Directory /workspace/32.spi_device_tpm_all/latest


Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2308484751
Short name T369
Test name
Test status
Simulation time 4296574393 ps
CPU time 6.47 seconds
Started Aug 13 05:52:19 PM PDT 24
Finished Aug 13 05:52:26 PM PDT 24
Peak memory 216488 kb
Host smart-7d01743a-b40b-489e-9075-fb29a18bc98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308484751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2308484751
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/32.spi_device_tpm_rw.2485339267
Short name T77
Test name
Test status
Simulation time 121329657 ps
CPU time 1.09 seconds
Started Aug 13 05:52:20 PM PDT 24
Finished Aug 13 05:52:21 PM PDT 24
Peak memory 207652 kb
Host smart-9079d5fd-2e3a-4c4c-92da-e9736cec52d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485339267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2485339267
Directory /workspace/32.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3500747664
Short name T29
Test name
Test status
Simulation time 31400775 ps
CPU time 0.84 seconds
Started Aug 13 05:52:20 PM PDT 24
Finished Aug 13 05:52:21 PM PDT 24
Peak memory 207128 kb
Host smart-c9ea2265-9dc7-424b-b583-3be5d8347f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500747664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3500747664
Directory /workspace/32.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/32.spi_device_upload.4250880870
Short name T845
Test name
Test status
Simulation time 227140856 ps
CPU time 2.27 seconds
Started Aug 13 05:52:20 PM PDT 24
Finished Aug 13 05:52:22 PM PDT 24
Peak memory 224304 kb
Host smart-8ed9f604-55a9-43ab-a6b5-88a9fc1b42de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250880870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4250880870
Directory /workspace/32.spi_device_upload/latest


Test location /workspace/coverage/default/33.spi_device_alert_test.1403869898
Short name T821
Test name
Test status
Simulation time 14226646 ps
CPU time 0.73 seconds
Started Aug 13 05:52:34 PM PDT 24
Finished Aug 13 05:52:35 PM PDT 24
Peak memory 205556 kb
Host smart-330e76ff-d1dd-4aa5-b643-fa759c21108d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403869898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1403869898
Directory /workspace/33.spi_device_alert_test/latest


Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1702207127
Short name T542
Test name
Test status
Simulation time 1280779501 ps
CPU time 14.01 seconds
Started Aug 13 05:52:29 PM PDT 24
Finished Aug 13 05:52:43 PM PDT 24
Peak memory 224688 kb
Host smart-c26b74e4-2059-464a-aa47-f2277941c22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702207127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1702207127
Directory /workspace/33.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/33.spi_device_csb_read.3898374747
Short name T965
Test name
Test status
Simulation time 36784176 ps
CPU time 0.8 seconds
Started Aug 13 05:52:27 PM PDT 24
Finished Aug 13 05:52:28 PM PDT 24
Peak memory 206624 kb
Host smart-45a337f9-aeeb-4969-afd2-f9629192d28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898374747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3898374747
Directory /workspace/33.spi_device_csb_read/latest


Test location /workspace/coverage/default/33.spi_device_flash_all.1772565753
Short name T218
Test name
Test status
Simulation time 947386531701 ps
CPU time 441.37 seconds
Started Aug 13 05:52:30 PM PDT 24
Finished Aug 13 05:59:52 PM PDT 24
Peak memory 249316 kb
Host smart-3aa1c772-c6b4-4fb3-a63d-cfaa7acd30c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772565753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1772565753
Directory /workspace/33.spi_device_flash_all/latest


Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1190666010
Short name T609
Test name
Test status
Simulation time 5827789168 ps
CPU time 71.39 seconds
Started Aug 13 05:52:28 PM PDT 24
Finished Aug 13 05:53:40 PM PDT 24
Peak memory 256824 kb
Host smart-fee30f23-771d-4121-bb38-2970b40f495b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190666010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1190666010
Directory /workspace/33.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2911610890
Short name T139
Test name
Test status
Simulation time 34809884360 ps
CPU time 284.36 seconds
Started Aug 13 05:52:30 PM PDT 24
Finished Aug 13 05:57:15 PM PDT 24
Peak memory 257304 kb
Host smart-6b3e05c8-6188-4481-8c5f-e29985945ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911610890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2911610890
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/33.spi_device_flash_mode.560878260
Short name T422
Test name
Test status
Simulation time 866979640 ps
CPU time 5.96 seconds
Started Aug 13 05:52:32 PM PDT 24
Finished Aug 13 05:52:39 PM PDT 24
Peak memory 224696 kb
Host smart-05a1c43c-420d-43c7-828a-03693115c90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560878260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.560878260
Directory /workspace/33.spi_device_flash_mode/latest


Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3752982662
Short name T722
Test name
Test status
Simulation time 7015904414 ps
CPU time 65.81 seconds
Started Aug 13 05:52:29 PM PDT 24
Finished Aug 13 05:53:35 PM PDT 24
Peak memory 250876 kb
Host smart-f017282e-0c18-4f1d-ae87-efbfc06180f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752982662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3752982662
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/33.spi_device_intercept.1852487803
Short name T238
Test name
Test status
Simulation time 3919118946 ps
CPU time 37.26 seconds
Started Aug 13 05:52:34 PM PDT 24
Finished Aug 13 05:53:11 PM PDT 24
Peak memory 232980 kb
Host smart-08a25614-6846-4ccb-a25e-b192f37e1f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852487803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1852487803
Directory /workspace/33.spi_device_intercept/latest


Test location /workspace/coverage/default/33.spi_device_mailbox.1351307532
Short name T738
Test name
Test status
Simulation time 7441579603 ps
CPU time 35.21 seconds
Started Aug 13 05:52:32 PM PDT 24
Finished Aug 13 05:53:07 PM PDT 24
Peak memory 233000 kb
Host smart-4e39ace0-2b5a-4a7e-aec1-0a83c59ee276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351307532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1351307532
Directory /workspace/33.spi_device_mailbox/latest


Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.587779708
Short name T757
Test name
Test status
Simulation time 29660968 ps
CPU time 2.61 seconds
Started Aug 13 05:52:30 PM PDT 24
Finished Aug 13 05:52:33 PM PDT 24
Peak memory 232436 kb
Host smart-4ea31f1e-3426-4fa1-b474-54975b406554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587779708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.587779708
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4259912335
Short name T931
Test name
Test status
Simulation time 82932487 ps
CPU time 2.89 seconds
Started Aug 13 05:52:28 PM PDT 24
Finished Aug 13 05:52:31 PM PDT 24
Peak memory 232880 kb
Host smart-c9065327-eccb-45c5-8e8c-cc0f5138a6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259912335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4259912335
Directory /workspace/33.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1969730714
Short name T954
Test name
Test status
Simulation time 160229888 ps
CPU time 5.08 seconds
Started Aug 13 05:52:33 PM PDT 24
Finished Aug 13 05:52:39 PM PDT 24
Peak memory 223136 kb
Host smart-915c8fa2-5b39-4680-a8f1-f8f178b1dbba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1969730714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1969730714
Directory /workspace/33.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/33.spi_device_stress_all.1675417784
Short name T466
Test name
Test status
Simulation time 12758191584 ps
CPU time 120.62 seconds
Started Aug 13 05:52:29 PM PDT 24
Finished Aug 13 05:54:29 PM PDT 24
Peak memory 248968 kb
Host smart-4fb44d54-898d-435e-a9df-f595975fb88f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675417784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1675417784
Directory /workspace/33.spi_device_stress_all/latest


Test location /workspace/coverage/default/33.spi_device_tpm_all.2585454073
Short name T762
Test name
Test status
Simulation time 825408990 ps
CPU time 2.84 seconds
Started Aug 13 05:52:29 PM PDT 24
Finished Aug 13 05:52:32 PM PDT 24
Peak memory 216524 kb
Host smart-cc8a7379-4f83-48d2-a42a-1a15b566474f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585454073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2585454073
Directory /workspace/33.spi_device_tpm_all/latest


Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1613712595
Short name T395
Test name
Test status
Simulation time 4968280594 ps
CPU time 7.29 seconds
Started Aug 13 05:52:28 PM PDT 24
Finished Aug 13 05:52:36 PM PDT 24
Peak memory 216572 kb
Host smart-951946df-0147-4c3e-a371-68b36e29ca04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613712595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1613712595
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/33.spi_device_tpm_rw.2406960667
Short name T595
Test name
Test status
Simulation time 494254900 ps
CPU time 7.1 seconds
Started Aug 13 05:52:28 PM PDT 24
Finished Aug 13 05:52:35 PM PDT 24
Peak memory 216452 kb
Host smart-b10ea724-19a0-4d17-9a3f-a7bc0d3dbcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406960667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2406960667
Directory /workspace/33.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3138694203
Short name T364
Test name
Test status
Simulation time 134116193 ps
CPU time 0.77 seconds
Started Aug 13 05:52:27 PM PDT 24
Finished Aug 13 05:52:28 PM PDT 24
Peak memory 206108 kb
Host smart-0ed33c76-0a8e-4a7c-8fdb-09033e358e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138694203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3138694203
Directory /workspace/33.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/33.spi_device_upload.2094129572
Short name T214
Test name
Test status
Simulation time 7434120427 ps
CPU time 5.8 seconds
Started Aug 13 05:52:34 PM PDT 24
Finished Aug 13 05:52:40 PM PDT 24
Peak memory 224740 kb
Host smart-67444208-5ad6-4310-8394-d2ac4da35bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094129572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2094129572
Directory /workspace/33.spi_device_upload/latest


Test location /workspace/coverage/default/34.spi_device_alert_test.1366092830
Short name T385
Test name
Test status
Simulation time 65441879 ps
CPU time 0.7 seconds
Started Aug 13 05:52:39 PM PDT 24
Finished Aug 13 05:52:40 PM PDT 24
Peak memory 205912 kb
Host smart-65e038ff-0d5b-4df4-95fe-fd2fff1ca0cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366092830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1366092830
Directory /workspace/34.spi_device_alert_test/latest


Test location /workspace/coverage/default/34.spi_device_cfg_cmd.257095995
Short name T354
Test name
Test status
Simulation time 120039734 ps
CPU time 3.14 seconds
Started Aug 13 05:52:38 PM PDT 24
Finished Aug 13 05:52:41 PM PDT 24
Peak memory 232860 kb
Host smart-c238792a-e14b-409a-be16-663d4e2ffa96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257095995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.257095995
Directory /workspace/34.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/34.spi_device_csb_read.2910420234
Short name T450
Test name
Test status
Simulation time 18202679 ps
CPU time 0.81 seconds
Started Aug 13 05:52:28 PM PDT 24
Finished Aug 13 05:52:29 PM PDT 24
Peak memory 206620 kb
Host smart-dfcf6858-cd6a-411e-af03-b226ddd7e66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910420234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2910420234
Directory /workspace/34.spi_device_csb_read/latest


Test location /workspace/coverage/default/34.spi_device_flash_all.2075594228
Short name T166
Test name
Test status
Simulation time 2629554863 ps
CPU time 55.53 seconds
Started Aug 13 05:52:40 PM PDT 24
Finished Aug 13 05:53:35 PM PDT 24
Peak memory 256768 kb
Host smart-83b7a630-6fcd-47d7-94ff-5369808dac12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075594228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2075594228
Directory /workspace/34.spi_device_flash_all/latest


Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1056773349
Short name T187
Test name
Test status
Simulation time 10165399860 ps
CPU time 71.58 seconds
Started Aug 13 05:52:38 PM PDT 24
Finished Aug 13 05:53:49 PM PDT 24
Peak memory 257020 kb
Host smart-5288278f-ec76-4bb6-9bfb-f136f872106d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056773349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1056773349
Directory /workspace/34.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3400584553
Short name T570
Test name
Test status
Simulation time 1727713318 ps
CPU time 10.2 seconds
Started Aug 13 05:52:37 PM PDT 24
Finished Aug 13 05:52:48 PM PDT 24
Peak memory 217860 kb
Host smart-6bb1165b-6e56-40e0-a0dc-daa1df43fe64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400584553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3400584553
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/34.spi_device_flash_mode.1315486322
Short name T312
Test name
Test status
Simulation time 274613312 ps
CPU time 8.21 seconds
Started Aug 13 05:52:38 PM PDT 24
Finished Aug 13 05:52:46 PM PDT 24
Peak memory 224724 kb
Host smart-60f808d4-a34b-4b63-a513-6ac60cf1778a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315486322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1315486322
Directory /workspace/34.spi_device_flash_mode/latest


Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3208221830
Short name T15
Test name
Test status
Simulation time 5853876015 ps
CPU time 36.44 seconds
Started Aug 13 05:52:38 PM PDT 24
Finished Aug 13 05:53:15 PM PDT 24
Peak memory 250492 kb
Host smart-f21bffc8-e01a-4a50-85c9-c3a983bcf036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208221830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3208221830
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/34.spi_device_intercept.1674190
Short name T758
Test name
Test status
Simulation time 1413936742 ps
CPU time 5.17 seconds
Started Aug 13 05:52:37 PM PDT 24
Finished Aug 13 05:52:42 PM PDT 24
Peak memory 229448 kb
Host smart-a737a26a-1dd8-46c9-a624-abea1dd56b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1674190
Directory /workspace/34.spi_device_intercept/latest


Test location /workspace/coverage/default/34.spi_device_mailbox.1845080908
Short name T247
Test name
Test status
Simulation time 12303747950 ps
CPU time 50.44 seconds
Started Aug 13 05:52:36 PM PDT 24
Finished Aug 13 05:53:27 PM PDT 24
Peak memory 224700 kb
Host smart-9d64a51a-e735-49dd-adc9-69073badee0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845080908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1845080908
Directory /workspace/34.spi_device_mailbox/latest


Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1556480755
Short name T257
Test name
Test status
Simulation time 30608397712 ps
CPU time 23.58 seconds
Started Aug 13 05:52:36 PM PDT 24
Finished Aug 13 05:53:00 PM PDT 24
Peak memory 239880 kb
Host smart-44b12aff-8a02-4189-8a22-98786602fc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556480755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1556480755
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2184046585
Short name T215
Test name
Test status
Simulation time 727578122 ps
CPU time 6.3 seconds
Started Aug 13 05:52:38 PM PDT 24
Finished Aug 13 05:52:45 PM PDT 24
Peak memory 219124 kb
Host smart-87d33adf-6cea-4838-a73f-7feb27c4ee68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184046585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2184046585
Directory /workspace/34.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1879155084
Short name T394
Test name
Test status
Simulation time 565878997 ps
CPU time 3.74 seconds
Started Aug 13 05:52:37 PM PDT 24
Finished Aug 13 05:52:40 PM PDT 24
Peak memory 218964 kb
Host smart-0408503c-3723-4eec-be9d-6d8d65aac10e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1879155084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1879155084
Directory /workspace/34.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/34.spi_device_stress_all.4101728437
Short name T862
Test name
Test status
Simulation time 109255807 ps
CPU time 1.2 seconds
Started Aug 13 05:52:38 PM PDT 24
Finished Aug 13 05:52:40 PM PDT 24
Peak memory 206848 kb
Host smart-4b43a75e-d5b5-44ed-a473-8dc34d329112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101728437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.4101728437
Directory /workspace/34.spi_device_stress_all/latest


Test location /workspace/coverage/default/34.spi_device_tpm_all.1158915597
Short name T495
Test name
Test status
Simulation time 6273550263 ps
CPU time 42.32 seconds
Started Aug 13 05:52:38 PM PDT 24
Finished Aug 13 05:53:21 PM PDT 24
Peak memory 216536 kb
Host smart-323be7ae-8b88-45f1-9b00-95aff552a5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158915597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1158915597
Directory /workspace/34.spi_device_tpm_all/latest


Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3885637209
Short name T517
Test name
Test status
Simulation time 1327065445 ps
CPU time 7.5 seconds
Started Aug 13 05:52:28 PM PDT 24
Finished Aug 13 05:52:36 PM PDT 24
Peak memory 216484 kb
Host smart-0b53c928-3b1a-4232-8d97-923f056da17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885637209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3885637209
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/34.spi_device_tpm_rw.2467116352
Short name T334
Test name
Test status
Simulation time 91335322 ps
CPU time 1.44 seconds
Started Aug 13 05:52:37 PM PDT 24
Finished Aug 13 05:52:38 PM PDT 24
Peak memory 216532 kb
Host smart-2848cb6c-aac2-4dd5-b9f2-ad44d22e373c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467116352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2467116352
Directory /workspace/34.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2050209249
Short name T653
Test name
Test status
Simulation time 89671784 ps
CPU time 0.94 seconds
Started Aug 13 05:52:38 PM PDT 24
Finished Aug 13 05:52:39 PM PDT 24
Peak memory 206136 kb
Host smart-cf1e6512-aa15-4e06-8759-aa997d15153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050209249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2050209249
Directory /workspace/34.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/34.spi_device_upload.3627954006
Short name T486
Test name
Test status
Simulation time 1027577003 ps
CPU time 5.12 seconds
Started Aug 13 05:52:38 PM PDT 24
Finished Aug 13 05:52:44 PM PDT 24
Peak memory 224640 kb
Host smart-fe668f7e-5b30-48c4-8ad5-4fc34b60a382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627954006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3627954006
Directory /workspace/34.spi_device_upload/latest


Test location /workspace/coverage/default/35.spi_device_alert_test.4023363998
Short name T978
Test name
Test status
Simulation time 24555742 ps
CPU time 0.79 seconds
Started Aug 13 05:52:49 PM PDT 24
Finished Aug 13 05:52:50 PM PDT 24
Peak memory 205004 kb
Host smart-276081bd-3637-415a-abab-0318a7d7c590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023363998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4023363998
Directory /workspace/35.spi_device_alert_test/latest


Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1716963239
Short name T963
Test name
Test status
Simulation time 1389684427 ps
CPU time 12.25 seconds
Started Aug 13 05:52:47 PM PDT 24
Finished Aug 13 05:53:00 PM PDT 24
Peak memory 224652 kb
Host smart-a258bcd1-91a2-4b34-8b12-c8ce5933ecaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716963239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1716963239
Directory /workspace/35.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/35.spi_device_csb_read.3505989687
Short name T392
Test name
Test status
Simulation time 46822451 ps
CPU time 0.81 seconds
Started Aug 13 05:52:38 PM PDT 24
Finished Aug 13 05:52:39 PM PDT 24
Peak memory 206536 kb
Host smart-73c93ff2-0d18-4ad8-a773-6568ca7166de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505989687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3505989687
Directory /workspace/35.spi_device_csb_read/latest


Test location /workspace/coverage/default/35.spi_device_flash_all.801309831
Short name T844
Test name
Test status
Simulation time 1672479355 ps
CPU time 40.4 seconds
Started Aug 13 05:52:49 PM PDT 24
Finished Aug 13 05:53:29 PM PDT 24
Peak memory 255060 kb
Host smart-053f15ec-db59-4be1-814e-b79bacc54729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801309831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.801309831
Directory /workspace/35.spi_device_flash_all/latest


Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3583087449
Short name T839
Test name
Test status
Simulation time 75648436251 ps
CPU time 361.19 seconds
Started Aug 13 05:52:49 PM PDT 24
Finished Aug 13 05:58:50 PM PDT 24
Peak memory 261144 kb
Host smart-5af10126-1cf3-491f-adcc-92e1db228490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583087449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3583087449
Directory /workspace/35.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3940990470
Short name T806
Test name
Test status
Simulation time 4701393221 ps
CPU time 32.74 seconds
Started Aug 13 05:52:51 PM PDT 24
Finished Aug 13 05:53:24 PM PDT 24
Peak memory 250476 kb
Host smart-22def3c8-a93c-4c74-b119-836e1ddb0808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940990470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3940990470
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/35.spi_device_flash_mode.1730488237
Short name T910
Test name
Test status
Simulation time 2158865172 ps
CPU time 10.38 seconds
Started Aug 13 05:52:48 PM PDT 24
Finished Aug 13 05:52:58 PM PDT 24
Peak memory 234756 kb
Host smart-29c281bb-2842-484b-be38-91dfe5b8c7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730488237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1730488237
Directory /workspace/35.spi_device_flash_mode/latest


Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.912350016
Short name T167
Test name
Test status
Simulation time 3851853015 ps
CPU time 53.23 seconds
Started Aug 13 05:52:49 PM PDT 24
Finished Aug 13 05:53:42 PM PDT 24
Peak memory 255224 kb
Host smart-5e548ba0-e590-4ba0-88d1-c0005eb9157a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912350016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.912350016
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/35.spi_device_intercept.2348762002
Short name T250
Test name
Test status
Simulation time 1193290385 ps
CPU time 4.1 seconds
Started Aug 13 05:52:48 PM PDT 24
Finished Aug 13 05:52:52 PM PDT 24
Peak memory 232884 kb
Host smart-e70f65ae-14c8-4be7-a366-687aa9a6108b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348762002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2348762002
Directory /workspace/35.spi_device_intercept/latest


Test location /workspace/coverage/default/35.spi_device_mailbox.1113902623
Short name T65
Test name
Test status
Simulation time 102642472 ps
CPU time 2.86 seconds
Started Aug 13 05:52:50 PM PDT 24
Finished Aug 13 05:52:53 PM PDT 24
Peak memory 232860 kb
Host smart-e0946163-9378-4c51-8279-f6822eb0c7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113902623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1113902623
Directory /workspace/35.spi_device_mailbox/latest


Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.4090014937
Short name T348
Test name
Test status
Simulation time 101798237 ps
CPU time 2.75 seconds
Started Aug 13 05:52:48 PM PDT 24
Finished Aug 13 05:52:51 PM PDT 24
Peak memory 232444 kb
Host smart-b5355ebf-de82-480d-a3d5-bfe1fb444bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090014937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.4090014937
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2708726378
Short name T563
Test name
Test status
Simulation time 11767903593 ps
CPU time 14.55 seconds
Started Aug 13 05:52:47 PM PDT 24
Finished Aug 13 05:53:02 PM PDT 24
Peak memory 248872 kb
Host smart-353d320c-0973-4a1d-bd89-30b3d9661456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708726378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2708726378
Directory /workspace/35.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3122983669
Short name T820
Test name
Test status
Simulation time 1634579515 ps
CPU time 9.81 seconds
Started Aug 13 05:52:49 PM PDT 24
Finished Aug 13 05:52:59 PM PDT 24
Peak memory 219112 kb
Host smart-c82cc0a8-dbee-492b-90d6-6be4eb2e07a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3122983669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3122983669
Directory /workspace/35.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/35.spi_device_stress_all.3017500078
Short name T143
Test name
Test status
Simulation time 118893040401 ps
CPU time 307.54 seconds
Started Aug 13 05:52:48 PM PDT 24
Finished Aug 13 05:57:56 PM PDT 24
Peak memory 265260 kb
Host smart-b8e5cd39-ff9b-4b2b-9494-2eff30c8a277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017500078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3017500078
Directory /workspace/35.spi_device_stress_all/latest


Test location /workspace/coverage/default/35.spi_device_tpm_all.3933170850
Short name T79
Test name
Test status
Simulation time 9856731990 ps
CPU time 22.14 seconds
Started Aug 13 05:52:38 PM PDT 24
Finished Aug 13 05:53:00 PM PDT 24
Peak memory 220876 kb
Host smart-47d2b696-b59f-4252-8e70-06db6e1b7232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933170850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3933170850
Directory /workspace/35.spi_device_tpm_all/latest


Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1674663603
Short name T794
Test name
Test status
Simulation time 51049155956 ps
CPU time 15.05 seconds
Started Aug 13 05:52:39 PM PDT 24
Finished Aug 13 05:52:54 PM PDT 24
Peak memory 216484 kb
Host smart-16a0eca4-7226-4d29-9ff3-3f9cc0904264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674663603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1674663603
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/35.spi_device_tpm_rw.791702778
Short name T670
Test name
Test status
Simulation time 99458547 ps
CPU time 1.49 seconds
Started Aug 13 05:52:38 PM PDT 24
Finished Aug 13 05:52:39 PM PDT 24
Peak memory 216460 kb
Host smart-bbdea4c4-f7c8-469a-8e97-5abe7751a189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791702778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.791702778
Directory /workspace/35.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2552499921
Short name T592
Test name
Test status
Simulation time 62755428 ps
CPU time 0.78 seconds
Started Aug 13 05:52:39 PM PDT 24
Finished Aug 13 05:52:40 PM PDT 24
Peak memory 206148 kb
Host smart-20caa56c-fb8d-45f8-90e0-8fa5f158bb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552499921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2552499921
Directory /workspace/35.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/35.spi_device_upload.1357921441
Short name T464
Test name
Test status
Simulation time 82168851 ps
CPU time 2.55 seconds
Started Aug 13 05:52:48 PM PDT 24
Finished Aug 13 05:52:50 PM PDT 24
Peak memory 224340 kb
Host smart-8f8b0ba0-cef8-492b-a909-da876f4c8bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357921441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1357921441
Directory /workspace/35.spi_device_upload/latest


Test location /workspace/coverage/default/36.spi_device_alert_test.3469087613
Short name T399
Test name
Test status
Simulation time 17163536 ps
CPU time 0.71 seconds
Started Aug 13 05:52:50 PM PDT 24
Finished Aug 13 05:52:51 PM PDT 24
Peak memory 205516 kb
Host smart-f6d1326b-d7f8-41c6-8bd0-e045b9fe9f03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469087613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3469087613
Directory /workspace/36.spi_device_alert_test/latest


Test location /workspace/coverage/default/36.spi_device_cfg_cmd.215894338
Short name T446
Test name
Test status
Simulation time 469672831 ps
CPU time 3.24 seconds
Started Aug 13 05:52:51 PM PDT 24
Finished Aug 13 05:52:54 PM PDT 24
Peak memory 224656 kb
Host smart-ae595a1f-5048-4925-afdd-eefda4b1c8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215894338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.215894338
Directory /workspace/36.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/36.spi_device_csb_read.3770084360
Short name T841
Test name
Test status
Simulation time 34690349 ps
CPU time 0.78 seconds
Started Aug 13 05:52:49 PM PDT 24
Finished Aug 13 05:52:50 PM PDT 24
Peak memory 206940 kb
Host smart-e0bf91fd-d2d6-4bc1-bff1-0b697d434d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770084360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3770084360
Directory /workspace/36.spi_device_csb_read/latest


Test location /workspace/coverage/default/36.spi_device_flash_all.1862964015
Short name T544
Test name
Test status
Simulation time 64194082 ps
CPU time 0.78 seconds
Started Aug 13 05:52:51 PM PDT 24
Finished Aug 13 05:52:52 PM PDT 24
Peak memory 215852 kb
Host smart-8c04f376-1817-472d-b2b3-ab0496edb1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862964015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1862964015
Directory /workspace/36.spi_device_flash_all/latest


Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.848826368
Short name T328
Test name
Test status
Simulation time 2156017797 ps
CPU time 32.69 seconds
Started Aug 13 05:52:53 PM PDT 24
Finished Aug 13 05:53:25 PM PDT 24
Peak memory 249416 kb
Host smart-7e6f9950-e271-41b5-9230-e5e7b19b82ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848826368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.848826368
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/36.spi_device_flash_mode.3196000548
Short name T647
Test name
Test status
Simulation time 253295762 ps
CPU time 7.41 seconds
Started Aug 13 05:52:50 PM PDT 24
Finished Aug 13 05:52:57 PM PDT 24
Peak memory 236040 kb
Host smart-96c6fc1c-116a-4f04-a9ef-20370c53d250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196000548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3196000548
Directory /workspace/36.spi_device_flash_mode/latest


Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2811584077
Short name T201
Test name
Test status
Simulation time 10088833153 ps
CPU time 117.77 seconds
Started Aug 13 05:52:50 PM PDT 24
Finished Aug 13 05:54:48 PM PDT 24
Peak memory 251680 kb
Host smart-ad5ff668-7dca-480a-b4cf-dfe98b92e6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811584077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2811584077
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/36.spi_device_intercept.783542074
Short name T909
Test name
Test status
Simulation time 2505546319 ps
CPU time 25.6 seconds
Started Aug 13 05:52:49 PM PDT 24
Finished Aug 13 05:53:15 PM PDT 24
Peak memory 232984 kb
Host smart-92447d39-1904-4ee6-b6f0-046b4a9088cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783542074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.783542074
Directory /workspace/36.spi_device_intercept/latest


Test location /workspace/coverage/default/36.spi_device_mailbox.3827344100
Short name T480
Test name
Test status
Simulation time 531103390 ps
CPU time 11.07 seconds
Started Aug 13 05:52:50 PM PDT 24
Finished Aug 13 05:53:01 PM PDT 24
Peak memory 224584 kb
Host smart-3cfde17d-2b89-4973-b29c-4d5248180107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827344100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3827344100
Directory /workspace/36.spi_device_mailbox/latest


Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1124159347
Short name T648
Test name
Test status
Simulation time 1028355152 ps
CPU time 5.99 seconds
Started Aug 13 05:52:49 PM PDT 24
Finished Aug 13 05:52:55 PM PDT 24
Peak memory 232916 kb
Host smart-e774aafd-9f9d-49d4-b417-fad93f8fa571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124159347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1124159347
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2518449222
Short name T504
Test name
Test status
Simulation time 6808992787 ps
CPU time 11.36 seconds
Started Aug 13 05:52:50 PM PDT 24
Finished Aug 13 05:53:02 PM PDT 24
Peak memory 232900 kb
Host smart-bce1b3c7-286c-44ba-ace7-7b5e7ef5ce15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518449222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2518449222
Directory /workspace/36.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1921925348
Short name T853
Test name
Test status
Simulation time 77419869 ps
CPU time 3.66 seconds
Started Aug 13 05:52:51 PM PDT 24
Finished Aug 13 05:52:55 PM PDT 24
Peak memory 223052 kb
Host smart-438ceab0-35ad-42c3-b824-e5a6b0797606
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1921925348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1921925348
Directory /workspace/36.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/36.spi_device_stress_all.3527338438
Short name T144
Test name
Test status
Simulation time 31063392692 ps
CPU time 107.69 seconds
Started Aug 13 05:52:50 PM PDT 24
Finished Aug 13 05:54:38 PM PDT 24
Peak memory 249904 kb
Host smart-dce78ffd-07b7-4b33-9118-b6ef80a4ce54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527338438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3527338438
Directory /workspace/36.spi_device_stress_all/latest


Test location /workspace/coverage/default/36.spi_device_tpm_all.2328375511
Short name T57
Test name
Test status
Simulation time 24195469112 ps
CPU time 31.59 seconds
Started Aug 13 05:52:51 PM PDT 24
Finished Aug 13 05:53:22 PM PDT 24
Peak memory 216552 kb
Host smart-3d489e19-accd-4362-bea8-048cbaed878f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328375511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2328375511
Directory /workspace/36.spi_device_tpm_all/latest


Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1863993177
Short name T62
Test name
Test status
Simulation time 5325451576 ps
CPU time 6.96 seconds
Started Aug 13 05:52:47 PM PDT 24
Finished Aug 13 05:52:54 PM PDT 24
Peak memory 216600 kb
Host smart-600ef065-ffcd-405d-9c22-1faf194cb973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863993177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1863993177
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/36.spi_device_tpm_rw.2753638252
Short name T849
Test name
Test status
Simulation time 90878353 ps
CPU time 2.2 seconds
Started Aug 13 05:52:51 PM PDT 24
Finished Aug 13 05:52:53 PM PDT 24
Peak memory 216532 kb
Host smart-f0c28780-b8e2-4f89-9019-bea45b75f20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753638252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2753638252
Directory /workspace/36.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1191928771
Short name T872
Test name
Test status
Simulation time 44951032 ps
CPU time 0.79 seconds
Started Aug 13 05:52:49 PM PDT 24
Finished Aug 13 05:52:50 PM PDT 24
Peak memory 206132 kb
Host smart-af7ef952-d9bd-4803-bceb-c6fd34dbfced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191928771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1191928771
Directory /workspace/36.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/36.spi_device_upload.2843288422
Short name T1005
Test name
Test status
Simulation time 134126514 ps
CPU time 2.63 seconds
Started Aug 13 05:52:51 PM PDT 24
Finished Aug 13 05:52:54 PM PDT 24
Peak memory 224656 kb
Host smart-fa74abfc-239a-4697-a18d-3117e9873e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843288422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2843288422
Directory /workspace/36.spi_device_upload/latest


Test location /workspace/coverage/default/37.spi_device_alert_test.4153078194
Short name T483
Test name
Test status
Simulation time 64240296 ps
CPU time 0.72 seconds
Started Aug 13 05:52:58 PM PDT 24
Finished Aug 13 05:52:59 PM PDT 24
Peak memory 205368 kb
Host smart-c1f0033a-97d8-46d9-ba4e-533f7917491f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153078194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
4153078194
Directory /workspace/37.spi_device_alert_test/latest


Test location /workspace/coverage/default/37.spi_device_cfg_cmd.66206297
Short name T889
Test name
Test status
Simulation time 697410289 ps
CPU time 4.25 seconds
Started Aug 13 05:52:56 PM PDT 24
Finished Aug 13 05:53:01 PM PDT 24
Peak memory 224700 kb
Host smart-4b7ffd3c-8c81-4b11-92f2-39b1d31b8afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66206297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.66206297
Directory /workspace/37.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/37.spi_device_csb_read.2438459895
Short name T950
Test name
Test status
Simulation time 84009610 ps
CPU time 0.82 seconds
Started Aug 13 05:52:53 PM PDT 24
Finished Aug 13 05:52:54 PM PDT 24
Peak memory 206608 kb
Host smart-ccb288db-7bf3-49eb-8a44-ffa8c94c2fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438459895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2438459895
Directory /workspace/37.spi_device_csb_read/latest


Test location /workspace/coverage/default/37.spi_device_flash_all.650264107
Short name T590
Test name
Test status
Simulation time 111087498 ps
CPU time 0.95 seconds
Started Aug 13 05:52:57 PM PDT 24
Finished Aug 13 05:52:58 PM PDT 24
Peak memory 216100 kb
Host smart-71ac6f24-0cdb-4f42-87c4-59bd9bb8a912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650264107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.650264107
Directory /workspace/37.spi_device_flash_all/latest


Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3656495019
Short name T1025
Test name
Test status
Simulation time 4127309490 ps
CPU time 53.07 seconds
Started Aug 13 05:52:57 PM PDT 24
Finished Aug 13 05:53:51 PM PDT 24
Peak memory 250100 kb
Host smart-1b9c6b72-70a2-433d-98b3-3d619ffcac32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656495019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3656495019
Directory /workspace/37.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2265373653
Short name T202
Test name
Test status
Simulation time 21841310563 ps
CPU time 64.05 seconds
Started Aug 13 05:52:56 PM PDT 24
Finished Aug 13 05:54:00 PM PDT 24
Peak memory 253268 kb
Host smart-ae24b7cf-663a-480a-97c1-75575859d687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265373653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2265373653
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/37.spi_device_flash_mode.4171194570
Short name T316
Test name
Test status
Simulation time 123871727 ps
CPU time 6.29 seconds
Started Aug 13 05:52:56 PM PDT 24
Finished Aug 13 05:53:02 PM PDT 24
Peak memory 224724 kb
Host smart-232f6274-cedb-465f-8064-3c8680526cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171194570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.4171194570
Directory /workspace/37.spi_device_flash_mode/latest


Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3530125181
Short name T297
Test name
Test status
Simulation time 6082165555 ps
CPU time 72.75 seconds
Started Aug 13 05:52:56 PM PDT 24
Finished Aug 13 05:54:09 PM PDT 24
Peak memory 251844 kb
Host smart-08fd7c97-b79d-4871-b445-72544e4883c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530125181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3530125181
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/37.spi_device_intercept.3221444698
Short name T591
Test name
Test status
Simulation time 270863731 ps
CPU time 3.74 seconds
Started Aug 13 05:52:57 PM PDT 24
Finished Aug 13 05:53:00 PM PDT 24
Peak memory 232912 kb
Host smart-f6b0b692-4430-425d-b809-d9aac5fb58e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221444698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3221444698
Directory /workspace/37.spi_device_intercept/latest


Test location /workspace/coverage/default/37.spi_device_mailbox.2096582473
Short name T94
Test name
Test status
Simulation time 563878114 ps
CPU time 6.56 seconds
Started Aug 13 05:52:55 PM PDT 24
Finished Aug 13 05:53:02 PM PDT 24
Peak memory 232912 kb
Host smart-080e00f8-353d-43bf-bf35-44b1f77a89a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096582473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2096582473
Directory /workspace/37.spi_device_mailbox/latest


Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2330054142
Short name T255
Test name
Test status
Simulation time 324083726 ps
CPU time 2.87 seconds
Started Aug 13 05:52:56 PM PDT 24
Finished Aug 13 05:52:59 PM PDT 24
Peak memory 232912 kb
Host smart-76094932-10c8-40b4-8c5d-cb429657a6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330054142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2330054142
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1603712881
Short name T533
Test name
Test status
Simulation time 77454620 ps
CPU time 2.55 seconds
Started Aug 13 05:52:54 PM PDT 24
Finished Aug 13 05:52:57 PM PDT 24
Peak memory 232796 kb
Host smart-035343e2-c28d-449c-b88f-a64389abc700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603712881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1603712881
Directory /workspace/37.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3315582938
Short name T808
Test name
Test status
Simulation time 3527811407 ps
CPU time 11.56 seconds
Started Aug 13 05:52:56 PM PDT 24
Finished Aug 13 05:53:08 PM PDT 24
Peak memory 222268 kb
Host smart-1501a9ea-3e52-4a7e-bbd8-5d23832972fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3315582938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3315582938
Directory /workspace/37.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/37.spi_device_stress_all.3154682686
Short name T852
Test name
Test status
Simulation time 252202961685 ps
CPU time 562.38 seconds
Started Aug 13 05:52:57 PM PDT 24
Finished Aug 13 06:02:19 PM PDT 24
Peak memory 265584 kb
Host smart-6e94a17e-b94e-478e-8963-fc49453dd2d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154682686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3154682686
Directory /workspace/37.spi_device_stress_all/latest


Test location /workspace/coverage/default/37.spi_device_tpm_all.3401364757
Short name T60
Test name
Test status
Simulation time 3166168539 ps
CPU time 6.06 seconds
Started Aug 13 05:52:57 PM PDT 24
Finished Aug 13 05:53:03 PM PDT 24
Peak memory 216572 kb
Host smart-61011015-3faa-4383-83c1-7d051e2fb1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401364757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3401364757
Directory /workspace/37.spi_device_tpm_all/latest


Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1502209440
Short name T779
Test name
Test status
Simulation time 2584338310 ps
CPU time 4.98 seconds
Started Aug 13 05:52:53 PM PDT 24
Finished Aug 13 05:52:58 PM PDT 24
Peak memory 216524 kb
Host smart-e9f497f3-7842-45f9-87ed-9bac144347bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502209440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1502209440
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/37.spi_device_tpm_rw.91243062
Short name T359
Test name
Test status
Simulation time 614468314 ps
CPU time 4.16 seconds
Started Aug 13 05:52:55 PM PDT 24
Finished Aug 13 05:53:00 PM PDT 24
Peak memory 216468 kb
Host smart-672d07ff-6f58-410e-b3bf-38402d9fde47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91243062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.91243062
Directory /workspace/37.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.727985699
Short name T438
Test name
Test status
Simulation time 78376813 ps
CPU time 0.93 seconds
Started Aug 13 05:52:55 PM PDT 24
Finished Aug 13 05:52:56 PM PDT 24
Peak memory 206132 kb
Host smart-7e0f19cf-9b20-44e4-8669-acd3413253ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727985699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.727985699
Directory /workspace/37.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/37.spi_device_upload.3727416788
Short name T840
Test name
Test status
Simulation time 3349854242 ps
CPU time 9.49 seconds
Started Aug 13 05:52:52 PM PDT 24
Finished Aug 13 05:53:02 PM PDT 24
Peak memory 249340 kb
Host smart-2503e310-45d1-49cb-97bd-b1fdb5b2fa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727416788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3727416788
Directory /workspace/37.spi_device_upload/latest


Test location /workspace/coverage/default/38.spi_device_alert_test.1050913100
Short name T69
Test name
Test status
Simulation time 15589094 ps
CPU time 0.72 seconds
Started Aug 13 05:53:06 PM PDT 24
Finished Aug 13 05:53:06 PM PDT 24
Peak memory 205568 kb
Host smart-f7f344d5-53ce-42c2-af88-b04dfc1ab40d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050913100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1050913100
Directory /workspace/38.spi_device_alert_test/latest


Test location /workspace/coverage/default/38.spi_device_cfg_cmd.33942321
Short name T243
Test name
Test status
Simulation time 75782210 ps
CPU time 2.49 seconds
Started Aug 13 05:53:02 PM PDT 24
Finished Aug 13 05:53:05 PM PDT 24
Peak memory 232860 kb
Host smart-c147182e-80bd-40bb-8d0b-3c5eb3837de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33942321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.33942321
Directory /workspace/38.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/38.spi_device_csb_read.2316215834
Short name T339
Test name
Test status
Simulation time 14610717 ps
CPU time 0.77 seconds
Started Aug 13 05:52:58 PM PDT 24
Finished Aug 13 05:52:59 PM PDT 24
Peak memory 206248 kb
Host smart-1e7cf2df-e6f9-427e-a210-401448d31022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316215834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2316215834
Directory /workspace/38.spi_device_csb_read/latest


Test location /workspace/coverage/default/38.spi_device_flash_all.3112741441
Short name T67
Test name
Test status
Simulation time 969941977 ps
CPU time 16.03 seconds
Started Aug 13 05:52:59 PM PDT 24
Finished Aug 13 05:53:15 PM PDT 24
Peak memory 232888 kb
Host smart-b26a4749-27cb-4633-b798-fc5e808d4659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112741441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3112741441
Directory /workspace/38.spi_device_flash_all/latest


Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.917637918
Short name T948
Test name
Test status
Simulation time 67134000708 ps
CPU time 108.21 seconds
Started Aug 13 05:52:59 PM PDT 24
Finished Aug 13 05:54:48 PM PDT 24
Peak memory 257024 kb
Host smart-bf9d300d-ed9c-4759-968e-1d290891c5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917637918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.917637918
Directory /workspace/38.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2682153403
Short name T914
Test name
Test status
Simulation time 5171009283 ps
CPU time 46 seconds
Started Aug 13 05:53:01 PM PDT 24
Finished Aug 13 05:53:47 PM PDT 24
Peak memory 249312 kb
Host smart-47cce4d4-a75c-45a4-9725-f004056af4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682153403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2682153403
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/38.spi_device_flash_mode.1492208061
Short name T525
Test name
Test status
Simulation time 391543226 ps
CPU time 4.59 seconds
Started Aug 13 05:52:58 PM PDT 24
Finished Aug 13 05:53:03 PM PDT 24
Peak memory 235928 kb
Host smart-7196694b-dd86-4aa1-8b1d-261e6b4bf470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492208061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1492208061
Directory /workspace/38.spi_device_flash_mode/latest


Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1985562552
Short name T305
Test name
Test status
Simulation time 12319630855 ps
CPU time 96.86 seconds
Started Aug 13 05:53:02 PM PDT 24
Finished Aug 13 05:54:39 PM PDT 24
Peak memory 251916 kb
Host smart-af898f77-adf5-4a75-be01-a3d4fba3cee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985562552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1985562552
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/38.spi_device_intercept.2566334796
Short name T951
Test name
Test status
Simulation time 270315516 ps
CPU time 4.72 seconds
Started Aug 13 05:53:00 PM PDT 24
Finished Aug 13 05:53:04 PM PDT 24
Peak memory 232856 kb
Host smart-e528ab1a-60e6-47f3-9382-a56c79bd7ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566334796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2566334796
Directory /workspace/38.spi_device_intercept/latest


Test location /workspace/coverage/default/38.spi_device_mailbox.2530504454
Short name T601
Test name
Test status
Simulation time 38305809 ps
CPU time 2.8 seconds
Started Aug 13 05:53:02 PM PDT 24
Finished Aug 13 05:53:05 PM PDT 24
Peak memory 232876 kb
Host smart-8f5e9133-d903-4579-b98f-5d372792eafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530504454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2530504454
Directory /workspace/38.spi_device_mailbox/latest


Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2114095906
Short name T197
Test name
Test status
Simulation time 296036662 ps
CPU time 5.54 seconds
Started Aug 13 05:52:54 PM PDT 24
Finished Aug 13 05:53:00 PM PDT 24
Peak memory 232860 kb
Host smart-72551835-f90f-41a1-85a5-07f007e79a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114095906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2114095906
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2562489437
Short name T602
Test name
Test status
Simulation time 300480191 ps
CPU time 3.6 seconds
Started Aug 13 05:52:59 PM PDT 24
Finished Aug 13 05:53:03 PM PDT 24
Peak memory 232912 kb
Host smart-268ac038-5c9c-48e4-971e-974411e49a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562489437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2562489437
Directory /workspace/38.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3348546688
Short name T937
Test name
Test status
Simulation time 2536889663 ps
CPU time 8.35 seconds
Started Aug 13 05:52:59 PM PDT 24
Finished Aug 13 05:53:08 PM PDT 24
Peak memory 220868 kb
Host smart-46c89286-0ff3-4243-83ed-b8b1668f21e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3348546688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3348546688
Directory /workspace/38.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/38.spi_device_stress_all.1924292825
Short name T162
Test name
Test status
Simulation time 7497232556 ps
CPU time 152.15 seconds
Started Aug 13 05:53:05 PM PDT 24
Finished Aug 13 05:55:37 PM PDT 24
Peak memory 273888 kb
Host smart-91291456-d3f5-4428-b077-bfe46dbf38ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924292825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1924292825
Directory /workspace/38.spi_device_stress_all/latest


Test location /workspace/coverage/default/38.spi_device_tpm_all.3875957093
Short name T665
Test name
Test status
Simulation time 10422961928 ps
CPU time 38.67 seconds
Started Aug 13 05:52:59 PM PDT 24
Finished Aug 13 05:53:38 PM PDT 24
Peak memory 220192 kb
Host smart-268e9de0-9534-411b-a146-c527cbe42698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875957093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3875957093
Directory /workspace/38.spi_device_tpm_all/latest


Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3147023515
Short name T760
Test name
Test status
Simulation time 6200824235 ps
CPU time 4.03 seconds
Started Aug 13 05:52:55 PM PDT 24
Finished Aug 13 05:52:59 PM PDT 24
Peak memory 216400 kb
Host smart-a2da747e-b44a-486b-b73a-924d2252df35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147023515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3147023515
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/38.spi_device_tpm_rw.4067680615
Short name T458
Test name
Test status
Simulation time 27818570 ps
CPU time 1.07 seconds
Started Aug 13 05:53:00 PM PDT 24
Finished Aug 13 05:53:01 PM PDT 24
Peak memory 207420 kb
Host smart-674597f0-b7da-4073-b5a3-3a06a5593728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067680615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4067680615
Directory /workspace/38.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3128781556
Short name T846
Test name
Test status
Simulation time 70246748 ps
CPU time 0.85 seconds
Started Aug 13 05:52:56 PM PDT 24
Finished Aug 13 05:52:57 PM PDT 24
Peak memory 206164 kb
Host smart-4193ccc1-a986-4ce3-89ab-ca370fcb519b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128781556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3128781556
Directory /workspace/38.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/38.spi_device_upload.2936279241
Short name T502
Test name
Test status
Simulation time 897048183 ps
CPU time 9.09 seconds
Started Aug 13 05:53:03 PM PDT 24
Finished Aug 13 05:53:12 PM PDT 24
Peak memory 240880 kb
Host smart-5278b1ce-bc13-461f-8d6a-02d1854ce0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936279241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2936279241
Directory /workspace/38.spi_device_upload/latest


Test location /workspace/coverage/default/39.spi_device_alert_test.1522261965
Short name T352
Test name
Test status
Simulation time 145730899 ps
CPU time 0.71 seconds
Started Aug 13 05:53:05 PM PDT 24
Finished Aug 13 05:53:06 PM PDT 24
Peak memory 205528 kb
Host smart-42ae96d1-670a-4c5c-9a1a-9faea669b2e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522261965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1522261965
Directory /workspace/39.spi_device_alert_test/latest


Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1907206580
Short name T578
Test name
Test status
Simulation time 1450653811 ps
CPU time 10.81 seconds
Started Aug 13 05:53:05 PM PDT 24
Finished Aug 13 05:53:16 PM PDT 24
Peak memory 232820 kb
Host smart-d68707d9-fc0f-4834-99d1-10aa27bdedb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907206580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1907206580
Directory /workspace/39.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/39.spi_device_csb_read.704715218
Short name T614
Test name
Test status
Simulation time 12402385 ps
CPU time 0.76 seconds
Started Aug 13 05:53:06 PM PDT 24
Finished Aug 13 05:53:07 PM PDT 24
Peak memory 205904 kb
Host smart-a1a42b7d-3d0b-4666-9e2c-6c2e8289efa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704715218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.704715218
Directory /workspace/39.spi_device_csb_read/latest


Test location /workspace/coverage/default/39.spi_device_flash_all.2712514601
Short name T66
Test name
Test status
Simulation time 209583362651 ps
CPU time 185.12 seconds
Started Aug 13 05:53:07 PM PDT 24
Finished Aug 13 05:56:13 PM PDT 24
Peak memory 255696 kb
Host smart-05b8bf85-d33d-4894-80ec-e13f91533bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712514601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2712514601
Directory /workspace/39.spi_device_flash_all/latest


Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.861635749
Short name T733
Test name
Test status
Simulation time 71664008416 ps
CPU time 620.15 seconds
Started Aug 13 05:53:04 PM PDT 24
Finished Aug 13 06:03:24 PM PDT 24
Peak memory 255648 kb
Host smart-752326e3-d901-4d47-bae1-458796c647a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861635749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.861635749
Directory /workspace/39.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3375578725
Short name T708
Test name
Test status
Simulation time 4379987779 ps
CPU time 96.49 seconds
Started Aug 13 05:53:05 PM PDT 24
Finished Aug 13 05:54:42 PM PDT 24
Peak memory 257316 kb
Host smart-deae71b1-28b7-43f9-aa9e-75181f931bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375578725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3375578725
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/39.spi_device_flash_mode.1837941243
Short name T1017
Test name
Test status
Simulation time 497368901 ps
CPU time 10.96 seconds
Started Aug 13 05:53:04 PM PDT 24
Finished Aug 13 05:53:15 PM PDT 24
Peak memory 224692 kb
Host smart-e59ed9ca-7053-47f8-ac5d-97d01fdc7d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837941243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1837941243
Directory /workspace/39.spi_device_flash_mode/latest


Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3045947912
Short name T685
Test name
Test status
Simulation time 15309762 ps
CPU time 0.74 seconds
Started Aug 13 05:53:06 PM PDT 24
Finished Aug 13 05:53:07 PM PDT 24
Peak memory 215896 kb
Host smart-4fba5484-30dd-40d9-b0d8-d787005d3548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045947912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3045947912
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/39.spi_device_intercept.659185126
Short name T803
Test name
Test status
Simulation time 1955519349 ps
CPU time 17.99 seconds
Started Aug 13 05:53:05 PM PDT 24
Finished Aug 13 05:53:23 PM PDT 24
Peak memory 224696 kb
Host smart-08f50dc8-4da8-4c70-88b9-5e362e1b102e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659185126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.659185126
Directory /workspace/39.spi_device_intercept/latest


Test location /workspace/coverage/default/39.spi_device_mailbox.182098208
Short name T888
Test name
Test status
Simulation time 3115033096 ps
CPU time 24.76 seconds
Started Aug 13 05:53:08 PM PDT 24
Finished Aug 13 05:53:33 PM PDT 24
Peak memory 228264 kb
Host smart-bed9af7d-c915-4962-a7fb-64d153c5c3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182098208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.182098208
Directory /workspace/39.spi_device_mailbox/latest


Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3367185994
Short name T269
Test name
Test status
Simulation time 2638870721 ps
CPU time 7.49 seconds
Started Aug 13 05:53:06 PM PDT 24
Finished Aug 13 05:53:14 PM PDT 24
Peak memory 224656 kb
Host smart-5dfe2190-f59d-452b-84ee-5e0327c7b86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367185994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3367185994
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2308394215
Short name T679
Test name
Test status
Simulation time 810592899 ps
CPU time 8.16 seconds
Started Aug 13 05:53:05 PM PDT 24
Finished Aug 13 05:53:13 PM PDT 24
Peak memory 224564 kb
Host smart-f815abf0-853e-4549-a0be-658914c37d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308394215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2308394215
Directory /workspace/39.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1312535834
Short name T817
Test name
Test status
Simulation time 950935535 ps
CPU time 11.55 seconds
Started Aug 13 05:53:06 PM PDT 24
Finished Aug 13 05:53:18 PM PDT 24
Peak memory 219328 kb
Host smart-4c04346c-dc81-4f1a-a5c0-2f1803b65a41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1312535834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1312535834
Directory /workspace/39.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/39.spi_device_tpm_all.4077563158
Short name T923
Test name
Test status
Simulation time 15362992405 ps
CPU time 39.85 seconds
Started Aug 13 05:53:04 PM PDT 24
Finished Aug 13 05:53:44 PM PDT 24
Peak memory 216552 kb
Host smart-3cb84e82-5903-4715-8d70-b05f23851a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077563158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4077563158
Directory /workspace/39.spi_device_tpm_all/latest


Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3352839279
Short name T771
Test name
Test status
Simulation time 211614127 ps
CPU time 1.9 seconds
Started Aug 13 05:53:06 PM PDT 24
Finished Aug 13 05:53:08 PM PDT 24
Peak memory 216296 kb
Host smart-8c747fd1-d4d3-44a4-94b1-2e7ffda15e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352839279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3352839279
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/39.spi_device_tpm_rw.1483550080
Short name T377
Test name
Test status
Simulation time 111249679 ps
CPU time 3.3 seconds
Started Aug 13 05:53:06 PM PDT 24
Finished Aug 13 05:53:09 PM PDT 24
Peak memory 216436 kb
Host smart-5dfcdd9e-574b-41cb-9e59-106ffc16c560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483550080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1483550080
Directory /workspace/39.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1490121067
Short name T916
Test name
Test status
Simulation time 226005262 ps
CPU time 0.91 seconds
Started Aug 13 05:53:04 PM PDT 24
Finished Aug 13 05:53:05 PM PDT 24
Peak memory 206100 kb
Host smart-0426d61f-4071-4d09-a236-a19261e014de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490121067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1490121067
Directory /workspace/39.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/39.spi_device_upload.1625134777
Short name T834
Test name
Test status
Simulation time 8618831416 ps
CPU time 8.26 seconds
Started Aug 13 05:53:03 PM PDT 24
Finished Aug 13 05:53:11 PM PDT 24
Peak memory 232932 kb
Host smart-e0bb2cc7-37d9-4b96-98bf-6edec48a99f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625134777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1625134777
Directory /workspace/39.spi_device_upload/latest


Test location /workspace/coverage/default/4.spi_device_alert_test.2408634726
Short name T141
Test name
Test status
Simulation time 21613604 ps
CPU time 0.69 seconds
Started Aug 13 05:49:16 PM PDT 24
Finished Aug 13 05:49:17 PM PDT 24
Peak memory 204912 kb
Host smart-4e4251f1-da05-4d5e-974a-981a5af2de69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408634726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
408634726
Directory /workspace/4.spi_device_alert_test/latest


Test location /workspace/coverage/default/4.spi_device_cfg_cmd.346183020
Short name T709
Test name
Test status
Simulation time 425922836 ps
CPU time 2.37 seconds
Started Aug 13 05:49:18 PM PDT 24
Finished Aug 13 05:49:20 PM PDT 24
Peak memory 224588 kb
Host smart-b822fa72-be80-46c5-9413-0cf0e25a5491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346183020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.346183020
Directory /workspace/4.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/4.spi_device_csb_read.1305362074
Short name T775
Test name
Test status
Simulation time 34563301 ps
CPU time 0.77 seconds
Started Aug 13 05:49:10 PM PDT 24
Finished Aug 13 05:49:12 PM PDT 24
Peak memory 206628 kb
Host smart-46fbb656-a610-490d-b793-1093185d90f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305362074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1305362074
Directory /workspace/4.spi_device_csb_read/latest


Test location /workspace/coverage/default/4.spi_device_flash_all.2697413689
Short name T1014
Test name
Test status
Simulation time 193883630387 ps
CPU time 201.6 seconds
Started Aug 13 05:49:18 PM PDT 24
Finished Aug 13 05:52:39 PM PDT 24
Peak memory 249396 kb
Host smart-557c2d2a-d936-467d-bd00-15558f5f6ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697413689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2697413689
Directory /workspace/4.spi_device_flash_all/latest


Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2212164920
Short name T778
Test name
Test status
Simulation time 9836651206 ps
CPU time 76.82 seconds
Started Aug 13 05:49:17 PM PDT 24
Finished Aug 13 05:50:34 PM PDT 24
Peak memory 260800 kb
Host smart-c8a05c73-62dd-4d69-a5ba-e10e56dc7943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212164920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2212164920
Directory /workspace/4.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1846117528
Short name T193
Test name
Test status
Simulation time 3374219606 ps
CPU time 50.44 seconds
Started Aug 13 05:49:19 PM PDT 24
Finished Aug 13 05:50:09 PM PDT 24
Peak memory 241240 kb
Host smart-01cfbd4f-aabc-4517-9bdc-4ad04d556a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846117528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1846117528
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/4.spi_device_flash_mode.1286498264
Short name T457
Test name
Test status
Simulation time 295069240 ps
CPU time 5.23 seconds
Started Aug 13 05:49:20 PM PDT 24
Finished Aug 13 05:49:26 PM PDT 24
Peak memory 236120 kb
Host smart-5f81cfa6-1b59-4af5-9b73-74bb2bbf17e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286498264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1286498264
Directory /workspace/4.spi_device_flash_mode/latest


Test location /workspace/coverage/default/4.spi_device_intercept.1103384884
Short name T232
Test name
Test status
Simulation time 5199492610 ps
CPU time 10.72 seconds
Started Aug 13 05:49:18 PM PDT 24
Finished Aug 13 05:49:29 PM PDT 24
Peak memory 224708 kb
Host smart-2c45afaf-0b90-421a-8662-e8079281d4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103384884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1103384884
Directory /workspace/4.spi_device_intercept/latest


Test location /workspace/coverage/default/4.spi_device_mailbox.2796630966
Short name T548
Test name
Test status
Simulation time 1482111297 ps
CPU time 11.33 seconds
Started Aug 13 05:49:26 PM PDT 24
Finished Aug 13 05:49:38 PM PDT 24
Peak memory 249308 kb
Host smart-d0cd03d7-4ab5-4ecb-9221-9948f38f8ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796630966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2796630966
Directory /workspace/4.spi_device_mailbox/latest


Test location /workspace/coverage/default/4.spi_device_mem_parity.441334888
Short name T593
Test name
Test status
Simulation time 15889639 ps
CPU time 1.11 seconds
Started Aug 13 05:49:11 PM PDT 24
Finished Aug 13 05:49:13 PM PDT 24
Peak memory 216724 kb
Host smart-1b4a900d-70d2-4586-b269-88353d5cdf57
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441334888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.441334888
Directory /workspace/4.spi_device_mem_parity/latest


Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3606523346
Short name T184
Test name
Test status
Simulation time 16909239193 ps
CPU time 14.22 seconds
Started Aug 13 05:49:21 PM PDT 24
Finished Aug 13 05:49:35 PM PDT 24
Peak memory 240992 kb
Host smart-dfbd9a52-e041-48f1-ab17-78ad840abf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606523346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3606523346
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2342386232
Short name T520
Test name
Test status
Simulation time 1278615483 ps
CPU time 3.6 seconds
Started Aug 13 05:49:27 PM PDT 24
Finished Aug 13 05:49:31 PM PDT 24
Peak memory 224708 kb
Host smart-ddce61ce-8fbe-4415-80aa-5c691e3f2944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342386232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2342386232
Directory /workspace/4.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.685179207
Short name T541
Test name
Test status
Simulation time 2421287859 ps
CPU time 17.29 seconds
Started Aug 13 05:49:21 PM PDT 24
Finished Aug 13 05:49:38 PM PDT 24
Peak memory 220316 kb
Host smart-5f094bfd-83b7-4ae2-ba56-709e3233c273
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=685179207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.685179207
Directory /workspace/4.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/4.spi_device_sec_cm.174887483
Short name T73
Test name
Test status
Simulation time 59482061 ps
CPU time 1.09 seconds
Started Aug 13 05:49:19 PM PDT 24
Finished Aug 13 05:49:20 PM PDT 24
Peak memory 235632 kb
Host smart-a480c267-9fa4-4c04-8990-ba549fb5ebe8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174887483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.174887483
Directory /workspace/4.spi_device_sec_cm/latest


Test location /workspace/coverage/default/4.spi_device_stress_all.585748162
Short name T38
Test name
Test status
Simulation time 3873825545 ps
CPU time 92.12 seconds
Started Aug 13 05:49:18 PM PDT 24
Finished Aug 13 05:50:50 PM PDT 24
Peak memory 256416 kb
Host smart-23058934-d120-4ba2-85fd-df2cd201d593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585748162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.585748162
Directory /workspace/4.spi_device_stress_all/latest


Test location /workspace/coverage/default/4.spi_device_tpm_all.731241953
Short name T463
Test name
Test status
Simulation time 49266662618 ps
CPU time 37.38 seconds
Started Aug 13 05:49:11 PM PDT 24
Finished Aug 13 05:49:48 PM PDT 24
Peak memory 216544 kb
Host smart-8e5de014-28d7-493b-bbaa-d0b356ce14db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731241953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.731241953
Directory /workspace/4.spi_device_tpm_all/latest


Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2656391387
Short name T134
Test name
Test status
Simulation time 5687273088 ps
CPU time 19.02 seconds
Started Aug 13 05:49:13 PM PDT 24
Finished Aug 13 05:49:32 PM PDT 24
Peak memory 216600 kb
Host smart-4cff5753-02b4-4406-8a4e-b95ca6dd26e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656391387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2656391387
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/4.spi_device_tpm_rw.513519889
Short name T454
Test name
Test status
Simulation time 13541015 ps
CPU time 0.72 seconds
Started Aug 13 05:49:16 PM PDT 24
Finished Aug 13 05:49:17 PM PDT 24
Peak memory 205648 kb
Host smart-50622e79-ee57-41ea-8506-e185903f637e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513519889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.513519889
Directory /workspace/4.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1153670313
Short name T135
Test name
Test status
Simulation time 157009924 ps
CPU time 0.92 seconds
Started Aug 13 05:49:18 PM PDT 24
Finished Aug 13 05:49:19 PM PDT 24
Peak memory 206152 kb
Host smart-adba2fd1-5a15-4d90-8e63-89bd1230a188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153670313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1153670313
Directory /workspace/4.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/4.spi_device_upload.738172817
Short name T976
Test name
Test status
Simulation time 1160747040 ps
CPU time 7.26 seconds
Started Aug 13 05:49:19 PM PDT 24
Finished Aug 13 05:49:27 PM PDT 24
Peak memory 232940 kb
Host smart-0b60d40d-0a80-49e0-bddb-72af234215c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738172817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.738172817
Directory /workspace/4.spi_device_upload/latest


Test location /workspace/coverage/default/40.spi_device_alert_test.2664836686
Short name T549
Test name
Test status
Simulation time 14028653 ps
CPU time 0.67 seconds
Started Aug 13 05:53:14 PM PDT 24
Finished Aug 13 05:53:14 PM PDT 24
Peak memory 204976 kb
Host smart-bb9be3f7-101c-42e2-8aac-ef0488b8df5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664836686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2664836686
Directory /workspace/40.spi_device_alert_test/latest


Test location /workspace/coverage/default/40.spi_device_cfg_cmd.4032875703
Short name T681
Test name
Test status
Simulation time 106183589 ps
CPU time 3.45 seconds
Started Aug 13 05:53:11 PM PDT 24
Finished Aug 13 05:53:15 PM PDT 24
Peak memory 224744 kb
Host smart-5f25bd01-4e47-420c-97a2-d3b8dc06da3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032875703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.4032875703
Directory /workspace/40.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/40.spi_device_csb_read.3850895731
Short name T873
Test name
Test status
Simulation time 57138966 ps
CPU time 0.77 seconds
Started Aug 13 05:53:05 PM PDT 24
Finished Aug 13 05:53:06 PM PDT 24
Peak memory 206572 kb
Host smart-9c323ad8-35bc-4a45-bbca-1ca218c7f61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850895731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3850895731
Directory /workspace/40.spi_device_csb_read/latest


Test location /workspace/coverage/default/40.spi_device_flash_all.826580956
Short name T50
Test name
Test status
Simulation time 27853207833 ps
CPU time 53.79 seconds
Started Aug 13 05:53:23 PM PDT 24
Finished Aug 13 05:54:16 PM PDT 24
Peak memory 256068 kb
Host smart-3cfa8780-4f7b-43ba-a3ba-8944d6866f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826580956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.826580956
Directory /workspace/40.spi_device_flash_all/latest


Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2843019633
Short name T6
Test name
Test status
Simulation time 17815986150 ps
CPU time 198.34 seconds
Started Aug 13 05:53:12 PM PDT 24
Finished Aug 13 05:56:31 PM PDT 24
Peak memory 257476 kb
Host smart-58e7ec64-8aa2-4583-b150-15a59a68be84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843019633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2843019633
Directory /workspace/40.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/40.spi_device_flash_mode.2969042444
Short name T1007
Test name
Test status
Simulation time 198379648 ps
CPU time 3.08 seconds
Started Aug 13 05:53:23 PM PDT 24
Finished Aug 13 05:53:26 PM PDT 24
Peak memory 224704 kb
Host smart-3b4854cd-0333-403b-a3fc-ea46bd341a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969042444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2969042444
Directory /workspace/40.spi_device_flash_mode/latest


Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1715807046
Short name T46
Test name
Test status
Simulation time 14319277738 ps
CPU time 48.88 seconds
Started Aug 13 05:53:14 PM PDT 24
Finished Aug 13 05:54:03 PM PDT 24
Peak memory 224772 kb
Host smart-9e7df98a-af8f-4800-b80c-d13184926b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715807046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1715807046
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/40.spi_device_intercept.1935215785
Short name T59
Test name
Test status
Simulation time 1112439936 ps
CPU time 11.71 seconds
Started Aug 13 05:53:12 PM PDT 24
Finished Aug 13 05:53:24 PM PDT 24
Peak memory 233024 kb
Host smart-8d275ae1-2e3b-4038-b244-c9f9328fc2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935215785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1935215785
Directory /workspace/40.spi_device_intercept/latest


Test location /workspace/coverage/default/40.spi_device_mailbox.3379247108
Short name T761
Test name
Test status
Simulation time 9452837382 ps
CPU time 37.67 seconds
Started Aug 13 05:53:13 PM PDT 24
Finished Aug 13 05:53:50 PM PDT 24
Peak memory 232912 kb
Host smart-a0e9667c-c2b5-427e-ab78-042bc6b0d16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379247108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3379247108
Directory /workspace/40.spi_device_mailbox/latest


Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.554765964
Short name T266
Test name
Test status
Simulation time 416500231 ps
CPU time 2.95 seconds
Started Aug 13 05:53:13 PM PDT 24
Finished Aug 13 05:53:16 PM PDT 24
Peak memory 232904 kb
Host smart-a1a10339-2340-4ffe-bcb7-55f805ffcb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554765964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.554765964
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1164948567
Short name T745
Test name
Test status
Simulation time 3995453161 ps
CPU time 11.26 seconds
Started Aug 13 05:53:22 PM PDT 24
Finished Aug 13 05:53:34 PM PDT 24
Peak memory 240128 kb
Host smart-c970302c-a711-4e96-b6c0-6bf0f7127799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164948567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1164948567
Directory /workspace/40.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1432212092
Short name T812
Test name
Test status
Simulation time 2591542598 ps
CPU time 15.81 seconds
Started Aug 13 05:53:13 PM PDT 24
Finished Aug 13 05:53:29 PM PDT 24
Peak memory 222220 kb
Host smart-1e39ed5c-c184-4a18-a1af-5f89378d0c07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1432212092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1432212092
Directory /workspace/40.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/40.spi_device_tpm_all.983179450
Short name T606
Test name
Test status
Simulation time 7340012435 ps
CPU time 19.64 seconds
Started Aug 13 05:53:07 PM PDT 24
Finished Aug 13 05:53:27 PM PDT 24
Peak memory 216804 kb
Host smart-41adff9b-b295-4aaf-941a-0013e041d142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983179450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.983179450
Directory /workspace/40.spi_device_tpm_all/latest


Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.562482201
Short name T539
Test name
Test status
Simulation time 492207643 ps
CPU time 1.42 seconds
Started Aug 13 05:53:04 PM PDT 24
Finished Aug 13 05:53:05 PM PDT 24
Peak memory 207956 kb
Host smart-a6b6f2b7-1027-495a-bb55-8b5b8b74cca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562482201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.562482201
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/40.spi_device_tpm_rw.1686253587
Short name T401
Test name
Test status
Simulation time 196410774 ps
CPU time 1.61 seconds
Started Aug 13 05:53:03 PM PDT 24
Finished Aug 13 05:53:04 PM PDT 24
Peak memory 216508 kb
Host smart-92137305-367a-45e6-953c-ae8a11decbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686253587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1686253587
Directory /workspace/40.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3292151424
Short name T455
Test name
Test status
Simulation time 52633707 ps
CPU time 0.9 seconds
Started Aug 13 05:53:07 PM PDT 24
Finished Aug 13 05:53:08 PM PDT 24
Peak memory 206108 kb
Host smart-d9962b26-7ac1-454b-bf46-84f336bc92d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292151424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3292151424
Directory /workspace/40.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/40.spi_device_upload.3192796164
Short name T390
Test name
Test status
Simulation time 9105341629 ps
CPU time 16.7 seconds
Started Aug 13 05:53:12 PM PDT 24
Finished Aug 13 05:53:29 PM PDT 24
Peak memory 240964 kb
Host smart-d5ad9375-2ea0-4f66-b69a-7e7bc87f35f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192796164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3192796164
Directory /workspace/40.spi_device_upload/latest


Test location /workspace/coverage/default/41.spi_device_alert_test.1996166494
Short name T962
Test name
Test status
Simulation time 13757819 ps
CPU time 0.79 seconds
Started Aug 13 05:53:22 PM PDT 24
Finished Aug 13 05:53:23 PM PDT 24
Peak memory 205500 kb
Host smart-5acdfa18-e7d2-4a09-ace2-ca87a892102c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996166494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1996166494
Directory /workspace/41.spi_device_alert_test/latest


Test location /workspace/coverage/default/41.spi_device_cfg_cmd.206689854
Short name T529
Test name
Test status
Simulation time 35188821 ps
CPU time 2.19 seconds
Started Aug 13 05:53:14 PM PDT 24
Finished Aug 13 05:53:17 PM PDT 24
Peak memory 224656 kb
Host smart-18c89808-9878-4eda-a242-c09a1cf0b4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206689854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.206689854
Directory /workspace/41.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/41.spi_device_csb_read.3773781893
Short name T855
Test name
Test status
Simulation time 20832188 ps
CPU time 0.82 seconds
Started Aug 13 05:53:17 PM PDT 24
Finished Aug 13 05:53:18 PM PDT 24
Peak memory 206592 kb
Host smart-b81f4987-7223-49df-a7ea-8fb9148eee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773781893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3773781893
Directory /workspace/41.spi_device_csb_read/latest


Test location /workspace/coverage/default/41.spi_device_flash_all.1075495525
Short name T816
Test name
Test status
Simulation time 5486395894 ps
CPU time 41.12 seconds
Started Aug 13 05:53:19 PM PDT 24
Finished Aug 13 05:54:01 PM PDT 24
Peak memory 249380 kb
Host smart-156c8bdf-7b70-47df-978f-e448592bbc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075495525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1075495525
Directory /workspace/41.spi_device_flash_all/latest


Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.467149943
Short name T295
Test name
Test status
Simulation time 10627365480 ps
CPU time 134.17 seconds
Started Aug 13 05:53:21 PM PDT 24
Finished Aug 13 05:55:35 PM PDT 24
Peak memory 249620 kb
Host smart-639fadcf-b6d4-4f95-b3f5-04ea4000c8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467149943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.467149943
Directory /workspace/41.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1698037093
Short name T885
Test name
Test status
Simulation time 12694874208 ps
CPU time 36.21 seconds
Started Aug 13 05:53:20 PM PDT 24
Finished Aug 13 05:53:56 PM PDT 24
Peak memory 235684 kb
Host smart-7462fa83-5dc1-4f3e-a3ea-4eea553e380e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698037093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1698037093
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/41.spi_device_flash_mode.2373907792
Short name T568
Test name
Test status
Simulation time 10663096165 ps
CPU time 28.17 seconds
Started Aug 13 05:53:13 PM PDT 24
Finished Aug 13 05:53:42 PM PDT 24
Peak memory 237688 kb
Host smart-c883efd6-d55d-4a53-b446-1bed6d85a9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373907792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2373907792
Directory /workspace/41.spi_device_flash_mode/latest


Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2304320024
Short name T223
Test name
Test status
Simulation time 46585277066 ps
CPU time 73.7 seconds
Started Aug 13 05:53:13 PM PDT 24
Finished Aug 13 05:54:27 PM PDT 24
Peak memory 249220 kb
Host smart-4a0b6784-5149-474a-ba5d-cebe9594c272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304320024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2304320024
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/41.spi_device_intercept.3435520406
Short name T693
Test name
Test status
Simulation time 45836104 ps
CPU time 2.43 seconds
Started Aug 13 05:53:13 PM PDT 24
Finished Aug 13 05:53:16 PM PDT 24
Peak memory 232780 kb
Host smart-f9235a00-5e1b-4671-bc86-21ea98cef7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435520406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3435520406
Directory /workspace/41.spi_device_intercept/latest


Test location /workspace/coverage/default/41.spi_device_mailbox.720732380
Short name T472
Test name
Test status
Simulation time 5234402627 ps
CPU time 8.98 seconds
Started Aug 13 05:53:13 PM PDT 24
Finished Aug 13 05:53:22 PM PDT 24
Peak memory 232816 kb
Host smart-ee3da180-aead-4e5c-8b2a-0a44fab32f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720732380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.720732380
Directory /workspace/41.spi_device_mailbox/latest


Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3337940774
Short name T268
Test name
Test status
Simulation time 244354993 ps
CPU time 2.84 seconds
Started Aug 13 05:53:12 PM PDT 24
Finished Aug 13 05:53:15 PM PDT 24
Peak memory 224588 kb
Host smart-db76d724-35f2-4f74-a0a6-d00e099b1fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337940774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3337940774
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1156333340
Short name T993
Test name
Test status
Simulation time 17288269820 ps
CPU time 43.61 seconds
Started Aug 13 05:53:12 PM PDT 24
Finished Aug 13 05:53:56 PM PDT 24
Peak memory 236632 kb
Host smart-0cf28d65-f92f-429c-8f34-9be46c76b56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156333340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1156333340
Directory /workspace/41.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3477204489
Short name T902
Test name
Test status
Simulation time 1984446559 ps
CPU time 10.65 seconds
Started Aug 13 05:53:23 PM PDT 24
Finished Aug 13 05:53:34 PM PDT 24
Peak memory 218932 kb
Host smart-c1a341f6-e74a-4735-af7b-13750b0771dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3477204489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3477204489
Directory /workspace/41.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/41.spi_device_stress_all.3807180046
Short name T1020
Test name
Test status
Simulation time 127477317 ps
CPU time 1.26 seconds
Started Aug 13 05:53:20 PM PDT 24
Finished Aug 13 05:53:22 PM PDT 24
Peak memory 206928 kb
Host smart-2c56dc0b-7c0f-4aba-9e0d-3602cc637ed3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807180046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3807180046
Directory /workspace/41.spi_device_stress_all/latest


Test location /workspace/coverage/default/41.spi_device_tpm_all.4248655511
Short name T639
Test name
Test status
Simulation time 2373441106 ps
CPU time 22.94 seconds
Started Aug 13 05:53:23 PM PDT 24
Finished Aug 13 05:53:47 PM PDT 24
Peak memory 216732 kb
Host smart-d67bdbd5-aa5a-48e2-badf-fc9c41f93dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248655511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.4248655511
Directory /workspace/41.spi_device_tpm_all/latest


Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4138414484
Short name T432
Test name
Test status
Simulation time 1268113624 ps
CPU time 8.4 seconds
Started Aug 13 05:53:13 PM PDT 24
Finished Aug 13 05:53:22 PM PDT 24
Peak memory 216456 kb
Host smart-2f27850b-1dac-424b-b381-c8c5034ee74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138414484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4138414484
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/41.spi_device_tpm_rw.3083133324
Short name T1029
Test name
Test status
Simulation time 60147385 ps
CPU time 1.11 seconds
Started Aug 13 05:53:22 PM PDT 24
Finished Aug 13 05:53:23 PM PDT 24
Peak memory 208108 kb
Host smart-32727e70-7cb9-45d9-b34e-fab966be7af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083133324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3083133324
Directory /workspace/41.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3692340422
Short name T32
Test name
Test status
Simulation time 26604483 ps
CPU time 0.78 seconds
Started Aug 13 05:53:12 PM PDT 24
Finished Aug 13 05:53:13 PM PDT 24
Peak memory 206112 kb
Host smart-c362bd88-adb7-4a5f-bb30-cccf8758bdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692340422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3692340422
Directory /workspace/41.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/41.spi_device_upload.3201087452
Short name T695
Test name
Test status
Simulation time 30144068148 ps
CPU time 22.12 seconds
Started Aug 13 05:53:22 PM PDT 24
Finished Aug 13 05:53:44 PM PDT 24
Peak memory 224764 kb
Host smart-964014cb-2707-4ad3-8f18-4544ee19e7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201087452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3201087452
Directory /workspace/41.spi_device_upload/latest


Test location /workspace/coverage/default/42.spi_device_alert_test.4012759091
Short name T540
Test name
Test status
Simulation time 54849051 ps
CPU time 0.72 seconds
Started Aug 13 05:53:21 PM PDT 24
Finished Aug 13 05:53:22 PM PDT 24
Peak memory 204984 kb
Host smart-c04f7324-3198-4a44-9567-71184a419e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012759091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4012759091
Directory /workspace/42.spi_device_alert_test/latest


Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2087507129
Short name T178
Test name
Test status
Simulation time 283735542 ps
CPU time 3.4 seconds
Started Aug 13 05:53:20 PM PDT 24
Finished Aug 13 05:53:24 PM PDT 24
Peak memory 224740 kb
Host smart-8b6f2f08-3f57-49c9-b977-54e23cb08554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087507129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2087507129
Directory /workspace/42.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/42.spi_device_csb_read.1811699601
Short name T343
Test name
Test status
Simulation time 57622305 ps
CPU time 0.78 seconds
Started Aug 13 05:53:20 PM PDT 24
Finished Aug 13 05:53:21 PM PDT 24
Peak memory 206548 kb
Host smart-d7d0662f-0def-45a9-9eb8-28d7f773b1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811699601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1811699601
Directory /workspace/42.spi_device_csb_read/latest


Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3598203575
Short name T63
Test name
Test status
Simulation time 17310081390 ps
CPU time 185.74 seconds
Started Aug 13 05:53:18 PM PDT 24
Finished Aug 13 05:56:24 PM PDT 24
Peak memory 241200 kb
Host smart-c7afe88b-f474-422a-97fc-aa6cdb7b9b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598203575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3598203575
Directory /workspace/42.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2343326447
Short name T203
Test name
Test status
Simulation time 448279843463 ps
CPU time 502.67 seconds
Started Aug 13 05:53:21 PM PDT 24
Finished Aug 13 06:01:44 PM PDT 24
Peak memory 263416 kb
Host smart-a4624eb2-da49-455e-b995-ab2ed8e699d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343326447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2343326447
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/42.spi_device_flash_mode.2116897119
Short name T366
Test name
Test status
Simulation time 464277597 ps
CPU time 7.47 seconds
Started Aug 13 05:53:21 PM PDT 24
Finished Aug 13 05:53:29 PM PDT 24
Peak memory 234412 kb
Host smart-b8dbba39-f2e8-48b7-9821-99ab633ff43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116897119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2116897119
Directory /workspace/42.spi_device_flash_mode/latest


Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.838564732
Short name T968
Test name
Test status
Simulation time 1352062231 ps
CPU time 5.73 seconds
Started Aug 13 05:53:20 PM PDT 24
Finished Aug 13 05:53:26 PM PDT 24
Peak memory 235604 kb
Host smart-7695397d-f5c6-4d31-a18c-3c12bb32fd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838564732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.838564732
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/42.spi_device_intercept.923676882
Short name T877
Test name
Test status
Simulation time 839635422 ps
CPU time 5.45 seconds
Started Aug 13 05:53:21 PM PDT 24
Finished Aug 13 05:53:26 PM PDT 24
Peak memory 232912 kb
Host smart-37d7058d-d3db-4002-a382-72fe98d2762a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923676882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.923676882
Directory /workspace/42.spi_device_intercept/latest


Test location /workspace/coverage/default/42.spi_device_mailbox.2528197966
Short name T213
Test name
Test status
Simulation time 427395246 ps
CPU time 11.05 seconds
Started Aug 13 05:53:20 PM PDT 24
Finished Aug 13 05:53:31 PM PDT 24
Peak memory 232844 kb
Host smart-c4c36bda-5b72-4802-a71a-d10e34c2280b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528197966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2528197966
Directory /workspace/42.spi_device_mailbox/latest


Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1191866038
Short name T799
Test name
Test status
Simulation time 579523368 ps
CPU time 5.95 seconds
Started Aug 13 05:53:19 PM PDT 24
Finished Aug 13 05:53:25 PM PDT 24
Peak memory 224648 kb
Host smart-254f8afc-8871-43bc-9871-dae3fba36c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191866038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1191866038
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1003473034
Short name T676
Test name
Test status
Simulation time 2859392734 ps
CPU time 5.89 seconds
Started Aug 13 05:53:20 PM PDT 24
Finished Aug 13 05:53:26 PM PDT 24
Peak memory 232960 kb
Host smart-67da81ac-77e2-4fbe-9a94-f6ba6eabc1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003473034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1003473034
Directory /workspace/42.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.4159541448
Short name T384
Test name
Test status
Simulation time 2574413870 ps
CPU time 6 seconds
Started Aug 13 05:53:20 PM PDT 24
Finished Aug 13 05:53:26 PM PDT 24
Peak memory 220576 kb
Host smart-85d9e00b-f5f4-4de9-bc1d-3db25c19b2bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4159541448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.4159541448
Directory /workspace/42.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/42.spi_device_stress_all.2064076823
Short name T918
Test name
Test status
Simulation time 53498331970 ps
CPU time 114.05 seconds
Started Aug 13 05:53:21 PM PDT 24
Finished Aug 13 05:55:15 PM PDT 24
Peak memory 253580 kb
Host smart-63a80f0c-3abc-4586-86d5-9f25ab0c770e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064076823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2064076823
Directory /workspace/42.spi_device_stress_all/latest


Test location /workspace/coverage/default/42.spi_device_tpm_all.2460528013
Short name T327
Test name
Test status
Simulation time 3072367004 ps
CPU time 4.56 seconds
Started Aug 13 05:53:22 PM PDT 24
Finished Aug 13 05:53:27 PM PDT 24
Peak memory 216488 kb
Host smart-f25268c4-5518-4b5b-8c36-551ae99e48a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460528013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2460528013
Directory /workspace/42.spi_device_tpm_all/latest


Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2735712633
Short name T895
Test name
Test status
Simulation time 1438930116 ps
CPU time 5.6 seconds
Started Aug 13 05:53:21 PM PDT 24
Finished Aug 13 05:53:27 PM PDT 24
Peak memory 216492 kb
Host smart-dcef6d11-17f6-471a-b83d-b0059c7dffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735712633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2735712633
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/42.spi_device_tpm_rw.158448588
Short name T335
Test name
Test status
Simulation time 139465031 ps
CPU time 2 seconds
Started Aug 13 05:53:19 PM PDT 24
Finished Aug 13 05:53:21 PM PDT 24
Peak memory 216484 kb
Host smart-2a78aff3-bd93-407f-8495-495e883f6123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158448588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.158448588
Directory /workspace/42.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.625838450
Short name T420
Test name
Test status
Simulation time 83527843 ps
CPU time 0.93 seconds
Started Aug 13 05:53:19 PM PDT 24
Finished Aug 13 05:53:20 PM PDT 24
Peak memory 206108 kb
Host smart-b26b1f75-e64a-49e7-afcc-1d174d73327b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625838450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.625838450
Directory /workspace/42.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/42.spi_device_upload.1047858152
Short name T47
Test name
Test status
Simulation time 2244232078 ps
CPU time 10.08 seconds
Started Aug 13 05:53:19 PM PDT 24
Finished Aug 13 05:53:30 PM PDT 24
Peak memory 232932 kb
Host smart-adfe277f-96ae-4b8e-9e22-3c1851fb745e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047858152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1047858152
Directory /workspace/42.spi_device_upload/latest


Test location /workspace/coverage/default/43.spi_device_alert_test.2976729539
Short name T672
Test name
Test status
Simulation time 20442167 ps
CPU time 0.73 seconds
Started Aug 13 05:53:28 PM PDT 24
Finished Aug 13 05:53:28 PM PDT 24
Peak memory 205876 kb
Host smart-2667f05e-b811-4ba2-811d-8ca8b9983d70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976729539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2976729539
Directory /workspace/43.spi_device_alert_test/latest


Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1890225392
Short name T10
Test name
Test status
Simulation time 480450412 ps
CPU time 4.61 seconds
Started Aug 13 05:53:29 PM PDT 24
Finished Aug 13 05:53:33 PM PDT 24
Peak memory 232900 kb
Host smart-b0d8894d-2f04-469e-93fa-53b5a03dc9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890225392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1890225392
Directory /workspace/43.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/43.spi_device_csb_read.2158868710
Short name T781
Test name
Test status
Simulation time 15492043 ps
CPU time 0.81 seconds
Started Aug 13 05:53:20 PM PDT 24
Finished Aug 13 05:53:21 PM PDT 24
Peak memory 206632 kb
Host smart-f87d61d6-fca0-4ef0-8e17-9947d84f01a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158868710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2158868710
Directory /workspace/43.spi_device_csb_read/latest


Test location /workspace/coverage/default/43.spi_device_flash_all.1841817437
Short name T991
Test name
Test status
Simulation time 5024002293 ps
CPU time 37.94 seconds
Started Aug 13 05:53:30 PM PDT 24
Finished Aug 13 05:54:08 PM PDT 24
Peak memory 249368 kb
Host smart-6455ac26-11f0-433c-b3b1-c236ff69cb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841817437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1841817437
Directory /workspace/43.spi_device_flash_all/latest


Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1381078024
Short name T677
Test name
Test status
Simulation time 21566681094 ps
CPU time 95.55 seconds
Started Aug 13 05:53:29 PM PDT 24
Finished Aug 13 05:55:05 PM PDT 24
Peak memory 256432 kb
Host smart-55819dd1-8ca2-4193-9058-86da3e30a746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381078024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1381078024
Directory /workspace/43.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.192672638
Short name T179
Test name
Test status
Simulation time 38078409165 ps
CPU time 353.66 seconds
Started Aug 13 05:53:27 PM PDT 24
Finished Aug 13 05:59:21 PM PDT 24
Peak memory 249432 kb
Host smart-2e74ff59-c643-4f10-baa6-b319acb91e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192672638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.192672638
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/43.spi_device_flash_mode.48301687
Short name T532
Test name
Test status
Simulation time 127593085 ps
CPU time 5.2 seconds
Started Aug 13 05:53:26 PM PDT 24
Finished Aug 13 05:53:31 PM PDT 24
Peak memory 233324 kb
Host smart-ee033d1e-8d1c-44d9-ad4c-f1dfbb14fcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48301687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.48301687
Directory /workspace/43.spi_device_flash_mode/latest


Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1979616241
Short name T388
Test name
Test status
Simulation time 58396909251 ps
CPU time 138.25 seconds
Started Aug 13 05:53:25 PM PDT 24
Finished Aug 13 05:55:43 PM PDT 24
Peak memory 252856 kb
Host smart-7bc51cc2-e936-43e2-b2f2-e3b76c7be5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979616241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1979616241
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/43.spi_device_intercept.66168986
Short name T372
Test name
Test status
Simulation time 420048237 ps
CPU time 3.23 seconds
Started Aug 13 05:53:29 PM PDT 24
Finished Aug 13 05:53:33 PM PDT 24
Peak memory 218916 kb
Host smart-af12f33c-4ef0-42cd-a26c-db45e4ac1bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66168986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.66168986
Directory /workspace/43.spi_device_intercept/latest


Test location /workspace/coverage/default/43.spi_device_mailbox.4164091322
Short name T409
Test name
Test status
Simulation time 33848780 ps
CPU time 2.42 seconds
Started Aug 13 05:53:25 PM PDT 24
Finished Aug 13 05:53:27 PM PDT 24
Peak memory 232472 kb
Host smart-9633c3f9-a2a3-4e5b-9e18-9b3ffd5379cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164091322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4164091322
Directory /workspace/43.spi_device_mailbox/latest


Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1798879410
Short name T797
Test name
Test status
Simulation time 872011023 ps
CPU time 7.64 seconds
Started Aug 13 05:53:25 PM PDT 24
Finished Aug 13 05:53:33 PM PDT 24
Peak memory 234516 kb
Host smart-f59158bd-4cb6-4c61-86b1-c6dfae8b196f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798879410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1798879410
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2998486190
Short name T196
Test name
Test status
Simulation time 29776010161 ps
CPU time 24.1 seconds
Started Aug 13 05:53:27 PM PDT 24
Finished Aug 13 05:53:52 PM PDT 24
Peak memory 232980 kb
Host smart-6d35b7b8-af80-4c6d-9506-597981c7d194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998486190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2998486190
Directory /workspace/43.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1529367744
Short name T150
Test name
Test status
Simulation time 299533987 ps
CPU time 3.67 seconds
Started Aug 13 05:53:28 PM PDT 24
Finished Aug 13 05:53:32 PM PDT 24
Peak memory 223240 kb
Host smart-f1f890cd-b881-4f1d-82a1-d2059bc143e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1529367744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1529367744
Directory /workspace/43.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/43.spi_device_stress_all.120250815
Short name T301
Test name
Test status
Simulation time 182827678983 ps
CPU time 560.32 seconds
Started Aug 13 05:53:28 PM PDT 24
Finished Aug 13 06:02:49 PM PDT 24
Peak memory 277892 kb
Host smart-96fe84f3-255c-4a1d-91ec-7b2d33856cca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120250815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.120250815
Directory /workspace/43.spi_device_stress_all/latest


Test location /workspace/coverage/default/43.spi_device_tpm_all.162588026
Short name T431
Test name
Test status
Simulation time 1486316653 ps
CPU time 16.88 seconds
Started Aug 13 05:53:25 PM PDT 24
Finished Aug 13 05:53:43 PM PDT 24
Peak memory 219608 kb
Host smart-789199ee-990b-47bc-8ff0-70a0fb4aa542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162588026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.162588026
Directory /workspace/43.spi_device_tpm_all/latest


Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1390196560
Short name T728
Test name
Test status
Simulation time 617156437 ps
CPU time 4.38 seconds
Started Aug 13 05:53:18 PM PDT 24
Finished Aug 13 05:53:22 PM PDT 24
Peak memory 216404 kb
Host smart-665db113-39d3-436b-922d-bf72fd38e3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390196560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1390196560
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/43.spi_device_tpm_rw.3717994422
Short name T490
Test name
Test status
Simulation time 10527899 ps
CPU time 0.72 seconds
Started Aug 13 05:53:30 PM PDT 24
Finished Aug 13 05:53:31 PM PDT 24
Peak memory 205652 kb
Host smart-c7dd6759-61fd-4373-9a3b-cc003205d9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717994422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3717994422
Directory /workspace/43.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.829021178
Short name T370
Test name
Test status
Simulation time 102915159 ps
CPU time 0.81 seconds
Started Aug 13 05:53:30 PM PDT 24
Finished Aug 13 05:53:31 PM PDT 24
Peak memory 206140 kb
Host smart-74a92b8d-f6e8-419c-be55-3b9494b50d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829021178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.829021178
Directory /workspace/43.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/43.spi_device_upload.3895828929
Short name T987
Test name
Test status
Simulation time 49789325 ps
CPU time 2.26 seconds
Started Aug 13 05:53:29 PM PDT 24
Finished Aug 13 05:53:32 PM PDT 24
Peak memory 232484 kb
Host smart-f052bcfc-da1b-4515-a6b5-527eda85bb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895828929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3895828929
Directory /workspace/43.spi_device_upload/latest


Test location /workspace/coverage/default/44.spi_device_alert_test.3007270098
Short name T428
Test name
Test status
Simulation time 34939982 ps
CPU time 0.71 seconds
Started Aug 13 05:53:37 PM PDT 24
Finished Aug 13 05:53:38 PM PDT 24
Peak memory 204980 kb
Host smart-1fab38c5-4a0a-4fbf-a65e-1ec25978ae2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007270098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3007270098
Directory /workspace/44.spi_device_alert_test/latest


Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3227239738
Short name T959
Test name
Test status
Simulation time 693734321 ps
CPU time 5.3 seconds
Started Aug 13 05:53:38 PM PDT 24
Finished Aug 13 05:53:44 PM PDT 24
Peak memory 224664 kb
Host smart-b167b494-0b90-46b7-a01a-7876470470f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227239738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3227239738
Directory /workspace/44.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/44.spi_device_csb_read.3524475670
Short name T373
Test name
Test status
Simulation time 110340796 ps
CPU time 0.8 seconds
Started Aug 13 05:53:29 PM PDT 24
Finished Aug 13 05:53:30 PM PDT 24
Peak memory 206932 kb
Host smart-67053ba5-630e-4546-ad27-d56d77e9fff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524475670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3524475670
Directory /workspace/44.spi_device_csb_read/latest


Test location /workspace/coverage/default/44.spi_device_flash_all.410706718
Short name T790
Test name
Test status
Simulation time 11553450419 ps
CPU time 96.81 seconds
Started Aug 13 05:53:35 PM PDT 24
Finished Aug 13 05:55:12 PM PDT 24
Peak memory 249796 kb
Host smart-5a01275f-470e-4fe5-a332-59d25a11d64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410706718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.410706718
Directory /workspace/44.spi_device_flash_all/latest


Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3638237164
Short name T949
Test name
Test status
Simulation time 14505664996 ps
CPU time 103.7 seconds
Started Aug 13 05:53:39 PM PDT 24
Finished Aug 13 05:55:23 PM PDT 24
Peak memory 265072 kb
Host smart-a7af1177-bb55-48f7-b03f-c641726966f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638237164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3638237164
Directory /workspace/44.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1936907772
Short name T822
Test name
Test status
Simulation time 87365040494 ps
CPU time 312.89 seconds
Started Aug 13 05:53:37 PM PDT 24
Finished Aug 13 05:58:50 PM PDT 24
Peak memory 267364 kb
Host smart-73e1c6f3-a7a9-4992-a101-76594db8199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936907772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1936907772
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/44.spi_device_flash_mode.265469764
Short name T780
Test name
Test status
Simulation time 493070750 ps
CPU time 2.85 seconds
Started Aug 13 05:53:37 PM PDT 24
Finished Aug 13 05:53:40 PM PDT 24
Peak memory 232872 kb
Host smart-60bbdd17-f19a-4117-adcf-b71295d37e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265469764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.265469764
Directory /workspace/44.spi_device_flash_mode/latest


Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3003414897
Short name T874
Test name
Test status
Simulation time 309115682799 ps
CPU time 624.22 seconds
Started Aug 13 05:53:38 PM PDT 24
Finished Aug 13 06:04:03 PM PDT 24
Peak memory 254104 kb
Host smart-b9e4af6a-ec7a-4c4b-894b-a06b22f4695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003414897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3003414897
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/44.spi_device_intercept.1202384178
Short name T698
Test name
Test status
Simulation time 295197989 ps
CPU time 6.22 seconds
Started Aug 13 05:53:38 PM PDT 24
Finished Aug 13 05:53:44 PM PDT 24
Peak memory 232852 kb
Host smart-49f4e1b9-dc68-448f-b2e4-d6d90117b030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202384178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1202384178
Directory /workspace/44.spi_device_intercept/latest


Test location /workspace/coverage/default/44.spi_device_mailbox.1888423212
Short name T237
Test name
Test status
Simulation time 155537565 ps
CPU time 2.75 seconds
Started Aug 13 05:53:38 PM PDT 24
Finished Aug 13 05:53:41 PM PDT 24
Peak memory 232928 kb
Host smart-60135318-1fce-42ba-8ec4-e0482a5cda67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888423212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1888423212
Directory /workspace/44.spi_device_mailbox/latest


Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2940564046
Short name T260
Test name
Test status
Simulation time 1949469179 ps
CPU time 5.74 seconds
Started Aug 13 05:53:37 PM PDT 24
Finished Aug 13 05:53:43 PM PDT 24
Peak memory 224668 kb
Host smart-0ac74590-91d1-476f-9644-6302e18e8cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940564046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2940564046
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2088748903
Short name T702
Test name
Test status
Simulation time 5925336126 ps
CPU time 8.5 seconds
Started Aug 13 05:53:36 PM PDT 24
Finished Aug 13 05:53:45 PM PDT 24
Peak memory 232972 kb
Host smart-e5e9e9ce-1f24-4c31-94a0-033b7b8f787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088748903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2088748903
Directory /workspace/44.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2675166779
Short name T935
Test name
Test status
Simulation time 3177348108 ps
CPU time 9.34 seconds
Started Aug 13 05:53:35 PM PDT 24
Finished Aug 13 05:53:45 PM PDT 24
Peak memory 220984 kb
Host smart-d71deb5e-fd9e-4c2b-829d-fc885eeb66f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2675166779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2675166779
Directory /workspace/44.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/44.spi_device_stress_all.2407545205
Short name T21
Test name
Test status
Simulation time 69551076407 ps
CPU time 167.15 seconds
Started Aug 13 05:53:38 PM PDT 24
Finished Aug 13 05:56:25 PM PDT 24
Peak memory 237844 kb
Host smart-40760327-2a91-4379-af23-75b33c1458e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407545205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2407545205
Directory /workspace/44.spi_device_stress_all/latest


Test location /workspace/coverage/default/44.spi_device_tpm_all.1116933125
Short name T425
Test name
Test status
Simulation time 4287842396 ps
CPU time 19.03 seconds
Started Aug 13 05:53:39 PM PDT 24
Finished Aug 13 05:53:58 PM PDT 24
Peak memory 216520 kb
Host smart-8f0b8eb3-27a6-498d-b84e-90aeb39635d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116933125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1116933125
Directory /workspace/44.spi_device_tpm_all/latest


Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3320955223
Short name T645
Test name
Test status
Simulation time 1400228360 ps
CPU time 6.43 seconds
Started Aug 13 05:53:35 PM PDT 24
Finished Aug 13 05:53:42 PM PDT 24
Peak memory 216420 kb
Host smart-be2d8f4d-eaa9-4b75-a36f-022c1d6b40ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320955223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3320955223
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/44.spi_device_tpm_rw.1587812536
Short name T551
Test name
Test status
Simulation time 17159726 ps
CPU time 0.89 seconds
Started Aug 13 05:53:37 PM PDT 24
Finished Aug 13 05:53:38 PM PDT 24
Peak memory 207168 kb
Host smart-996ac730-9fd8-4db1-8260-5ea5c59c4682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587812536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1587812536
Directory /workspace/44.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1251819782
Short name T537
Test name
Test status
Simulation time 42996207 ps
CPU time 0.85 seconds
Started Aug 13 05:53:36 PM PDT 24
Finished Aug 13 05:53:37 PM PDT 24
Peak memory 206092 kb
Host smart-1325009d-8c69-4950-8712-6cc999e45897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251819782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1251819782
Directory /workspace/44.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/44.spi_device_upload.1692360116
Short name T953
Test name
Test status
Simulation time 81592748 ps
CPU time 2.55 seconds
Started Aug 13 05:53:36 PM PDT 24
Finished Aug 13 05:53:38 PM PDT 24
Peak memory 235368 kb
Host smart-3c5a77d2-d4d7-4dcb-ba54-b871e33ee753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692360116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1692360116
Directory /workspace/44.spi_device_upload/latest


Test location /workspace/coverage/default/45.spi_device_alert_test.4026515852
Short name T379
Test name
Test status
Simulation time 31329449 ps
CPU time 0.72 seconds
Started Aug 13 05:53:45 PM PDT 24
Finished Aug 13 05:53:46 PM PDT 24
Peak memory 205536 kb
Host smart-c8d29fbd-02b2-4ac5-86c3-a0591dae341b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026515852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4026515852
Directory /workspace/45.spi_device_alert_test/latest


Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1818629622
Short name T692
Test name
Test status
Simulation time 58221164 ps
CPU time 2.73 seconds
Started Aug 13 05:53:38 PM PDT 24
Finished Aug 13 05:53:41 PM PDT 24
Peak memory 232868 kb
Host smart-e8532891-20be-405c-9442-a7c647a53202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818629622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1818629622
Directory /workspace/45.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/45.spi_device_csb_read.2767004684
Short name T12
Test name
Test status
Simulation time 25786364 ps
CPU time 0.76 seconds
Started Aug 13 05:53:35 PM PDT 24
Finished Aug 13 05:53:36 PM PDT 24
Peak memory 205504 kb
Host smart-b01c0df2-d3e6-4862-b3b6-32991289b531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767004684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2767004684
Directory /workspace/45.spi_device_csb_read/latest


Test location /workspace/coverage/default/45.spi_device_flash_all.821722843
Short name T306
Test name
Test status
Simulation time 6425415319 ps
CPU time 40.39 seconds
Started Aug 13 05:53:46 PM PDT 24
Finished Aug 13 05:54:26 PM PDT 24
Peak memory 241152 kb
Host smart-46b0b21d-17e3-4435-ae69-d6349b97b9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821722843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.821722843
Directory /workspace/45.spi_device_flash_all/latest


Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4101996449
Short name T898
Test name
Test status
Simulation time 1480474943 ps
CPU time 15.05 seconds
Started Aug 13 05:53:44 PM PDT 24
Finished Aug 13 05:53:59 PM PDT 24
Peak memory 237728 kb
Host smart-a4352e49-0655-409b-93d3-659648ff7845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101996449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4101996449
Directory /workspace/45.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3493558509
Short name T43
Test name
Test status
Simulation time 84057616668 ps
CPU time 145.95 seconds
Started Aug 13 05:53:45 PM PDT 24
Finished Aug 13 05:56:11 PM PDT 24
Peak memory 249324 kb
Host smart-3dcc9fcf-f35a-4269-9cc5-988c7c7dea7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493558509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3493558509
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/45.spi_device_flash_mode.451846210
Short name T802
Test name
Test status
Simulation time 6779316204 ps
CPU time 11.2 seconds
Started Aug 13 05:53:39 PM PDT 24
Finished Aug 13 05:53:50 PM PDT 24
Peak memory 224740 kb
Host smart-b66177c3-a3a8-4310-8676-aa21390fa9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451846210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.451846210
Directory /workspace/45.spi_device_flash_mode/latest


Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.834434451
Short name T703
Test name
Test status
Simulation time 73588156613 ps
CPU time 150.11 seconds
Started Aug 13 05:53:40 PM PDT 24
Finished Aug 13 05:56:10 PM PDT 24
Peak memory 258328 kb
Host smart-57593661-4a49-4a4c-ace5-4e34d3d994c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834434451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.834434451
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/45.spi_device_intercept.3580100566
Short name T248
Test name
Test status
Simulation time 2292059253 ps
CPU time 5.11 seconds
Started Aug 13 05:53:40 PM PDT 24
Finished Aug 13 05:53:46 PM PDT 24
Peak memory 224740 kb
Host smart-4e969336-3114-4707-bc9f-97ad73349fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580100566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3580100566
Directory /workspace/45.spi_device_intercept/latest


Test location /workspace/coverage/default/45.spi_device_mailbox.1324817937
Short name T519
Test name
Test status
Simulation time 980799535 ps
CPU time 16.42 seconds
Started Aug 13 05:53:38 PM PDT 24
Finished Aug 13 05:53:55 PM PDT 24
Peak memory 224716 kb
Host smart-9dce92b0-8af2-4beb-8a4c-6970f9d9e8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324817937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1324817937
Directory /workspace/45.spi_device_mailbox/latest


Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.171915639
Short name T337
Test name
Test status
Simulation time 267720434 ps
CPU time 2.28 seconds
Started Aug 13 05:53:37 PM PDT 24
Finished Aug 13 05:53:39 PM PDT 24
Peak memory 223140 kb
Host smart-8c965d01-772f-4806-954f-a83f64ae0590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171915639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.171915639
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.952750233
Short name T241
Test name
Test status
Simulation time 1198930486 ps
CPU time 4.19 seconds
Started Aug 13 05:53:39 PM PDT 24
Finished Aug 13 05:53:44 PM PDT 24
Peak memory 232896 kb
Host smart-545cf3bf-a076-444d-b718-b91358f0217a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952750233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.952750233
Directory /workspace/45.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2509066074
Short name T153
Test name
Test status
Simulation time 1084786362 ps
CPU time 12.08 seconds
Started Aug 13 05:53:36 PM PDT 24
Finished Aug 13 05:53:49 PM PDT 24
Peak memory 220440 kb
Host smart-f8905a47-2b4a-4acb-83ab-27bdc3771b3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2509066074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2509066074
Directory /workspace/45.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/45.spi_device_stress_all.901353845
Short name T833
Test name
Test status
Simulation time 50565678033 ps
CPU time 633.54 seconds
Started Aug 13 05:53:46 PM PDT 24
Finished Aug 13 06:04:20 PM PDT 24
Peak memory 283216 kb
Host smart-1a32ca1c-dc08-442c-b7a0-48ef3e83c42a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901353845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.901353845
Directory /workspace/45.spi_device_stress_all/latest


Test location /workspace/coverage/default/45.spi_device_tpm_all.1469776398
Short name T1
Test name
Test status
Simulation time 16675209108 ps
CPU time 20.68 seconds
Started Aug 13 05:53:35 PM PDT 24
Finished Aug 13 05:53:56 PM PDT 24
Peak memory 216440 kb
Host smart-99d82004-5877-422f-b57d-382243b5a640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469776398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1469776398
Directory /workspace/45.spi_device_tpm_all/latest


Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1348339700
Short name T932
Test name
Test status
Simulation time 7652092238 ps
CPU time 14.41 seconds
Started Aug 13 05:53:37 PM PDT 24
Finished Aug 13 05:53:51 PM PDT 24
Peak memory 216508 kb
Host smart-2394f3c9-99e5-47a6-b8ac-8fd4b003a936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348339700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1348339700
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/45.spi_device_tpm_rw.2344084473
Short name T644
Test name
Test status
Simulation time 330812885 ps
CPU time 6.84 seconds
Started Aug 13 05:53:35 PM PDT 24
Finished Aug 13 05:53:42 PM PDT 24
Peak memory 216504 kb
Host smart-c149d192-99de-4867-9dc7-1d6f8889430b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344084473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2344084473
Directory /workspace/45.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3731965018
Short name T970
Test name
Test status
Simulation time 21202951 ps
CPU time 0.75 seconds
Started Aug 13 05:53:36 PM PDT 24
Finished Aug 13 05:53:37 PM PDT 24
Peak memory 206120 kb
Host smart-bf8d84ac-e976-43c0-96a2-8d3a9d5d8354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731965018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3731965018
Directory /workspace/45.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/45.spi_device_upload.1974840554
Short name T621
Test name
Test status
Simulation time 1712513045 ps
CPU time 3.86 seconds
Started Aug 13 05:53:37 PM PDT 24
Finished Aug 13 05:53:41 PM PDT 24
Peak memory 224648 kb
Host smart-a58a12f9-dec9-49f6-b691-c9ddb0ab455b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974840554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1974840554
Directory /workspace/45.spi_device_upload/latest


Test location /workspace/coverage/default/46.spi_device_alert_test.3025943517
Short name T901
Test name
Test status
Simulation time 18750823 ps
CPU time 0.73 seconds
Started Aug 13 05:53:44 PM PDT 24
Finished Aug 13 05:53:45 PM PDT 24
Peak memory 205536 kb
Host smart-736b6a17-032c-4e4f-8c56-3b332353f0fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025943517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3025943517
Directory /workspace/46.spi_device_alert_test/latest


Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3156577325
Short name T986
Test name
Test status
Simulation time 195950204 ps
CPU time 3.73 seconds
Started Aug 13 05:53:46 PM PDT 24
Finished Aug 13 05:53:50 PM PDT 24
Peak memory 232856 kb
Host smart-91776f52-4af4-472f-a0b4-3d25c71cf689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156577325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3156577325
Directory /workspace/46.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/46.spi_device_csb_read.1479102769
Short name T597
Test name
Test status
Simulation time 15902919 ps
CPU time 0.78 seconds
Started Aug 13 05:53:44 PM PDT 24
Finished Aug 13 05:53:45 PM PDT 24
Peak memory 206636 kb
Host smart-a1c8c911-3fc4-469e-b162-40cc22b7ee01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479102769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1479102769
Directory /workspace/46.spi_device_csb_read/latest


Test location /workspace/coverage/default/46.spi_device_flash_all.4218103760
Short name T612
Test name
Test status
Simulation time 3084446681 ps
CPU time 29.12 seconds
Started Aug 13 05:53:45 PM PDT 24
Finished Aug 13 05:54:14 PM PDT 24
Peak memory 249344 kb
Host smart-3a588cf4-8fd0-4bb6-969c-b0ef24b60dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218103760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4218103760
Directory /workspace/46.spi_device_flash_all/latest


Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.4289625630
Short name T748
Test name
Test status
Simulation time 53970758826 ps
CPU time 129.62 seconds
Started Aug 13 05:53:45 PM PDT 24
Finished Aug 13 05:55:55 PM PDT 24
Peak memory 250372 kb
Host smart-b885eb4a-b5a7-48ce-86d5-7ca36b3f7d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289625630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.4289625630
Directory /workspace/46.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2360410138
Short name T308
Test name
Test status
Simulation time 17468469624 ps
CPU time 65.77 seconds
Started Aug 13 05:53:43 PM PDT 24
Finished Aug 13 05:54:49 PM PDT 24
Peak memory 255516 kb
Host smart-7658c0ac-7844-46b1-b284-6ba1f8eccff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360410138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2360410138
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/46.spi_device_flash_mode.3193358499
Short name T751
Test name
Test status
Simulation time 421369996 ps
CPU time 5.11 seconds
Started Aug 13 05:53:43 PM PDT 24
Finished Aug 13 05:53:48 PM PDT 24
Peak memory 232908 kb
Host smart-f2f3cd13-6a87-4fa3-a673-b859a93b7c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193358499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3193358499
Directory /workspace/46.spi_device_flash_mode/latest


Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2961491300
Short name T209
Test name
Test status
Simulation time 75452834003 ps
CPU time 126.37 seconds
Started Aug 13 05:53:43 PM PDT 24
Finished Aug 13 05:55:49 PM PDT 24
Peak memory 241144 kb
Host smart-0268690a-be00-4dd4-a349-3067ac98b328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961491300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2961491300
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/46.spi_device_intercept.1003805230
Short name T48
Test name
Test status
Simulation time 893892500 ps
CPU time 10.66 seconds
Started Aug 13 05:53:44 PM PDT 24
Finished Aug 13 05:53:55 PM PDT 24
Peak memory 224744 kb
Host smart-07291c79-5149-4f79-8e88-7311e03583d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003805230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1003805230
Directory /workspace/46.spi_device_intercept/latest


Test location /workspace/coverage/default/46.spi_device_mailbox.602314932
Short name T939
Test name
Test status
Simulation time 121691662 ps
CPU time 2.45 seconds
Started Aug 13 05:53:44 PM PDT 24
Finished Aug 13 05:53:47 PM PDT 24
Peak memory 232540 kb
Host smart-de0b7a67-eecd-4308-b813-e9be9bef8aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602314932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.602314932
Directory /workspace/46.spi_device_mailbox/latest


Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.889846250
Short name T977
Test name
Test status
Simulation time 4227497250 ps
CPU time 13.69 seconds
Started Aug 13 05:53:45 PM PDT 24
Finished Aug 13 05:53:59 PM PDT 24
Peak memory 232920 kb
Host smart-5fade5cb-3fc7-48af-8474-5fc9e6c2bf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889846250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.889846250
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.414356872
Short name T726
Test name
Test status
Simulation time 6874332066 ps
CPU time 18.86 seconds
Started Aug 13 05:53:46 PM PDT 24
Finished Aug 13 05:54:05 PM PDT 24
Peak memory 227996 kb
Host smart-84a32afc-ac03-46bf-b7d4-225f769dabc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414356872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.414356872
Directory /workspace/46.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1285105545
Short name T706
Test name
Test status
Simulation time 727526356 ps
CPU time 4.61 seconds
Started Aug 13 05:53:44 PM PDT 24
Finished Aug 13 05:53:49 PM PDT 24
Peak memory 220192 kb
Host smart-97f163e6-a3e9-4831-bfca-202286e22a2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1285105545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1285105545
Directory /workspace/46.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/46.spi_device_tpm_all.1491965339
Short name T56
Test name
Test status
Simulation time 23324858356 ps
CPU time 28.09 seconds
Started Aug 13 05:53:46 PM PDT 24
Finished Aug 13 05:54:14 PM PDT 24
Peak memory 216576 kb
Host smart-d7dd2e6d-951c-426a-956b-0b352725aca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491965339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1491965339
Directory /workspace/46.spi_device_tpm_all/latest


Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.646403221
Short name T471
Test name
Test status
Simulation time 20564151280 ps
CPU time 8.06 seconds
Started Aug 13 05:53:43 PM PDT 24
Finished Aug 13 05:53:51 PM PDT 24
Peak memory 216532 kb
Host smart-7279fb31-2e02-4d50-bc49-1f041b5a7893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646403221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.646403221
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/46.spi_device_tpm_rw.1967647814
Short name T850
Test name
Test status
Simulation time 2723846905 ps
CPU time 4.63 seconds
Started Aug 13 05:53:44 PM PDT 24
Finished Aug 13 05:53:49 PM PDT 24
Peak memory 216492 kb
Host smart-488360f8-79b2-4cd2-aee1-ef1bdb41cc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967647814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1967647814
Directory /workspace/46.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3158036110
Short name T499
Test name
Test status
Simulation time 25864552 ps
CPU time 0.8 seconds
Started Aug 13 05:53:42 PM PDT 24
Finished Aug 13 05:53:43 PM PDT 24
Peak memory 206260 kb
Host smart-32668262-c7a4-4de4-a805-152af5a3c187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158036110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3158036110
Directory /workspace/46.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/46.spi_device_upload.3350203070
Short name T690
Test name
Test status
Simulation time 236787020 ps
CPU time 4.51 seconds
Started Aug 13 05:53:43 PM PDT 24
Finished Aug 13 05:53:48 PM PDT 24
Peak memory 232848 kb
Host smart-aa5a84ab-d16a-4349-9b99-dd03bb6339b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350203070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3350203070
Directory /workspace/46.spi_device_upload/latest


Test location /workspace/coverage/default/47.spi_device_alert_test.2529076087
Short name T626
Test name
Test status
Simulation time 12266278 ps
CPU time 0.72 seconds
Started Aug 13 05:53:54 PM PDT 24
Finished Aug 13 05:53:55 PM PDT 24
Peak memory 205932 kb
Host smart-5affaabd-328f-4864-bed6-b3a677d59b96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529076087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2529076087
Directory /workspace/47.spi_device_alert_test/latest


Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3381700582
Short name T513
Test name
Test status
Simulation time 1698221380 ps
CPU time 10.32 seconds
Started Aug 13 05:53:53 PM PDT 24
Finished Aug 13 05:54:04 PM PDT 24
Peak memory 232868 kb
Host smart-cc624cd6-d6fa-41f5-a96c-95d930e01449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381700582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3381700582
Directory /workspace/47.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/47.spi_device_csb_read.1015298892
Short name T880
Test name
Test status
Simulation time 114137354 ps
CPU time 0.79 seconds
Started Aug 13 05:53:45 PM PDT 24
Finished Aug 13 05:53:46 PM PDT 24
Peak memory 206572 kb
Host smart-c9cabe7b-0ff1-44c3-96af-0eca6166527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015298892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1015298892
Directory /workspace/47.spi_device_csb_read/latest


Test location /workspace/coverage/default/47.spi_device_flash_all.7490196
Short name T205
Test name
Test status
Simulation time 1103633822 ps
CPU time 23.92 seconds
Started Aug 13 05:53:53 PM PDT 24
Finished Aug 13 05:54:17 PM PDT 24
Peak memory 249312 kb
Host smart-a80ff8d8-d6b7-4a05-8cc0-ec5a955ac364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7490196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.7490196
Directory /workspace/47.spi_device_flash_all/latest


Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.926430143
Short name T922
Test name
Test status
Simulation time 32339521008 ps
CPU time 254.77 seconds
Started Aug 13 05:53:54 PM PDT 24
Finished Aug 13 05:58:09 PM PDT 24
Peak memory 249664 kb
Host smart-67f64791-c7ba-45fa-b77e-024aed8141d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926430143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.926430143
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/47.spi_device_flash_mode.2571778511
Short name T782
Test name
Test status
Simulation time 1106732039 ps
CPU time 11.45 seconds
Started Aug 13 05:53:53 PM PDT 24
Finished Aug 13 05:54:05 PM PDT 24
Peak memory 224688 kb
Host smart-614135a1-a99f-482c-944a-e8df54cfa0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571778511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2571778511
Directory /workspace/47.spi_device_flash_mode/latest


Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.261015715
Short name T501
Test name
Test status
Simulation time 6175438271 ps
CPU time 60.64 seconds
Started Aug 13 05:53:53 PM PDT 24
Finished Aug 13 05:54:54 PM PDT 24
Peak memory 256920 kb
Host smart-5a5a6f1d-9cb0-4a29-92b6-508d9acc7d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261015715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.261015715
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/47.spi_device_intercept.3070747215
Short name T206
Test name
Test status
Simulation time 29508263984 ps
CPU time 15.75 seconds
Started Aug 13 05:53:55 PM PDT 24
Finished Aug 13 05:54:11 PM PDT 24
Peak memory 224656 kb
Host smart-9d19d7a8-d06f-4c21-b3fb-cead7140fdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070747215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3070747215
Directory /workspace/47.spi_device_intercept/latest


Test location /workspace/coverage/default/47.spi_device_mailbox.2136557495
Short name T278
Test name
Test status
Simulation time 7246153099 ps
CPU time 65.47 seconds
Started Aug 13 05:53:53 PM PDT 24
Finished Aug 13 05:54:58 PM PDT 24
Peak memory 232924 kb
Host smart-5b209b5f-d9cf-46a1-864a-af3ede8f9a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136557495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2136557495
Directory /workspace/47.spi_device_mailbox/latest


Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.890095964
Short name T208
Test name
Test status
Simulation time 13689826135 ps
CPU time 26.14 seconds
Started Aug 13 05:53:44 PM PDT 24
Finished Aug 13 05:54:10 PM PDT 24
Peak memory 248904 kb
Host smart-caaee67c-7ab4-4912-b6f0-5be450eb8763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890095964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.890095964
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3084092774
Short name T1012
Test name
Test status
Simulation time 1894116868 ps
CPU time 10.31 seconds
Started Aug 13 05:53:46 PM PDT 24
Finished Aug 13 05:53:56 PM PDT 24
Peak memory 232892 kb
Host smart-4bccc838-aaa3-43dc-bc64-5b3aede27654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084092774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3084092774
Directory /workspace/47.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.327095250
Short name T397
Test name
Test status
Simulation time 3184529943 ps
CPU time 12.53 seconds
Started Aug 13 05:53:57 PM PDT 24
Finished Aug 13 05:54:10 PM PDT 24
Peak memory 220728 kb
Host smart-c5c00bbd-07e1-4a9b-b882-013469ba1667
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=327095250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.327095250
Directory /workspace/47.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/47.spi_device_stress_all.1191282346
Short name T512
Test name
Test status
Simulation time 20387361747 ps
CPU time 80.86 seconds
Started Aug 13 05:53:57 PM PDT 24
Finished Aug 13 05:55:18 PM PDT 24
Peak memory 251424 kb
Host smart-1776c207-dfec-4f54-89c9-57e684287639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191282346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1191282346
Directory /workspace/47.spi_device_stress_all/latest


Test location /workspace/coverage/default/47.spi_device_tpm_all.3644771610
Short name T331
Test name
Test status
Simulation time 5648512194 ps
CPU time 18.01 seconds
Started Aug 13 05:53:47 PM PDT 24
Finished Aug 13 05:54:05 PM PDT 24
Peak memory 216496 kb
Host smart-05160d12-933d-4aa4-bf8b-647863a6abaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644771610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3644771610
Directory /workspace/47.spi_device_tpm_all/latest


Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.743199991
Short name T691
Test name
Test status
Simulation time 2261060116 ps
CPU time 9.2 seconds
Started Aug 13 05:53:42 PM PDT 24
Finished Aug 13 05:53:51 PM PDT 24
Peak memory 216536 kb
Host smart-d6fb7de7-5090-4e7a-af7a-60ef047049be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743199991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.743199991
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/47.spi_device_tpm_rw.696111601
Short name T398
Test name
Test status
Simulation time 48521985 ps
CPU time 0.9 seconds
Started Aug 13 05:53:45 PM PDT 24
Finished Aug 13 05:53:46 PM PDT 24
Peak memory 206108 kb
Host smart-6e8f25c8-c286-4350-9e52-3efb969ef715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696111601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.696111601
Directory /workspace/47.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2226256900
Short name T969
Test name
Test status
Simulation time 74828086 ps
CPU time 0.96 seconds
Started Aug 13 05:53:44 PM PDT 24
Finished Aug 13 05:53:45 PM PDT 24
Peak memory 207132 kb
Host smart-261eb5ed-55f0-486f-aee4-bd2f5732199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226256900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2226256900
Directory /workspace/47.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/47.spi_device_upload.3708665951
Short name T879
Test name
Test status
Simulation time 338416463 ps
CPU time 3.5 seconds
Started Aug 13 05:53:51 PM PDT 24
Finished Aug 13 05:53:55 PM PDT 24
Peak memory 232872 kb
Host smart-8c097ce5-8969-4730-b633-ab18c84b2d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708665951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3708665951
Directory /workspace/47.spi_device_upload/latest


Test location /workspace/coverage/default/48.spi_device_alert_test.116988932
Short name T658
Test name
Test status
Simulation time 114667685 ps
CPU time 0.72 seconds
Started Aug 13 05:54:02 PM PDT 24
Finished Aug 13 05:54:03 PM PDT 24
Peak memory 205572 kb
Host smart-299cf52b-a424-427a-9165-be63756498d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116988932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.116988932
Directory /workspace/48.spi_device_alert_test/latest


Test location /workspace/coverage/default/48.spi_device_cfg_cmd.607424972
Short name T559
Test name
Test status
Simulation time 464932729 ps
CPU time 6.34 seconds
Started Aug 13 05:54:02 PM PDT 24
Finished Aug 13 05:54:09 PM PDT 24
Peak memory 224680 kb
Host smart-622e7639-c6a4-4fd9-8eb9-ed70ba01b668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607424972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.607424972
Directory /workspace/48.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/48.spi_device_csb_read.744928779
Short name T28
Test name
Test status
Simulation time 16350695 ps
CPU time 0.73 seconds
Started Aug 13 05:53:53 PM PDT 24
Finished Aug 13 05:53:54 PM PDT 24
Peak memory 205616 kb
Host smart-394ed474-c19b-4d4d-8b26-3fdb07531e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744928779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.744928779
Directory /workspace/48.spi_device_csb_read/latest


Test location /workspace/coverage/default/48.spi_device_flash_all.3510141240
Short name T188
Test name
Test status
Simulation time 119765507564 ps
CPU time 275.31 seconds
Started Aug 13 05:54:02 PM PDT 24
Finished Aug 13 05:58:38 PM PDT 24
Peak memory 265736 kb
Host smart-602b3cd1-6867-4295-a93b-798b94472ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510141240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3510141240
Directory /workspace/48.spi_device_flash_all/latest


Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.480922501
Short name T940
Test name
Test status
Simulation time 342229093994 ps
CPU time 635.15 seconds
Started Aug 13 05:54:04 PM PDT 24
Finished Aug 13 06:04:39 PM PDT 24
Peak memory 271332 kb
Host smart-22f60995-86f5-419a-a7d5-29f22e296236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480922501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.480922501
Directory /workspace/48.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.480359361
Short name T596
Test name
Test status
Simulation time 1767218452 ps
CPU time 10.97 seconds
Started Aug 13 05:54:03 PM PDT 24
Finished Aug 13 05:54:14 PM PDT 24
Peak memory 217584 kb
Host smart-93e1cf46-433d-4f39-94e0-d5ab7106cd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480359361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.480359361
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/48.spi_device_flash_mode.713790110
Short name T921
Test name
Test status
Simulation time 4446825064 ps
CPU time 18 seconds
Started Aug 13 05:54:03 PM PDT 24
Finished Aug 13 05:54:21 PM PDT 24
Peak memory 224792 kb
Host smart-7a0ff771-6225-4e60-88c5-238f7fd54f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713790110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.713790110
Directory /workspace/48.spi_device_flash_mode/latest


Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3342809444
Short name T881
Test name
Test status
Simulation time 9329479161 ps
CPU time 23.02 seconds
Started Aug 13 05:54:00 PM PDT 24
Finished Aug 13 05:54:23 PM PDT 24
Peak memory 249916 kb
Host smart-17d5045e-9e83-4915-b6bb-f5c3f74e1a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342809444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3342809444
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/48.spi_device_intercept.718413263
Short name T92
Test name
Test status
Simulation time 260229004 ps
CPU time 5.26 seconds
Started Aug 13 05:53:53 PM PDT 24
Finished Aug 13 05:53:58 PM PDT 24
Peak memory 224632 kb
Host smart-f7ec0fd3-73ab-4553-b58c-c5e26457a4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718413263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.718413263
Directory /workspace/48.spi_device_intercept/latest


Test location /workspace/coverage/default/48.spi_device_mailbox.980351047
Short name T526
Test name
Test status
Simulation time 30387128245 ps
CPU time 31.98 seconds
Started Aug 13 05:53:53 PM PDT 24
Finished Aug 13 05:54:25 PM PDT 24
Peak memory 249140 kb
Host smart-44f64eb7-e047-475c-aec9-50743753df94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980351047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.980351047
Directory /workspace/48.spi_device_mailbox/latest


Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2436852029
Short name T524
Test name
Test status
Simulation time 146019936 ps
CPU time 2.31 seconds
Started Aug 13 05:53:57 PM PDT 24
Finished Aug 13 05:54:00 PM PDT 24
Peak memory 223216 kb
Host smart-0bb5e104-57f5-4e13-8ff6-ba7a49a75f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436852029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2436852029
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3802031462
Short name T603
Test name
Test status
Simulation time 2437394897 ps
CPU time 7.34 seconds
Started Aug 13 05:53:54 PM PDT 24
Finished Aug 13 05:54:02 PM PDT 24
Peak memory 232904 kb
Host smart-0136e355-a40e-48d2-b39f-f1a8081c129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802031462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3802031462
Directory /workspace/48.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3492038855
Short name T906
Test name
Test status
Simulation time 1118313221 ps
CPU time 6.29 seconds
Started Aug 13 05:54:03 PM PDT 24
Finished Aug 13 05:54:09 PM PDT 24
Peak memory 223220 kb
Host smart-35e915b4-abb0-4aa3-9633-14484d9c767e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3492038855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3492038855
Directory /workspace/48.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/48.spi_device_stress_all.3480671904
Short name T39
Test name
Test status
Simulation time 44242865645 ps
CPU time 316.85 seconds
Started Aug 13 05:54:03 PM PDT 24
Finished Aug 13 05:59:20 PM PDT 24
Peak memory 263304 kb
Host smart-edd19ab8-7fdf-4d98-b466-83a7fdea8ecd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480671904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3480671904
Directory /workspace/48.spi_device_stress_all/latest


Test location /workspace/coverage/default/48.spi_device_tpm_all.2281569577
Short name T875
Test name
Test status
Simulation time 14288280926 ps
CPU time 29.29 seconds
Started Aug 13 05:53:55 PM PDT 24
Finished Aug 13 05:54:24 PM PDT 24
Peak memory 220424 kb
Host smart-cf7664ba-009c-449f-9394-11b94d953c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281569577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2281569577
Directory /workspace/48.spi_device_tpm_all/latest


Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1372467468
Short name T577
Test name
Test status
Simulation time 833344553 ps
CPU time 5.5 seconds
Started Aug 13 05:53:54 PM PDT 24
Finished Aug 13 05:53:59 PM PDT 24
Peak memory 216392 kb
Host smart-d8f5d06b-d241-47a8-ad1f-c7dcee22130f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372467468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1372467468
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/48.spi_device_tpm_rw.2075180861
Short name T615
Test name
Test status
Simulation time 34306116 ps
CPU time 0.82 seconds
Started Aug 13 05:53:53 PM PDT 24
Finished Aug 13 05:53:54 PM PDT 24
Peak memory 206936 kb
Host smart-b6a425f2-4000-4f29-8611-254135ae8bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075180861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2075180861
Directory /workspace/48.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.372004017
Short name T362
Test name
Test status
Simulation time 105319330 ps
CPU time 0.78 seconds
Started Aug 13 05:53:55 PM PDT 24
Finished Aug 13 05:53:55 PM PDT 24
Peak memory 206120 kb
Host smart-da6d7ec8-a646-4cf9-9b50-2e4e7df05574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372004017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.372004017
Directory /workspace/48.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/48.spi_device_upload.741719062
Short name T765
Test name
Test status
Simulation time 12524636619 ps
CPU time 20.41 seconds
Started Aug 13 05:53:52 PM PDT 24
Finished Aug 13 05:54:12 PM PDT 24
Peak memory 232924 kb
Host smart-b73fa072-a26a-45fc-a813-b88c9668d317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741719062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.741719062
Directory /workspace/48.spi_device_upload/latest


Test location /workspace/coverage/default/49.spi_device_alert_test.3269655577
Short name T415
Test name
Test status
Simulation time 22599895 ps
CPU time 0.72 seconds
Started Aug 13 05:54:07 PM PDT 24
Finished Aug 13 05:54:08 PM PDT 24
Peak memory 205896 kb
Host smart-547a67f7-8437-485d-af3d-028867bc36e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269655577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3269655577
Directory /workspace/49.spi_device_alert_test/latest


Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3871504943
Short name T818
Test name
Test status
Simulation time 9960992084 ps
CPU time 14.05 seconds
Started Aug 13 05:54:03 PM PDT 24
Finished Aug 13 05:54:17 PM PDT 24
Peak memory 232984 kb
Host smart-d09c78d6-cf9b-4a9b-8c8b-7784fc40bc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871504943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3871504943
Directory /workspace/49.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/49.spi_device_csb_read.1134060313
Short name T911
Test name
Test status
Simulation time 66648778 ps
CPU time 0.87 seconds
Started Aug 13 05:54:02 PM PDT 24
Finished Aug 13 05:54:03 PM PDT 24
Peak memory 206620 kb
Host smart-1f8fa69b-a3b2-4eaf-b71a-29afa7625e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134060313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1134060313
Directory /workspace/49.spi_device_csb_read/latest


Test location /workspace/coverage/default/49.spi_device_flash_all.3541406378
Short name T290
Test name
Test status
Simulation time 26051057397 ps
CPU time 86.67 seconds
Started Aug 13 05:54:07 PM PDT 24
Finished Aug 13 05:55:34 PM PDT 24
Peak memory 253836 kb
Host smart-fc87699b-f9bd-40eb-94cd-0ea5e0019121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541406378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3541406378
Directory /workspace/49.spi_device_flash_all/latest


Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2546400036
Short name T235
Test name
Test status
Simulation time 22301130491 ps
CPU time 59.36 seconds
Started Aug 13 05:54:04 PM PDT 24
Finished Aug 13 05:55:03 PM PDT 24
Peak memory 231540 kb
Host smart-2023e5e7-1961-4dc7-86a7-43b5b53d1260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546400036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2546400036
Directory /workspace/49.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2818121087
Short name T801
Test name
Test status
Simulation time 5643327699 ps
CPU time 30.88 seconds
Started Aug 13 05:54:05 PM PDT 24
Finished Aug 13 05:54:36 PM PDT 24
Peak memory 256336 kb
Host smart-ad2d7da9-eef4-4684-87b8-749faa392abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818121087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2818121087
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.956028707
Short name T42
Test name
Test status
Simulation time 29958441404 ps
CPU time 220.77 seconds
Started Aug 13 05:54:03 PM PDT 24
Finished Aug 13 05:57:44 PM PDT 24
Peak memory 249832 kb
Host smart-a9ba2b7e-dccc-405b-99b7-b39540728b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956028707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.956028707
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/49.spi_device_intercept.3424810202
Short name T271
Test name
Test status
Simulation time 2597401648 ps
CPU time 20.93 seconds
Started Aug 13 05:54:03 PM PDT 24
Finished Aug 13 05:54:24 PM PDT 24
Peak memory 220164 kb
Host smart-14c77c18-1a62-4f45-a4a7-13c6005c55a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424810202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3424810202
Directory /workspace/49.spi_device_intercept/latest


Test location /workspace/coverage/default/49.spi_device_mailbox.3156334874
Short name T619
Test name
Test status
Simulation time 36169770366 ps
CPU time 55.7 seconds
Started Aug 13 05:54:03 PM PDT 24
Finished Aug 13 05:54:58 PM PDT 24
Peak memory 232920 kb
Host smart-23b485a5-952b-4b35-b4d6-2c5143e350f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156334874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3156334874
Directory /workspace/49.spi_device_mailbox/latest


Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1442893754
Short name T985
Test name
Test status
Simulation time 1204665094 ps
CPU time 6.12 seconds
Started Aug 13 05:54:03 PM PDT 24
Finished Aug 13 05:54:09 PM PDT 24
Peak memory 224612 kb
Host smart-5d002deb-a387-4be6-92a4-6b8485de3cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442893754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1442893754
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2048364318
Short name T742
Test name
Test status
Simulation time 244237715 ps
CPU time 3.71 seconds
Started Aug 13 05:54:04 PM PDT 24
Finished Aug 13 05:54:07 PM PDT 24
Peak memory 224620 kb
Host smart-a2e59388-c381-4dcc-8992-4b3dc8f2ecc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048364318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2048364318
Directory /workspace/49.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1744637424
Short name T506
Test name
Test status
Simulation time 1326846299 ps
CPU time 8.08 seconds
Started Aug 13 05:54:03 PM PDT 24
Finished Aug 13 05:54:11 PM PDT 24
Peak memory 220224 kb
Host smart-327ad5bd-b067-47f4-9232-f8297dc6ff00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1744637424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1744637424
Directory /workspace/49.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/49.spi_device_tpm_all.3044407385
Short name T336
Test name
Test status
Simulation time 22688824 ps
CPU time 0.76 seconds
Started Aug 13 05:54:04 PM PDT 24
Finished Aug 13 05:54:04 PM PDT 24
Peak memory 205752 kb
Host smart-18979597-672e-449b-9644-68b8ea805903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044407385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3044407385
Directory /workspace/49.spi_device_tpm_all/latest


Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.357366904
Short name T682
Test name
Test status
Simulation time 903034855 ps
CPU time 6.38 seconds
Started Aug 13 05:54:00 PM PDT 24
Finished Aug 13 05:54:06 PM PDT 24
Peak memory 216440 kb
Host smart-8f80f390-7081-43b6-aea7-e26083f688b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357366904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.357366904
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/49.spi_device_tpm_rw.2396230494
Short name T421
Test name
Test status
Simulation time 48174694 ps
CPU time 1.17 seconds
Started Aug 13 05:54:04 PM PDT 24
Finished Aug 13 05:54:05 PM PDT 24
Peak memory 208068 kb
Host smart-2973c273-0e70-427d-a1c2-a4c6a1154e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396230494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2396230494
Directory /workspace/49.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1102489217
Short name T411
Test name
Test status
Simulation time 156923359 ps
CPU time 0.98 seconds
Started Aug 13 05:54:02 PM PDT 24
Finished Aug 13 05:54:03 PM PDT 24
Peak memory 206144 kb
Host smart-a6588c12-6423-443d-8558-5b27c0af661d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102489217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1102489217
Directory /workspace/49.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/49.spi_device_upload.217485763
Short name T470
Test name
Test status
Simulation time 932771471 ps
CPU time 2.97 seconds
Started Aug 13 05:54:05 PM PDT 24
Finished Aug 13 05:54:08 PM PDT 24
Peak memory 232848 kb
Host smart-a4960f1a-cd2e-4343-8705-812dd39b302d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217485763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.217485763
Directory /workspace/49.spi_device_upload/latest


Test location /workspace/coverage/default/5.spi_device_alert_test.249960966
Short name T494
Test name
Test status
Simulation time 70911510 ps
CPU time 0.75 seconds
Started Aug 13 05:49:29 PM PDT 24
Finished Aug 13 05:49:30 PM PDT 24
Peak memory 204968 kb
Host smart-55cb5a5d-047b-4b86-871e-1bde9063a290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249960966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.249960966
Directory /workspace/5.spi_device_alert_test/latest


Test location /workspace/coverage/default/5.spi_device_cfg_cmd.274453006
Short name T531
Test name
Test status
Simulation time 2464814910 ps
CPU time 5.12 seconds
Started Aug 13 05:49:29 PM PDT 24
Finished Aug 13 05:49:35 PM PDT 24
Peak memory 232940 kb
Host smart-fe2ddebf-7937-42ed-b80b-ccd7f5b515b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274453006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.274453006
Directory /workspace/5.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/5.spi_device_csb_read.4038498580
Short name T461
Test name
Test status
Simulation time 117306313 ps
CPU time 0.8 seconds
Started Aug 13 05:49:18 PM PDT 24
Finished Aug 13 05:49:19 PM PDT 24
Peak memory 206632 kb
Host smart-621692ca-3ead-4e6d-b0a1-2673d0fe2731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038498580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4038498580
Directory /workspace/5.spi_device_csb_read/latest


Test location /workspace/coverage/default/5.spi_device_flash_all.2341705164
Short name T287
Test name
Test status
Simulation time 63024990944 ps
CPU time 148.5 seconds
Started Aug 13 05:49:27 PM PDT 24
Finished Aug 13 05:51:56 PM PDT 24
Peak memory 249336 kb
Host smart-6edf543d-3633-4c77-9786-817eb0eda4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341705164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2341705164
Directory /workspace/5.spi_device_flash_all/latest


Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.588338610
Short name T650
Test name
Test status
Simulation time 51909562793 ps
CPU time 349.26 seconds
Started Aug 13 05:49:27 PM PDT 24
Finished Aug 13 05:55:16 PM PDT 24
Peak memory 249436 kb
Host smart-2171804a-fea3-471b-8170-ea287484eb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588338610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.588338610
Directory /workspace/5.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3574784196
Short name T550
Test name
Test status
Simulation time 4552872533 ps
CPU time 53.78 seconds
Started Aug 13 05:49:32 PM PDT 24
Finished Aug 13 05:50:26 PM PDT 24
Peak memory 257588 kb
Host smart-28479d32-1a25-4e0b-92ef-385eac14c20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574784196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3574784196
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/5.spi_device_flash_mode.282973879
Short name T810
Test name
Test status
Simulation time 717393264 ps
CPU time 7.02 seconds
Started Aug 13 05:49:27 PM PDT 24
Finished Aug 13 05:49:34 PM PDT 24
Peak memory 249452 kb
Host smart-4fb068a9-aba2-40d0-a6dc-088b3bd8e7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282973879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.282973879
Directory /workspace/5.spi_device_flash_mode/latest


Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2844112177
Short name T300
Test name
Test status
Simulation time 314205573706 ps
CPU time 292.89 seconds
Started Aug 13 05:49:31 PM PDT 24
Finished Aug 13 05:54:24 PM PDT 24
Peak memory 253956 kb
Host smart-dec8cf3b-6022-4fe3-8f80-7b936ada8e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844112177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2844112177
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/5.spi_device_intercept.1553093843
Short name T273
Test name
Test status
Simulation time 3135939117 ps
CPU time 24.31 seconds
Started Aug 13 05:49:26 PM PDT 24
Finished Aug 13 05:49:51 PM PDT 24
Peak memory 224728 kb
Host smart-dd74ca67-54c5-4447-96bd-6c3fcb450bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553093843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1553093843
Directory /workspace/5.spi_device_intercept/latest


Test location /workspace/coverage/default/5.spi_device_mailbox.2572926042
Short name T835
Test name
Test status
Simulation time 14253477229 ps
CPU time 26.96 seconds
Started Aug 13 05:49:33 PM PDT 24
Finished Aug 13 05:50:00 PM PDT 24
Peak memory 232932 kb
Host smart-9cbc3a1a-dfd9-4944-a4ef-4a65774c95e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572926042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2572926042
Directory /workspace/5.spi_device_mailbox/latest


Test location /workspace/coverage/default/5.spi_device_mem_parity.2664735563
Short name T573
Test name
Test status
Simulation time 50368605 ps
CPU time 1 seconds
Started Aug 13 05:49:18 PM PDT 24
Finished Aug 13 05:49:19 PM PDT 24
Peak memory 216744 kb
Host smart-eaae9921-e033-42b9-9124-8d961a24139a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664735563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2664735563
Directory /workspace/5.spi_device_mem_parity/latest


Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1001779643
Short name T514
Test name
Test status
Simulation time 100976248106 ps
CPU time 37.02 seconds
Started Aug 13 05:49:26 PM PDT 24
Finished Aug 13 05:50:04 PM PDT 24
Peak memory 240712 kb
Host smart-97342db9-ff38-4756-afec-47d201b79cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001779643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1001779643
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3543268148
Short name T270
Test name
Test status
Simulation time 12265164537 ps
CPU time 6.7 seconds
Started Aug 13 05:49:30 PM PDT 24
Finished Aug 13 05:49:37 PM PDT 24
Peak memory 232952 kb
Host smart-1a00f825-2652-4686-8dc1-c5973cb79cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543268148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3543268148
Directory /workspace/5.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.429018617
Short name T769
Test name
Test status
Simulation time 1999610514 ps
CPU time 10.28 seconds
Started Aug 13 05:49:30 PM PDT 24
Finished Aug 13 05:49:40 PM PDT 24
Peak memory 222460 kb
Host smart-d55cc341-3e66-4568-9946-1d401f1e4aa7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=429018617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.429018617
Directory /workspace/5.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/5.spi_device_stress_all.3577737893
Short name T759
Test name
Test status
Simulation time 83209945040 ps
CPU time 762.66 seconds
Started Aug 13 05:49:28 PM PDT 24
Finished Aug 13 06:02:11 PM PDT 24
Peak memory 265800 kb
Host smart-e43351a6-d761-4ca7-99cb-a6d8508abfc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577737893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3577737893
Directory /workspace/5.spi_device_stress_all/latest


Test location /workspace/coverage/default/5.spi_device_tpm_all.1239092934
Short name T678
Test name
Test status
Simulation time 22958809977 ps
CPU time 39.46 seconds
Started Aug 13 05:49:27 PM PDT 24
Finished Aug 13 05:50:07 PM PDT 24
Peak memory 216716 kb
Host smart-5757e5db-d565-40a0-a564-5a21ae065487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239092934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1239092934
Directory /workspace/5.spi_device_tpm_all/latest


Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3188112271
Short name T7
Test name
Test status
Simulation time 1255824002 ps
CPU time 5.76 seconds
Started Aug 13 05:49:27 PM PDT 24
Finished Aug 13 05:49:33 PM PDT 24
Peak memory 216400 kb
Host smart-fa7049c2-2f23-40e6-af3d-782b84d2476f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188112271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3188112271
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/5.spi_device_tpm_rw.1341917817
Short name T815
Test name
Test status
Simulation time 115688757 ps
CPU time 1.89 seconds
Started Aug 13 05:49:27 PM PDT 24
Finished Aug 13 05:49:29 PM PDT 24
Peak memory 216476 kb
Host smart-aff506bf-5968-46ed-928d-5ab27db1da46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341917817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1341917817
Directory /workspace/5.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1432324744
Short name T462
Test name
Test status
Simulation time 88080612 ps
CPU time 0.79 seconds
Started Aug 13 05:49:26 PM PDT 24
Finished Aug 13 05:49:27 PM PDT 24
Peak memory 206100 kb
Host smart-16de8fdf-0afe-4944-bff4-e8135f766dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432324744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1432324744
Directory /workspace/5.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/5.spi_device_upload.493556946
Short name T547
Test name
Test status
Simulation time 6354317015 ps
CPU time 8.41 seconds
Started Aug 13 05:49:33 PM PDT 24
Finished Aug 13 05:49:41 PM PDT 24
Peak memory 232964 kb
Host smart-e4ed6e5b-c4fc-4de7-a5c5-0767d70ec3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493556946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.493556946
Directory /workspace/5.spi_device_upload/latest


Test location /workspace/coverage/default/6.spi_device_alert_test.1672703615
Short name T947
Test name
Test status
Simulation time 13562162 ps
CPU time 0.74 seconds
Started Aug 13 05:49:33 PM PDT 24
Finished Aug 13 05:49:34 PM PDT 24
Peak memory 204912 kb
Host smart-064641dd-3c6c-48d5-ad8e-0e04415105f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672703615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
672703615
Directory /workspace/6.spi_device_alert_test/latest


Test location /workspace/coverage/default/6.spi_device_cfg_cmd.4149552304
Short name T496
Test name
Test status
Simulation time 417307162 ps
CPU time 2.31 seconds
Started Aug 13 05:49:31 PM PDT 24
Finished Aug 13 05:49:33 PM PDT 24
Peak memory 232468 kb
Host smart-1d32c311-4fb0-435a-ac83-c0ae0d68aa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149552304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.4149552304
Directory /workspace/6.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/6.spi_device_csb_read.1149415147
Short name T616
Test name
Test status
Simulation time 16193374 ps
CPU time 0.8 seconds
Started Aug 13 05:49:27 PM PDT 24
Finished Aug 13 05:49:28 PM PDT 24
Peak memory 206584 kb
Host smart-197afce0-ad53-4f9c-aca5-4aba468ea03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149415147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1149415147
Directory /workspace/6.spi_device_csb_read/latest


Test location /workspace/coverage/default/6.spi_device_flash_all.1478656068
Short name T997
Test name
Test status
Simulation time 2943574073 ps
CPU time 53.15 seconds
Started Aug 13 05:49:33 PM PDT 24
Finished Aug 13 05:50:26 PM PDT 24
Peak memory 251772 kb
Host smart-cdbf6bfc-5d0f-4503-b284-64b3f9dfb02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478656068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1478656068
Directory /workspace/6.spi_device_flash_all/latest


Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3135424340
Short name T1009
Test name
Test status
Simulation time 70688252119 ps
CPU time 132.35 seconds
Started Aug 13 05:49:32 PM PDT 24
Finished Aug 13 05:51:45 PM PDT 24
Peak memory 250504 kb
Host smart-6ae6b2f4-63f1-4061-a6d7-89b1da3c2535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135424340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3135424340
Directory /workspace/6.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3951018063
Short name T739
Test name
Test status
Simulation time 182817667176 ps
CPU time 459.57 seconds
Started Aug 13 05:49:30 PM PDT 24
Finished Aug 13 05:57:10 PM PDT 24
Peak memory 266140 kb
Host smart-7550202f-4e74-43db-87c6-f4ebd1ecd7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951018063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3951018063
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/6.spi_device_flash_mode.3025162397
Short name T313
Test name
Test status
Simulation time 2107589753 ps
CPU time 12.19 seconds
Started Aug 13 05:49:35 PM PDT 24
Finished Aug 13 05:49:48 PM PDT 24
Peak memory 241032 kb
Host smart-77686b5f-8bb9-4b9f-b265-35be10a31688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025162397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3025162397
Directory /workspace/6.spi_device_flash_mode/latest


Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3772704973
Short name T95
Test name
Test status
Simulation time 11275314110 ps
CPU time 61.16 seconds
Started Aug 13 05:49:32 PM PDT 24
Finished Aug 13 05:50:33 PM PDT 24
Peak memory 257132 kb
Host smart-dc573fcf-171f-4207-b1e0-29a096c1ec00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772704973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3772704973
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/6.spi_device_intercept.3130661485
Short name T491
Test name
Test status
Simulation time 2737857534 ps
CPU time 9.55 seconds
Started Aug 13 05:49:32 PM PDT 24
Finished Aug 13 05:49:42 PM PDT 24
Peak memory 232992 kb
Host smart-7ec801c6-4a18-47b8-9e92-c1cbf01dcaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130661485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3130661485
Directory /workspace/6.spi_device_intercept/latest


Test location /workspace/coverage/default/6.spi_device_mailbox.597366789
Short name T905
Test name
Test status
Simulation time 3989795064 ps
CPU time 23.78 seconds
Started Aug 13 05:49:35 PM PDT 24
Finished Aug 13 05:49:59 PM PDT 24
Peak memory 239276 kb
Host smart-fa1a3fc7-baf7-4a74-a2ef-eb687b265e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597366789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.597366789
Directory /workspace/6.spi_device_mailbox/latest


Test location /workspace/coverage/default/6.spi_device_mem_parity.2212827741
Short name T667
Test name
Test status
Simulation time 50348323 ps
CPU time 1 seconds
Started Aug 13 05:49:24 PM PDT 24
Finished Aug 13 05:49:26 PM PDT 24
Peak memory 218016 kb
Host smart-b120103a-2ca8-42a8-836e-e7cd2f58eba4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212827741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2212827741
Directory /workspace/6.spi_device_mem_parity/latest


Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2576651436
Short name T913
Test name
Test status
Simulation time 431280652 ps
CPU time 3.51 seconds
Started Aug 13 05:49:33 PM PDT 24
Finished Aug 13 05:49:36 PM PDT 24
Peak memory 232896 kb
Host smart-0a2c2d43-6f97-48e8-acef-33731a8d4085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576651436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2576651436
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2380125923
Short name T715
Test name
Test status
Simulation time 335378977 ps
CPU time 3.01 seconds
Started Aug 13 05:49:33 PM PDT 24
Finished Aug 13 05:49:36 PM PDT 24
Peak memory 224660 kb
Host smart-81d49835-56dc-4c0c-8e01-2e279a0314e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380125923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2380125923
Directory /workspace/6.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1734552632
Short name T5
Test name
Test status
Simulation time 1280331733 ps
CPU time 7.42 seconds
Started Aug 13 05:49:31 PM PDT 24
Finished Aug 13 05:49:39 PM PDT 24
Peak memory 219000 kb
Host smart-3ff6a72f-21a1-4dee-be85-7d8769ab3570
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1734552632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1734552632
Directory /workspace/6.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/6.spi_device_stress_all.2581572207
Short name T460
Test name
Test status
Simulation time 325343897697 ps
CPU time 300.71 seconds
Started Aug 13 05:49:35 PM PDT 24
Finished Aug 13 05:54:36 PM PDT 24
Peak memory 250420 kb
Host smart-c008815d-4186-4b82-968d-176074c0cab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581572207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2581572207
Directory /workspace/6.spi_device_stress_all/latest


Test location /workspace/coverage/default/6.spi_device_tpm_all.2883793809
Short name T718
Test name
Test status
Simulation time 1716900591 ps
CPU time 12.5 seconds
Started Aug 13 05:49:30 PM PDT 24
Finished Aug 13 05:49:42 PM PDT 24
Peak memory 216524 kb
Host smart-ae4111dc-60c5-404f-adc5-76f5dba9fde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883793809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2883793809
Directory /workspace/6.spi_device_tpm_all/latest


Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3666958186
Short name T30
Test name
Test status
Simulation time 4426513600 ps
CPU time 6.55 seconds
Started Aug 13 05:49:32 PM PDT 24
Finished Aug 13 05:49:39 PM PDT 24
Peak memory 216524 kb
Host smart-a75d4890-43da-457c-9be1-c8bb4ade2f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666958186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3666958186
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/6.spi_device_tpm_rw.2665763685
Short name T669
Test name
Test status
Simulation time 579217894 ps
CPU time 4.85 seconds
Started Aug 13 05:49:32 PM PDT 24
Finished Aug 13 05:49:37 PM PDT 24
Peak memory 216508 kb
Host smart-a3850e51-eda4-4cf7-80d6-a290117f0158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665763685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2665763685
Directory /workspace/6.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3901181337
Short name T341
Test name
Test status
Simulation time 57399755 ps
CPU time 0.88 seconds
Started Aug 13 05:49:26 PM PDT 24
Finished Aug 13 05:49:27 PM PDT 24
Peak memory 206108 kb
Host smart-9665178e-28f6-48a4-bfbd-599c30b9316a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901181337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3901181337
Directory /workspace/6.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/6.spi_device_upload.3184120532
Short name T975
Test name
Test status
Simulation time 1504083088 ps
CPU time 3.37 seconds
Started Aug 13 05:49:35 PM PDT 24
Finished Aug 13 05:49:39 PM PDT 24
Peak memory 224640 kb
Host smart-ea0a1ac9-1ad1-4bd9-aaf4-4f124dd7f162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184120532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3184120532
Directory /workspace/6.spi_device_upload/latest


Test location /workspace/coverage/default/7.spi_device_alert_test.1132259759
Short name T662
Test name
Test status
Simulation time 27955241 ps
CPU time 0.74 seconds
Started Aug 13 05:49:46 PM PDT 24
Finished Aug 13 05:49:47 PM PDT 24
Peak memory 205548 kb
Host smart-64232ed0-ff34-45f1-a35f-b5ff49c9f1bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132259759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
132259759
Directory /workspace/7.spi_device_alert_test/latest


Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1774475573
Short name T784
Test name
Test status
Simulation time 1854138931 ps
CPU time 6.38 seconds
Started Aug 13 05:49:40 PM PDT 24
Finished Aug 13 05:49:46 PM PDT 24
Peak memory 232912 kb
Host smart-6cc2b912-6d6c-41dc-b003-7e9a82ee4cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774475573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1774475573
Directory /workspace/7.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/7.spi_device_csb_read.3689008533
Short name T408
Test name
Test status
Simulation time 52863921 ps
CPU time 0.8 seconds
Started Aug 13 05:49:41 PM PDT 24
Finished Aug 13 05:49:42 PM PDT 24
Peak memory 206588 kb
Host smart-b6608d86-98d2-41ba-9807-8972f196dc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689008533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3689008533
Directory /workspace/7.spi_device_csb_read/latest


Test location /workspace/coverage/default/7.spi_device_flash_all.439137358
Short name T1015
Test name
Test status
Simulation time 11083184789 ps
CPU time 42.2 seconds
Started Aug 13 05:49:39 PM PDT 24
Finished Aug 13 05:50:21 PM PDT 24
Peak memory 237128 kb
Host smart-d87fe5c2-56b3-4724-a320-ddaa78820375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439137358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.439137358
Directory /workspace/7.spi_device_flash_all/latest


Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1984163523
Short name T961
Test name
Test status
Simulation time 298356783390 ps
CPU time 661.49 seconds
Started Aug 13 05:49:39 PM PDT 24
Finished Aug 13 06:00:40 PM PDT 24
Peak memory 273616 kb
Host smart-18aedd49-bf7e-49cb-82b5-6bdc43f09b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984163523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1984163523
Directory /workspace/7.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1886222662
Short name T289
Test name
Test status
Simulation time 15292420364 ps
CPU time 98.7 seconds
Started Aug 13 05:49:47 PM PDT 24
Finished Aug 13 05:51:26 PM PDT 24
Peak memory 249416 kb
Host smart-4c083e9c-70cd-4d9b-ae38-7b8fd9f3a41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886222662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1886222662
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/7.spi_device_flash_mode.2717841106
Short name T477
Test name
Test status
Simulation time 3593802941 ps
CPU time 18.7 seconds
Started Aug 13 05:49:39 PM PDT 24
Finished Aug 13 05:49:57 PM PDT 24
Peak memory 241024 kb
Host smart-d25888b7-ab2a-4c2c-a45a-718ff4b06197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717841106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2717841106
Directory /workspace/7.spi_device_flash_mode/latest


Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2993815660
Short name T1004
Test name
Test status
Simulation time 3936452693 ps
CPU time 25.24 seconds
Started Aug 13 05:49:40 PM PDT 24
Finished Aug 13 05:50:05 PM PDT 24
Peak memory 257272 kb
Host smart-d802b874-8f77-4b70-8a14-4b16a528eb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993815660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2993815660
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/7.spi_device_intercept.107222574
Short name T582
Test name
Test status
Simulation time 313798708 ps
CPU time 6.11 seconds
Started Aug 13 05:49:40 PM PDT 24
Finished Aug 13 05:49:46 PM PDT 24
Peak memory 224636 kb
Host smart-0cf2e966-f5b4-4932-ac69-c0cf6cafeeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107222574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.107222574
Directory /workspace/7.spi_device_intercept/latest


Test location /workspace/coverage/default/7.spi_device_mailbox.3307029561
Short name T600
Test name
Test status
Simulation time 46102026085 ps
CPU time 74.93 seconds
Started Aug 13 05:49:40 PM PDT 24
Finished Aug 13 05:50:56 PM PDT 24
Peak memory 227928 kb
Host smart-513bcf40-f3e4-4982-9dce-7386ea259234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307029561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3307029561
Directory /workspace/7.spi_device_mailbox/latest


Test location /workspace/coverage/default/7.spi_device_mem_parity.1255395131
Short name T664
Test name
Test status
Simulation time 34603228 ps
CPU time 1.18 seconds
Started Aug 13 05:49:40 PM PDT 24
Finished Aug 13 05:49:41 PM PDT 24
Peak memory 216756 kb
Host smart-cb4d78fd-f1b4-4e70-a037-6557b1075454
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255395131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1255395131
Directory /workspace/7.spi_device_mem_parity/latest


Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1856041739
Short name T435
Test name
Test status
Simulation time 140658154 ps
CPU time 4.12 seconds
Started Aug 13 05:49:41 PM PDT 24
Finished Aug 13 05:49:46 PM PDT 24
Peak memory 224616 kb
Host smart-072a3344-517a-4763-b07b-f8d2894a14f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856041739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1856041739
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3785545651
Short name T507
Test name
Test status
Simulation time 57630929 ps
CPU time 2.41 seconds
Started Aug 13 05:49:41 PM PDT 24
Finished Aug 13 05:49:44 PM PDT 24
Peak memory 224592 kb
Host smart-994e7f5a-439d-4ca1-8e06-da6318d12d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785545651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3785545651
Directory /workspace/7.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3899588989
Short name T4
Test name
Test status
Simulation time 831699001 ps
CPU time 3.47 seconds
Started Aug 13 05:49:38 PM PDT 24
Finished Aug 13 05:49:42 PM PDT 24
Peak memory 220124 kb
Host smart-706f63a7-b1a1-4c0b-a743-c8ae36bc43ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3899588989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3899588989
Directory /workspace/7.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/7.spi_device_stress_all.3830098687
Short name T1024
Test name
Test status
Simulation time 17761888577 ps
CPU time 217.38 seconds
Started Aug 13 05:49:48 PM PDT 24
Finished Aug 13 05:53:26 PM PDT 24
Peak memory 256636 kb
Host smart-5c49ef73-282c-49f7-8f12-58a42ca1e9a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830098687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3830098687
Directory /workspace/7.spi_device_stress_all/latest


Test location /workspace/coverage/default/7.spi_device_tpm_all.2309774714
Short name T719
Test name
Test status
Simulation time 2523890623 ps
CPU time 7.75 seconds
Started Aug 13 05:49:39 PM PDT 24
Finished Aug 13 05:49:47 PM PDT 24
Peak memory 216568 kb
Host smart-e022478e-bea6-4166-804d-f86a8845ffce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309774714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2309774714
Directory /workspace/7.spi_device_tpm_all/latest


Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1064033029
Short name T444
Test name
Test status
Simulation time 14678043543 ps
CPU time 12.75 seconds
Started Aug 13 05:49:41 PM PDT 24
Finished Aug 13 05:49:53 PM PDT 24
Peak memory 216552 kb
Host smart-c30066c5-d86e-4de0-b49b-e4819eaa5b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064033029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1064033029
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/7.spi_device_tpm_rw.846670439
Short name T2
Test name
Test status
Simulation time 35307586 ps
CPU time 0.71 seconds
Started Aug 13 05:49:41 PM PDT 24
Finished Aug 13 05:49:42 PM PDT 24
Peak memory 205644 kb
Host smart-ab073450-602d-4192-abbb-8a07d274045c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846670439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.846670439
Directory /workspace/7.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1693831697
Short name T649
Test name
Test status
Simulation time 87683972 ps
CPU time 0.93 seconds
Started Aug 13 05:49:40 PM PDT 24
Finished Aug 13 05:49:41 PM PDT 24
Peak memory 206152 kb
Host smart-57e52588-f451-446c-815c-032c9a548ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693831697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1693831697
Directory /workspace/7.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/7.spi_device_upload.1997429649
Short name T857
Test name
Test status
Simulation time 142748466 ps
CPU time 2.8 seconds
Started Aug 13 05:49:40 PM PDT 24
Finished Aug 13 05:49:43 PM PDT 24
Peak memory 224724 kb
Host smart-623609c9-27f1-425f-a5b1-015f43140524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997429649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1997429649
Directory /workspace/7.spi_device_upload/latest


Test location /workspace/coverage/default/8.spi_device_alert_test.3891342703
Short name T24
Test name
Test status
Simulation time 115723953 ps
CPU time 0.73 seconds
Started Aug 13 05:49:47 PM PDT 24
Finished Aug 13 05:49:47 PM PDT 24
Peak memory 204956 kb
Host smart-1c61950c-4d03-4374-a3b8-49959d5faabe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891342703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
891342703
Directory /workspace/8.spi_device_alert_test/latest


Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1426209637
Short name T605
Test name
Test status
Simulation time 90647625 ps
CPU time 4.08 seconds
Started Aug 13 05:49:46 PM PDT 24
Finished Aug 13 05:49:50 PM PDT 24
Peak memory 232836 kb
Host smart-d918466a-a1df-4594-a445-fb622e135ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426209637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1426209637
Directory /workspace/8.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/8.spi_device_csb_read.2396461504
Short name T912
Test name
Test status
Simulation time 31924459 ps
CPU time 0.83 seconds
Started Aug 13 05:49:48 PM PDT 24
Finished Aug 13 05:49:48 PM PDT 24
Peak memory 206624 kb
Host smart-4c08fb47-3fc1-489d-baa0-93dff25290ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396461504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2396461504
Directory /workspace/8.spi_device_csb_read/latest


Test location /workspace/coverage/default/8.spi_device_flash_all.3845893061
Short name T926
Test name
Test status
Simulation time 21283398634 ps
CPU time 76.57 seconds
Started Aug 13 05:49:47 PM PDT 24
Finished Aug 13 05:51:04 PM PDT 24
Peak memory 250404 kb
Host smart-c500cabc-88f1-4dbc-9c3e-113c7b33174a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845893061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3845893061
Directory /workspace/8.spi_device_flash_all/latest


Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3693513124
Short name T476
Test name
Test status
Simulation time 130347957312 ps
CPU time 170.28 seconds
Started Aug 13 05:49:49 PM PDT 24
Finished Aug 13 05:52:39 PM PDT 24
Peak memory 253300 kb
Host smart-7a3508c9-9af7-4779-9856-6e6924f1bf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693513124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3693513124
Directory /workspace/8.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1462472011
Short name T451
Test name
Test status
Simulation time 234533366995 ps
CPU time 196.08 seconds
Started Aug 13 05:49:48 PM PDT 24
Finished Aug 13 05:53:05 PM PDT 24
Peak memory 254776 kb
Host smart-b23dd7d5-6446-4acf-af92-f0477eefec34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462472011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1462472011
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/8.spi_device_flash_mode.1728182539
Short name T314
Test name
Test status
Simulation time 186799936 ps
CPU time 8.17 seconds
Started Aug 13 05:49:50 PM PDT 24
Finished Aug 13 05:49:58 PM PDT 24
Peak memory 234972 kb
Host smart-947dac1b-4fee-4d1a-be58-a68c5d14c93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728182539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1728182539
Directory /workspace/8.spi_device_flash_mode/latest


Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3485057542
Short name T561
Test name
Test status
Simulation time 564855921 ps
CPU time 14.59 seconds
Started Aug 13 05:49:48 PM PDT 24
Finished Aug 13 05:50:03 PM PDT 24
Peak memory 234400 kb
Host smart-ec0c3731-71f0-467d-a6e4-4c36d7d70405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485057542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3485057542
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/8.spi_device_intercept.1285824408
Short name T989
Test name
Test status
Simulation time 1403450710 ps
CPU time 14.34 seconds
Started Aug 13 05:49:47 PM PDT 24
Finished Aug 13 05:50:02 PM PDT 24
Peak memory 224664 kb
Host smart-b5d044c9-c373-43de-836b-6b7e74ba34c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285824408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1285824408
Directory /workspace/8.spi_device_intercept/latest


Test location /workspace/coverage/default/8.spi_device_mailbox.2656208364
Short name T225
Test name
Test status
Simulation time 1834289605 ps
CPU time 9.13 seconds
Started Aug 13 05:49:47 PM PDT 24
Finished Aug 13 05:49:56 PM PDT 24
Peak memory 223228 kb
Host smart-e90a774e-3b9f-4d98-b6d9-5e1fcd2290fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656208364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2656208364
Directory /workspace/8.spi_device_mailbox/latest


Test location /workspace/coverage/default/8.spi_device_mem_parity.846140190
Short name T41
Test name
Test status
Simulation time 91488389 ps
CPU time 1.09 seconds
Started Aug 13 05:49:45 PM PDT 24
Finished Aug 13 05:49:46 PM PDT 24
Peak memory 216716 kb
Host smart-fbb7b44c-8c5d-4e74-941b-8c4c7d239737
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846140190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.846140190
Directory /workspace/8.spi_device_mem_parity/latest


Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.296165688
Short name T627
Test name
Test status
Simulation time 447072420 ps
CPU time 3.11 seconds
Started Aug 13 05:49:46 PM PDT 24
Finished Aug 13 05:49:49 PM PDT 24
Peak memory 224716 kb
Host smart-400b0d3d-ccc1-4824-9ac8-fbfcc477a8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296165688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
296165688
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3224636287
Short name T13
Test name
Test status
Simulation time 3176388514 ps
CPU time 9.2 seconds
Started Aug 13 05:49:50 PM PDT 24
Finished Aug 13 05:49:59 PM PDT 24
Peak memory 232980 kb
Host smart-528aff68-7d9a-48a5-9594-bc1e77c8c1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224636287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3224636287
Directory /workspace/8.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.439518215
Short name T776
Test name
Test status
Simulation time 4255849407 ps
CPU time 8.55 seconds
Started Aug 13 05:49:44 PM PDT 24
Finished Aug 13 05:49:52 PM PDT 24
Peak memory 222896 kb
Host smart-f1a559c3-c1ea-4d48-a18c-3f74bab7ca12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=439518215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.439518215
Directory /workspace/8.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/8.spi_device_stress_all.702669869
Short name T981
Test name
Test status
Simulation time 5440787341 ps
CPU time 51.93 seconds
Started Aug 13 05:49:48 PM PDT 24
Finished Aug 13 05:50:40 PM PDT 24
Peak memory 224796 kb
Host smart-4b3e97aa-74e1-4e2b-b807-a73f062d7ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702669869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.702669869
Directory /workspace/8.spi_device_stress_all/latest


Test location /workspace/coverage/default/8.spi_device_tpm_all.28007801
Short name T1023
Test name
Test status
Simulation time 20055579 ps
CPU time 0.75 seconds
Started Aug 13 05:49:46 PM PDT 24
Finished Aug 13 05:49:47 PM PDT 24
Peak memory 205756 kb
Host smart-5be433d0-93e0-4f66-ad99-a1de86fb0af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28007801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.28007801
Directory /workspace/8.spi_device_tpm_all/latest


Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.4081144613
Short name T640
Test name
Test status
Simulation time 466429024 ps
CPU time 2.75 seconds
Started Aug 13 05:49:46 PM PDT 24
Finished Aug 13 05:49:49 PM PDT 24
Peak memory 216544 kb
Host smart-f8939dd3-6777-4a74-a54b-686980fceb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081144613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.4081144613
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/8.spi_device_tpm_rw.1243239883
Short name T829
Test name
Test status
Simulation time 74036059 ps
CPU time 1.03 seconds
Started Aug 13 05:49:47 PM PDT 24
Finished Aug 13 05:49:48 PM PDT 24
Peak memory 208116 kb
Host smart-c40d2f5c-2c4e-478d-a7b9-810c9b52027e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243239883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1243239883
Directory /workspace/8.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3394721573
Short name T86
Test name
Test status
Simulation time 14159034 ps
CPU time 0.7 seconds
Started Aug 13 05:49:47 PM PDT 24
Finished Aug 13 05:49:48 PM PDT 24
Peak memory 205676 kb
Host smart-0da012d8-ebb2-4962-8f39-7080c9a18f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394721573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3394721573
Directory /workspace/8.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/8.spi_device_upload.1485557265
Short name T938
Test name
Test status
Simulation time 6971184538 ps
CPU time 18.88 seconds
Started Aug 13 05:49:50 PM PDT 24
Finished Aug 13 05:50:09 PM PDT 24
Peak memory 249340 kb
Host smart-d32fe372-5099-473e-8da3-73ad1eed4c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485557265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1485557265
Directory /workspace/8.spi_device_upload/latest


Test location /workspace/coverage/default/9.spi_device_alert_test.406252497
Short name T870
Test name
Test status
Simulation time 12289132 ps
CPU time 0.73 seconds
Started Aug 13 05:49:56 PM PDT 24
Finished Aug 13 05:49:57 PM PDT 24
Peak memory 204924 kb
Host smart-35ae3d63-bfc3-4a31-96db-66b393fcb815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406252497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.406252497
Directory /workspace/9.spi_device_alert_test/latest


Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1181048698
Short name T878
Test name
Test status
Simulation time 401040226 ps
CPU time 2.18 seconds
Started Aug 13 05:49:55 PM PDT 24
Finished Aug 13 05:49:58 PM PDT 24
Peak memory 224704 kb
Host smart-b07d9779-fe0c-42d8-9a2a-dbeb30011d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181048698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1181048698
Directory /workspace/9.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/9.spi_device_csb_read.3453818162
Short name T355
Test name
Test status
Simulation time 16320699 ps
CPU time 0.75 seconds
Started Aug 13 05:49:47 PM PDT 24
Finished Aug 13 05:49:48 PM PDT 24
Peak memory 205584 kb
Host smart-408eca46-743b-4483-88c5-1f313e308a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453818162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3453818162
Directory /workspace/9.spi_device_csb_read/latest


Test location /workspace/coverage/default/9.spi_device_flash_all.1072332257
Short name T307
Test name
Test status
Simulation time 201319777291 ps
CPU time 362.01 seconds
Started Aug 13 05:49:57 PM PDT 24
Finished Aug 13 05:55:59 PM PDT 24
Peak memory 249360 kb
Host smart-337776e5-43bd-4241-835f-e7e7b31880ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072332257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1072332257
Directory /workspace/9.spi_device_flash_all/latest


Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4145711861
Short name T536
Test name
Test status
Simulation time 33415860605 ps
CPU time 248.42 seconds
Started Aug 13 05:49:57 PM PDT 24
Finished Aug 13 05:54:06 PM PDT 24
Peak memory 257580 kb
Host smart-2175623a-578c-4c70-9018-c74473d8e583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145711861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4145711861
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/9.spi_device_flash_mode.78457165
Short name T315
Test name
Test status
Simulation time 284262641 ps
CPU time 8.24 seconds
Started Aug 13 05:49:56 PM PDT 24
Finished Aug 13 05:50:05 PM PDT 24
Peak memory 232904 kb
Host smart-f4177ed4-f6c3-4df6-98c5-b53f1f35492d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78457165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.78457165
Directory /workspace/9.spi_device_flash_mode/latest


Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.500871593
Short name T176
Test name
Test status
Simulation time 1310570738 ps
CPU time 18.25 seconds
Started Aug 13 05:49:55 PM PDT 24
Finished Aug 13 05:50:14 PM PDT 24
Peak memory 255560 kb
Host smart-533383eb-e3c0-4526-b14e-6b7a092aa374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500871593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
500871593
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/9.spi_device_intercept.3058491884
Short name T192
Test name
Test status
Simulation time 133666311 ps
CPU time 3.97 seconds
Started Aug 13 05:49:57 PM PDT 24
Finished Aug 13 05:50:01 PM PDT 24
Peak memory 224680 kb
Host smart-b17478cc-c0f4-4d02-bf26-8091840b13aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058491884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3058491884
Directory /workspace/9.spi_device_intercept/latest


Test location /workspace/coverage/default/9.spi_device_mailbox.2033367600
Short name T498
Test name
Test status
Simulation time 5207368234 ps
CPU time 27.35 seconds
Started Aug 13 05:49:57 PM PDT 24
Finished Aug 13 05:50:24 PM PDT 24
Peak memory 237824 kb
Host smart-a16f8556-4f50-4e5a-9662-66137d6e5228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033367600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2033367600
Directory /workspace/9.spi_device_mailbox/latest


Test location /workspace/coverage/default/9.spi_device_mem_parity.2855253762
Short name T946
Test name
Test status
Simulation time 122995912 ps
CPU time 1.13 seconds
Started Aug 13 05:49:57 PM PDT 24
Finished Aug 13 05:49:58 PM PDT 24
Peak memory 216768 kb
Host smart-6002e5ed-a65e-4ff6-9a4d-ab2567d364a4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855253762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2855253762
Directory /workspace/9.spi_device_mem_parity/latest


Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1488011257
Short name T809
Test name
Test status
Simulation time 12176652832 ps
CPU time 5.57 seconds
Started Aug 13 05:49:57 PM PDT 24
Finished Aug 13 05:50:02 PM PDT 24
Peak memory 232980 kb
Host smart-1475cfc3-0f3a-4975-8b56-c2ff783bf660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488011257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1488011257
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2390384520
Short name T972
Test name
Test status
Simulation time 34677423997 ps
CPU time 16.56 seconds
Started Aug 13 05:49:57 PM PDT 24
Finished Aug 13 05:50:14 PM PDT 24
Peak memory 224740 kb
Host smart-19ea9e88-966e-45f6-860f-69efb2843b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390384520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2390384520
Directory /workspace/9.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1080942086
Short name T999
Test name
Test status
Simulation time 395803038 ps
CPU time 6.87 seconds
Started Aug 13 05:49:55 PM PDT 24
Finished Aug 13 05:50:02 PM PDT 24
Peak memory 222260 kb
Host smart-7c96d07d-e15a-4594-af8d-1dca4f2e3ff2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1080942086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1080942086
Directory /workspace/9.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/9.spi_device_stress_all.2099588172
Short name T1008
Test name
Test status
Simulation time 48503487 ps
CPU time 0.99 seconds
Started Aug 13 05:49:53 PM PDT 24
Finished Aug 13 05:49:54 PM PDT 24
Peak memory 206580 kb
Host smart-1578b388-8b40-4df7-9d2a-ee8a31bade41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099588172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2099588172
Directory /workspace/9.spi_device_stress_all/latest


Test location /workspace/coverage/default/9.spi_device_tpm_all.68705799
Short name T724
Test name
Test status
Simulation time 12138977477 ps
CPU time 8.09 seconds
Started Aug 13 05:49:58 PM PDT 24
Finished Aug 13 05:50:06 PM PDT 24
Peak memory 216688 kb
Host smart-6a614166-10b7-4d35-a5b8-81cade1aec75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68705799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.68705799
Directory /workspace/9.spi_device_tpm_all/latest


Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3936751751
Short name T449
Test name
Test status
Simulation time 4316297936 ps
CPU time 3.06 seconds
Started Aug 13 05:49:55 PM PDT 24
Finished Aug 13 05:49:59 PM PDT 24
Peak memory 216544 kb
Host smart-7f1b0c58-f981-47c9-9823-fefdc215f41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936751751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3936751751
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/9.spi_device_tpm_rw.2506682424
Short name T700
Test name
Test status
Simulation time 329152053 ps
CPU time 2.1 seconds
Started Aug 13 05:49:57 PM PDT 24
Finished Aug 13 05:49:59 PM PDT 24
Peak memory 216540 kb
Host smart-3a436bde-82df-4c68-915a-ca7140d891fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506682424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2506682424
Directory /workspace/9.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2963947325
Short name T656
Test name
Test status
Simulation time 213951166 ps
CPU time 0.8 seconds
Started Aug 13 05:49:57 PM PDT 24
Finished Aug 13 05:49:58 PM PDT 24
Peak memory 206120 kb
Host smart-1f271313-cf4e-43a3-8bd6-43cb522e9557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963947325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2963947325
Directory /workspace/9.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/9.spi_device_upload.3170431344
Short name T943
Test name
Test status
Simulation time 3021688476 ps
CPU time 5.45 seconds
Started Aug 13 05:49:57 PM PDT 24
Finished Aug 13 05:50:02 PM PDT 24
Peak memory 232996 kb
Host smart-a7f68933-565c-4c48-a294-da7b1c78c8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170431344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3170431344
Directory /workspace/9.spi_device_upload/latest
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