Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2369323	1			T2	1372		T3	1		T4	4960
all_values[1]	2369323	1			T2	1372		T3	1		T4	4960
all_values[2]	2369323	1			T2	1372		T3	1		T4	4960
all_values[3]	2369323	1			T2	1372		T3	1		T4	4960
all_values[4]	2369323	1			T2	1372		T3	1		T4	4960
all_values[5]	2369323	1			T2	1372		T3	1		T4	4960
all_values[6]	2369323	1			T2	1372		T3	1		T4	4960
all_values[7]	2369323	1			T2	1372		T3	1		T4	4960

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18500061

1

T2

10976

T3

8

T4

39680

auto[1]

454523

1

T8

66

T16

29

T17

74

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18929367

1

T2

10976

T3

8

T4

39513

auto[1]

25217

1

T4

167

T7

30

T8

64

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2260411	1			T2	1372		T3	1		T4	4835
all_values[0]	auto[0]	auto[1]	11264	1			T4	125		T7	13		T8	8
all_values[0]	auto[1]	auto[0]	96737	1			T8	4		T16	1		T17	9
all_values[0]	auto[1]	auto[1]	911	1			T8	2		T17	4		T19	2
all_values[1]	auto[0]	auto[0]	2299927	1			T2	1372		T3	1		T4	4926
all_values[1]	auto[0]	auto[1]	7305	1			T4	34		T7	13		T8	4
all_values[1]	auto[1]	auto[0]	61652	1			T8	5		T16	2		T17	2
all_values[1]	auto[1]	auto[1]	439	1			T8	3		T16	4		T17	6
all_values[2]	auto[0]	auto[0]	2337740	1			T2	1372		T3	1		T4	4952
all_values[2]	auto[0]	auto[1]	3139	1			T4	8		T7	4		T8	7
all_values[2]	auto[1]	auto[0]	28186	1			T8	1		T17	7		T19	2
all_values[2]	auto[1]	auto[1]	258	1			T8	3		T17	2		T19	2
all_values[3]	auto[0]	auto[0]	2314233	1			T2	1372		T3	1		T4	4960
all_values[3]	auto[0]	auto[1]	206	1			T8	4		T17	6		T20	5
all_values[3]	auto[1]	auto[0]	54694	1			T8	4		T16	4		T17	6
all_values[3]	auto[1]	auto[1]	190	1			T8	6		T16	1		T17	6
all_values[4]	auto[0]	auto[0]	2289049	1			T2	1372		T3	1		T4	4960
all_values[4]	auto[0]	auto[1]	211	1			T8	2		T16	3		T17	7
all_values[4]	auto[1]	auto[0]	79861	1			T8	5		T16	2		T17	7
all_values[4]	auto[1]	auto[1]	202	1			T8	4		T16	3		T17	2
all_values[5]	auto[0]	auto[0]	2309860	1			T2	1372		T3	1		T4	4960
all_values[5]	auto[0]	auto[1]	155	1			T8	5		T16	2		T17	4
all_values[5]	auto[1]	auto[0]	59137	1			T8	6		T16	1		T17	6
all_values[5]	auto[1]	auto[1]	171	1			T8	2		T17	2		T19	2
all_values[6]	auto[0]	auto[0]	2304629	1			T2	1372		T3	1		T4	4960
all_values[6]	auto[0]	auto[1]	202	1			T8	1		T16	2		T17	6
all_values[6]	auto[1]	auto[0]	64287	1			T8	5		T16	1		T17	7
all_values[6]	auto[1]	auto[1]	205	1			T8	8		T16	3		T17	3
all_values[7]	auto[0]	auto[0]	2361549	1			T2	1372		T3	1		T4	4960
all_values[7]	auto[0]	auto[1]	181	1			T8	3		T17	7		T19	1
all_values[7]	auto[1]	auto[0]	7415	1			T8	6		T16	4		T19	1
all_values[7]	auto[1]	auto[1]	178	1			T8	2		T16	3		T17	5