Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33899	1			T2	108		T4	122		T6	2
auto[SpiFlashAddrCfg]	7593	1			T2	37		T4	22		T7	20
auto[SpiFlashAddr3b]	9263	1			T2	54		T3	8		T4	29
auto[SpiFlashAddr4b]	7609	1			T2	41		T3	2		T4	20

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33284

1

T2

134

T3

10

T4

104

auto[1]

25080

1

T2

106

T4

89

T7

47

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31124

1

T2

111

T3

6

T4

132

auto[1]

27240

1

T2

129

T3

4

T4

61

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38584	1			T2	118		T3	6		T4	137
values[1]	1140	1			T2	9		T4	3		T7	4
values[2]	1499	1			T2	4		T4	1		T12	1
values[3]	1432	1			T2	12		T4	1		T7	2
values[4]	1543	1			T2	16		T4	6		T7	1
values[5]	1349	1			T2	8		T4	7		T7	5
values[6]	1492	1			T2	11		T4	5		T7	7
values[7]	1458	1			T2	9		T4	1		T7	5
values[8]	9867	1			T2	53		T3	4		T4	32

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35063

1

T2

240

T3

10

T6

2

auto[1]

23301

1

T4

193

T12

20

T42

172

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55249

1

T2

226

T3

10

T4

177

write

3115

1

T2

14

T4

16

T7

5

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19017

1

T2

112

T3

4

T4

69

valids[0x1]

39347

1

T2

128

T3

6

T4

124

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1494	1			T2	9		T4	6		T7	1
internal_process_ops[0x5a]	1613	1			T2	7		T3	4		T4	7
internal_process_ops[0x05]	20540	1			T2	10		T4	59		T7	9
internal_process_ops[0x35]	1497	1			T2	5		T4	9		T7	4
internal_process_ops[0x15]	1551	1			T2	10		T4	8		T7	2
internal_process_ops[0x03]	1128	1			T2	7		T4	1		T7	4
internal_process_ops[0x0b]	1126	1			T2	7		T3	2		T7	2
internal_process_ops[0x3b]	1086	1			T2	4		T4	2		T7	3
internal_process_ops[0x6b]	1136	1			T2	9		T3	4		T4	1
internal_process_ops[0xbb]	1072	1			T2	9		T4	3		T7	3
internal_process_ops[0xeb]	1134	1			T2	5		T7	4		T9	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56846

1

T2

231

T3

10

T4

189

auto[1]

1518

1

T2

9

T4

4

T7

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56047

1

T2

227

T3

10

T4

179

auto[1]

2317

1

T2

13

T4

14

T7

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11476

1

T2

81

T6

2

T7

17

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7497

1

T2

22

T7

14

T13

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2228

1

T2

11

T7

6

T9

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2213

1

T2

20

T7

12

T13

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2971

1

T2

18

T3

8

T7

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2513

1

T2

34

T7

5

T13

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2389

1

T2

15

T3

2

T7

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2053

1

T2

25

T7

11

T13

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

129

1

T37

5

T38

1

T48

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

101

1

T2

1

T37

1

T38

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

111

1

T2

2

T48

3

T17

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

86

1

T2

2

T94

1

T17

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

131

1

T2

2

T46

2

T37

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

124

1

T2

4

T37

1

T38

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

89

1

T48

1

T49

1

T174

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

105

1

T7

2

T37

1

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

95

1

T48

3

T17

2

T174

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

91

1

T2

2

T48

4

T50

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

86

1

T7

1

T37

1

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

113

1

T37

1

T38

2

T47

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

129

1

T11

2

T37

1

T38

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

92

1

T38

1

T17

1

T50

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

124

1

T2

1

T7

1

T37

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

117

1

T7

1

T38

1

T170

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8726

1

T4

70

T12

2

T42

117

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5422

1

T4

48

T12

3

T42

7

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1220

1

T4

8

T12

4

T42

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1154

1

T4

11

T42

4

T52

21

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1541

1

T4

8

T12

3

T42

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1490

1

T4

20

T12

3

T42

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1173

1

T4

10

T12

1

T42

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1183

1

T4

2

T12

2

T42

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

81

1

T4

4

T83

2

T93

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

101

1

T42

3

T88

1

T83

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

79

1

T42

1

T88

2

T83

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

90

1

T42

1

T52

1

T83

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

81

1

T4

2

T17

1

T93

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

49

1

T42

2

T52

2

T83

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

89

1

T42

3

T88

2

T83

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

110

1

T4

1

T88

3

T83

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

90

1

T12

2

T88

1

T83

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

89

1

T88

3

T82

1

T17

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

91

1

T4

1

T173

2

T175

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

93

1

T88

1

T83

1

T173

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

89

1

T4

1

T173

3

T93

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

88

1

T4

1

T52

1

T88

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

103

1

T4

4

T42

1

T88

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

69

1

T4

2

T42

1

T52

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4226	1			T2	50		T6	2		T7	8
auto[0]	values[0]	valids[0x1]	18045	1			T2	68		T3	6		T7	30
auto[0]	values[1]	valids[0x1]	683	1			T2	9		T7	4		T45	1
auto[0]	values[2]	valids[0x0]	607	1			T2	1		T45	1		T37	3
auto[0]	values[2]	valids[0x1]	339	1			T2	3		T45	1		T94	2
auto[0]	values[3]	valids[0x0]	599	1			T2	10		T7	2		T45	1
auto[0]	values[3]	valids[0x1]	324	1			T2	2		T37	3		T38	1
auto[0]	values[4]	valids[0x0]	676	1			T2	11		T45	1		T94	1
auto[0]	values[4]	valids[0x1]	357	1			T2	5		T7	1		T13	4
auto[0]	values[5]	valids[0x0]	519	1			T2	6		T7	2		T9	2
auto[0]	values[5]	valids[0x1]	357	1			T2	2		T7	3		T13	2
auto[0]	values[6]	valids[0x0]	618	1			T2	4		T7	1		T43	2
auto[0]	values[6]	valids[0x1]	377	1			T2	7		T7	6		T37	4
auto[0]	values[7]	valids[0x0]	608	1			T2	4		T7	5		T120	2
auto[0]	values[7]	valids[0x1]	332	1			T2	5		T120	2		T45	1
auto[0]	values[8]	valids[0x0]	4060	1			T2	26		T3	4		T7	17
auto[0]	values[8]	valids[0x1]	2336	1			T2	27		T7	7		T9	6
auto[1]	values[0]	valids[0x0]	3185	1			T4	35		T12	1		T42	21
auto[1]	values[0]	valids[0x1]	13128	1			T4	102		T12	9		T42	118
auto[1]	values[1]	valids[0x1]	457	1			T4	3		T42	11		T52	3
auto[1]	values[2]	valids[0x0]	337	1			T4	1		T12	1		T42	2
auto[1]	values[2]	valids[0x1]	216	1			T52	2		T88	3		T83	1
auto[1]	values[3]	valids[0x0]	295	1			T52	1		T88	6		T83	6
auto[1]	values[3]	valids[0x1]	214	1			T4	1		T88	1		T83	3
auto[1]	values[4]	valids[0x0]	319	1			T4	3		T52	7		T88	4
auto[1]	values[4]	valids[0x1]	191	1			T4	3		T12	1		T52	1
auto[1]	values[5]	valids[0x0]	279	1			T4	3		T52	4		T88	3
auto[1]	values[5]	valids[0x1]	194	1			T4	4		T42	1		T52	2
auto[1]	values[6]	valids[0x0]	291	1			T4	5		T52	3		T88	3
auto[1]	values[6]	valids[0x1]	206	1			T42	5		T52	7		T88	9
auto[1]	values[7]	valids[0x0]	330	1			T4	1		T121	1		T52	5
auto[1]	values[7]	valids[0x1]	188	1			T12	1		T88	6		T83	2
auto[1]	values[8]	valids[0x0]	2068	1			T4	21		T12	4		T42	5
auto[1]	values[8]	valids[0x1]	1403	1			T4	11		T12	3		T42	9