Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3392951

1

T2

21521

T3

2773

T4

11008

auto[1]

30886

1

T2

572

T4

53

T7

6

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

932740

1

T2

559

T3

2773

T4

61

auto[1]

2491097

1

T2

21534

T4

11000

T7

2861

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	611365	1			T2	5689		T3	47		T4	443
auto[524288:1048575]	441060	1			T2	173		T4	2793		T7	9
auto[1048576:1572863]	365887	1			T2	382		T3	4		T4	3941
auto[1572864:2097151]	404443	1			T2	3676		T3	549		T4	1
auto[2097152:2621439]	363683	1			T2	8564		T3	1077		T4	3562
auto[2621440:3145727]	466165	1			T2	3323		T4	276		T7	1075
auto[3145728:3670015]	401288	1			T2	273		T3	468		T4	10
auto[3670016:4194303]	369946	1			T2	13		T3	628		T4	35

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2525721

1

T2

22085

T3

365

T4

11061

auto[1]

898116

1

T2

8

T3

2408

T9

538

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2978990

1

T2

21451

T3

2773

T4

11029

auto[1]

444847

1

T2

642

T4

32

T14

8

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	194203	1			T2	65		T3	47		T4	8
auto[0]	auto[0]	auto[0:524287]	auto[1]	359973	1			T2	5474		T4	435		T7	1527
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	118667	1			T2	37		T4	4		T7	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	264253	1			T2	128		T4	2782		T7	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	140134	1			T2	31		T3	4		T4	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	176571	1			T2	340		T4	3924		T45	1315
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	97859	1			T2	94		T3	549		T4	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	243793	1			T2	3149		T12	5		T43	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	92310	1			T2	66		T3	1077		T4	10
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	226715	1			T2	8309		T4	3541		T12	640
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	132380	1			T2	78		T4	5		T7	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	268114	1			T2	3231		T4	262		T7	1068
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	64614	1			T2	10		T3	468		T4	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	252719	1			T2	1		T4	6		T52	1217
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	78434	1			T2	10		T3	628		T4	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	242518	1			T4	6		T7	260		T94	512
auto[0]	auto[1]	auto[0:524287]	auto[0]	1493	1			T2	13		T232	43		T42	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	51150	1			T2	133		T38	5		T88	1159
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	3907	1			T4	1		T14	5		T45	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	49998	1			T45	1462		T38	1109		T88	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	582	1			T4	5		T14	2		T37	18
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	45250	1			T4	1		T38	1		T47	919
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	564	1			T2	35		T14	1		T232	10
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	58339	1			T2	252		T38	205		T93	258
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	899	1			T2	4		T45	1		T52	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	40870	1			T38	256		T88	129		T82	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	780	1			T2	14		T232	2		T42	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	61847	1			T42	514		T38	311		T88	513
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	605	1			T2	44		T37	17		T38	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	77853	1			T38	1		T15	8		T82	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1358	1			T2	3		T4	5		T45	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	44199	1			T4	4		T37	1239		T38	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	537	1			T2	4		T7	1		T11	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3420	1			T7	1		T11	22		T45	31
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	398	1			T2	8		T4	2		T7	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2903	1			T4	4		T42	8		T37	34
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	339	1			T2	11		T42	1		T52	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2543	1			T42	16		T38	14		T88	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	406	1			T2	6		T37	3		T52	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2191	1			T52	1		T88	1		T83	8
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	383	1			T2	9		T4	4		T37	6
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2242	1			T2	176		T4	7		T37	64
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	350	1			T4	2		T7	1		T52	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2076	1			T4	7		T7	1		T52	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	382	1			T2	5		T4	1		T38	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	4412	1			T2	209		T4	1		T38	26
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	446	1			T4	2		T42	4		T37	7
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2705	1			T4	7		T42	32		T37	172
auto[1]	auto[1]	auto[0:524287]	auto[0]	124	1			T88	3		T15	1		T49	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	465	1			T88	1		T15	1		T17	5
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	84	1			T38	1		T48	2		T175	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	850	1			T38	17		T48	2		T175	23
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	98	1			T4	1		T38	1		T47	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	370	1			T4	8		T38	4		T93	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	78	1			T2	8		T23	1		T175	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1213	1			T2	132		T23	2		T175	18
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	63	1			T88	1		T50	1		T209	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	201	1			T50	1		T197	2		T199	34
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	96	1			T42	2		T38	3		T88	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	522	1			T42	28		T38	32		T88	7
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	94	1			T2	4		T37	12		T38	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	609	1			T38	8		T82	56		T170	13
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	73	1			T4	2		T38	1		T83	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	213	1			T4	5		T83	4		T82	44

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2061171	1			T2	21023		T3	365		T4	10992
auto[0]	auto[0]	auto[1]	892086	1			T3	2408		T9	538		T232	1048
auto[0]	auto[1]	auto[0]	434355	1			T2	498		T4	16		T14	8
auto[0]	auto[1]	auto[1]	5339	1			T232	51		T42	1		T38	5
auto[1]	auto[0]	auto[0]	25180	1			T2	421		T4	37		T7	6
auto[1]	auto[0]	auto[1]	553	1			T2	7		T42	5		T37	9
auto[1]	auto[1]	auto[0]	5015	1			T2	143		T4	16		T42	28
auto[1]	auto[1]	auto[1]	138	1			T2	1		T42	2		T37	2