Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2369323	1			T2	1372		T3	1		T4	4960
all_pins[1]	2369323	1			T2	1372		T3	1		T4	4960
all_pins[2]	2369323	1			T2	1372		T3	1		T4	4960
all_pins[3]	2369323	1			T2	1372		T3	1		T4	4960
all_pins[4]	2369323	1			T2	1372		T3	1		T4	4960
all_pins[5]	2369323	1			T2	1372		T3	1		T4	4960
all_pins[6]	2369323	1			T2	1372		T3	1		T4	4960
all_pins[7]	2369323	1			T2	1372		T3	1		T4	4960

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18899299	1			T2	10976		T3	8		T4	39680
values[0x1]	55285	1			T8	30		T16	14		T17	30
transitions[0x0=>0x1]	54219	1			T8	23		T16	13		T17	19
transitions[0x1=>0x0]	54233	1			T8	23		T16	13		T17	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2368344	1			T2	1372		T3	1		T4	4960
all_pins[0]	values[0x1]	979	1			T8	2		T17	4		T19	2
all_pins[0]	transitions[0x0=>0x1]	653	1			T8	2		T20	2		T21	1
all_pins[0]	transitions[0x1=>0x0]	144	1			T8	3		T16	4		T17	2
all_pins[1]	values[0x0]	2368853	1			T2	1372		T3	1		T4	4960
all_pins[1]	values[0x1]	470	1			T8	3		T16	4		T17	6
all_pins[1]	transitions[0x0=>0x1]	425	1			T8	2		T16	4		T17	4
all_pins[1]	transitions[0x1=>0x0]	218	1			T8	2		T19	1		T20	1
all_pins[2]	values[0x0]	2369060	1			T2	1372		T3	1		T4	4960
all_pins[2]	values[0x1]	263	1			T8	3		T17	2		T19	2
all_pins[2]	transitions[0x0=>0x1]	227	1			T8	2		T17	1		T19	1
all_pins[2]	transitions[0x1=>0x0]	154	1			T8	5		T16	1		T17	5
all_pins[3]	values[0x0]	2369133	1			T2	1372		T3	1		T4	4960
all_pins[3]	values[0x1]	190	1			T8	6		T16	1		T17	6
all_pins[3]	transitions[0x0=>0x1]	143	1			T8	3		T16	1		T17	5
all_pins[3]	transitions[0x1=>0x0]	155	1			T8	1		T16	3		T17	1
all_pins[4]	values[0x0]	2369121	1			T2	1372		T3	1		T4	4960
all_pins[4]	values[0x1]	202	1			T8	4		T16	3		T17	2
all_pins[4]	transitions[0x0=>0x1]	162	1			T8	3		T16	3		T17	2
all_pins[4]	transitions[0x1=>0x0]	885	1			T8	1		T17	2		T19	1
all_pins[5]	values[0x0]	2368398	1			T2	1372		T3	1		T4	4960
all_pins[5]	values[0x1]	925	1			T8	2		T17	2		T19	2
all_pins[5]	transitions[0x0=>0x1]	450	1			T8	1		T17	1		T19	1
all_pins[5]	transitions[0x1=>0x0]	51603	1			T8	7		T16	3		T17	2
all_pins[6]	values[0x0]	2317245	1			T2	1372		T3	1		T4	4960
all_pins[6]	values[0x1]	52078	1			T8	8		T16	3		T17	3
all_pins[6]	transitions[0x0=>0x1]	52026	1			T8	8		T16	2		T17	2
all_pins[6]	transitions[0x1=>0x0]	126	1			T8	2		T16	2		T17	4
all_pins[7]	values[0x0]	2369145	1			T2	1372		T3	1		T4	4960
all_pins[7]	values[0x1]	178	1			T8	2		T16	3		T17	5
all_pins[7]	transitions[0x0=>0x1]	133	1			T8	2		T16	3		T17	4
all_pins[7]	transitions[0x1=>0x0]	948	1			T8	2		T17	3		T19	2