Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 0 18 100.00
Crosses 128 0 128 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_addr_swap_en 2 0 2 100.00 100 1 1 2
cp_data 8 0 8 100.00 100 1 1 0
cp_mask 8 0 8 100.00 100 1 1 0


Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 128 0 128 100.00 100 1 1 0


Summary for Variable cp_addr_swap_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_addr_swap_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 19956 1 T2 134 T3 10 T6 2
auto[1] 15107 1 T2 106 T7 47 T13 20



Summary for Variable cp_data

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_data

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 3976 1 T2 40 T9 14 T45 20
values[1] 4620 1 T2 60 T7 22 T14 16
values[2] 4892 1 T2 40 T3 10 T120 6
values[3] 4557 1 T2 40 T6 2 T11 30
values[4] 4691 1 T2 20 T7 42 T43 10
values[5] 4390 1 T2 20 T37 80 T38 102
values[6] 3422 1 T2 20 T13 20 T232 14
values[7] 4515 1 T7 22 T89 10 T94 20



Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 4167 1 T2 40 T37 20 T38 49
values[1] 3553 1 T2 40 T43 10 T37 20
values[2] 4028 1 T2 20 T6 2 T7 44
values[3] 4071 1 T2 40 T3 10 T232 14
values[4] 4756 1 T2 40 T7 22 T9 14
values[5] 5107 1 T7 20 T120 6 T37 20
values[6] 4105 1 T2 40 T11 30 T46 14
values[7] 5276 1 T2 20 T14 16 T37 80



Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_addr_swap_encp_datacp_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] values[0] 211 1 T2 24 T193 18 T160 13
auto[0] values[0] values[1] 261 1 T38 10 T211 9 T209 17
auto[0] values[0] values[2] 285 1 T45 10 T17 23 T51 9
auto[0] values[0] values[3] 189 1 T212 16 T203 12 T216 12
auto[0] values[0] values[4] 262 1 T9 14 T90 6 T17 8
auto[0] values[0] values[5] 403 1 T38 15 T50 16 T79 4
auto[0] values[0] values[6] 241 1 T17 12 T51 12 T233 10
auto[0] values[0] values[7] 290 1 T15 18 T212 14 T234 71
auto[0] values[1] values[0] 356 1 T15 23 T174 6 T235 17
auto[0] values[1] values[1] 476 1 T2 5 T174 27 T216 53
auto[0] values[1] values[2] 115 1 T2 10 T216 9 T67 5
auto[0] values[1] values[3] 331 1 T2 14 T38 15 T51 11
auto[0] values[1] values[4] 356 1 T7 13 T47 16 T50 7
auto[0] values[1] values[5] 559 1 T105 26 T48 114 T17 19
auto[0] values[1] values[6] 281 1 T17 16 T174 26 T193 14
auto[0] values[1] values[7] 354 1 T14 16 T48 17 T15 16
auto[0] values[2] values[0] 412 1 T37 15 T236 4 T49 11
auto[0] values[2] values[1] 160 1 T187 4 T15 26 T189 13
auto[0] values[2] values[2] 325 1 T49 16 T195 11 T222 8
auto[0] values[2] values[3] 330 1 T2 14 T3 10 T174 20
auto[0] values[2] values[4] 316 1 T2 10 T49 12 T50 27
auto[0] values[2] values[5] 499 1 T120 6 T48 9 T219 14
auto[0] values[2] values[6] 302 1 T193 11 T209 9 T237 2
auto[0] values[2] values[7] 538 1 T53 59 T50 7 T238 6
auto[0] values[3] values[0] 319 1 T17 8 T50 6 T170 12
auto[0] values[3] values[1] 333 1 T2 9 T37 15 T38 25
auto[0] values[3] values[2] 194 1 T6 2 T50 33 T51 8
auto[0] values[3] values[3] 270 1 T81 18 T54 8 T191 11
auto[0] values[3] values[4] 545 1 T50 31 T51 8 T170 14
auto[0] values[3] values[5] 183 1 T174 11 T202 16 T219 13
auto[0] values[3] values[6] 287 1 T2 14 T11 30 T38 9
auto[0] values[3] values[7] 307 1 T239 10 T216 31 T188 12
auto[0] values[4] values[0] 217 1 T51 16 T160 8 T185 9
auto[0] values[4] values[1] 133 1 T43 10 T217 12 T185 11
auto[0] values[4] values[2] 307 1 T7 8 T51 11 T188 8
auto[0] values[4] values[3] 276 1 T240 14 T216 11 T160 9
auto[0] values[4] values[4] 368 1 T45 10 T37 7 T38 19
auto[0] values[4] values[5] 453 1 T7 10 T210 20 T170 51
auto[0] values[4] values[6] 432 1 T46 14 T51 11 T75 21
auto[0] values[4] values[7] 314 1 T2 8 T48 11 T203 50
auto[0] values[5] values[0] 396 1 T38 8 T48 14 T203 18
auto[0] values[5] values[1] 274 1 T38 14 T49 10 T196 9
auto[0] values[5] values[2] 478 1 T37 14 T206 8 T17 21
auto[0] values[5] values[3] 240 1 T38 14 T51 8 T195 56
auto[0] values[5] values[4] 380 1 T50 8 T212 6 T241 60
auto[0] values[5] values[5] 236 1 T202 7 T242 2 T225 83
auto[0] values[5] values[6] 197 1 T2 12 T243 4 T225 10
auto[0] values[5] values[7] 404 1 T37 32 T17 44 T193 14
auto[0] values[6] values[0] 101 1 T50 10 T209 17 T244 14
auto[0] values[6] values[1] 233 1 T170 62 T245 6 T195 9
auto[0] values[6] values[2] 200 1 T47 7 T48 11 T202 14
auto[0] values[6] values[3] 294 1 T232 14 T48 32 T170 16
auto[0] values[6] values[4] 218 1 T2 14 T202 10 T195 14
auto[0] values[6] values[5] 284 1 T48 14 T51 10 T204 34
auto[0] values[6] values[6] 160 1 T229 12 T203 10 T216 14
auto[0] values[6] values[7] 320 1 T37 16 T38 21 T49 10
auto[0] values[7] values[0] 361 1 T38 10 T193 47 T197 7
auto[0] values[7] values[1] 162 1 T203 10 T225 11 T246 16
auto[0] values[7] values[2] 473 1 T7 8 T89 10 T50 52
auto[0] values[7] values[3] 430 1 T94 12 T192 10 T195 13
auto[0] values[7] values[4] 297 1 T38 7 T17 15 T209 9
auto[0] values[7] values[5] 273 1 T37 7 T170 8 T247 8
auto[0] values[7] values[6] 382 1 T248 6 T213 26 T249 8
auto[0] values[7] values[7] 373 1 T211 13 T203 92 T197 11
auto[1] values[0] values[0] 187 1 T2 16 T193 10 T160 58
auto[1] values[0] values[1] 385 1 T38 10 T211 21 T209 6
auto[1] values[0] values[2] 193 1 T45 10 T96 12 T17 38
auto[1] values[0] values[3] 163 1 T212 4 T203 8 T216 14
auto[1] values[0] values[4] 257 1 T17 16 T174 7 T209 17
auto[1] values[0] values[5] 228 1 T38 5 T50 4 T170 11
auto[1] values[0] values[6] 270 1 T44 10 T17 13 T51 8
auto[1] values[0] values[7] 151 1 T15 22 T212 6 T234 10
auto[1] values[1] values[0] 215 1 T15 20 T174 14 T235 4
auto[1] values[1] values[1] 162 1 T2 15 T174 5 T216 4
auto[1] values[1] values[2] 82 1 T2 10 T216 11 T67 15
auto[1] values[1] values[3] 123 1 T2 6 T38 12 T51 9
auto[1] values[1] values[4] 212 1 T7 9 T47 5 T50 13
auto[1] values[1] values[5] 449 1 T48 18 T17 5 T174 3
auto[1] values[1] values[6] 212 1 T17 4 T174 6 T193 6
auto[1] values[1] values[7] 337 1 T48 3 T15 4 T49 8
auto[1] values[2] values[0] 258 1 T37 5 T49 9 T203 20
auto[1] values[2] values[1] 108 1 T15 9 T189 7 T250 47
auto[1] values[2] values[2] 163 1 T106 8 T49 4 T195 9
auto[1] values[2] values[3] 310 1 T2 6 T174 9 T211 16
auto[1] values[2] values[4] 243 1 T2 10 T49 8 T50 5
auto[1] values[2] values[5] 314 1 T48 27 T219 10 T209 8
auto[1] values[2] values[6] 259 1 T193 9 T209 18 T251 10
auto[1] values[2] values[7] 355 1 T50 60 T193 8 T212 9
auto[1] values[3] values[0] 234 1 T17 15 T50 14 T170 51
auto[1] values[3] values[1] 174 1 T2 11 T37 5 T38 12
auto[1] values[3] values[2] 221 1 T50 4 T51 12 T202 19
auto[1] values[3] values[3] 277 1 T54 154 T191 9 T252 6
auto[1] values[3] values[4] 430 1 T50 6 T51 12 T170 24
auto[1] values[3] values[5] 185 1 T174 9 T202 8 T219 7
auto[1] values[3] values[6] 317 1 T2 6 T38 72 T15 9
auto[1] values[3] values[7] 281 1 T216 149 T188 8 T189 8
auto[1] values[4] values[0] 165 1 T51 4 T160 12 T207 18
auto[1] values[4] values[1] 148 1 T253 4 T217 8 T185 9
auto[1] values[4] values[2] 373 1 T7 14 T51 9 T188 12
auto[1] values[4] values[3] 250 1 T216 11 T160 11 T213 13
auto[1] values[4] values[4] 245 1 T45 42 T37 13 T38 40
auto[1] values[4] values[5] 368 1 T7 10 T170 19 T211 6
auto[1] values[4] values[6] 274 1 T51 9 T75 13 T209 8
auto[1] values[4] values[7] 368 1 T2 12 T48 69 T203 9
auto[1] values[5] values[0] 372 1 T38 12 T48 21 T203 55
auto[1] values[5] values[1] 221 1 T38 44 T49 10 T196 11
auto[1] values[5] values[2] 158 1 T37 6 T17 8 T67 9
auto[1] values[5] values[3] 134 1 T38 10 T51 12 T195 8
auto[1] values[5] values[4] 168 1 T50 12 T212 14 T225 7
auto[1] values[5] values[5] 145 1 T202 13 T254 18 T225 10
auto[1] values[5] values[6] 246 1 T2 8 T225 10 T194 7
auto[1] values[5] values[7] 341 1 T37 28 T95 16 T17 8
auto[1] values[6] values[0] 71 1 T50 15 T209 24 T244 6
auto[1] values[6] values[1] 182 1 T170 7 T195 26 T225 14
auto[1] values[6] values[2] 261 1 T13 20 T47 17 T48 9
auto[1] values[6] values[3] 140 1 T48 6 T170 4 T225 3
auto[1] values[6] values[4] 160 1 T2 6 T202 10 T195 22
auto[1] values[6] values[5] 371 1 T48 10 T51 10 T204 5
auto[1] values[6] values[6] 85 1 T203 10 T216 6 T249 9
auto[1] values[6] values[7] 342 1 T37 4 T38 48 T49 10
auto[1] values[7] values[0] 292 1 T38 19 T193 12 T197 21
auto[1] values[7] values[1] 141 1 T203 38 T255 4 T190 6
auto[1] values[7] values[2] 200 1 T7 14 T50 5 T197 29
auto[1] values[7] values[3] 314 1 T94 8 T195 7 T196 11
auto[1] values[7] values[4] 299 1 T38 13 T17 61 T209 11
auto[1] values[7] values[5] 157 1 T37 13 T170 12 T160 9
auto[1] values[7] values[6] 160 1 T213 11 T249 15 T185 7
auto[1] values[7] values[7] 201 1 T211 8 T203 8 T197 11

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